arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_CLOCKSOURCE_DATA
   5         select ARCH_HAS_DEBUG_VIRTUAL
   6         select ARCH_HAS_DEVMEM_IS_ALLOWED
   7         select ARCH_HAS_ELF_RANDOMIZE
   8         select ARCH_HAS_SET_MEMORY
   9         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  10         select ARCH_HAS_STRICT_MODULE_RWX if MMU
  11         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  12         select ARCH_HAVE_CUSTOM_GPIO_H
  13         select ARCH_HAS_GCOV_PROFILE_ALL
  14         select ARCH_MIGHT_HAVE_PC_PARPORT
  15         select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  16         select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  17         select ARCH_SUPPORTS_ATOMIC_RMW
  18         select ARCH_USE_BUILTIN_BSWAP
  19         select ARCH_USE_CMPXCHG_LOCKREF
  20         select ARCH_WANT_IPC_PARSE_VERSION
  21         select BUILDTIME_EXTABLE_SORT if MMU
  22         select CLONE_BACKWARDS
  23         select CPU_PM if (SUSPEND || CPU_IDLE)
  24         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  25         select EDAC_SUPPORT
  26         select EDAC_ATOMIC_SCRUB
  27         select GENERIC_ALLOCATOR
  28         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  29         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  30         select GENERIC_EARLY_IOREMAP
  31         select GENERIC_IDLE_POLL_SETUP
  32         select GENERIC_IRQ_PROBE
  33         select GENERIC_IRQ_SHOW
  34         select GENERIC_IRQ_SHOW_LEVEL
  35         select GENERIC_PCI_IOMAP
  36         select GENERIC_SCHED_CLOCK
  37         select GENERIC_SMP_IDLE_THREAD
  38         select GENERIC_STRNCPY_FROM_USER
  39         select GENERIC_STRNLEN_USER
  40         select HANDLE_DOMAIN_IRQ
  41         select HARDIRQS_SW_RESEND
  42         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  43         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  44         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  45         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  46         select HAVE_ARCH_MMAP_RND_BITS if MMU
  47         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  48         select HAVE_ARCH_TRACEHOOK
  49         select HAVE_ARM_SMCCC if CPU_V7
  50         select HAVE_CBPF_JIT
  51         select HAVE_CC_STACKPROTECTOR
  52         select HAVE_CONTEXT_TRACKING
  53         select HAVE_C_RECORDMCOUNT
  54         select HAVE_DEBUG_KMEMLEAK
  55         select HAVE_DMA_API_DEBUG
  56         select HAVE_DMA_CONTIGUOUS if MMU
  57         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  58         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  59         select HAVE_EXIT_THREAD
  60         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  61         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  62         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  63         select HAVE_GCC_PLUGINS
  64         select HAVE_GENERIC_DMA_COHERENT
  65         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  66         select HAVE_IDE if PCI || ISA || PCMCIA
  67         select HAVE_IRQ_TIME_ACCOUNTING
  68         select HAVE_KERNEL_GZIP
  69         select HAVE_KERNEL_LZ4
  70         select HAVE_KERNEL_LZMA
  71         select HAVE_KERNEL_LZO
  72         select HAVE_KERNEL_XZ
  73         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  74         select HAVE_KRETPROBES if (HAVE_KPROBES)
  75         select HAVE_MEMBLOCK
  76         select HAVE_MOD_ARCH_SPECIFIC
  77         select HAVE_NMI
  78         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  79         select HAVE_OPTPROBES if !THUMB2_KERNEL
  80         select HAVE_PERF_EVENTS
  81         select HAVE_PERF_REGS
  82         select HAVE_PERF_USER_STACK_DUMP
  83         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  84         select HAVE_REGS_AND_STACK_ACCESS_API
  85         select HAVE_SYSCALL_TRACEPOINTS
  86         select HAVE_UID16
  87         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  88         select IRQ_FORCED_THREADING
  89         select MODULES_USE_ELF_REL
  90         select NO_BOOTMEM
  91         select OF_EARLY_FLATTREE if OF
  92         select OF_RESERVED_MEM if OF
  93         select OLD_SIGACTION
  94         select OLD_SIGSUSPEND3
  95         select PERF_USE_VMALLOC
  96         select RTC_LIB
  97         select SYS_SUPPORTS_APM_EMULATION
  98         # Above selects are sorted alphabetically; please add new ones
  99         # according to that.  Thanks.
 100         help
 101           The ARM series is a line of low-power-consumption RISC chip designs
 102           licensed by ARM Ltd and targeted at embedded applications and
 103           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 104           manufactured, but legacy ARM-based PC hardware remains popular in
 105           Europe.  There is an ARM Linux project with a web page at
 106           <http://www.arm.linux.org.uk/>.
 107
 108 config ARM_HAS_SG_CHAIN
 109         select ARCH_HAS_SG_CHAIN
 110         bool
 111
 112 config NEED_SG_DMA_LENGTH
 113         bool
 114
 115 config ARM_DMA_USE_IOMMU
 116         bool
 117         select ARM_HAS_SG_CHAIN
 118         select NEED_SG_DMA_LENGTH
 119
 120 if ARM_DMA_USE_IOMMU
 121
 122 config ARM_DMA_IOMMU_ALIGNMENT
 123         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 124         range 4 9
 125         default 8
 126         help
 127           DMA mapping framework by default aligns all buffers to the smallest
 128           PAGE_SIZE order which is greater than or equal to the requested buffer
 129           size. This works well for buffers up to a few hundreds kilobytes, but
 130           for larger buffers it just a waste of address space. Drivers which has
 131           relatively small addressing window (like 64Mib) might run out of
 132           virtual space with just a few allocations.
 133
 134           With this parameter you can specify the maximum PAGE_SIZE order for
 135           DMA IOMMU buffers. Larger buffers will be aligned only to this
 136           specified order. The order is expressed as a power of two multiplied
 137           by the PAGE_SIZE.
 138
 139 endif
 140
 141 config MIGHT_HAVE_PCI
 142         bool
 143
 144 config SYS_SUPPORTS_APM_EMULATION
 145         bool
 146
 147 config HAVE_TCM
 148         bool
 149         select GENERIC_ALLOCATOR
 150
 151 config HAVE_PROC_CPU
 152         bool
 153
 154 config NO_IOPORT_MAP
 155         bool
 156
 157 config EISA
 158         bool
 159         ---help---
 160           The Extended Industry Standard Architecture (EISA) bus was
 161           developed as an open alternative to the IBM MicroChannel bus.
 162
 163           The EISA bus provided some of the features of the IBM MicroChannel
 164           bus while maintaining backward compatibility with cards made for
 165           the older ISA bus.  The EISA bus saw limited use between 1988 and
 166           1995 when it was made obsolete by the PCI bus.
 167
 168           Say Y here if you are building a kernel for an EISA-based machine.
 169
 170           Otherwise, say N.
 171
 172 config SBUS
 173         bool
 174
 175 config STACKTRACE_SUPPORT
 176         bool
 177         default y
 178
 179 config LOCKDEP_SUPPORT
 180         bool
 181         default y
 182
 183 config TRACE_IRQFLAGS_SUPPORT
 184         bool
 185         default !CPU_V7M
 186
 187 config RWSEM_XCHGADD_ALGORITHM
 188         bool
 189         default y
 190
 191 config ARCH_HAS_ILOG2_U32
 192         bool
 193
 194 config ARCH_HAS_ILOG2_U64
 195         bool
 196
 197 config ARCH_HAS_BANDGAP
 198         bool
 199
 200 config FIX_EARLYCON_MEM
 201         def_bool y if MMU
 202
 203 config GENERIC_HWEIGHT
 204         bool
 205         default y
 206
 207 config GENERIC_CALIBRATE_DELAY
 208         bool
 209         default y
 210
 211 config ARCH_MAY_HAVE_PC_FDC
 212         bool
 213
 214 config ZONE_DMA
 215         bool
 216
 217 config NEED_DMA_MAP_STATE
 218        def_bool y
 219
 220 config ARCH_SUPPORTS_UPROBES
 221         def_bool y
 222
 223 config ARCH_HAS_DMA_SET_COHERENT_MASK
 224         bool
 225
 226 config GENERIC_ISA_DMA
 227         bool
 228
 229 config FIQ
 230         bool
 231
 232 config NEED_RET_TO_USER
 233         bool
 234
 235 config ARCH_MTD_XIP
 236         bool
 237
 238 config VECTORS_BASE
 239         hex
 240         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 241         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 242         default 0x00000000
 243         help
 244           The base address of exception vectors.  This must be two pages
 245           in size.
 246
 247 config ARM_PATCH_PHYS_VIRT
 248         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 249         default y
 250         depends on !XIP_KERNEL && MMU
 251         help
 252           Patch phys-to-virt and virt-to-phys translation functions at
 253           boot and module load time according to the position of the
 254           kernel in system memory.
 255
 256           This can only be used with non-XIP MMU kernels where the base
 257           of physical memory is at a 16MB boundary.
 258
 259           Only disable this option if you know that you do not require
 260           this feature (eg, building a kernel for a single machine) and
 261           you need to shrink the kernel to the minimal size.
 262
 263 config NEED_MACH_IO_H
 264         bool
 265         help
 266           Select this when mach/io.h is required to provide special
 267           definitions for this platform.  The need for mach/io.h should
 268           be avoided when possible.
 269
 270 config NEED_MACH_MEMORY_H
 271         bool
 272         help
 273           Select this when mach/memory.h is required to provide special
 274           definitions for this platform.  The need for mach/memory.h should
 275           be avoided when possible.
 276
 277 config PHYS_OFFSET
 278         hex "Physical address of main memory" if MMU
 279         depends on !ARM_PATCH_PHYS_VIRT
 280         default DRAM_BASE if !MMU
 281         default 0x00000000 if ARCH_EBSA110 || \
 282                         ARCH_FOOTBRIDGE || \
 283                         ARCH_INTEGRATOR || \
 284                         ARCH_IOP13XX || \
 285                         ARCH_KS8695 || \
 286                         ARCH_REALVIEW
 287         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 288         default 0x20000000 if ARCH_S5PV210
 289         default 0xc0000000 if ARCH_SA1100
 290         help
 291           Please provide the physical address corresponding to the
 292           location of main memory in your system.
 293
 294 config GENERIC_BUG
 295         def_bool y
 296         depends on BUG
 297
 298 config PGTABLE_LEVELS
 299         int
 300         default 3 if ARM_LPAE
 301         default 2
 302
 303 source "init/Kconfig"
 304
 305 source "kernel/Kconfig.freezer"
 306
 307 menu "System Type"
 308
 309 config MMU
 310         bool "MMU-based Paged Memory Management Support"
 311         default y
 312         help
 313           Select if you want MMU-based virtualised addressing space
 314           support by paged memory management. If unsure, say 'Y'.
 315
 316 config ARCH_MMAP_RND_BITS_MIN
 317         default 8
 318
 319 config ARCH_MMAP_RND_BITS_MAX
 320         default 14 if PAGE_OFFSET=0x40000000
 321         default 15 if PAGE_OFFSET=0x80000000
 322         default 16
 323
 324 #
 325 # The "ARM system type" choice list is ordered alphabetically by option
 326 # text.  Please add new entries in the option alphabetic order.
 327 #
 328 choice
 329         prompt "ARM system type"
 330         default ARM_SINGLE_ARMV7M if !MMU
 331         default ARCH_MULTIPLATFORM if MMU
 332
 333 config ARCH_MULTIPLATFORM
 334         bool "Allow multiple platforms to be selected"
 335         depends on MMU
 336         select ARM_HAS_SG_CHAIN
 337         select ARM_PATCH_PHYS_VIRT
 338         select AUTO_ZRELADDR
 339         select CLKSRC_OF
 340         select COMMON_CLK
 341         select GENERIC_CLOCKEVENTS
 342         select MIGHT_HAVE_PCI
 343         select MULTI_IRQ_HANDLER
 344         select PCI_DOMAINS if PCI
 345         select SPARSE_IRQ
 346         select USE_OF
 347
 348 config ARM_SINGLE_ARMV7M
 349         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 350         depends on !MMU
 351         select ARM_NVIC
 352         select AUTO_ZRELADDR
 353         select CLKSRC_OF
 354         select COMMON_CLK
 355         select CPU_V7M
 356         select GENERIC_CLOCKEVENTS
 357         select NO_IOPORT_MAP
 358         select SPARSE_IRQ
 359         select USE_OF
 360
 361 config ARCH_GEMINI
 362         bool "Cortina Systems Gemini"
 363         select CLKSRC_MMIO
 364         select CPU_FA526
 365         select GENERIC_CLOCKEVENTS
 366         select GPIOLIB
 367         help
 368           Support for the Cortina Systems Gemini family SoCs
 369
 370 config ARCH_EBSA110
 371         bool "EBSA-110"
 372         select ARCH_USES_GETTIMEOFFSET
 373         select CPU_SA110
 374         select ISA
 375         select NEED_MACH_IO_H
 376         select NEED_MACH_MEMORY_H
 377         select NO_IOPORT_MAP
 378         help
 379           This is an evaluation board for the StrongARM processor available
 380           from Digital. It has limited hardware on-board, including an
 381           Ethernet interface, two PCMCIA sockets, two serial ports and a
 382           parallel port.
 383
 384 config ARCH_EP93XX
 385         bool "EP93xx-based"
 386         select ARCH_HAS_HOLES_MEMORYMODEL
 387         select ARM_AMBA
 388         select ARM_PATCH_PHYS_VIRT
 389         select ARM_VIC
 390         select AUTO_ZRELADDR
 391         select CLKDEV_LOOKUP
 392         select CLKSRC_MMIO
 393         select CPU_ARM920T
 394         select GENERIC_CLOCKEVENTS
 395         select GPIOLIB
 396         help
 397           This enables support for the Cirrus EP93xx series of CPUs.
 398
 399 config ARCH_FOOTBRIDGE
 400         bool "FootBridge"
 401         select CPU_SA110
 402         select FOOTBRIDGE
 403         select GENERIC_CLOCKEVENTS
 404         select HAVE_IDE
 405         select NEED_MACH_IO_H if !MMU
 406         select NEED_MACH_MEMORY_H
 407         help
 408           Support for systems based on the DC21285 companion chip
 409           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 410
 411 config ARCH_NETX
 412         bool "Hilscher NetX based"
 413         select ARM_VIC
 414         select CLKSRC_MMIO
 415         select CPU_ARM926T
 416         select GENERIC_CLOCKEVENTS
 417         help
 418           This enables support for systems based on the Hilscher NetX Soc
 419
 420 config ARCH_IOP13XX
 421         bool "IOP13xx-based"
 422         depends on MMU
 423         select CPU_XSC3
 424         select NEED_MACH_MEMORY_H
 425         select NEED_RET_TO_USER
 426         select PCI
 427         select PLAT_IOP
 428         select VMSPLIT_1G
 429         select SPARSE_IRQ
 430         help
 431           Support for Intel's IOP13XX (XScale) family of processors.
 432
 433 config ARCH_IOP32X
 434         bool "IOP32x-based"
 435         depends on MMU
 436         select CPU_XSCALE
 437         select GPIO_IOP
 438         select GPIOLIB
 439         select NEED_RET_TO_USER
 440         select PCI
 441         select PLAT_IOP
 442         help
 443           Support for Intel's 80219 and IOP32X (XScale) family of
 444           processors.
 445
 446 config ARCH_IOP33X
 447         bool "IOP33x-based"
 448         depends on MMU
 449         select CPU_XSCALE
 450         select GPIO_IOP
 451         select GPIOLIB
 452         select NEED_RET_TO_USER
 453         select PCI
 454         select PLAT_IOP
 455         help
 456           Support for Intel's IOP33X (XScale) family of processors.
 457
 458 config ARCH_IXP4XX
 459         bool "IXP4xx-based"
 460         depends on MMU
 461         select ARCH_HAS_DMA_SET_COHERENT_MASK
 462         select ARCH_SUPPORTS_BIG_ENDIAN
 463         select CLKSRC_MMIO
 464         select CPU_XSCALE
 465         select DMABOUNCE if PCI
 466         select GENERIC_CLOCKEVENTS
 467         select GPIOLIB
 468         select MIGHT_HAVE_PCI
 469         select NEED_MACH_IO_H
 470         select USB_EHCI_BIG_ENDIAN_DESC
 471         select USB_EHCI_BIG_ENDIAN_MMIO
 472         help
 473           Support for Intel's IXP4XX (XScale) family of processors.
 474
 475 config ARCH_DOVE
 476         bool "Marvell Dove"
 477         select CPU_PJ4
 478         select GENERIC_CLOCKEVENTS
 479         select GPIOLIB
 480         select MIGHT_HAVE_PCI
 481         select MULTI_IRQ_HANDLER
 482         select MVEBU_MBUS
 483         select PINCTRL
 484         select PINCTRL_DOVE
 485         select PLAT_ORION_LEGACY
 486         select SPARSE_IRQ
 487         select PM_GENERIC_DOMAINS if PM
 488         help
 489           Support for the Marvell Dove SoC 88AP510
 490
 491 config ARCH_KS8695
 492         bool "Micrel/Kendin KS8695"
 493         select CLKSRC_MMIO
 494         select CPU_ARM922T
 495         select GENERIC_CLOCKEVENTS
 496         select GPIOLIB
 497         select NEED_MACH_MEMORY_H
 498         help
 499           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 500           System-on-Chip devices.
 501
 502 config ARCH_W90X900
 503         bool "Nuvoton W90X900 CPU"
 504         select CLKDEV_LOOKUP
 505         select CLKSRC_MMIO
 506         select CPU_ARM926T
 507         select GENERIC_CLOCKEVENTS
 508         select GPIOLIB
 509         help
 510           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 511           At present, the w90x900 has been renamed nuc900, regarding
 512           the ARM series product line, you can login the following
 513           link address to know more.
 514
 515           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 516                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 517
 518 config ARCH_LPC32XX
 519         bool "NXP LPC32XX"
 520         select ARM_AMBA
 521         select CLKDEV_LOOKUP
 522         select CLKSRC_LPC32XX
 523         select COMMON_CLK
 524         select CPU_ARM926T
 525         select GENERIC_CLOCKEVENTS
 526         select GPIOLIB
 527         select MULTI_IRQ_HANDLER
 528         select SPARSE_IRQ
 529         select USE_OF
 530         help
 531           Support for the NXP LPC32XX family of processors
 532
 533 config ARCH_PXA
 534         bool "PXA2xx/PXA3xx-based"
 535         depends on MMU
 536         select ARCH_MTD_XIP
 537         select ARM_CPU_SUSPEND if PM
 538         select AUTO_ZRELADDR
 539         select COMMON_CLK
 540         select CLKDEV_LOOKUP
 541         select CLKSRC_PXA
 542         select CLKSRC_MMIO
 543         select CLKSRC_OF
 544         select CPU_XSCALE if !CPU_XSC3
 545         select GENERIC_CLOCKEVENTS
 546         select GPIO_PXA
 547         select GPIOLIB
 548         select HAVE_IDE
 549         select IRQ_DOMAIN
 550         select MULTI_IRQ_HANDLER
 551         select PLAT_PXA
 552         select SPARSE_IRQ
 553         help
 554           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 555
 556 config ARCH_RPC
 557         bool "RiscPC"
 558         depends on MMU
 559         select ARCH_ACORN
 560         select ARCH_MAY_HAVE_PC_FDC
 561         select ARCH_SPARSEMEM_ENABLE
 562         select ARCH_USES_GETTIMEOFFSET
 563         select CPU_SA110
 564         select FIQ
 565         select HAVE_IDE
 566         select HAVE_PATA_PLATFORM
 567         select ISA_DMA_API
 568         select NEED_MACH_IO_H
 569         select NEED_MACH_MEMORY_H
 570         select NO_IOPORT_MAP
 571         help
 572           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 573           CD-ROM interface, serial and parallel port, and the floppy drive.
 574
 575 config ARCH_SA1100
 576         bool "SA1100-based"
 577         select ARCH_MTD_XIP
 578         select ARCH_SPARSEMEM_ENABLE
 579         select CLKDEV_LOOKUP
 580         select CLKSRC_MMIO
 581         select CLKSRC_PXA
 582         select CLKSRC_OF if OF
 583         select CPU_FREQ
 584         select CPU_SA1100
 585         select GENERIC_CLOCKEVENTS
 586         select GPIOLIB
 587         select HAVE_IDE
 588         select IRQ_DOMAIN
 589         select ISA
 590         select MULTI_IRQ_HANDLER
 591         select NEED_MACH_MEMORY_H
 592         select SPARSE_IRQ
 593         help
 594           Support for StrongARM 11x0 based boards.
 595
 596 config ARCH_S3C24XX
 597         bool "Samsung S3C24XX SoCs"
 598         select ATAGS
 599         select CLKDEV_LOOKUP
 600         select CLKSRC_SAMSUNG_PWM
 601         select GENERIC_CLOCKEVENTS
 602         select GPIO_SAMSUNG
 603         select GPIOLIB
 604         select HAVE_S3C2410_I2C if I2C
 605         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 606         select HAVE_S3C_RTC if RTC_CLASS
 607         select MULTI_IRQ_HANDLER
 608         select NEED_MACH_IO_H
 609         select SAMSUNG_ATAGS
 610         help
 611           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 612           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 613           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 614           Samsung SMDK2410 development board (and derivatives).
 615
 616 config ARCH_DAVINCI
 617         bool "TI DaVinci"
 618         select ARCH_HAS_HOLES_MEMORYMODEL
 619         select CLKDEV_LOOKUP
 620         select CPU_ARM926T
 621         select GENERIC_ALLOCATOR
 622         select GENERIC_CLOCKEVENTS
 623         select GENERIC_IRQ_CHIP
 624         select GPIOLIB
 625         select HAVE_IDE
 626         select USE_OF
 627         select ZONE_DMA
 628         help
 629           Support for TI's DaVinci platform.
 630
 631 config ARCH_OMAP1
 632         bool "TI OMAP1"
 633         depends on MMU
 634         select ARCH_HAS_HOLES_MEMORYMODEL
 635         select ARCH_OMAP
 636         select CLKDEV_LOOKUP
 637         select CLKSRC_MMIO
 638         select GENERIC_CLOCKEVENTS
 639         select GENERIC_IRQ_CHIP
 640         select GPIOLIB
 641         select HAVE_IDE
 642         select IRQ_DOMAIN
 643         select MULTI_IRQ_HANDLER
 644         select NEED_MACH_IO_H if PCCARD
 645         select NEED_MACH_MEMORY_H
 646         select SPARSE_IRQ
 647         help
 648           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 649
 650 endchoice
 651
 652 menu "Multiple platform selection"
 653         depends on ARCH_MULTIPLATFORM
 654
 655 comment "CPU Core family selection"
 656
 657 config ARCH_MULTI_V4
 658         bool "ARMv4 based platforms (FA526)"
 659         depends on !ARCH_MULTI_V6_V7
 660         select ARCH_MULTI_V4_V5
 661         select CPU_FA526
 662
 663 config ARCH_MULTI_V4T
 664         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 665         depends on !ARCH_MULTI_V6_V7
 666         select ARCH_MULTI_V4_V5
 667         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 668                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 669                 CPU_ARM925T || CPU_ARM940T)
 670
 671 config ARCH_MULTI_V5
 672         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 673         depends on !ARCH_MULTI_V6_V7
 674         select ARCH_MULTI_V4_V5
 675         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 676                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 677                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 678
 679 config ARCH_MULTI_V4_V5
 680         bool
 681
 682 config ARCH_MULTI_V6
 683         bool "ARMv6 based platforms (ARM11)"
 684         select ARCH_MULTI_V6_V7
 685         select CPU_V6K
 686
 687 config ARCH_MULTI_V7
 688         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 689         default y
 690         select ARCH_MULTI_V6_V7
 691         select CPU_V7
 692         select HAVE_SMP
 693
 694 config ARCH_MULTI_V6_V7
 695         bool
 696         select MIGHT_HAVE_CACHE_L2X0
 697
 698 config ARCH_MULTI_CPU_AUTO
 699         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 700         select ARCH_MULTI_V5
 701
 702 endmenu
 703
 704 config ARCH_VIRT
 705         bool "Dummy Virtual Machine"
 706         depends on ARCH_MULTI_V7
 707         select ARM_AMBA
 708         select ARM_GIC
 709         select ARM_GIC_V2M if PCI
 710         select ARM_GIC_V3
 711         select ARM_GIC_V3_ITS if PCI
 712         select ARM_PSCI
 713         select HAVE_ARM_ARCH_TIMER
 714
 715 #
 716 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 717 # Kconfigs may be included either alphabetically (according to the
 718 # plat- suffix) or along side the corresponding mach-* source.
 719 #
 720 source "arch/arm/mach-mvebu/Kconfig"
 721
 722 source "arch/arm/mach-alpine/Kconfig"
 723
 724 source "arch/arm/mach-artpec/Kconfig"
 725
 726 source "arch/arm/mach-asm9260/Kconfig"
 727
 728 source "arch/arm/mach-at91/Kconfig"
 729
 730 source "arch/arm/mach-axxia/Kconfig"
 731
 732 source "arch/arm/mach-bcm/Kconfig"
 733
 734 source "arch/arm/mach-berlin/Kconfig"
 735
 736 source "arch/arm/mach-clps711x/Kconfig"
 737
 738 source "arch/arm/mach-cns3xxx/Kconfig"
 739
 740 source "arch/arm/mach-davinci/Kconfig"
 741
 742 source "arch/arm/mach-digicolor/Kconfig"
 743
 744 source "arch/arm/mach-dove/Kconfig"
 745
 746 source "arch/arm/mach-ep93xx/Kconfig"
 747
 748 source "arch/arm/mach-footbridge/Kconfig"
 749
 750 source "arch/arm/mach-gemini/Kconfig"
 751
 752 source "arch/arm/mach-highbank/Kconfig"
 753
 754 source "arch/arm/mach-hisi/Kconfig"
 755
 756 source "arch/arm/mach-integrator/Kconfig"
 757
 758 source "arch/arm/mach-iop32x/Kconfig"
 759
 760 source "arch/arm/mach-iop33x/Kconfig"
 761
 762 source "arch/arm/mach-iop13xx/Kconfig"
 763
 764 source "arch/arm/mach-ixp4xx/Kconfig"
 765
 766 source "arch/arm/mach-keystone/Kconfig"
 767
 768 source "arch/arm/mach-ks8695/Kconfig"
 769
 770 source "arch/arm/mach-meson/Kconfig"
 771
 772 source "arch/arm/mach-moxart/Kconfig"
 773
 774 source "arch/arm/mach-aspeed/Kconfig"
 775
 776 source "arch/arm/mach-mv78xx0/Kconfig"
 777
 778 source "arch/arm/mach-imx/Kconfig"
 779
 780 source "arch/arm/mach-mediatek/Kconfig"
 781
 782 source "arch/arm/mach-mxs/Kconfig"
 783
 784 source "arch/arm/mach-netx/Kconfig"
 785
 786 source "arch/arm/mach-nomadik/Kconfig"
 787
 788 source "arch/arm/mach-nspire/Kconfig"
 789
 790 source "arch/arm/plat-omap/Kconfig"
 791
 792 source "arch/arm/mach-omap1/Kconfig"
 793
 794 source "arch/arm/mach-omap2/Kconfig"
 795
 796 source "arch/arm/mach-orion5x/Kconfig"
 797
 798 source "arch/arm/mach-picoxcell/Kconfig"
 799
 800 source "arch/arm/mach-pxa/Kconfig"
 801 source "arch/arm/plat-pxa/Kconfig"
 802
 803 source "arch/arm/mach-mmp/Kconfig"
 804
 805 source "arch/arm/mach-oxnas/Kconfig"
 806
 807 source "arch/arm/mach-qcom/Kconfig"
 808
 809 source "arch/arm/mach-realview/Kconfig"
 810
 811 source "arch/arm/mach-rockchip/Kconfig"
 812
 813 source "arch/arm/mach-sa1100/Kconfig"
 814
 815 source "arch/arm/mach-socfpga/Kconfig"
 816
 817 source "arch/arm/mach-spear/Kconfig"
 818
 819 source "arch/arm/mach-sti/Kconfig"
 820
 821 source "arch/arm/mach-s3c24xx/Kconfig"
 822
 823 source "arch/arm/mach-s3c64xx/Kconfig"
 824
 825 source "arch/arm/mach-s5pv210/Kconfig"
 826
 827 source "arch/arm/mach-exynos/Kconfig"
 828 source "arch/arm/plat-samsung/Kconfig"
 829
 830 source "arch/arm/mach-shmobile/Kconfig"
 831
 832 source "arch/arm/mach-sunxi/Kconfig"
 833
 834 source "arch/arm/mach-prima2/Kconfig"
 835
 836 source "arch/arm/mach-tango/Kconfig"
 837
 838 source "arch/arm/mach-tegra/Kconfig"
 839
 840 source "arch/arm/mach-u300/Kconfig"
 841
 842 source "arch/arm/mach-uniphier/Kconfig"
 843
 844 source "arch/arm/mach-ux500/Kconfig"
 845
 846 source "arch/arm/mach-versatile/Kconfig"
 847
 848 source "arch/arm/mach-vexpress/Kconfig"
 849 source "arch/arm/plat-versatile/Kconfig"
 850
 851 source "arch/arm/mach-vt8500/Kconfig"
 852
 853 source "arch/arm/mach-w90x900/Kconfig"
 854
 855 source "arch/arm/mach-zx/Kconfig"
 856
 857 source "arch/arm/mach-zynq/Kconfig"
 858
 859 # ARMv7-M architecture
 860 config ARCH_EFM32
 861         bool "Energy Micro efm32"
 862         depends on ARM_SINGLE_ARMV7M
 863         select GPIOLIB
 864         help
 865           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 866           processors.
 867
 868 config ARCH_LPC18XX
 869         bool "NXP LPC18xx/LPC43xx"
 870         depends on ARM_SINGLE_ARMV7M
 871         select ARCH_HAS_RESET_CONTROLLER
 872         select ARM_AMBA
 873         select CLKSRC_LPC32XX
 874         select PINCTRL
 875         help
 876           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 877           high performance microcontrollers.
 878
 879 config ARCH_STM32
 880         bool "STMicrolectronics STM32"
 881         depends on ARM_SINGLE_ARMV7M
 882         select ARCH_HAS_RESET_CONTROLLER
 883         select ARMV7M_SYSTICK
 884         select CLKSRC_STM32
 885         select PINCTRL
 886         select RESET_CONTROLLER
 887         select STM32_EXTI
 888         help
 889           Support for STMicroelectronics STM32 processors.
 890
 891 config MACH_STM32F429
 892         bool "STMicrolectronics STM32F429"
 893         depends on ARCH_STM32
 894         default y
 895
 896 config MACH_STM32F746
 897         bool "STMicrolectronics STM32F746"
 898         depends on ARCH_STM32
 899         default y
 900
 901 config ARCH_MPS2
 902         bool "ARM MPS2 platform"
 903         depends on ARM_SINGLE_ARMV7M
 904         select ARM_AMBA
 905         select CLKSRC_MPS2
 906         help
 907           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 908           with a range of available cores like Cortex-M3/M4/M7.
 909
 910           Please, note that depends which Application Note is used memory map
 911           for the platform may vary, so adjustment of RAM base might be needed.
 912
 913 # Definitions to make life easier
 914 config ARCH_ACORN
 915         bool
 916
 917 config PLAT_IOP
 918         bool
 919         select GENERIC_CLOCKEVENTS
 920
 921 config PLAT_ORION
 922         bool
 923         select CLKSRC_MMIO
 924         select COMMON_CLK
 925         select GENERIC_IRQ_CHIP
 926         select IRQ_DOMAIN
 927
 928 config PLAT_ORION_LEGACY
 929         bool
 930         select PLAT_ORION
 931
 932 config PLAT_PXA
 933         bool
 934
 935 config PLAT_VERSATILE
 936         bool
 937
 938 source "arch/arm/firmware/Kconfig"
 939
 940 source arch/arm/mm/Kconfig
 941
 942 config IWMMXT
 943         bool "Enable iWMMXt support"
 944         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 945         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 946         help
 947           Enable support for iWMMXt context switching at run time if
 948           running on a CPU that supports it.
 949
 950 config MULTI_IRQ_HANDLER
 951         bool
 952         help
 953           Allow each machine to specify it's own IRQ handler at run time.
 954
 955 if !MMU
 956 source "arch/arm/Kconfig-nommu"
 957 endif
 958
 959 config PJ4B_ERRATA_4742
 960         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 961         depends on CPU_PJ4B && MACH_ARMADA_370
 962         default y
 963         help
 964           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 965           Event (WFE) IDLE states, a specific timing sensitivity exists between
 966           the retiring WFI/WFE instructions and the newly issued subsequent
 967           instructions.  This sensitivity can result in a CPU hang scenario.
 968           Workaround:
 969           The software must insert either a Data Synchronization Barrier (DSB)
 970           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 971           instruction
 972
 973 config ARM_ERRATA_326103
 974         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 975         depends on CPU_V6
 976         help
 977           Executing a SWP instruction to read-only memory does not set bit 11
 978           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 979           treat the access as a read, preventing a COW from occurring and
 980           causing the faulting task to livelock.
 981
 982 config ARM_ERRATA_411920
 983         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 984         depends on CPU_V6 || CPU_V6K
 985         help
 986           Invalidation of the Instruction Cache operation can
 987           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 988           It does not affect the MPCore. This option enables the ARM Ltd.
 989           recommended workaround.
 990
 991 config ARM_ERRATA_430973
 992         bool "ARM errata: Stale prediction on replaced interworking branch"
 993         depends on CPU_V7
 994         help
 995           This option enables the workaround for the 430973 Cortex-A8
 996           r1p* erratum. If a code sequence containing an ARM/Thumb
 997           interworking branch is replaced with another code sequence at the
 998           same virtual address, whether due to self-modifying code or virtual
 999           to physical address re-mapping, Cortex-A8 does not recover from the
1000           stale interworking branch prediction. This results in Cortex-A8
1001           executing the new code sequence in the incorrect ARM or Thumb state.
1002           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1003           and also flushes the branch target cache at every context switch.
1004           Note that setting specific bits in the ACTLR register may not be
1005           available in non-secure mode.
1006
1007 config ARM_ERRATA_458693
1008         bool "ARM errata: Processor deadlock when a false hazard is created"
1009         depends on CPU_V7
1010         depends on !ARCH_MULTIPLATFORM
1011         help
1012           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1013           erratum. For very specific sequences of memory operations, it is
1014           possible for a hazard condition intended for a cache line to instead
1015           be incorrectly associated with a different cache line. This false
1016           hazard might then cause a processor deadlock. The workaround enables
1017           the L1 caching of the NEON accesses and disables the PLD instruction
1018           in the ACTLR register. Note that setting specific bits in the ACTLR
1019           register may not be available in non-secure mode.
1020
1021 config ARM_ERRATA_460075
1022         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1023         depends on CPU_V7
1024         depends on !ARCH_MULTIPLATFORM
1025         help
1026           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1027           erratum. Any asynchronous access to the L2 cache may encounter a
1028           situation in which recent store transactions to the L2 cache are lost
1029           and overwritten with stale memory contents from external memory. The
1030           workaround disables the write-allocate mode for the L2 cache via the
1031           ACTLR register. Note that setting specific bits in the ACTLR register
1032           may not be available in non-secure mode.
1033
1034 config ARM_ERRATA_742230
1035         bool "ARM errata: DMB operation may be faulty"
1036         depends on CPU_V7 && SMP
1037         depends on !ARCH_MULTIPLATFORM
1038         help
1039           This option enables the workaround for the 742230 Cortex-A9
1040           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1041           between two write operations may not ensure the correct visibility
1042           ordering of the two writes. This workaround sets a specific bit in
1043           the diagnostic register of the Cortex-A9 which causes the DMB
1044           instruction to behave as a DSB, ensuring the correct behaviour of
1045           the two writes.
1046
1047 config ARM_ERRATA_742231
1048         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1049         depends on CPU_V7 && SMP
1050         depends on !ARCH_MULTIPLATFORM
1051         help
1052           This option enables the workaround for the 742231 Cortex-A9
1053           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1054           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1055           accessing some data located in the same cache line, may get corrupted
1056           data due to bad handling of the address hazard when the line gets
1057           replaced from one of the CPUs at the same time as another CPU is
1058           accessing it. This workaround sets specific bits in the diagnostic
1059           register of the Cortex-A9 which reduces the linefill issuing
1060           capabilities of the processor.
1061
1062 config ARM_ERRATA_643719
1063         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1064         depends on CPU_V7 && SMP
1065         default y
1066         help
1067           This option enables the workaround for the 643719 Cortex-A9 (prior to
1068           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1069           register returns zero when it should return one. The workaround
1070           corrects this value, ensuring cache maintenance operations which use
1071           it behave as intended and avoiding data corruption.
1072
1073 config ARM_ERRATA_720789
1074         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1075         depends on CPU_V7
1076         help
1077           This option enables the workaround for the 720789 Cortex-A9 (prior to
1078           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1079           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1080           As a consequence of this erratum, some TLB entries which should be
1081           invalidated are not, resulting in an incoherency in the system page
1082           tables. The workaround changes the TLB flushing routines to invalidate
1083           entries regardless of the ASID.
1084
1085 config ARM_ERRATA_743622
1086         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1087         depends on CPU_V7
1088         depends on !ARCH_MULTIPLATFORM
1089         help
1090           This option enables the workaround for the 743622 Cortex-A9
1091           (r2p*) erratum. Under very rare conditions, a faulty
1092           optimisation in the Cortex-A9 Store Buffer may lead to data
1093           corruption. This workaround sets a specific bit in the diagnostic
1094           register of the Cortex-A9 which disables the Store Buffer
1095           optimisation, preventing the defect from occurring. This has no
1096           visible impact on the overall performance or power consumption of the
1097           processor.
1098
1099 config ARM_ERRATA_751472
1100         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1101         depends on CPU_V7
1102         depends on !ARCH_MULTIPLATFORM
1103         help
1104           This option enables the workaround for the 751472 Cortex-A9 (prior
1105           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1106           completion of a following broadcasted operation if the second
1107           operation is received by a CPU before the ICIALLUIS has completed,
1108           potentially leading to corrupted entries in the cache or TLB.
1109
1110 config ARM_ERRATA_754322
1111         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1112         depends on CPU_V7
1113         help
1114           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1115           r3p*) erratum. A speculative memory access may cause a page table walk
1116           which starts prior to an ASID switch but completes afterwards. This
1117           can populate the micro-TLB with a stale entry which may be hit with
1118           the new ASID. This workaround places two dsb instructions in the mm
1119           switching code so that no page table walks can cross the ASID switch.
1120
1121 config ARM_ERRATA_754327
1122         bool "ARM errata: no automatic Store Buffer drain"
1123         depends on CPU_V7 && SMP
1124         help
1125           This option enables the workaround for the 754327 Cortex-A9 (prior to
1126           r2p0) erratum. The Store Buffer does not have any automatic draining
1127           mechanism and therefore a livelock may occur if an external agent
1128           continuously polls a memory location waiting to observe an update.
1129           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1130           written polling loops from denying visibility of updates to memory.
1131
1132 config ARM_ERRATA_364296
1133         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1134         depends on CPU_V6
1135         help
1136           This options enables the workaround for the 364296 ARM1136
1137           r0p2 erratum (possible cache data corruption with
1138           hit-under-miss enabled). It sets the undocumented bit 31 in
1139           the auxiliary control register and the FI bit in the control
1140           register, thus disabling hit-under-miss without putting the
1141           processor into full low interrupt latency mode. ARM11MPCore
1142           is not affected.
1143
1144 config ARM_ERRATA_764369
1145         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1146         depends on CPU_V7 && SMP
1147         help
1148           This option enables the workaround for erratum 764369
1149           affecting Cortex-A9 MPCore with two or more processors (all
1150           current revisions). Under certain timing circumstances, a data
1151           cache line maintenance operation by MVA targeting an Inner
1152           Shareable memory region may fail to proceed up to either the
1153           Point of Coherency or to the Point of Unification of the
1154           system. This workaround adds a DSB instruction before the
1155           relevant cache maintenance functions and sets a specific bit
1156           in the diagnostic control register of the SCU.
1157
1158 config ARM_ERRATA_775420
1159        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1160        depends on CPU_V7
1161        help
1162          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1163          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1164          operation aborts with MMU exception, it might cause the processor
1165          to deadlock. This workaround puts DSB before executing ISB if
1166          an abort may occur on cache maintenance.
1167
1168 config ARM_ERRATA_798181
1169         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1170         depends on CPU_V7 && SMP
1171         help
1172           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1173           adequately shooting down all use of the old entries. This
1174           option enables the Linux kernel workaround for this erratum
1175           which sends an IPI to the CPUs that are running the same ASID
1176           as the one being invalidated.
1177
1178 config ARM_ERRATA_773022
1179         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1180         depends on CPU_V7
1181         help
1182           This option enables the workaround for the 773022 Cortex-A15
1183           (up to r0p4) erratum. In certain rare sequences of code, the
1184           loop buffer may deliver incorrect instructions. This
1185           workaround disables the loop buffer to avoid the erratum.
1186
1187 config ARM_ERRATA_818325_852422
1188         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1189         depends on CPU_V7
1190         help
1191           This option enables the workaround for:
1192           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1193             instruction might deadlock.  Fixed in r0p1.
1194           - Cortex-A12 852422: Execution of a sequence of instructions might
1195             lead to either a data corruption or a CPU deadlock.  Not fixed in
1196             any Cortex-A12 cores yet.
1197           This workaround for all both errata involves setting bit[12] of the
1198           Feature Register. This bit disables an optimisation applied to a
1199           sequence of 2 instructions that use opposing condition codes.
1200
1201 config ARM_ERRATA_821420
1202         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1203         depends on CPU_V7
1204         help
1205           This option enables the workaround for the 821420 Cortex-A12
1206           (all revs) erratum. In very rare timing conditions, a sequence
1207           of VMOV to Core registers instructions, for which the second
1208           one is in the shadow of a branch or abort, can lead to a
1209           deadlock when the VMOV instructions are issued out-of-order.
1210
1211 config ARM_ERRATA_825619
1212         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1213         depends on CPU_V7
1214         help
1215           This option enables the workaround for the 825619 Cortex-A12
1216           (all revs) erratum. Within rare timing constraints, executing a
1217           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1218           and Device/Strongly-Ordered loads and stores might cause deadlock
1219
1220 config ARM_ERRATA_852421
1221         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1222         depends on CPU_V7
1223         help
1224           This option enables the workaround for the 852421 Cortex-A17
1225           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1226           execution of a DMB ST instruction might fail to properly order
1227           stores from GroupA and stores from GroupB.
1228
1229 config ARM_ERRATA_852423
1230         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1231         depends on CPU_V7
1232         help
1233           This option enables the workaround for:
1234           - Cortex-A17 852423: Execution of a sequence of instructions might
1235             lead to either a data corruption or a CPU deadlock.  Not fixed in
1236             any Cortex-A17 cores yet.
1237           This is identical to Cortex-A12 erratum 852422.  It is a separate
1238           config option from the A12 erratum due to the way errata are checked
1239           for and handled.
1240
1241 endmenu
1242
1243 source "arch/arm/common/Kconfig"
1244
1245 menu "Bus support"
1246
1247 config ISA
1248         bool
1249         help
1250           Find out whether you have ISA slots on your motherboard.  ISA is the
1251           name of a bus system, i.e. the way the CPU talks to the other stuff
1252           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1253           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1254           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1255
1256 # Select ISA DMA controller support
1257 config ISA_DMA
1258         bool
1259         select ISA_DMA_API
1260
1261 # Select ISA DMA interface
1262 config ISA_DMA_API
1263         bool
1264
1265 config PCI
1266         bool "PCI support" if MIGHT_HAVE_PCI
1267         help
1268           Find out whether you have a PCI motherboard. PCI is the name of a
1269           bus system, i.e. the way the CPU talks to the other stuff inside
1270           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1271           VESA. If you have PCI, say Y, otherwise N.
1272
1273 config PCI_DOMAINS
1274         bool
1275         depends on PCI
1276
1277 config PCI_DOMAINS_GENERIC
1278         def_bool PCI_DOMAINS
1279
1280 config PCI_NANOENGINE
1281         bool "BSE nanoEngine PCI support"
1282         depends on SA1100_NANOENGINE
1283         help
1284           Enable PCI on the BSE nanoEngine board.
1285
1286 config PCI_SYSCALL
1287         def_bool PCI
1288
1289 config PCI_HOST_ITE8152
1290         bool
1291         depends on PCI && MACH_ARMCORE
1292         default y
1293         select DMABOUNCE
1294
1295 source "drivers/pci/Kconfig"
1296
1297 source "drivers/pcmcia/Kconfig"
1298
1299 endmenu
1300
1301 menu "Kernel Features"
1302
1303 config HAVE_SMP
1304         bool
1305         help
1306           This option should be selected by machines which have an SMP-
1307           capable CPU.
1308
1309           The only effect of this option is to make the SMP-related
1310           options available to the user for configuration.
1311
1312 config SMP
1313         bool "Symmetric Multi-Processing"
1314         depends on CPU_V6K || CPU_V7
1315         depends on GENERIC_CLOCKEVENTS
1316         depends on HAVE_SMP
1317         depends on MMU || ARM_MPU
1318         select IRQ_WORK
1319         help
1320           This enables support for systems with more than one CPU. If you have
1321           a system with only one CPU, say N. If you have a system with more
1322           than one CPU, say Y.
1323
1324           If you say N here, the kernel will run on uni- and multiprocessor
1325           machines, but will use only one CPU of a multiprocessor machine. If
1326           you say Y here, the kernel will run on many, but not all,
1327           uniprocessor machines. On a uniprocessor machine, the kernel
1328           will run faster if you say N here.
1329
1330           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1331           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1332           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1333
1334           If you don't know what to do here, say N.
1335
1336 config SMP_ON_UP
1337         bool "Allow booting SMP kernel on uniprocessor systems"
1338         depends on SMP && !XIP_KERNEL && MMU
1339         default y
1340         help
1341           SMP kernels contain instructions which fail on non-SMP processors.
1342           Enabling this option allows the kernel to modify itself to make
1343           these instructions safe.  Disabling it allows about 1K of space
1344           savings.
1345
1346           If you don't know what to do here, say Y.
1347
1348 config ARM_CPU_TOPOLOGY
1349         bool "Support cpu topology definition"
1350         depends on SMP && CPU_V7
1351         default y
1352         help
1353           Support ARM cpu topology definition. The MPIDR register defines
1354           affinity between processors which is then used to describe the cpu
1355           topology of an ARM System.
1356
1357 config SCHED_MC
1358         bool "Multi-core scheduler support"
1359         depends on ARM_CPU_TOPOLOGY
1360         help
1361           Multi-core scheduler support improves the CPU scheduler's decision
1362           making when dealing with multi-core CPU chips at a cost of slightly
1363           increased overhead in some places. If unsure say N here.
1364
1365 config SCHED_SMT
1366         bool "SMT scheduler support"
1367         depends on ARM_CPU_TOPOLOGY
1368         help
1369           Improves the CPU scheduler's decision making when dealing with
1370           MultiThreading at a cost of slightly increased overhead in some
1371           places. If unsure say N here.
1372
1373 config HAVE_ARM_SCU
1374         bool
1375         help
1376           This option enables support for the ARM system coherency unit
1377
1378 config HAVE_ARM_ARCH_TIMER
1379         bool "Architected timer support"
1380         depends on CPU_V7
1381         select ARM_ARCH_TIMER
1382         select GENERIC_CLOCKEVENTS
1383         help
1384           This option enables support for the ARM architected timer
1385
1386 config HAVE_ARM_TWD
1387         bool
1388         select CLKSRC_OF if OF
1389         help
1390           This options enables support for the ARM timer and watchdog unit
1391
1392 config MCPM
1393         bool "Multi-Cluster Power Management"
1394         depends on CPU_V7 && SMP
1395         help
1396           This option provides the common power management infrastructure
1397           for (multi-)cluster based systems, such as big.LITTLE based
1398           systems.
1399
1400 config MCPM_QUAD_CLUSTER
1401         bool
1402         depends on MCPM
1403         help
1404           To avoid wasting resources unnecessarily, MCPM only supports up
1405           to 2 clusters by default.
1406           Platforms with 3 or 4 clusters that use MCPM must select this
1407           option to allow the additional clusters to be managed.
1408
1409 config BIG_LITTLE
1410         bool "big.LITTLE support (Experimental)"
1411         depends on CPU_V7 && SMP
1412         select MCPM
1413         help
1414           This option enables support selections for the big.LITTLE
1415           system architecture.
1416
1417 config BL_SWITCHER
1418         bool "big.LITTLE switcher support"
1419         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1420         select CPU_PM
1421         help
1422           The big.LITTLE "switcher" provides the core functionality to
1423           transparently handle transition between a cluster of A15's
1424           and a cluster of A7's in a big.LITTLE system.
1425
1426 config BL_SWITCHER_DUMMY_IF
1427         tristate "Simple big.LITTLE switcher user interface"
1428         depends on BL_SWITCHER && DEBUG_KERNEL
1429         help
1430           This is a simple and dummy char dev interface to control
1431           the big.LITTLE switcher core code.  It is meant for
1432           debugging purposes only.
1433
1434 choice
1435         prompt "Memory split"
1436         depends on MMU
1437         default VMSPLIT_3G
1438         help
1439           Select the desired split between kernel and user memory.
1440
1441           If you are not absolutely sure what you are doing, leave this
1442           option alone!
1443
1444         config VMSPLIT_3G
1445                 bool "3G/1G user/kernel split"
1446         config VMSPLIT_3G_OPT
1447                 bool "3G/1G user/kernel split (for full 1G low memory)"
1448         config VMSPLIT_2G
1449                 bool "2G/2G user/kernel split"
1450         config VMSPLIT_1G
1451                 bool "1G/3G user/kernel split"
1452 endchoice
1453
1454 config PAGE_OFFSET
1455         hex
1456         default PHYS_OFFSET if !MMU
1457         default 0x40000000 if VMSPLIT_1G
1458         default 0x80000000 if VMSPLIT_2G
1459         default 0xB0000000 if VMSPLIT_3G_OPT
1460         default 0xC0000000
1461
1462 config NR_CPUS
1463         int "Maximum number of CPUs (2-32)"
1464         range 2 32
1465         depends on SMP
1466         default "4"
1467
1468 config HOTPLUG_CPU
1469         bool "Support for hot-pluggable CPUs"
1470         depends on SMP
1471         help
1472           Say Y here to experiment with turning CPUs off and on.  CPUs
1473           can be controlled through /sys/devices/system/cpu.
1474
1475 config ARM_PSCI
1476         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1477         depends on HAVE_ARM_SMCCC
1478         select ARM_PSCI_FW
1479         help
1480           Say Y here if you want Linux to communicate with system firmware
1481           implementing the PSCI specification for CPU-centric power
1482           management operations described in ARM document number ARM DEN
1483           0022A ("Power State Coordination Interface System Software on
1484           ARM processors").
1485
1486 # The GPIO number here must be sorted by descending number. In case of
1487 # a multiplatform kernel, we just want the highest value required by the
1488 # selected platforms.
1489 config ARCH_NR_GPIO
1490         int
1491         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1492                 ARCH_ZYNQ
1493         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1494                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1495         default 416 if ARCH_SUNXI
1496         default 392 if ARCH_U8500
1497         default 352 if ARCH_VT8500
1498         default 288 if ARCH_ROCKCHIP
1499         default 264 if MACH_H4700
1500         default 0
1501         help
1502           Maximum number of GPIOs in the system.
1503
1504           If unsure, leave the default value.
1505
1506 source kernel/Kconfig.preempt
1507
1508 config HZ_FIXED
1509         int
1510         default 200 if ARCH_EBSA110
1511         default 128 if SOC_AT91RM9200
1512         default 0
1513
1514 choice
1515         depends on HZ_FIXED = 0
1516         prompt "Timer frequency"
1517
1518 config HZ_100
1519         bool "100 Hz"
1520
1521 config HZ_200
1522         bool "200 Hz"
1523
1524 config HZ_250
1525         bool "250 Hz"
1526
1527 config HZ_300
1528         bool "300 Hz"
1529
1530 config HZ_500
1531         bool "500 Hz"
1532
1533 config HZ_1000
1534         bool "1000 Hz"
1535
1536 endchoice
1537
1538 config HZ
1539         int
1540         default HZ_FIXED if HZ_FIXED != 0
1541         default 100 if HZ_100
1542         default 200 if HZ_200
1543         default 250 if HZ_250
1544         default 300 if HZ_300
1545         default 500 if HZ_500
1546         default 1000
1547
1548 config SCHED_HRTICK
1549         def_bool HIGH_RES_TIMERS
1550
1551 config THUMB2_KERNEL
1552         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1553         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1554         default y if CPU_THUMBONLY
1555         select AEABI
1556         select ARM_ASM_UNIFIED
1557         select ARM_UNWIND
1558         help
1559           By enabling this option, the kernel will be compiled in
1560           Thumb-2 mode. A compiler/assembler that understand the unified
1561           ARM-Thumb syntax is needed.
1562
1563           If unsure, say N.
1564
1565 config THUMB2_AVOID_R_ARM_THM_JUMP11
1566         bool "Work around buggy Thumb-2 short branch relocations in gas"
1567         depends on THUMB2_KERNEL && MODULES
1568         default y
1569         help
1570           Various binutils versions can resolve Thumb-2 branches to
1571           locally-defined, preemptible global symbols as short-range "b.n"
1572           branch instructions.
1573
1574           This is a problem, because there's no guarantee the final
1575           destination of the symbol, or any candidate locations for a
1576           trampoline, are within range of the branch.  For this reason, the
1577           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1578           relocation in modules at all, and it makes little sense to add
1579           support.
1580
1581           The symptom is that the kernel fails with an "unsupported
1582           relocation" error when loading some modules.
1583
1584           Until fixed tools are available, passing
1585           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1586           code which hits this problem, at the cost of a bit of extra runtime
1587           stack usage in some cases.
1588
1589           The problem is described in more detail at:
1590               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1591
1592           Only Thumb-2 kernels are affected.
1593
1594           Unless you are sure your tools don't have this problem, say Y.
1595
1596 config ARM_ASM_UNIFIED
1597         bool
1598
1599 config ARM_PATCH_IDIV
1600         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1601         depends on CPU_32v7 && !XIP_KERNEL
1602         default y
1603         help
1604           The ARM compiler inserts calls to __aeabi_idiv() and
1605           __aeabi_uidiv() when it needs to perform division on signed
1606           and unsigned integers. Some v7 CPUs have support for the sdiv
1607           and udiv instructions that can be used to implement those
1608           functions.
1609
1610           Enabling this option allows the kernel to modify itself to
1611           replace the first two instructions of these library functions
1612           with the sdiv or udiv plus "bx lr" instructions when the CPU
1613           it is running on supports them. Typically this will be faster
1614           and less power intensive than running the original library
1615           code to do integer division.
1616
1617 config AEABI
1618         bool "Use the ARM EABI to compile the kernel"
1619         help
1620           This option allows for the kernel to be compiled using the latest
1621           ARM ABI (aka EABI).  This is only useful if you are using a user
1622           space environment that is also compiled with EABI.
1623
1624           Since there are major incompatibilities between the legacy ABI and
1625           EABI, especially with regard to structure member alignment, this
1626           option also changes the kernel syscall calling convention to
1627           disambiguate both ABIs and allow for backward compatibility support
1628           (selected with CONFIG_OABI_COMPAT).
1629
1630           To use this you need GCC version 4.0.0 or later.
1631
1632 config OABI_COMPAT
1633         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1634         depends on AEABI && !THUMB2_KERNEL
1635         help
1636           This option preserves the old syscall interface along with the
1637           new (ARM EABI) one. It also provides a compatibility layer to
1638           intercept syscalls that have structure arguments which layout
1639           in memory differs between the legacy ABI and the new ARM EABI
1640           (only for non "thumb" binaries). This option adds a tiny
1641           overhead to all syscalls and produces a slightly larger kernel.
1642
1643           The seccomp filter system will not be available when this is
1644           selected, since there is no way yet to sensibly distinguish
1645           between calling conventions during filtering.
1646
1647           If you know you'll be using only pure EABI user space then you
1648           can say N here. If this option is not selected and you attempt
1649           to execute a legacy ABI binary then the result will be
1650           UNPREDICTABLE (in fact it can be predicted that it won't work
1651           at all). If in doubt say N.
1652
1653 config ARCH_HAS_HOLES_MEMORYMODEL
1654         bool
1655
1656 config ARCH_SPARSEMEM_ENABLE
1657         bool
1658
1659 config ARCH_SPARSEMEM_DEFAULT
1660         def_bool ARCH_SPARSEMEM_ENABLE
1661
1662 config ARCH_SELECT_MEMORY_MODEL
1663         def_bool ARCH_SPARSEMEM_ENABLE
1664
1665 config HAVE_ARCH_PFN_VALID
1666         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1667
1668 config HAVE_GENERIC_RCU_GUP
1669         def_bool y
1670         depends on ARM_LPAE
1671
1672 config HIGHMEM
1673         bool "High Memory Support"
1674         depends on MMU
1675         help
1676           The address space of ARM processors is only 4 Gigabytes large
1677           and it has to accommodate user address space, kernel address
1678           space as well as some memory mapped IO. That means that, if you
1679           have a large amount of physical memory and/or IO, not all of the
1680           memory can be "permanently mapped" by the kernel. The physical
1681           memory that is not permanently mapped is called "high memory".
1682
1683           Depending on the selected kernel/user memory split, minimum
1684           vmalloc space and actual amount of RAM, you may not need this
1685           option which should result in a slightly faster kernel.
1686
1687           If unsure, say n.
1688
1689 config HIGHPTE
1690         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1691         depends on HIGHMEM
1692         default y
1693         help
1694           The VM uses one page of physical memory for each page table.
1695           For systems with a lot of processes, this can use a lot of
1696           precious low memory, eventually leading to low memory being
1697           consumed by page tables.  Setting this option will allow
1698           user-space 2nd level page tables to reside in high memory.
1699
1700 config CPU_SW_DOMAIN_PAN
1701         bool "Enable use of CPU domains to implement privileged no-access"
1702         depends on MMU && !ARM_LPAE
1703         default y
1704         help
1705           Increase kernel security by ensuring that normal kernel accesses
1706           are unable to access userspace addresses.  This can help prevent
1707           use-after-free bugs becoming an exploitable privilege escalation
1708           by ensuring that magic values (such as LIST_POISON) will always
1709           fault when dereferenced.
1710
1711           CPUs with low-vector mappings use a best-efforts implementation.
1712           Their lower 1MB needs to remain accessible for the vectors, but
1713           the remainder of userspace will become appropriately inaccessible.
1714
1715 config HW_PERF_EVENTS
1716         def_bool y
1717         depends on ARM_PMU
1718
1719 config SYS_SUPPORTS_HUGETLBFS
1720        def_bool y
1721        depends on ARM_LPAE
1722
1723 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1724        def_bool y
1725        depends on ARM_LPAE
1726
1727 config ARCH_WANT_GENERAL_HUGETLB
1728         def_bool y
1729
1730 config ARM_MODULE_PLTS
1731         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1732         depends on MODULES
1733         help
1734           Allocate PLTs when loading modules so that jumps and calls whose
1735           targets are too far away for their relative offsets to be encoded
1736           in the instructions themselves can be bounced via veneers in the
1737           module's PLT. This allows modules to be allocated in the generic
1738           vmalloc area after the dedicated module memory area has been
1739           exhausted. The modules will use slightly more memory, but after
1740           rounding up to page size, the actual memory footprint is usually
1741           the same.
1742
1743           Say y if you are getting out of memory errors while loading modules
1744
1745 source "mm/Kconfig"
1746
1747 config FORCE_MAX_ZONEORDER
1748         int "Maximum zone order"
1749         default "12" if SOC_AM33XX
1750         default "9" if SA1111 || ARCH_EFM32
1751         default "11"
1752         help
1753           The kernel memory allocator divides physically contiguous memory
1754           blocks into "zones", where each zone is a power of two number of
1755           pages.  This option selects the largest power of two that the kernel
1756           keeps in the memory allocator.  If you need to allocate very large
1757           blocks of physically contiguous memory, then you may need to
1758           increase this value.
1759
1760           This config option is actually maximum order plus one. For example,
1761           a value of 11 means that the largest free memory block is 2^10 pages.
1762
1763 config ALIGNMENT_TRAP
1764         bool
1765         depends on CPU_CP15_MMU
1766         default y if !ARCH_EBSA110
1767         select HAVE_PROC_CPU if PROC_FS
1768         help
1769           ARM processors cannot fetch/store information which is not
1770           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1771           address divisible by 4. On 32-bit ARM processors, these non-aligned
1772           fetch/store instructions will be emulated in software if you say
1773           here, which has a severe performance impact. This is necessary for
1774           correct operation of some network protocols. With an IP-only
1775           configuration it is safe to say N, otherwise say Y.
1776
1777 config UACCESS_WITH_MEMCPY
1778         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1779         depends on MMU
1780         default y if CPU_FEROCEON
1781         help
1782           Implement faster copy_to_user and clear_user methods for CPU
1783           cores where a 8-word STM instruction give significantly higher
1784           memory write throughput than a sequence of individual 32bit stores.
1785
1786           A possible side effect is a slight increase in scheduling latency
1787           between threads sharing the same address space if they invoke
1788           such copy operations with large buffers.
1789
1790           However, if the CPU data cache is using a write-allocate mode,
1791           this option is unlikely to provide any performance gain.
1792
1793 config SECCOMP
1794         bool
1795         prompt "Enable seccomp to safely compute untrusted bytecode"
1796         ---help---
1797           This kernel feature is useful for number crunching applications
1798           that may need to compute untrusted bytecode during their
1799           execution. By using pipes or other transports made available to
1800           the process as file descriptors supporting the read/write
1801           syscalls, it's possible to isolate those applications in
1802           their own address space using seccomp. Once seccomp is
1803           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1804           and the task is only allowed to execute a few safe syscalls
1805           defined by each seccomp mode.
1806
1807 config SWIOTLB
1808         def_bool y
1809
1810 config IOMMU_HELPER
1811         def_bool SWIOTLB
1812
1813 config PARAVIRT
1814         bool "Enable paravirtualization code"
1815         help
1816           This changes the kernel so it can modify itself when it is run
1817           under a hypervisor, potentially improving performance significantly
1818           over full virtualization.
1819
1820 config PARAVIRT_TIME_ACCOUNTING
1821         bool "Paravirtual steal time accounting"
1822         select PARAVIRT
1823         default n
1824         help
1825           Select this option to enable fine granularity task steal time
1826           accounting. Time spent executing other tasks in parallel with
1827           the current vCPU is discounted from the vCPU power. To account for
1828           that, there can be a small performance impact.
1829
1830           If in doubt, say N here.
1831
1832 config XEN_DOM0
1833         def_bool y
1834         depends on XEN
1835
1836 config XEN
1837         bool "Xen guest support on ARM"
1838         depends on ARM && AEABI && OF
1839         depends on CPU_V7 && !CPU_V6
1840         depends on !GENERIC_ATOMIC64
1841         depends on MMU
1842         select ARCH_DMA_ADDR_T_64BIT
1843         select ARM_PSCI
1844         select SWIOTLB_XEN
1845         select PARAVIRT
1846         help
1847           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1848
1849 endmenu
1850
1851 menu "Boot options"
1852
1853 config USE_OF
1854         bool "Flattened Device Tree support"
1855         select IRQ_DOMAIN
1856         select OF
1857         help
1858           Include support for flattened device tree machine descriptions.
1859
1860 config ATAGS
1861         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1862         default y
1863         help
1864           This is the traditional way of passing data to the kernel at boot
1865           time. If you are solely relying on the flattened device tree (or
1866           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1867           to remove ATAGS support from your kernel binary.  If unsure,
1868           leave this to y.
1869
1870 config DEPRECATED_PARAM_STRUCT
1871         bool "Provide old way to pass kernel parameters"
1872         depends on ATAGS
1873         help
1874           This was deprecated in 2001 and announced to live on for 5 years.
1875           Some old boot loaders still use this way.
1876
1877 # Compressed boot loader in ROM.  Yes, we really want to ask about
1878 # TEXT and BSS so we preserve their values in the config files.
1879 config ZBOOT_ROM_TEXT
1880         hex "Compressed ROM boot loader base address"
1881         default "0"
1882         help
1883           The physical address at which the ROM-able zImage is to be
1884           placed in the target.  Platforms which normally make use of
1885           ROM-able zImage formats normally set this to a suitable
1886           value in their defconfig file.
1887
1888           If ZBOOT_ROM is not enabled, this has no effect.
1889
1890 config ZBOOT_ROM_BSS
1891         hex "Compressed ROM boot loader BSS address"
1892         default "0"
1893         help
1894           The base address of an area of read/write memory in the target
1895           for the ROM-able zImage which must be available while the
1896           decompressor is running. It must be large enough to hold the
1897           entire decompressed kernel plus an additional 128 KiB.
1898           Platforms which normally make use of ROM-able zImage formats
1899           normally set this to a suitable value in their defconfig file.
1900
1901           If ZBOOT_ROM is not enabled, this has no effect.
1902
1903 config ZBOOT_ROM
1904         bool "Compressed boot loader in ROM/flash"
1905         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1906         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1907         help
1908           Say Y here if you intend to execute your compressed kernel image
1909           (zImage) directly from ROM or flash.  If unsure, say N.
1910
1911 config ARM_APPENDED_DTB
1912         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1913         depends on OF
1914         help
1915           With this option, the boot code will look for a device tree binary
1916           (DTB) appended to zImage
1917           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1918
1919           This is meant as a backward compatibility convenience for those
1920           systems with a bootloader that can't be upgraded to accommodate
1921           the documented boot protocol using a device tree.
1922
1923           Beware that there is very little in terms of protection against
1924           this option being confused by leftover garbage in memory that might
1925           look like a DTB header after a reboot if no actual DTB is appended
1926           to zImage.  Do not leave this option active in a production kernel
1927           if you don't intend to always append a DTB.  Proper passing of the
1928           location into r2 of a bootloader provided DTB is always preferable
1929           to this option.
1930
1931 config ARM_ATAG_DTB_COMPAT
1932         bool "Supplement the appended DTB with traditional ATAG information"
1933         depends on ARM_APPENDED_DTB
1934         help
1935           Some old bootloaders can't be updated to a DTB capable one, yet
1936           they provide ATAGs with memory configuration, the ramdisk address,
1937           the kernel cmdline string, etc.  Such information is dynamically
1938           provided by the bootloader and can't always be stored in a static
1939           DTB.  To allow a device tree enabled kernel to be used with such
1940           bootloaders, this option allows zImage to extract the information
1941           from the ATAG list and store it at run time into the appended DTB.
1942
1943 choice
1944         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1945         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1946
1947 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1948         bool "Use bootloader kernel arguments if available"
1949         help
1950           Uses the command-line options passed by the boot loader instead of
1951           the device tree bootargs property. If the boot loader doesn't provide
1952           any, the device tree bootargs property will be used.
1953
1954 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1955         bool "Extend with bootloader kernel arguments"
1956         help
1957           The command-line arguments provided by the boot loader will be
1958           appended to the the device tree bootargs property.
1959
1960 endchoice
1961
1962 config CMDLINE
1963         string "Default kernel command string"
1964         default ""
1965         help
1966           On some architectures (EBSA110 and CATS), there is currently no way
1967           for the boot loader to pass arguments to the kernel. For these
1968           architectures, you should supply some command-line options at build
1969           time by entering them here. As a minimum, you should specify the
1970           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1971
1972 choice
1973         prompt "Kernel command line type" if CMDLINE != ""
1974         default CMDLINE_FROM_BOOTLOADER
1975         depends on ATAGS
1976
1977 config CMDLINE_FROM_BOOTLOADER
1978         bool "Use bootloader kernel arguments if available"
1979         help
1980           Uses the command-line options passed by the boot loader. If
1981           the boot loader doesn't provide any, the default kernel command
1982           string provided in CMDLINE will be used.
1983
1984 config CMDLINE_EXTEND
1985         bool "Extend bootloader kernel arguments"
1986         help
1987           The command-line arguments provided by the boot loader will be
1988           appended to the default kernel command string.
1989
1990 config CMDLINE_FORCE
1991         bool "Always use the default kernel command string"
1992         help
1993           Always use the default kernel command string, even if the boot
1994           loader passes other arguments to the kernel.
1995           This is useful if you cannot or don't want to change the
1996           command-line options your boot loader passes to the kernel.
1997 endchoice
1998
1999 config XIP_KERNEL
2000         bool "Kernel Execute-In-Place from ROM"
2001         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2002         help
2003           Execute-In-Place allows the kernel to run from non-volatile storage
2004           directly addressable by the CPU, such as NOR flash. This saves RAM
2005           space since the text section of the kernel is not loaded from flash
2006           to RAM.  Read-write sections, such as the data section and stack,
2007           are still copied to RAM.  The XIP kernel is not compressed since
2008           it has to run directly from flash, so it will take more space to
2009           store it.  The flash address used to link the kernel object files,
2010           and for storing it, is configuration dependent. Therefore, if you
2011           say Y here, you must know the proper physical address where to
2012           store the kernel image depending on your own flash memory usage.
2013
2014           Also note that the make target becomes "make xipImage" rather than
2015           "make zImage" or "make Image".  The final kernel binary to put in
2016           ROM memory will be arch/arm/boot/xipImage.
2017
2018           If unsure, say N.
2019
2020 config XIP_PHYS_ADDR
2021         hex "XIP Kernel Physical Location"
2022         depends on XIP_KERNEL
2023         default "0x00080000"
2024         help
2025           This is the physical address in your flash memory the kernel will
2026           be linked for and stored to.  This address is dependent on your
2027           own flash usage.
2028
2029 config KEXEC
2030         bool "Kexec system call (EXPERIMENTAL)"
2031         depends on (!SMP || PM_SLEEP_SMP)
2032         depends on !CPU_V7M
2033         select KEXEC_CORE
2034         help
2035           kexec is a system call that implements the ability to shutdown your
2036           current kernel, and to start another kernel.  It is like a reboot
2037           but it is independent of the system firmware.   And like a reboot
2038           you can start any kernel with it, not just Linux.
2039
2040           It is an ongoing process to be certain the hardware in a machine
2041           is properly shutdown, so do not be surprised if this code does not
2042           initially work for you.
2043
2044 config ATAGS_PROC
2045         bool "Export atags in procfs"
2046         depends on ATAGS && KEXEC
2047         default y
2048         help
2049           Should the atags used to boot the kernel be exported in an "atags"
2050           file in procfs. Useful with kexec.
2051
2052 config CRASH_DUMP
2053         bool "Build kdump crash kernel (EXPERIMENTAL)"
2054         help
2055           Generate crash dump after being started by kexec. This should
2056           be normally only set in special crash dump kernels which are
2057           loaded in the main kernel with kexec-tools into a specially
2058           reserved region and then later executed after a crash by
2059           kdump/kexec. The crash dump kernel must be compiled to a
2060           memory address not used by the main kernel
2061
2062           For more details see Documentation/kdump/kdump.txt
2063
2064 config AUTO_ZRELADDR
2065         bool "Auto calculation of the decompressed kernel image address"
2066         help
2067           ZRELADDR is the physical address where the decompressed kernel
2068           image will be placed. If AUTO_ZRELADDR is selected, the address
2069           will be determined at run-time by masking the current IP with
2070           0xf8000000. This assumes the zImage being placed in the first 128MB
2071           from start of memory.
2072
2073 config EFI_STUB
2074         bool
2075
2076 config EFI
2077         bool "UEFI runtime support"
2078         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2079         select UCS2_STRING
2080         select EFI_PARAMS_FROM_FDT
2081         select EFI_STUB
2082         select EFI_ARMSTUB
2083         select EFI_RUNTIME_WRAPPERS
2084         ---help---
2085           This option provides support for runtime services provided
2086           by UEFI firmware (such as non-volatile variables, realtime
2087           clock, and platform reset). A UEFI stub is also provided to
2088           allow the kernel to be booted as an EFI application. This
2089           is only useful for kernels that may run on systems that have
2090           UEFI firmware.
2091
2092 endmenu
2093
2094 menu "CPU Power Management"
2095
2096 source "drivers/cpufreq/Kconfig"
2097
2098 source "drivers/cpuidle/Kconfig"
2099
2100 endmenu
2101
2102 menu "Floating point emulation"
2103
2104 comment "At least one emulation must be selected"
2105
2106 config FPE_NWFPE
2107         bool "NWFPE math emulation"
2108         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2109         ---help---
2110           Say Y to include the NWFPE floating point emulator in the kernel.
2111           This is necessary to run most binaries. Linux does not currently
2112           support floating point hardware so you need to say Y here even if
2113           your machine has an FPA or floating point co-processor podule.
2114
2115           You may say N here if you are going to load the Acorn FPEmulator
2116           early in the bootup.
2117
2118 config FPE_NWFPE_XP
2119         bool "Support extended precision"
2120         depends on FPE_NWFPE
2121         help
2122           Say Y to include 80-bit support in the kernel floating-point
2123           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2124           Note that gcc does not generate 80-bit operations by default,
2125           so in most cases this option only enlarges the size of the
2126           floating point emulator without any good reason.
2127
2128           You almost surely want to say N here.
2129
2130 config FPE_FASTFPE
2131         bool "FastFPE math emulation (EXPERIMENTAL)"
2132         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2133         ---help---
2134           Say Y here to include the FAST floating point emulator in the kernel.
2135           This is an experimental much faster emulator which now also has full
2136           precision for the mantissa.  It does not support any exceptions.
2137           It is very simple, and approximately 3-6 times faster than NWFPE.
2138
2139           It should be sufficient for most programs.  It may be not suitable
2140           for scientific calculations, but you have to check this for yourself.
2141           If you do not feel you need a faster FP emulation you should better
2142           choose NWFPE.
2143
2144 config VFP
2145         bool "VFP-format floating point maths"
2146         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2147         help
2148           Say Y to include VFP support code in the kernel. This is needed
2149           if your hardware includes a VFP unit.
2150
2151           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2152           release notes and additional status information.
2153
2154           Say N if your target does not have VFP hardware.
2155
2156 config VFPv3
2157         bool
2158         depends on VFP
2159         default y if CPU_V7
2160
2161 config NEON
2162         bool "Advanced SIMD (NEON) Extension support"
2163         depends on VFPv3 && CPU_V7
2164         help
2165           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2166           Extension.
2167
2168 config KERNEL_MODE_NEON
2169         bool "Support for NEON in kernel mode"
2170         depends on NEON && AEABI
2171         help
2172           Say Y to include support for NEON in kernel mode.
2173
2174 endmenu
2175
2176 menu "Userspace binary formats"
2177
2178 source "fs/Kconfig.binfmt"
2179
2180 endmenu
2181
2182 menu "Power management options"
2183
2184 source "kernel/power/Kconfig"
2185
2186 config ARCH_SUSPEND_POSSIBLE
2187         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2188                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2189         def_bool y
2190
2191 config ARM_CPU_SUSPEND
2192         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2193         depends on ARCH_SUSPEND_POSSIBLE
2194
2195 config ARCH_HIBERNATION_POSSIBLE
2196         bool
2197         depends on MMU
2198         default y if ARCH_SUSPEND_POSSIBLE
2199
2200 endmenu
2201
2202 source "net/Kconfig"
2203
2204 source "drivers/Kconfig"
2205
2206 source "drivers/firmware/Kconfig"
2207
2208 source "fs/Kconfig"
2209
2210 source "arch/arm/Kconfig.debug"
2211
2212 source "security/Kconfig"
2213
2214 source "crypto/Kconfig"
2215 if CRYPTO
2216 source "arch/arm/crypto/Kconfig"
2217 endif
2218
2219 source "lib/Kconfig"
2220
2221 source "arch/arm/kvm/Kconfig"