4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
32 select HAVE_ARCH_TRACEHOOK
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_CONTEXT_TRACKING
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DMA_API_DEBUG
40 select HAVE_DMA_CONTIGUOUS if MMU
41 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
42 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
43 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
44 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
45 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
46 select HAVE_GENERIC_DMA_COHERENT
47 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
48 select HAVE_IDE if PCI || ISA || PCMCIA
49 select HAVE_IRQ_TIME_ACCOUNTING
50 select HAVE_KERNEL_GZIP
51 select HAVE_KERNEL_LZ4
52 select HAVE_KERNEL_LZMA
53 select HAVE_KERNEL_LZO
55 select HAVE_KPROBES if !XIP_KERNEL
56 select HAVE_KRETPROBES if (HAVE_KPROBES)
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
86 select ARCH_HAS_SG_CHAIN
89 config NEED_SG_DMA_LENGTH
92 config ARM_DMA_USE_IOMMU
94 select ARM_HAS_SG_CHAIN
95 select NEED_SG_DMA_LENGTH
99 config ARM_DMA_IOMMU_ALIGNMENT
100 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
104 DMA mapping framework by default aligns all buffers to the smallest
105 PAGE_SIZE order which is greater than or equal to the requested buffer
106 size. This works well for buffers up to a few hundreds kilobytes, but
107 for larger buffers it just a waste of address space. Drivers which has
108 relatively small addressing window (like 64Mib) might run out of
109 virtual space with just a few allocations.
111 With this parameter you can specify the maximum PAGE_SIZE order for
112 DMA IOMMU buffers. Larger buffers will be aligned only to this
113 specified order. The order is expressed as a power of two multiplied
118 config MIGHT_HAVE_PCI
121 config SYS_SUPPORTS_APM_EMULATION
126 select GENERIC_ALLOCATOR
137 The Extended Industry Standard Architecture (EISA) bus was
138 developed as an open alternative to the IBM MicroChannel bus.
140 The EISA bus provided some of the features of the IBM MicroChannel
141 bus while maintaining backward compatibility with cards made for
142 the older ISA bus. The EISA bus saw limited use between 1988 and
143 1995 when it was made obsolete by the PCI bus.
145 Say Y here if you are building a kernel for an EISA-based machine.
152 config STACKTRACE_SUPPORT
156 config HAVE_LATENCYTOP_SUPPORT
161 config LOCKDEP_SUPPORT
165 config TRACE_IRQFLAGS_SUPPORT
169 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_BANDGAP
182 config GENERIC_HWEIGHT
186 config GENERIC_CALIBRATE_DELAY
190 config ARCH_MAY_HAVE_PC_FDC
196 config NEED_DMA_MAP_STATE
199 config ARCH_SUPPORTS_UPROBES
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
205 config GENERIC_ISA_DMA
211 config NEED_RET_TO_USER
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
223 The base address of exception vectors. This must be two pages
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_GPIO_H
246 Select this when mach/gpio.h is required to provide special
247 definitions for this platform. The need for mach/gpio.h should
248 be avoided when possible.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT
267 default DRAM_BASE if !MMU
268 default 0x00000000 if ARCH_EBSA110 || \
269 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
274 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276 default 0x20000000 if ARCH_S5PV210
277 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
278 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
279 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
280 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
281 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 source "init/Kconfig"
292 source "kernel/Kconfig.freezer"
297 bool "MMU-based Paged Memory Management Support"
300 Select if you want MMU-based virtualised addressing space
301 support by paged memory management. If unsure, say 'Y'.
304 # The "ARM system type" choice list is ordered alphabetically by option
305 # text. Please add new entries in the option alphabetic order.
308 prompt "ARM system type"
309 default ARCH_VERSATILE if !MMU
310 default ARCH_MULTIPLATFORM if MMU
312 config ARCH_MULTIPLATFORM
313 bool "Allow multiple platforms to be selected"
315 select ARCH_WANT_OPTIONAL_GPIOLIB
316 select ARM_HAS_SG_CHAIN
317 select ARM_PATCH_PHYS_VIRT
321 select GENERIC_CLOCKEVENTS
322 select MIGHT_HAVE_PCI
323 select MULTI_IRQ_HANDLER
327 config ARCH_INTEGRATOR
328 bool "ARM Ltd. Integrator family"
330 select ARM_PATCH_PHYS_VIRT if MMU
333 select COMMON_CLK_VERSATILE
334 select GENERIC_CLOCKEVENTS
337 select MULTI_IRQ_HANDLER
338 select NEED_MACH_MEMORY_H
339 select PLAT_VERSATILE
342 select VERSATILE_FPGA_IRQ
344 Support for ARM's Integrator platform.
347 bool "ARM Ltd. RealView family"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_TIMER_SP804
352 select COMMON_CLK_VERSATILE
353 select GENERIC_CLOCKEVENTS
354 select GPIO_PL061 if GPIOLIB
356 select NEED_MACH_MEMORY_H
357 select PLAT_VERSATILE
358 select PLAT_VERSATILE_CLCD
360 This enables support for ARM Ltd RealView boards.
362 config ARCH_VERSATILE
363 bool "ARM Ltd. Versatile family"
364 select ARCH_WANT_OPTIONAL_GPIOLIB
366 select ARM_TIMER_SP804
369 select GENERIC_CLOCKEVENTS
370 select HAVE_MACH_CLKDEV
372 select PLAT_VERSATILE
373 select PLAT_VERSATILE_CLCD
374 select PLAT_VERSATILE_CLOCK
375 select VERSATILE_FPGA_IRQ
377 This enables support for ARM Ltd Versatile board.
381 select ARCH_REQUIRE_GPIOLIB
384 select NEED_MACH_IO_H if PCCARD
386 select PINCTRL_AT91 if USE_OF
388 This enables support for systems based on Atmel
389 AT91RM9200 and AT91SAM9* processors.
392 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
393 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_CLOCKEVENTS
401 Support for Cirrus Logic 711x/721x/731x based boards.
404 bool "Cortina Systems Gemini"
405 select ARCH_REQUIRE_GPIOLIB
408 select GENERIC_CLOCKEVENTS
410 Support for the Cortina Systems Gemini family SoCs
414 select ARCH_USES_GETTIMEOFFSET
417 select NEED_MACH_IO_H
418 select NEED_MACH_MEMORY_H
421 This is an evaluation board for the StrongARM processor available
422 from Digital. It has limited hardware on-board, including an
423 Ethernet interface, two PCMCIA sockets, two serial ports and a
427 bool "Energy Micro efm32"
429 select ARCH_REQUIRE_GPIOLIB
435 select GENERIC_CLOCKEVENTS
441 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
446 select ARCH_HAS_HOLES_MEMORYMODEL
447 select ARCH_REQUIRE_GPIOLIB
448 select ARCH_USES_GETTIMEOFFSET
454 This enables support for the Cirrus EP93xx series of CPUs.
456 config ARCH_FOOTBRIDGE
460 select GENERIC_CLOCKEVENTS
462 select NEED_MACH_IO_H if !MMU
463 select NEED_MACH_MEMORY_H
465 Support for systems based on the DC21285 companion chip
466 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
469 bool "Hilscher NetX based"
473 select GENERIC_CLOCKEVENTS
475 This enables support for systems based on the Hilscher NetX Soc
481 select NEED_MACH_MEMORY_H
482 select NEED_RET_TO_USER
488 Support for Intel's IOP13XX (XScale) family of processors.
493 select ARCH_REQUIRE_GPIOLIB
496 select NEED_RET_TO_USER
500 Support for Intel's 80219 and IOP32X (XScale) family of
506 select ARCH_REQUIRE_GPIOLIB
509 select NEED_RET_TO_USER
513 Support for Intel's IOP33X (XScale) family of processors.
518 select ARCH_HAS_DMA_SET_COHERENT_MASK
519 select ARCH_REQUIRE_GPIOLIB
520 select ARCH_SUPPORTS_BIG_ENDIAN
523 select DMABOUNCE if PCI
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
526 select NEED_MACH_IO_H
527 select USB_EHCI_BIG_ENDIAN_DESC
528 select USB_EHCI_BIG_ENDIAN_MMIO
530 Support for Intel's IXP4XX (XScale) family of processors.
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
537 select MIGHT_HAVE_PCI
541 select PLAT_ORION_LEGACY
543 Support for the Marvell Dove SoC 88AP510
546 bool "Marvell Kirkwood"
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
554 select PINCTRL_KIRKWOOD
555 select PLAT_ORION_LEGACY
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
561 bool "Marvell MV78xx0"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
567 select PLAT_ORION_LEGACY
569 Support for the following Marvell MV78xx0 series SoCs:
575 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
580 select PLAT_ORION_LEGACY
582 Support for the following Marvell Orion 5x series SoCs:
583 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
584 Orion-2 (5281), Orion-1-90 (6183).
587 bool "Marvell PXA168/910/MMP2"
589 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_ALLOCATOR
592 select GENERIC_CLOCKEVENTS
595 select MULTI_IRQ_HANDLER
600 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
603 bool "Micrel/Kendin KS8695"
604 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
608 select NEED_MACH_MEMORY_H
610 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
611 System-on-Chip devices.
614 bool "Nuvoton W90X900 CPU"
615 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
621 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
622 At present, the w90x900 has been renamed nuc900, regarding
623 the ARM series product line, you can login the following
624 link address to know more.
626 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
627 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
631 select ARCH_REQUIRE_GPIOLIB
636 select GENERIC_CLOCKEVENTS
640 Support for the NXP LPC32XX family of processors
643 bool "PXA2xx/PXA3xx-based"
646 select ARCH_REQUIRE_GPIOLIB
647 select ARM_CPU_SUSPEND if PM
652 select GENERIC_CLOCKEVENTS
655 select MULTI_IRQ_HANDLER
659 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
662 bool "Qualcomm MSM (non-multiplatform)"
663 select ARCH_REQUIRE_GPIOLIB
665 select GENERIC_CLOCKEVENTS
667 Support for Qualcomm MSM/QSD based systems. This runs on the
668 apps processor of the MSM/QSD and depends on a shared memory
669 interface to the modem processor which runs the baseband
670 stack and controls some vital subsystems
671 (clock and power control, etc).
673 config ARCH_SHMOBILE_LEGACY
674 bool "Renesas ARM SoCs (non-multiplatform)"
676 select ARM_PATCH_PHYS_VIRT if MMU
678 select GENERIC_CLOCKEVENTS
679 select HAVE_ARM_SCU if SMP
680 select HAVE_ARM_TWD if SMP
681 select HAVE_MACH_CLKDEV
683 select MIGHT_HAVE_CACHE_L2X0
684 select MULTI_IRQ_HANDLER
687 select PM_GENERIC_DOMAINS if PM
690 Support for Renesas ARM SoC platforms using a non-multiplatform
691 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
697 select ARCH_MAY_HAVE_PC_FDC
698 select ARCH_SPARSEMEM_ENABLE
699 select ARCH_USES_GETTIMEOFFSET
703 select HAVE_PATA_PLATFORM
705 select NEED_MACH_IO_H
706 select NEED_MACH_MEMORY_H
710 On the Acorn Risc-PC, Linux can support the internal IDE disk and
711 CD-ROM interface, serial and parallel port, and the floppy drive.
716 select ARCH_REQUIRE_GPIOLIB
717 select ARCH_SPARSEMEM_ENABLE
722 select GENERIC_CLOCKEVENTS
725 select NEED_MACH_MEMORY_H
728 Support for StrongARM 11x0 based boards.
731 bool "Samsung S3C24XX SoCs"
732 select ARCH_REQUIRE_GPIOLIB
735 select CLKSRC_SAMSUNG_PWM
736 select GENERIC_CLOCKEVENTS
738 select HAVE_S3C2410_I2C if I2C
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
740 select HAVE_S3C_RTC if RTC_CLASS
741 select MULTI_IRQ_HANDLER
742 select NEED_MACH_IO_H
745 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
746 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
747 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
748 Samsung SMDK2410 development board (and derivatives).
751 bool "Samsung S3C64XX"
752 select ARCH_REQUIRE_GPIOLIB
757 select CLKSRC_SAMSUNG_PWM
758 select COMMON_CLK_SAMSUNG
760 select GENERIC_CLOCKEVENTS
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
767 select PM_GENERIC_DOMAINS if PM
769 select S3C_GPIO_TRACK
771 select SAMSUNG_WAKEMASK
772 select SAMSUNG_WDT_RESET
774 Samsung S3C64XX series based systems
777 bool "Samsung S5P6440 S5P6450"
780 select CLKSRC_SAMSUNG_PWM
782 select GENERIC_CLOCKEVENTS
784 select HAVE_S3C2410_I2C if I2C
785 select HAVE_S3C2410_WATCHDOG if WATCHDOG
786 select HAVE_S3C_RTC if RTC_CLASS
787 select NEED_MACH_GPIO_H
789 select SAMSUNG_WDT_RESET
791 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
795 bool "Samsung S5PC100"
796 select ARCH_REQUIRE_GPIOLIB
799 select CLKSRC_SAMSUNG_PWM
801 select GENERIC_CLOCKEVENTS
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select HAVE_S3C_RTC if RTC_CLASS
806 select NEED_MACH_GPIO_H
808 select SAMSUNG_WDT_RESET
810 Samsung S5PC100 series based systems
813 bool "Samsung S5PV210/S5PC110"
814 select ARCH_HAS_HOLES_MEMORYMODEL
815 select ARCH_SPARSEMEM_ENABLE
818 select CLKSRC_SAMSUNG_PWM
820 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select HAVE_S3C_RTC if RTC_CLASS
825 select NEED_MACH_GPIO_H
826 select NEED_MACH_MEMORY_H
829 Samsung S5PV210/S5PC110 series based systems
833 select ARCH_HAS_HOLES_MEMORYMODEL
834 select ARCH_REQUIRE_GPIOLIB
836 select GENERIC_ALLOCATOR
837 select GENERIC_CLOCKEVENTS
838 select GENERIC_IRQ_CHIP
844 Support for TI's DaVinci platform.
849 select ARCH_HAS_HOLES_MEMORYMODEL
851 select ARCH_REQUIRE_GPIOLIB
854 select GENERIC_CLOCKEVENTS
855 select GENERIC_IRQ_CHIP
858 select NEED_MACH_IO_H if PCCARD
859 select NEED_MACH_MEMORY_H
861 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
865 menu "Multiple platform selection"
866 depends on ARCH_MULTIPLATFORM
868 comment "CPU Core family selection"
871 bool "ARMv4 based platforms (FA526)"
872 depends on !ARCH_MULTI_V6_V7
873 select ARCH_MULTI_V4_V5
876 config ARCH_MULTI_V4T
877 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
878 depends on !ARCH_MULTI_V6_V7
879 select ARCH_MULTI_V4_V5
880 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
881 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
882 CPU_ARM925T || CPU_ARM940T)
885 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
888 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
889 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
890 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
892 config ARCH_MULTI_V4_V5
896 bool "ARMv6 based platforms (ARM11)"
897 select ARCH_MULTI_V6_V7
901 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
903 select ARCH_MULTI_V6_V7
907 config ARCH_MULTI_V6_V7
909 select MIGHT_HAVE_CACHE_L2X0
911 config ARCH_MULTI_CPU_AUTO
912 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
918 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
922 select HAVE_ARM_ARCH_TIMER
925 # This is sorted alphabetically by mach-* pathname. However, plat-*
926 # Kconfigs may be included either alphabetically (according to the
927 # plat- suffix) or along side the corresponding mach-* source.
929 source "arch/arm/mach-mvebu/Kconfig"
931 source "arch/arm/mach-at91/Kconfig"
933 source "arch/arm/mach-axxia/Kconfig"
935 source "arch/arm/mach-bcm/Kconfig"
937 source "arch/arm/mach-berlin/Kconfig"
939 source "arch/arm/mach-clps711x/Kconfig"
941 source "arch/arm/mach-cns3xxx/Kconfig"
943 source "arch/arm/mach-davinci/Kconfig"
945 source "arch/arm/mach-dove/Kconfig"
947 source "arch/arm/mach-ep93xx/Kconfig"
949 source "arch/arm/mach-footbridge/Kconfig"
951 source "arch/arm/mach-gemini/Kconfig"
953 source "arch/arm/mach-highbank/Kconfig"
955 source "arch/arm/mach-hisi/Kconfig"
957 source "arch/arm/mach-integrator/Kconfig"
959 source "arch/arm/mach-iop32x/Kconfig"
961 source "arch/arm/mach-iop33x/Kconfig"
963 source "arch/arm/mach-iop13xx/Kconfig"
965 source "arch/arm/mach-ixp4xx/Kconfig"
967 source "arch/arm/mach-keystone/Kconfig"
969 source "arch/arm/mach-kirkwood/Kconfig"
971 source "arch/arm/mach-ks8695/Kconfig"
973 source "arch/arm/mach-msm/Kconfig"
975 source "arch/arm/mach-moxart/Kconfig"
977 source "arch/arm/mach-mv78xx0/Kconfig"
979 source "arch/arm/mach-imx/Kconfig"
981 source "arch/arm/mach-mxs/Kconfig"
983 source "arch/arm/mach-netx/Kconfig"
985 source "arch/arm/mach-nomadik/Kconfig"
987 source "arch/arm/mach-nspire/Kconfig"
989 source "arch/arm/plat-omap/Kconfig"
991 source "arch/arm/mach-omap1/Kconfig"
993 source "arch/arm/mach-omap2/Kconfig"
995 source "arch/arm/mach-orion5x/Kconfig"
997 source "arch/arm/mach-picoxcell/Kconfig"
999 source "arch/arm/mach-pxa/Kconfig"
1000 source "arch/arm/plat-pxa/Kconfig"
1002 source "arch/arm/mach-mmp/Kconfig"
1004 source "arch/arm/mach-qcom/Kconfig"
1006 source "arch/arm/mach-realview/Kconfig"
1008 source "arch/arm/mach-rockchip/Kconfig"
1010 source "arch/arm/mach-sa1100/Kconfig"
1012 source "arch/arm/mach-socfpga/Kconfig"
1014 source "arch/arm/mach-spear/Kconfig"
1016 source "arch/arm/mach-sti/Kconfig"
1018 source "arch/arm/mach-s3c24xx/Kconfig"
1020 source "arch/arm/mach-s3c64xx/Kconfig"
1022 source "arch/arm/mach-s5p64x0/Kconfig"
1024 source "arch/arm/mach-s5pc100/Kconfig"
1026 source "arch/arm/mach-s5pv210/Kconfig"
1028 source "arch/arm/mach-exynos/Kconfig"
1029 source "arch/arm/plat-samsung/Kconfig"
1031 source "arch/arm/mach-shmobile/Kconfig"
1033 source "arch/arm/mach-sunxi/Kconfig"
1035 source "arch/arm/mach-prima2/Kconfig"
1037 source "arch/arm/mach-tegra/Kconfig"
1039 source "arch/arm/mach-u300/Kconfig"
1041 source "arch/arm/mach-ux500/Kconfig"
1043 source "arch/arm/mach-versatile/Kconfig"
1045 source "arch/arm/mach-vexpress/Kconfig"
1046 source "arch/arm/plat-versatile/Kconfig"
1048 source "arch/arm/mach-vt8500/Kconfig"
1050 source "arch/arm/mach-w90x900/Kconfig"
1052 source "arch/arm/mach-zynq/Kconfig"
1054 # Definitions to make life easier
1060 select GENERIC_CLOCKEVENTS
1066 select GENERIC_IRQ_CHIP
1069 config PLAT_ORION_LEGACY
1076 config PLAT_VERSATILE
1079 config ARM_TIMER_SP804
1082 select CLKSRC_OF if OF
1084 source "arch/arm/firmware/Kconfig"
1086 source arch/arm/mm/Kconfig
1089 bool "Enable iWMMXt support"
1090 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1091 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1093 Enable support for iWMMXt context switching at run time if
1094 running on a CPU that supports it.
1096 config MULTI_IRQ_HANDLER
1099 Allow each machine to specify it's own IRQ handler at run time.
1102 source "arch/arm/Kconfig-nommu"
1105 config PJ4B_ERRATA_4742
1106 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1107 depends on CPU_PJ4B && MACH_ARMADA_370
1110 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1111 Event (WFE) IDLE states, a specific timing sensitivity exists between
1112 the retiring WFI/WFE instructions and the newly issued subsequent
1113 instructions. This sensitivity can result in a CPU hang scenario.
1115 The software must insert either a Data Synchronization Barrier (DSB)
1116 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1119 config ARM_ERRATA_326103
1120 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1123 Executing a SWP instruction to read-only memory does not set bit 11
1124 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1125 treat the access as a read, preventing a COW from occurring and
1126 causing the faulting task to livelock.
1128 config ARM_ERRATA_411920
1129 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1130 depends on CPU_V6 || CPU_V6K
1132 Invalidation of the Instruction Cache operation can
1133 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1134 It does not affect the MPCore. This option enables the ARM Ltd.
1135 recommended workaround.
1137 config ARM_ERRATA_430973
1138 bool "ARM errata: Stale prediction on replaced interworking branch"
1141 This option enables the workaround for the 430973 Cortex-A8
1142 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1143 interworking branch is replaced with another code sequence at the
1144 same virtual address, whether due to self-modifying code or virtual
1145 to physical address re-mapping, Cortex-A8 does not recover from the
1146 stale interworking branch prediction. This results in Cortex-A8
1147 executing the new code sequence in the incorrect ARM or Thumb state.
1148 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1149 and also flushes the branch target cache at every context switch.
1150 Note that setting specific bits in the ACTLR register may not be
1151 available in non-secure mode.
1153 config ARM_ERRATA_458693
1154 bool "ARM errata: Processor deadlock when a false hazard is created"
1156 depends on !ARCH_MULTIPLATFORM
1158 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1159 erratum. For very specific sequences of memory operations, it is
1160 possible for a hazard condition intended for a cache line to instead
1161 be incorrectly associated with a different cache line. This false
1162 hazard might then cause a processor deadlock. The workaround enables
1163 the L1 caching of the NEON accesses and disables the PLD instruction
1164 in the ACTLR register. Note that setting specific bits in the ACTLR
1165 register may not be available in non-secure mode.
1167 config ARM_ERRATA_460075
1168 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1170 depends on !ARCH_MULTIPLATFORM
1172 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1173 erratum. Any asynchronous access to the L2 cache may encounter a
1174 situation in which recent store transactions to the L2 cache are lost
1175 and overwritten with stale memory contents from external memory. The
1176 workaround disables the write-allocate mode for the L2 cache via the
1177 ACTLR register. Note that setting specific bits in the ACTLR register
1178 may not be available in non-secure mode.
1180 config ARM_ERRATA_742230
1181 bool "ARM errata: DMB operation may be faulty"
1182 depends on CPU_V7 && SMP
1183 depends on !ARCH_MULTIPLATFORM
1185 This option enables the workaround for the 742230 Cortex-A9
1186 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1187 between two write operations may not ensure the correct visibility
1188 ordering of the two writes. This workaround sets a specific bit in
1189 the diagnostic register of the Cortex-A9 which causes the DMB
1190 instruction to behave as a DSB, ensuring the correct behaviour of
1193 config ARM_ERRATA_742231
1194 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1195 depends on CPU_V7 && SMP
1196 depends on !ARCH_MULTIPLATFORM
1198 This option enables the workaround for the 742231 Cortex-A9
1199 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1200 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1201 accessing some data located in the same cache line, may get corrupted
1202 data due to bad handling of the address hazard when the line gets
1203 replaced from one of the CPUs at the same time as another CPU is
1204 accessing it. This workaround sets specific bits in the diagnostic
1205 register of the Cortex-A9 which reduces the linefill issuing
1206 capabilities of the processor.
1208 config ARM_ERRATA_643719
1209 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1210 depends on CPU_V7 && SMP
1212 This option enables the workaround for the 643719 Cortex-A9 (prior to
1213 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1214 register returns zero when it should return one. The workaround
1215 corrects this value, ensuring cache maintenance operations which use
1216 it behave as intended and avoiding data corruption.
1218 config ARM_ERRATA_720789
1219 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1222 This option enables the workaround for the 720789 Cortex-A9 (prior to
1223 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1224 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1225 As a consequence of this erratum, some TLB entries which should be
1226 invalidated are not, resulting in an incoherency in the system page
1227 tables. The workaround changes the TLB flushing routines to invalidate
1228 entries regardless of the ASID.
1230 config ARM_ERRATA_743622
1231 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1233 depends on !ARCH_MULTIPLATFORM
1235 This option enables the workaround for the 743622 Cortex-A9
1236 (r2p*) erratum. Under very rare conditions, a faulty
1237 optimisation in the Cortex-A9 Store Buffer may lead to data
1238 corruption. This workaround sets a specific bit in the diagnostic
1239 register of the Cortex-A9 which disables the Store Buffer
1240 optimisation, preventing the defect from occurring. This has no
1241 visible impact on the overall performance or power consumption of the
1244 config ARM_ERRATA_751472
1245 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1247 depends on !ARCH_MULTIPLATFORM
1249 This option enables the workaround for the 751472 Cortex-A9 (prior
1250 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1251 completion of a following broadcasted operation if the second
1252 operation is received by a CPU before the ICIALLUIS has completed,
1253 potentially leading to corrupted entries in the cache or TLB.
1255 config ARM_ERRATA_754322
1256 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1259 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1260 r3p*) erratum. A speculative memory access may cause a page table walk
1261 which starts prior to an ASID switch but completes afterwards. This
1262 can populate the micro-TLB with a stale entry which may be hit with
1263 the new ASID. This workaround places two dsb instructions in the mm
1264 switching code so that no page table walks can cross the ASID switch.
1266 config ARM_ERRATA_754327
1267 bool "ARM errata: no automatic Store Buffer drain"
1268 depends on CPU_V7 && SMP
1270 This option enables the workaround for the 754327 Cortex-A9 (prior to
1271 r2p0) erratum. The Store Buffer does not have any automatic draining
1272 mechanism and therefore a livelock may occur if an external agent
1273 continuously polls a memory location waiting to observe an update.
1274 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1275 written polling loops from denying visibility of updates to memory.
1277 config ARM_ERRATA_364296
1278 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1281 This options enables the workaround for the 364296 ARM1136
1282 r0p2 erratum (possible cache data corruption with
1283 hit-under-miss enabled). It sets the undocumented bit 31 in
1284 the auxiliary control register and the FI bit in the control
1285 register, thus disabling hit-under-miss without putting the
1286 processor into full low interrupt latency mode. ARM11MPCore
1289 config ARM_ERRATA_764369
1290 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1291 depends on CPU_V7 && SMP
1293 This option enables the workaround for erratum 764369
1294 affecting Cortex-A9 MPCore with two or more processors (all
1295 current revisions). Under certain timing circumstances, a data
1296 cache line maintenance operation by MVA targeting an Inner
1297 Shareable memory region may fail to proceed up to either the
1298 Point of Coherency or to the Point of Unification of the
1299 system. This workaround adds a DSB instruction before the
1300 relevant cache maintenance functions and sets a specific bit
1301 in the diagnostic control register of the SCU.
1303 config ARM_ERRATA_775420
1304 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1307 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1308 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1309 operation aborts with MMU exception, it might cause the processor
1310 to deadlock. This workaround puts DSB before executing ISB if
1311 an abort may occur on cache maintenance.
1313 config ARM_ERRATA_798181
1314 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1315 depends on CPU_V7 && SMP
1317 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1318 adequately shooting down all use of the old entries. This
1319 option enables the Linux kernel workaround for this erratum
1320 which sends an IPI to the CPUs that are running the same ASID
1321 as the one being invalidated.
1323 config ARM_ERRATA_773022
1324 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1327 This option enables the workaround for the 773022 Cortex-A15
1328 (up to r0p4) erratum. In certain rare sequences of code, the
1329 loop buffer may deliver incorrect instructions. This
1330 workaround disables the loop buffer to avoid the erratum.
1334 source "arch/arm/common/Kconfig"
1344 Find out whether you have ISA slots on your motherboard. ISA is the
1345 name of a bus system, i.e. the way the CPU talks to the other stuff
1346 inside your box. Other bus systems are PCI, EISA, MicroChannel
1347 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1348 newer boards don't support it. If you have ISA, say Y, otherwise N.
1350 # Select ISA DMA controller support
1355 # Select ISA DMA interface
1360 bool "PCI support" if MIGHT_HAVE_PCI
1362 Find out whether you have a PCI motherboard. PCI is the name of a
1363 bus system, i.e. the way the CPU talks to the other stuff inside
1364 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1365 VESA. If you have PCI, say Y, otherwise N.
1371 config PCI_NANOENGINE
1372 bool "BSE nanoEngine PCI support"
1373 depends on SA1100_NANOENGINE
1375 Enable PCI on the BSE nanoEngine board.
1380 config PCI_HOST_ITE8152
1382 depends on PCI && MACH_ARMCORE
1386 source "drivers/pci/Kconfig"
1387 source "drivers/pci/pcie/Kconfig"
1389 source "drivers/pcmcia/Kconfig"
1393 menu "Kernel Features"
1398 This option should be selected by machines which have an SMP-
1401 The only effect of this option is to make the SMP-related
1402 options available to the user for configuration.
1405 bool "Symmetric Multi-Processing"
1406 depends on CPU_V6K || CPU_V7
1407 depends on GENERIC_CLOCKEVENTS
1409 depends on MMU || ARM_MPU
1411 This enables support for systems with more than one CPU. If you have
1412 a system with only one CPU, say N. If you have a system with more
1413 than one CPU, say Y.
1415 If you say N here, the kernel will run on uni- and multiprocessor
1416 machines, but will use only one CPU of a multiprocessor machine. If
1417 you say Y here, the kernel will run on many, but not all,
1418 uniprocessor machines. On a uniprocessor machine, the kernel
1419 will run faster if you say N here.
1421 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1422 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1423 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1425 If you don't know what to do here, say N.
1428 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1429 depends on SMP && !XIP_KERNEL && MMU
1432 SMP kernels contain instructions which fail on non-SMP processors.
1433 Enabling this option allows the kernel to modify itself to make
1434 these instructions safe. Disabling it allows about 1K of space
1437 If you don't know what to do here, say Y.
1439 config ARM_CPU_TOPOLOGY
1440 bool "Support cpu topology definition"
1441 depends on SMP && CPU_V7
1444 Support ARM cpu topology definition. The MPIDR register defines
1445 affinity between processors which is then used to describe the cpu
1446 topology of an ARM System.
1449 bool "Multi-core scheduler support"
1450 depends on ARM_CPU_TOPOLOGY
1452 Multi-core scheduler support improves the CPU scheduler's decision
1453 making when dealing with multi-core CPU chips at a cost of slightly
1454 increased overhead in some places. If unsure say N here.
1457 bool "SMT scheduler support"
1458 depends on ARM_CPU_TOPOLOGY
1460 Improves the CPU scheduler's decision making when dealing with
1461 MultiThreading at a cost of slightly increased overhead in some
1462 places. If unsure say N here.
1467 This option enables support for the ARM system coherency unit
1469 config HAVE_ARM_ARCH_TIMER
1470 bool "Architected timer support"
1472 select ARM_ARCH_TIMER
1473 select GENERIC_CLOCKEVENTS
1475 This option enables support for the ARM architected timer
1480 select CLKSRC_OF if OF
1482 This options enables support for the ARM timer and watchdog unit
1485 bool "Multi-Cluster Power Management"
1486 depends on CPU_V7 && SMP
1488 This option provides the common power management infrastructure
1489 for (multi-)cluster based systems, such as big.LITTLE based
1493 bool "big.LITTLE support (Experimental)"
1494 depends on CPU_V7 && SMP
1497 This option enables support selections for the big.LITTLE
1498 system architecture.
1501 bool "big.LITTLE switcher support"
1502 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1503 select ARM_CPU_SUSPEND
1506 The big.LITTLE "switcher" provides the core functionality to
1507 transparently handle transition between a cluster of A15's
1508 and a cluster of A7's in a big.LITTLE system.
1510 config BL_SWITCHER_DUMMY_IF
1511 tristate "Simple big.LITTLE switcher user interface"
1512 depends on BL_SWITCHER && DEBUG_KERNEL
1514 This is a simple and dummy char dev interface to control
1515 the big.LITTLE switcher core code. It is meant for
1516 debugging purposes only.
1519 prompt "Memory split"
1523 Select the desired split between kernel and user memory.
1525 If you are not absolutely sure what you are doing, leave this
1529 bool "3G/1G user/kernel split"
1531 bool "2G/2G user/kernel split"
1533 bool "1G/3G user/kernel split"
1538 default PHYS_OFFSET if !MMU
1539 default 0x40000000 if VMSPLIT_1G
1540 default 0x80000000 if VMSPLIT_2G
1544 int "Maximum number of CPUs (2-32)"
1550 bool "Support for hot-pluggable CPUs"
1553 Say Y here to experiment with turning CPUs off and on. CPUs
1554 can be controlled through /sys/devices/system/cpu.
1557 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1560 Say Y here if you want Linux to communicate with system firmware
1561 implementing the PSCI specification for CPU-centric power
1562 management operations described in ARM document number ARM DEN
1563 0022A ("Power State Coordination Interface System Software on
1566 # The GPIO number here must be sorted by descending number. In case of
1567 # a multiplatform kernel, we just want the highest value required by the
1568 # selected platforms.
1571 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1572 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1573 default 416 if ARCH_SUNXI
1574 default 392 if ARCH_U8500
1575 default 352 if ARCH_VT8500
1576 default 264 if MACH_H4700
1579 Maximum number of GPIOs in the system.
1581 If unsure, leave the default value.
1583 source kernel/Kconfig.preempt
1587 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1588 ARCH_S5PV210 || ARCH_EXYNOS4
1589 default AT91_TIMER_HZ if ARCH_AT91
1590 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1594 depends on HZ_FIXED = 0
1595 prompt "Timer frequency"
1619 default HZ_FIXED if HZ_FIXED != 0
1620 default 100 if HZ_100
1621 default 200 if HZ_200
1622 default 250 if HZ_250
1623 default 300 if HZ_300
1624 default 500 if HZ_500
1628 def_bool HIGH_RES_TIMERS
1630 config THUMB2_KERNEL
1631 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1632 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1633 default y if CPU_THUMBONLY
1635 select ARM_ASM_UNIFIED
1638 By enabling this option, the kernel will be compiled in
1639 Thumb-2 mode. A compiler/assembler that understand the unified
1640 ARM-Thumb syntax is needed.
1644 config THUMB2_AVOID_R_ARM_THM_JUMP11
1645 bool "Work around buggy Thumb-2 short branch relocations in gas"
1646 depends on THUMB2_KERNEL && MODULES
1649 Various binutils versions can resolve Thumb-2 branches to
1650 locally-defined, preemptible global symbols as short-range "b.n"
1651 branch instructions.
1653 This is a problem, because there's no guarantee the final
1654 destination of the symbol, or any candidate locations for a
1655 trampoline, are within range of the branch. For this reason, the
1656 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1657 relocation in modules at all, and it makes little sense to add
1660 The symptom is that the kernel fails with an "unsupported
1661 relocation" error when loading some modules.
1663 Until fixed tools are available, passing
1664 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1665 code which hits this problem, at the cost of a bit of extra runtime
1666 stack usage in some cases.
1668 The problem is described in more detail at:
1669 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1671 Only Thumb-2 kernels are affected.
1673 Unless you are sure your tools don't have this problem, say Y.
1675 config ARM_ASM_UNIFIED
1679 bool "Use the ARM EABI to compile the kernel"
1681 This option allows for the kernel to be compiled using the latest
1682 ARM ABI (aka EABI). This is only useful if you are using a user
1683 space environment that is also compiled with EABI.
1685 Since there are major incompatibilities between the legacy ABI and
1686 EABI, especially with regard to structure member alignment, this
1687 option also changes the kernel syscall calling convention to
1688 disambiguate both ABIs and allow for backward compatibility support
1689 (selected with CONFIG_OABI_COMPAT).
1691 To use this you need GCC version 4.0.0 or later.
1694 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1695 depends on AEABI && !THUMB2_KERNEL
1697 This option preserves the old syscall interface along with the
1698 new (ARM EABI) one. It also provides a compatibility layer to
1699 intercept syscalls that have structure arguments which layout
1700 in memory differs between the legacy ABI and the new ARM EABI
1701 (only for non "thumb" binaries). This option adds a tiny
1702 overhead to all syscalls and produces a slightly larger kernel.
1704 The seccomp filter system will not be available when this is
1705 selected, since there is no way yet to sensibly distinguish
1706 between calling conventions during filtering.
1708 If you know you'll be using only pure EABI user space then you
1709 can say N here. If this option is not selected and you attempt
1710 to execute a legacy ABI binary then the result will be
1711 UNPREDICTABLE (in fact it can be predicted that it won't work
1712 at all). If in doubt say N.
1714 config ARCH_HAS_HOLES_MEMORYMODEL
1717 config ARCH_SPARSEMEM_ENABLE
1720 config ARCH_SPARSEMEM_DEFAULT
1721 def_bool ARCH_SPARSEMEM_ENABLE
1723 config ARCH_SELECT_MEMORY_MODEL
1724 def_bool ARCH_SPARSEMEM_ENABLE
1726 config HAVE_ARCH_PFN_VALID
1727 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1730 bool "High Memory Support"
1733 The address space of ARM processors is only 4 Gigabytes large
1734 and it has to accommodate user address space, kernel address
1735 space as well as some memory mapped IO. That means that, if you
1736 have a large amount of physical memory and/or IO, not all of the
1737 memory can be "permanently mapped" by the kernel. The physical
1738 memory that is not permanently mapped is called "high memory".
1740 Depending on the selected kernel/user memory split, minimum
1741 vmalloc space and actual amount of RAM, you may not need this
1742 option which should result in a slightly faster kernel.
1747 bool "Allocate 2nd-level pagetables from highmem"
1750 config HW_PERF_EVENTS
1751 bool "Enable hardware performance counter support for perf events"
1752 depends on PERF_EVENTS
1755 Enable hardware performance counter support for perf events. If
1756 disabled, perf events will use software events only.
1758 config SYS_SUPPORTS_HUGETLBFS
1762 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1766 config ARCH_WANT_GENERAL_HUGETLB
1771 config FORCE_MAX_ZONEORDER
1772 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1773 range 11 64 if ARCH_SHMOBILE_LEGACY
1774 default "12" if SOC_AM33XX
1775 default "9" if SA1111 || ARCH_EFM32
1778 The kernel memory allocator divides physically contiguous memory
1779 blocks into "zones", where each zone is a power of two number of
1780 pages. This option selects the largest power of two that the kernel
1781 keeps in the memory allocator. If you need to allocate very large
1782 blocks of physically contiguous memory, then you may need to
1783 increase this value.
1785 This config option is actually maximum order plus one. For example,
1786 a value of 11 means that the largest free memory block is 2^10 pages.
1788 config ALIGNMENT_TRAP
1790 depends on CPU_CP15_MMU
1791 default y if !ARCH_EBSA110
1792 select HAVE_PROC_CPU if PROC_FS
1794 ARM processors cannot fetch/store information which is not
1795 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1796 address divisible by 4. On 32-bit ARM processors, these non-aligned
1797 fetch/store instructions will be emulated in software if you say
1798 here, which has a severe performance impact. This is necessary for
1799 correct operation of some network protocols. With an IP-only
1800 configuration it is safe to say N, otherwise say Y.
1802 config UACCESS_WITH_MEMCPY
1803 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1805 default y if CPU_FEROCEON
1807 Implement faster copy_to_user and clear_user methods for CPU
1808 cores where a 8-word STM instruction give significantly higher
1809 memory write throughput than a sequence of individual 32bit stores.
1811 A possible side effect is a slight increase in scheduling latency
1812 between threads sharing the same address space if they invoke
1813 such copy operations with large buffers.
1815 However, if the CPU data cache is using a write-allocate mode,
1816 this option is unlikely to provide any performance gain.
1820 prompt "Enable seccomp to safely compute untrusted bytecode"
1822 This kernel feature is useful for number crunching applications
1823 that may need to compute untrusted bytecode during their
1824 execution. By using pipes or other transports made available to
1825 the process as file descriptors supporting the read/write
1826 syscalls, it's possible to isolate those applications in
1827 their own address space using seccomp. Once seccomp is
1828 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1829 and the task is only allowed to execute a few safe syscalls
1830 defined by each seccomp mode.
1843 bool "Xen guest support on ARM (EXPERIMENTAL)"
1844 depends on ARM && AEABI && OF
1845 depends on CPU_V7 && !CPU_V6
1846 depends on !GENERIC_ATOMIC64
1848 select ARCH_DMA_ADDR_T_64BIT
1852 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1859 bool "Flattened Device Tree support"
1862 select OF_EARLY_FLATTREE
1863 select OF_RESERVED_MEM
1865 Include support for flattened device tree machine descriptions.
1868 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1871 This is the traditional way of passing data to the kernel at boot
1872 time. If you are solely relying on the flattened device tree (or
1873 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1874 to remove ATAGS support from your kernel binary. If unsure,
1877 config DEPRECATED_PARAM_STRUCT
1878 bool "Provide old way to pass kernel parameters"
1881 This was deprecated in 2001 and announced to live on for 5 years.
1882 Some old boot loaders still use this way.
1884 # Compressed boot loader in ROM. Yes, we really want to ask about
1885 # TEXT and BSS so we preserve their values in the config files.
1886 config ZBOOT_ROM_TEXT
1887 hex "Compressed ROM boot loader base address"
1890 The physical address at which the ROM-able zImage is to be
1891 placed in the target. Platforms which normally make use of
1892 ROM-able zImage formats normally set this to a suitable
1893 value in their defconfig file.
1895 If ZBOOT_ROM is not enabled, this has no effect.
1897 config ZBOOT_ROM_BSS
1898 hex "Compressed ROM boot loader BSS address"
1901 The base address of an area of read/write memory in the target
1902 for the ROM-able zImage which must be available while the
1903 decompressor is running. It must be large enough to hold the
1904 entire decompressed kernel plus an additional 128 KiB.
1905 Platforms which normally make use of ROM-able zImage formats
1906 normally set this to a suitable value in their defconfig file.
1908 If ZBOOT_ROM is not enabled, this has no effect.
1911 bool "Compressed boot loader in ROM/flash"
1912 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1913 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1915 Say Y here if you intend to execute your compressed kernel image
1916 (zImage) directly from ROM or flash. If unsure, say N.
1919 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1920 depends on ZBOOT_ROM && ARCH_SH7372
1921 default ZBOOT_ROM_NONE
1923 Include experimental SD/MMC loading code in the ROM-able zImage.
1924 With this enabled it is possible to write the ROM-able zImage
1925 kernel image to an MMC or SD card and boot the kernel straight
1926 from the reset vector. At reset the processor Mask ROM will load
1927 the first part of the ROM-able zImage which in turn loads the
1928 rest the kernel image to RAM.
1930 config ZBOOT_ROM_NONE
1931 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1933 Do not load image from SD or MMC
1935 config ZBOOT_ROM_MMCIF
1936 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1938 Load image from MMCIF hardware block.
1940 config ZBOOT_ROM_SH_MOBILE_SDHI
1941 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1943 Load image from SDHI hardware block
1947 config ARM_APPENDED_DTB
1948 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1951 With this option, the boot code will look for a device tree binary
1952 (DTB) appended to zImage
1953 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1955 This is meant as a backward compatibility convenience for those
1956 systems with a bootloader that can't be upgraded to accommodate
1957 the documented boot protocol using a device tree.
1959 Beware that there is very little in terms of protection against
1960 this option being confused by leftover garbage in memory that might
1961 look like a DTB header after a reboot if no actual DTB is appended
1962 to zImage. Do not leave this option active in a production kernel
1963 if you don't intend to always append a DTB. Proper passing of the
1964 location into r2 of a bootloader provided DTB is always preferable
1967 config ARM_ATAG_DTB_COMPAT
1968 bool "Supplement the appended DTB with traditional ATAG information"
1969 depends on ARM_APPENDED_DTB
1971 Some old bootloaders can't be updated to a DTB capable one, yet
1972 they provide ATAGs with memory configuration, the ramdisk address,
1973 the kernel cmdline string, etc. Such information is dynamically
1974 provided by the bootloader and can't always be stored in a static
1975 DTB. To allow a device tree enabled kernel to be used with such
1976 bootloaders, this option allows zImage to extract the information
1977 from the ATAG list and store it at run time into the appended DTB.
1980 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1981 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1983 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1984 bool "Use bootloader kernel arguments if available"
1986 Uses the command-line options passed by the boot loader instead of
1987 the device tree bootargs property. If the boot loader doesn't provide
1988 any, the device tree bootargs property will be used.
1990 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1991 bool "Extend with bootloader kernel arguments"
1993 The command-line arguments provided by the boot loader will be
1994 appended to the the device tree bootargs property.
1999 string "Default kernel command string"
2002 On some architectures (EBSA110 and CATS), there is currently no way
2003 for the boot loader to pass arguments to the kernel. For these
2004 architectures, you should supply some command-line options at build
2005 time by entering them here. As a minimum, you should specify the
2006 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2009 prompt "Kernel command line type" if CMDLINE != ""
2010 default CMDLINE_FROM_BOOTLOADER
2013 config CMDLINE_FROM_BOOTLOADER
2014 bool "Use bootloader kernel arguments if available"
2016 Uses the command-line options passed by the boot loader. If
2017 the boot loader doesn't provide any, the default kernel command
2018 string provided in CMDLINE will be used.
2020 config CMDLINE_EXTEND
2021 bool "Extend bootloader kernel arguments"
2023 The command-line arguments provided by the boot loader will be
2024 appended to the default kernel command string.
2026 config CMDLINE_FORCE
2027 bool "Always use the default kernel command string"
2029 Always use the default kernel command string, even if the boot
2030 loader passes other arguments to the kernel.
2031 This is useful if you cannot or don't want to change the
2032 command-line options your boot loader passes to the kernel.
2036 bool "Kernel Execute-In-Place from ROM"
2037 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2039 Execute-In-Place allows the kernel to run from non-volatile storage
2040 directly addressable by the CPU, such as NOR flash. This saves RAM
2041 space since the text section of the kernel is not loaded from flash
2042 to RAM. Read-write sections, such as the data section and stack,
2043 are still copied to RAM. The XIP kernel is not compressed since
2044 it has to run directly from flash, so it will take more space to
2045 store it. The flash address used to link the kernel object files,
2046 and for storing it, is configuration dependent. Therefore, if you
2047 say Y here, you must know the proper physical address where to
2048 store the kernel image depending on your own flash memory usage.
2050 Also note that the make target becomes "make xipImage" rather than
2051 "make zImage" or "make Image". The final kernel binary to put in
2052 ROM memory will be arch/arm/boot/xipImage.
2056 config XIP_PHYS_ADDR
2057 hex "XIP Kernel Physical Location"
2058 depends on XIP_KERNEL
2059 default "0x00080000"
2061 This is the physical address in your flash memory the kernel will
2062 be linked for and stored to. This address is dependent on your
2066 bool "Kexec system call (EXPERIMENTAL)"
2067 depends on (!SMP || PM_SLEEP_SMP)
2069 kexec is a system call that implements the ability to shutdown your
2070 current kernel, and to start another kernel. It is like a reboot
2071 but it is independent of the system firmware. And like a reboot
2072 you can start any kernel with it, not just Linux.
2074 It is an ongoing process to be certain the hardware in a machine
2075 is properly shutdown, so do not be surprised if this code does not
2076 initially work for you.
2079 bool "Export atags in procfs"
2080 depends on ATAGS && KEXEC
2083 Should the atags used to boot the kernel be exported in an "atags"
2084 file in procfs. Useful with kexec.
2087 bool "Build kdump crash kernel (EXPERIMENTAL)"
2089 Generate crash dump after being started by kexec. This should
2090 be normally only set in special crash dump kernels which are
2091 loaded in the main kernel with kexec-tools into a specially
2092 reserved region and then later executed after a crash by
2093 kdump/kexec. The crash dump kernel must be compiled to a
2094 memory address not used by the main kernel
2096 For more details see Documentation/kdump/kdump.txt
2098 config AUTO_ZRELADDR
2099 bool "Auto calculation of the decompressed kernel image address"
2101 ZRELADDR is the physical address where the decompressed kernel
2102 image will be placed. If AUTO_ZRELADDR is selected, the address
2103 will be determined at run-time by masking the current IP with
2104 0xf8000000. This assumes the zImage being placed in the first 128MB
2105 from start of memory.
2109 menu "CPU Power Management"
2111 source "drivers/cpufreq/Kconfig"
2113 source "drivers/cpuidle/Kconfig"
2117 menu "Floating point emulation"
2119 comment "At least one emulation must be selected"
2122 bool "NWFPE math emulation"
2123 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2125 Say Y to include the NWFPE floating point emulator in the kernel.
2126 This is necessary to run most binaries. Linux does not currently
2127 support floating point hardware so you need to say Y here even if
2128 your machine has an FPA or floating point co-processor podule.
2130 You may say N here if you are going to load the Acorn FPEmulator
2131 early in the bootup.
2134 bool "Support extended precision"
2135 depends on FPE_NWFPE
2137 Say Y to include 80-bit support in the kernel floating-point
2138 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2139 Note that gcc does not generate 80-bit operations by default,
2140 so in most cases this option only enlarges the size of the
2141 floating point emulator without any good reason.
2143 You almost surely want to say N here.
2146 bool "FastFPE math emulation (EXPERIMENTAL)"
2147 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2149 Say Y here to include the FAST floating point emulator in the kernel.
2150 This is an experimental much faster emulator which now also has full
2151 precision for the mantissa. It does not support any exceptions.
2152 It is very simple, and approximately 3-6 times faster than NWFPE.
2154 It should be sufficient for most programs. It may be not suitable
2155 for scientific calculations, but you have to check this for yourself.
2156 If you do not feel you need a faster FP emulation you should better
2160 bool "VFP-format floating point maths"
2161 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2163 Say Y to include VFP support code in the kernel. This is needed
2164 if your hardware includes a VFP unit.
2166 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2167 release notes and additional status information.
2169 Say N if your target does not have VFP hardware.
2177 bool "Advanced SIMD (NEON) Extension support"
2178 depends on VFPv3 && CPU_V7
2180 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2183 config KERNEL_MODE_NEON
2184 bool "Support for NEON in kernel mode"
2185 depends on NEON && AEABI
2187 Say Y to include support for NEON in kernel mode.
2191 menu "Userspace binary formats"
2193 source "fs/Kconfig.binfmt"
2196 tristate "RISC OS personality"
2199 Say Y here to include the kernel code necessary if you want to run
2200 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2201 experimental; if this sounds frightening, say N and sleep in peace.
2202 You can also say M here to compile this support as a module (which
2203 will be called arthur).
2207 menu "Power management options"
2209 source "kernel/power/Kconfig"
2211 config ARCH_SUSPEND_POSSIBLE
2212 depends on !ARCH_S5PC100
2213 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2214 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2217 config ARM_CPU_SUSPEND
2220 config ARCH_HIBERNATION_POSSIBLE
2223 default y if ARCH_SUSPEND_POSSIBLE
2227 source "net/Kconfig"
2229 source "drivers/Kconfig"
2233 source "arch/arm/Kconfig.debug"
2235 source "security/Kconfig"
2237 source "crypto/Kconfig"
2239 source "lib/Kconfig"
2241 source "arch/arm/kvm/Kconfig"