4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_IRQ_PROBE
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select HARDIRQS_SW_RESEND
44 select CPU_PM if (SUSPEND || CPU_IDLE)
45 select GENERIC_PCI_IOMAP
47 select GENERIC_SMP_IDLE_THREAD
49 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
54 The ARM series is a line of low-power-consumption RISC chip designs
55 licensed by ARM Ltd and targeted at embedded applications and
56 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
57 manufactured, but legacy ARM-based PC hardware remains popular in
58 Europe. There is an ARM Linux project with a web page at
59 <http://www.arm.linux.org.uk/>.
61 config ARM_HAS_SG_CHAIN
64 config NEED_SG_DMA_LENGTH
67 config ARM_DMA_USE_IOMMU
68 select NEED_SG_DMA_LENGTH
69 select ARM_HAS_SG_CHAIN
78 config SYS_SUPPORTS_APM_EMULATION
86 select GENERIC_ALLOCATOR
97 The Extended Industry Standard Architecture (EISA) bus was
98 developed as an open alternative to the IBM MicroChannel bus.
100 The EISA bus provided some of the features of the IBM MicroChannel
101 bus while maintaining backward compatibility with cards made for
102 the older ISA bus. The EISA bus saw limited use between 1988 and
103 1995 when it was made obsolete by the PCI bus.
105 Say Y here if you are building a kernel for an EISA-based machine.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config GENERIC_LOCKBREAK
132 depends on SMP && PREEMPT
134 config RWSEM_GENERIC_SPINLOCK
138 config RWSEM_XCHGADD_ALGORITHM
141 config ARCH_HAS_ILOG2_U32
144 config ARCH_HAS_ILOG2_U64
147 config ARCH_HAS_CPUFREQ
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
154 config GENERIC_HWEIGHT
158 config GENERIC_CALIBRATE_DELAY
162 config ARCH_MAY_HAVE_PC_FDC
168 config NEED_DMA_MAP_STATE
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
174 config GENERIC_ISA_DMA
180 config NEED_RET_TO_USER
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_IO_H
214 Select this when mach/io.h is required to provide special
215 definitions for this platform. The need for mach/io.h should
216 be avoided when possible.
218 config NEED_MACH_MEMORY_H
221 Select this when mach/memory.h is required to provide special
222 definitions for this platform. The need for mach/memory.h should
223 be avoided when possible.
226 hex "Physical address of main memory" if MMU
227 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
228 default DRAM_BASE if !MMU
230 Please provide the physical address corresponding to the
231 location of main memory in your system.
237 source "init/Kconfig"
239 source "kernel/Kconfig.freezer"
244 bool "MMU-based Paged Memory Management Support"
247 Select if you want MMU-based virtualised addressing space
248 support by paged memory management. If unsure, say 'Y'.
251 # The "ARM system type" choice list is ordered alphabetically by option
252 # text. Please add new entries in the option alphabetic order.
255 prompt "ARM system type"
256 default ARCH_VERSATILE
259 bool "Altera SOCFPGA family"
260 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select DW_APB_TIMER_OF
269 select GENERIC_CLOCKEVENTS
270 select GPIO_PL061 if GPIOLIB
275 This enables support for Altera SOCFPGA Cyclone V platform
277 config ARCH_INTEGRATOR
278 bool "ARM Ltd. Integrator family"
280 select ARCH_HAS_CPUFREQ
285 select GENERIC_CLOCKEVENTS
286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_FPGA_IRQ
288 select NEED_MACH_IO_H
289 select NEED_MACH_MEMORY_H
291 select MULTI_IRQ_HANDLER
293 Support for ARM's Integrator platform.
296 bool "ARM Ltd. RealView family"
299 select HAVE_MACH_CLKDEV
301 select GENERIC_CLOCKEVENTS
302 select ARCH_WANT_OPTIONAL_GPIOLIB
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLOCK
305 select PLAT_VERSATILE_CLCD
306 select ARM_TIMER_SP804
307 select GPIO_PL061 if GPIOLIB
308 select NEED_MACH_MEMORY_H
310 This enables support for ARM Ltd RealView boards.
312 config ARCH_VERSATILE
313 bool "ARM Ltd. Versatile family"
317 select HAVE_MACH_CLKDEV
319 select GENERIC_CLOCKEVENTS
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select NEED_MACH_IO_H if PCI
322 select PLAT_VERSATILE
323 select PLAT_VERSATILE_CLOCK
324 select PLAT_VERSATILE_CLCD
325 select PLAT_VERSATILE_FPGA_IRQ
326 select ARM_TIMER_SP804
328 This enables support for ARM Ltd Versatile board.
331 bool "ARM Ltd. Versatile Express family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
337 select GENERIC_CLOCKEVENTS
339 select HAVE_PATA_PLATFORM
342 select PLAT_VERSATILE
343 select PLAT_VERSATILE_CLCD
344 select REGULATOR_FIXED_VOLTAGE if REGULATOR
346 This enables support for the ARM Ltd Versatile Express boards.
350 select ARCH_REQUIRE_GPIOLIB
354 select NEED_MACH_IO_H if PCCARD
356 This enables support for systems based on Atmel
357 AT91RM9200 and AT91SAM9* processors.
360 bool "Broadcom BCMRING"
364 select ARM_TIMER_SP804
366 select GENERIC_CLOCKEVENTS
367 select ARCH_WANT_OPTIONAL_GPIOLIB
369 Support for Broadcom's BCMRing platform.
372 bool "Calxeda Highbank-based"
373 select ARCH_WANT_OPTIONAL_GPIOLIB
376 select ARM_TIMER_SP804
381 select GENERIC_CLOCKEVENTS
387 Support for the Calxeda Highbank SoC based boards.
390 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
392 select ARCH_USES_GETTIMEOFFSET
393 select NEED_MACH_MEMORY_H
395 Support for Cirrus Logic 711x/721x/731x based boards.
398 bool "Cavium Networks CNS3XXX family"
400 select GENERIC_CLOCKEVENTS
402 select MIGHT_HAVE_CACHE_L2X0
403 select MIGHT_HAVE_PCI
404 select PCI_DOMAINS if PCI
406 Support for Cavium Networks CNS3XXX platform.
409 bool "Cortina Systems Gemini"
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_USES_GETTIMEOFFSET
414 Support for the Cortina Systems Gemini family SoCs
417 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
420 select ARCH_REQUIRE_GPIOLIB
421 select GENERIC_CLOCKEVENTS
423 select GENERIC_IRQ_CHIP
424 select MIGHT_HAVE_CACHE_L2X0
430 Support for CSR SiRFSoC ARM Cortex A9 Platform
437 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_IO_H
439 select NEED_MACH_MEMORY_H
441 This is an evaluation board for the StrongARM processor available
442 from Digital. It has limited hardware on-board, including an
443 Ethernet interface, two PCMCIA sockets, two serial ports and a
452 select ARCH_REQUIRE_GPIOLIB
453 select ARCH_HAS_HOLES_MEMORYMODEL
454 select ARCH_USES_GETTIMEOFFSET
455 select NEED_MACH_MEMORY_H
457 This enables support for the Cirrus EP93xx series of CPUs.
459 config ARCH_FOOTBRIDGE
463 select GENERIC_CLOCKEVENTS
465 select NEED_MACH_IO_H
466 select NEED_MACH_MEMORY_H
468 Support for systems based on the DC21285 companion chip
469 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
472 bool "Freescale MXC/iMX-based"
473 select GENERIC_CLOCKEVENTS
474 select ARCH_REQUIRE_GPIOLIB
477 select GENERIC_IRQ_CHIP
478 select MULTI_IRQ_HANDLER
482 Support for Freescale MXC/iMX-based family of processors
485 bool "Freescale MXS-based"
486 select GENERIC_CLOCKEVENTS
487 select ARCH_REQUIRE_GPIOLIB
491 select HAVE_CLK_PREPARE
495 Support for Freescale MXS-based family of processors
498 bool "Hilscher NetX based"
502 select GENERIC_CLOCKEVENTS
504 This enables support for systems based on the Hilscher NetX Soc
507 bool "Hynix HMS720x-based"
510 select ARCH_USES_GETTIMEOFFSET
512 This enables support for systems based on the Hynix HMS720x
520 select ARCH_SUPPORTS_MSI
522 select NEED_MACH_IO_H
523 select NEED_MACH_MEMORY_H
524 select NEED_RET_TO_USER
526 Support for Intel's IOP13XX (XScale) family of processors.
532 select NEED_MACH_IO_H
533 select NEED_RET_TO_USER
536 select ARCH_REQUIRE_GPIOLIB
538 Support for Intel's 80219 and IOP32X (XScale) family of
545 select NEED_MACH_IO_H
546 select NEED_RET_TO_USER
549 select ARCH_REQUIRE_GPIOLIB
551 Support for Intel's IOP33X (XScale) family of processors.
556 select ARCH_HAS_DMA_SET_COHERENT_MASK
559 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
561 select MIGHT_HAVE_PCI
562 select NEED_MACH_IO_H
563 select DMABOUNCE if PCI
565 Support for Intel's IXP4XX (XScale) family of processors.
568 bool "Marvell SOCs with Device Tree support"
569 select GENERIC_CLOCKEVENTS
570 select MULTI_IRQ_HANDLER
573 select GENERIC_IRQ_CHIP
577 Support for the Marvell SoC Family with device tree support
583 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
585 select NEED_MACH_IO_H
588 Support for the Marvell Dove SoC 88AP510
591 bool "Marvell Kirkwood"
594 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
596 select NEED_MACH_IO_H
599 Support for the following Marvell Kirkwood series SoCs:
600 88F6180, 88F6192 and 88F6281.
606 select ARCH_REQUIRE_GPIOLIB
609 select USB_ARCH_HAS_OHCI
611 select GENERIC_CLOCKEVENTS
615 Support for the NXP LPC32XX family of processors
618 bool "Marvell MV78xx0"
621 select ARCH_REQUIRE_GPIOLIB
622 select GENERIC_CLOCKEVENTS
623 select NEED_MACH_IO_H
626 Support for the following Marvell MV78xx0 series SoCs:
634 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
636 select NEED_MACH_IO_H
639 Support for the following Marvell Orion 5x series SoCs:
640 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
641 Orion-2 (5281), Orion-1-90 (6183).
644 bool "Marvell PXA168/910/MMP2"
646 select ARCH_REQUIRE_GPIOLIB
648 select GENERIC_CLOCKEVENTS
653 select GENERIC_ALLOCATOR
655 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
658 bool "Micrel/Kendin KS8695"
660 select ARCH_REQUIRE_GPIOLIB
661 select ARCH_USES_GETTIMEOFFSET
662 select NEED_MACH_MEMORY_H
664 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
665 System-on-Chip devices.
668 bool "Nuvoton W90X900 CPU"
670 select ARCH_REQUIRE_GPIOLIB
673 select GENERIC_CLOCKEVENTS
675 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
676 At present, the w90x900 has been renamed nuc900, regarding
677 the ARM series product line, you can login the following
678 link address to know more.
680 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
681 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
687 select GENERIC_CLOCKEVENTS
691 select MIGHT_HAVE_CACHE_L2X0
692 select NEED_MACH_IO_H if PCI
693 select ARCH_HAS_CPUFREQ
696 This enables support for NVIDIA Tegra based systems (Tegra APX,
697 Tegra 6xx and Tegra 2 series).
699 config ARCH_PICOXCELL
700 bool "Picochip picoXcell"
701 select ARCH_REQUIRE_GPIOLIB
702 select ARM_PATCH_PHYS_VIRT
706 select DW_APB_TIMER_OF
707 select GENERIC_CLOCKEVENTS
714 This enables support for systems based on the Picochip picoXcell
715 family of Femtocell devices. The picoxcell support requires device tree
719 bool "Philips Nexperia PNX4008 Mobile"
722 select ARCH_USES_GETTIMEOFFSET
724 This enables support for Philips PNX4008 mobile platform.
727 bool "PXA2xx/PXA3xx-based"
730 select ARCH_HAS_CPUFREQ
733 select ARCH_REQUIRE_GPIOLIB
734 select GENERIC_CLOCKEVENTS
739 select MULTI_IRQ_HANDLER
740 select ARM_CPU_SUSPEND if PM
743 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
748 select GENERIC_CLOCKEVENTS
749 select ARCH_REQUIRE_GPIOLIB
752 Support for Qualcomm MSM/QSD based systems. This runs on the
753 apps processor of the MSM/QSD and depends on a shared memory
754 interface to the modem processor which runs the baseband
755 stack and controls some vital subsystems
756 (clock and power control, etc).
759 bool "Renesas SH-Mobile / R-Mobile"
762 select HAVE_MACH_CLKDEV
764 select GENERIC_CLOCKEVENTS
765 select MIGHT_HAVE_CACHE_L2X0
768 select MULTI_IRQ_HANDLER
769 select PM_GENERIC_DOMAINS if PM
770 select NEED_MACH_MEMORY_H
772 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
778 select ARCH_MAY_HAVE_PC_FDC
779 select HAVE_PATA_PLATFORM
782 select ARCH_SPARSEMEM_ENABLE
783 select ARCH_USES_GETTIMEOFFSET
785 select NEED_MACH_IO_H
786 select NEED_MACH_MEMORY_H
788 On the Acorn Risc-PC, Linux can support the internal IDE disk and
789 CD-ROM interface, serial and parallel port, and the floppy drive.
796 select ARCH_SPARSEMEM_ENABLE
798 select ARCH_HAS_CPUFREQ
800 select GENERIC_CLOCKEVENTS
802 select ARCH_REQUIRE_GPIOLIB
804 select NEED_MACH_MEMORY_H
807 Support for StrongARM 11x0 based boards.
810 bool "Samsung S3C24XX SoCs"
812 select ARCH_HAS_CPUFREQ
815 select ARCH_USES_GETTIMEOFFSET
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
818 select HAVE_S3C2410_WATCHDOG if WATCHDOG
819 select NEED_MACH_IO_H
821 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
822 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
823 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
824 Samsung SMDK2410 development board (and derivatives).
827 bool "Samsung S3C64XX"
835 select ARCH_USES_GETTIMEOFFSET
836 select ARCH_HAS_CPUFREQ
837 select ARCH_REQUIRE_GPIOLIB
838 select SAMSUNG_CLKSRC
839 select SAMSUNG_IRQ_VIC_TIMER
840 select S3C_GPIO_TRACK
842 select USB_ARCH_HAS_OHCI
843 select SAMSUNG_GPIOLIB_4BIT
844 select HAVE_S3C2410_I2C if I2C
845 select HAVE_S3C2410_WATCHDOG if WATCHDOG
847 Samsung S3C64XX series based systems
850 bool "Samsung S5P6440 S5P6450"
856 select HAVE_S3C2410_WATCHDOG if WATCHDOG
857 select GENERIC_CLOCKEVENTS
858 select HAVE_S3C2410_I2C if I2C
859 select HAVE_S3C_RTC if RTC_CLASS
861 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
865 bool "Samsung S5PC100"
870 select ARCH_USES_GETTIMEOFFSET
871 select HAVE_S3C2410_I2C if I2C
872 select HAVE_S3C_RTC if RTC_CLASS
873 select HAVE_S3C2410_WATCHDOG if WATCHDOG
875 Samsung S5PC100 series based systems
878 bool "Samsung S5PV210/S5PC110"
880 select ARCH_SPARSEMEM_ENABLE
881 select ARCH_HAS_HOLES_MEMORYMODEL
886 select ARCH_HAS_CPUFREQ
887 select GENERIC_CLOCKEVENTS
888 select HAVE_S3C2410_I2C if I2C
889 select HAVE_S3C_RTC if RTC_CLASS
890 select HAVE_S3C2410_WATCHDOG if WATCHDOG
891 select NEED_MACH_MEMORY_H
893 Samsung S5PV210/S5PC110 series based systems
896 bool "SAMSUNG EXYNOS"
898 select ARCH_SPARSEMEM_ENABLE
899 select ARCH_HAS_HOLES_MEMORYMODEL
903 select ARCH_HAS_CPUFREQ
904 select GENERIC_CLOCKEVENTS
905 select HAVE_S3C_RTC if RTC_CLASS
906 select HAVE_S3C2410_I2C if I2C
907 select HAVE_S3C2410_WATCHDOG if WATCHDOG
908 select NEED_MACH_MEMORY_H
910 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
919 select ARCH_USES_GETTIMEOFFSET
920 select NEED_MACH_MEMORY_H
921 select NEED_MACH_IO_H
923 Support for the StrongARM based Digital DNARD machine, also known
924 as "Shark" (<http://www.shark-linux.de/shark.html>).
927 bool "ST-Ericsson U300 Series"
933 select ARM_PATCH_PHYS_VIRT
935 select GENERIC_CLOCKEVENTS
939 select ARCH_REQUIRE_GPIOLIB
941 Support for ST-Ericsson U300 series mobile platforms.
944 bool "ST-Ericsson U8500 Series"
948 select GENERIC_CLOCKEVENTS
950 select ARCH_REQUIRE_GPIOLIB
951 select ARCH_HAS_CPUFREQ
953 select MIGHT_HAVE_CACHE_L2X0
955 Support for ST-Ericsson's Ux500 architecture
958 bool "STMicroelectronics Nomadik"
963 select GENERIC_CLOCKEVENTS
965 select MIGHT_HAVE_CACHE_L2X0
966 select ARCH_REQUIRE_GPIOLIB
968 Support for the Nomadik platform by ST-Ericsson
972 select GENERIC_CLOCKEVENTS
973 select ARCH_REQUIRE_GPIOLIB
977 select GENERIC_ALLOCATOR
978 select GENERIC_IRQ_CHIP
979 select ARCH_HAS_HOLES_MEMORYMODEL
981 Support for TI's DaVinci platform.
987 select ARCH_REQUIRE_GPIOLIB
988 select ARCH_HAS_CPUFREQ
990 select GENERIC_CLOCKEVENTS
991 select ARCH_HAS_HOLES_MEMORYMODEL
993 Support for TI's OMAP platform (OMAP1/2/3/4).
998 select ARCH_REQUIRE_GPIOLIB
1002 select GENERIC_CLOCKEVENTS
1005 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1008 bool "VIA/WonderMedia 85xx"
1011 select ARCH_HAS_CPUFREQ
1012 select GENERIC_CLOCKEVENTS
1013 select ARCH_REQUIRE_GPIOLIB
1015 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1018 bool "Xilinx Zynq ARM Cortex A9 Platform"
1020 select GENERIC_CLOCKEVENTS
1021 select CLKDEV_LOOKUP
1025 select MIGHT_HAVE_CACHE_L2X0
1028 Support for Xilinx Zynq ARM Cortex A9 Platform
1032 # This is sorted alphabetically by mach-* pathname. However, plat-*
1033 # Kconfigs may be included either alphabetically (according to the
1034 # plat- suffix) or along side the corresponding mach-* source.
1036 source "arch/arm/mach-mvebu/Kconfig"
1038 source "arch/arm/mach-at91/Kconfig"
1040 source "arch/arm/mach-bcmring/Kconfig"
1042 source "arch/arm/mach-clps711x/Kconfig"
1044 source "arch/arm/mach-cns3xxx/Kconfig"
1046 source "arch/arm/mach-davinci/Kconfig"
1048 source "arch/arm/mach-dove/Kconfig"
1050 source "arch/arm/mach-ep93xx/Kconfig"
1052 source "arch/arm/mach-footbridge/Kconfig"
1054 source "arch/arm/mach-gemini/Kconfig"
1056 source "arch/arm/mach-h720x/Kconfig"
1058 source "arch/arm/mach-integrator/Kconfig"
1060 source "arch/arm/mach-iop32x/Kconfig"
1062 source "arch/arm/mach-iop33x/Kconfig"
1064 source "arch/arm/mach-iop13xx/Kconfig"
1066 source "arch/arm/mach-ixp4xx/Kconfig"
1068 source "arch/arm/mach-kirkwood/Kconfig"
1070 source "arch/arm/mach-ks8695/Kconfig"
1072 source "arch/arm/mach-msm/Kconfig"
1074 source "arch/arm/mach-mv78xx0/Kconfig"
1076 source "arch/arm/plat-mxc/Kconfig"
1078 source "arch/arm/mach-mxs/Kconfig"
1080 source "arch/arm/mach-netx/Kconfig"
1082 source "arch/arm/mach-nomadik/Kconfig"
1083 source "arch/arm/plat-nomadik/Kconfig"
1085 source "arch/arm/plat-omap/Kconfig"
1087 source "arch/arm/mach-omap1/Kconfig"
1089 source "arch/arm/mach-omap2/Kconfig"
1091 source "arch/arm/mach-orion5x/Kconfig"
1093 source "arch/arm/mach-pxa/Kconfig"
1094 source "arch/arm/plat-pxa/Kconfig"
1096 source "arch/arm/mach-mmp/Kconfig"
1098 source "arch/arm/mach-realview/Kconfig"
1100 source "arch/arm/mach-sa1100/Kconfig"
1102 source "arch/arm/plat-samsung/Kconfig"
1103 source "arch/arm/plat-s3c24xx/Kconfig"
1105 source "arch/arm/plat-spear/Kconfig"
1107 source "arch/arm/mach-s3c24xx/Kconfig"
1109 source "arch/arm/mach-s3c2412/Kconfig"
1110 source "arch/arm/mach-s3c2440/Kconfig"
1114 source "arch/arm/mach-s3c64xx/Kconfig"
1117 source "arch/arm/mach-s5p64x0/Kconfig"
1119 source "arch/arm/mach-s5pc100/Kconfig"
1121 source "arch/arm/mach-s5pv210/Kconfig"
1123 source "arch/arm/mach-exynos/Kconfig"
1125 source "arch/arm/mach-shmobile/Kconfig"
1127 source "arch/arm/mach-tegra/Kconfig"
1129 source "arch/arm/mach-u300/Kconfig"
1131 source "arch/arm/mach-ux500/Kconfig"
1133 source "arch/arm/mach-versatile/Kconfig"
1135 source "arch/arm/mach-vexpress/Kconfig"
1136 source "arch/arm/plat-versatile/Kconfig"
1138 source "arch/arm/mach-vt8500/Kconfig"
1140 source "arch/arm/mach-w90x900/Kconfig"
1142 # Definitions to make life easier
1148 select GENERIC_CLOCKEVENTS
1153 select GENERIC_IRQ_CHIP
1160 config PLAT_VERSATILE
1163 config ARM_TIMER_SP804
1166 select HAVE_SCHED_CLOCK
1168 source arch/arm/mm/Kconfig
1172 default 16 if ARCH_EP93XX
1176 bool "Enable iWMMXt support"
1177 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1178 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1180 Enable support for iWMMXt context switching at run time if
1181 running on a CPU that supports it.
1185 depends on CPU_XSCALE
1189 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1190 (!ARCH_OMAP3 || OMAP3_EMU)
1194 config MULTI_IRQ_HANDLER
1197 Allow each machine to specify it's own IRQ handler at run time.
1200 source "arch/arm/Kconfig-nommu"
1203 config ARM_ERRATA_326103
1204 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1207 Executing a SWP instruction to read-only memory does not set bit 11
1208 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1209 treat the access as a read, preventing a COW from occurring and
1210 causing the faulting task to livelock.
1212 config ARM_ERRATA_411920
1213 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1214 depends on CPU_V6 || CPU_V6K
1216 Invalidation of the Instruction Cache operation can
1217 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1218 It does not affect the MPCore. This option enables the ARM Ltd.
1219 recommended workaround.
1221 config ARM_ERRATA_430973
1222 bool "ARM errata: Stale prediction on replaced interworking branch"
1225 This option enables the workaround for the 430973 Cortex-A8
1226 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1227 interworking branch is replaced with another code sequence at the
1228 same virtual address, whether due to self-modifying code or virtual
1229 to physical address re-mapping, Cortex-A8 does not recover from the
1230 stale interworking branch prediction. This results in Cortex-A8
1231 executing the new code sequence in the incorrect ARM or Thumb state.
1232 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1233 and also flushes the branch target cache at every context switch.
1234 Note that setting specific bits in the ACTLR register may not be
1235 available in non-secure mode.
1237 config ARM_ERRATA_458693
1238 bool "ARM errata: Processor deadlock when a false hazard is created"
1241 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1242 erratum. For very specific sequences of memory operations, it is
1243 possible for a hazard condition intended for a cache line to instead
1244 be incorrectly associated with a different cache line. This false
1245 hazard might then cause a processor deadlock. The workaround enables
1246 the L1 caching of the NEON accesses and disables the PLD instruction
1247 in the ACTLR register. Note that setting specific bits in the ACTLR
1248 register may not be available in non-secure mode.
1250 config ARM_ERRATA_460075
1251 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1254 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1255 erratum. Any asynchronous access to the L2 cache may encounter a
1256 situation in which recent store transactions to the L2 cache are lost
1257 and overwritten with stale memory contents from external memory. The
1258 workaround disables the write-allocate mode for the L2 cache via the
1259 ACTLR register. Note that setting specific bits in the ACTLR register
1260 may not be available in non-secure mode.
1262 config ARM_ERRATA_742230
1263 bool "ARM errata: DMB operation may be faulty"
1264 depends on CPU_V7 && SMP
1266 This option enables the workaround for the 742230 Cortex-A9
1267 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1268 between two write operations may not ensure the correct visibility
1269 ordering of the two writes. This workaround sets a specific bit in
1270 the diagnostic register of the Cortex-A9 which causes the DMB
1271 instruction to behave as a DSB, ensuring the correct behaviour of
1274 config ARM_ERRATA_742231
1275 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1276 depends on CPU_V7 && SMP
1278 This option enables the workaround for the 742231 Cortex-A9
1279 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1280 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1281 accessing some data located in the same cache line, may get corrupted
1282 data due to bad handling of the address hazard when the line gets
1283 replaced from one of the CPUs at the same time as another CPU is
1284 accessing it. This workaround sets specific bits in the diagnostic
1285 register of the Cortex-A9 which reduces the linefill issuing
1286 capabilities of the processor.
1288 config PL310_ERRATA_588369
1289 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1290 depends on CACHE_L2X0
1292 The PL310 L2 cache controller implements three types of Clean &
1293 Invalidate maintenance operations: by Physical Address
1294 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1295 They are architecturally defined to behave as the execution of a
1296 clean operation followed immediately by an invalidate operation,
1297 both performing to the same memory location. This functionality
1298 is not correctly implemented in PL310 as clean lines are not
1299 invalidated as a result of these operations.
1301 config ARM_ERRATA_720789
1302 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1305 This option enables the workaround for the 720789 Cortex-A9 (prior to
1306 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1307 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1308 As a consequence of this erratum, some TLB entries which should be
1309 invalidated are not, resulting in an incoherency in the system page
1310 tables. The workaround changes the TLB flushing routines to invalidate
1311 entries regardless of the ASID.
1313 config PL310_ERRATA_727915
1314 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1315 depends on CACHE_L2X0
1317 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1318 operation (offset 0x7FC). This operation runs in background so that
1319 PL310 can handle normal accesses while it is in progress. Under very
1320 rare circumstances, due to this erratum, write data can be lost when
1321 PL310 treats a cacheable write transaction during a Clean &
1322 Invalidate by Way operation.
1324 config ARM_ERRATA_743622
1325 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1328 This option enables the workaround for the 743622 Cortex-A9
1329 (r2p*) erratum. Under very rare conditions, a faulty
1330 optimisation in the Cortex-A9 Store Buffer may lead to data
1331 corruption. This workaround sets a specific bit in the diagnostic
1332 register of the Cortex-A9 which disables the Store Buffer
1333 optimisation, preventing the defect from occurring. This has no
1334 visible impact on the overall performance or power consumption of the
1337 config ARM_ERRATA_751472
1338 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1341 This option enables the workaround for the 751472 Cortex-A9 (prior
1342 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1343 completion of a following broadcasted operation if the second
1344 operation is received by a CPU before the ICIALLUIS has completed,
1345 potentially leading to corrupted entries in the cache or TLB.
1347 config PL310_ERRATA_753970
1348 bool "PL310 errata: cache sync operation may be faulty"
1349 depends on CACHE_PL310
1351 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1353 Under some condition the effect of cache sync operation on
1354 the store buffer still remains when the operation completes.
1355 This means that the store buffer is always asked to drain and
1356 this prevents it from merging any further writes. The workaround
1357 is to replace the normal offset of cache sync operation (0x730)
1358 by another offset targeting an unmapped PL310 register 0x740.
1359 This has the same effect as the cache sync operation: store buffer
1360 drain and waiting for all buffers empty.
1362 config ARM_ERRATA_754322
1363 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1366 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1367 r3p*) erratum. A speculative memory access may cause a page table walk
1368 which starts prior to an ASID switch but completes afterwards. This
1369 can populate the micro-TLB with a stale entry which may be hit with
1370 the new ASID. This workaround places two dsb instructions in the mm
1371 switching code so that no page table walks can cross the ASID switch.
1373 config ARM_ERRATA_754327
1374 bool "ARM errata: no automatic Store Buffer drain"
1375 depends on CPU_V7 && SMP
1377 This option enables the workaround for the 754327 Cortex-A9 (prior to
1378 r2p0) erratum. The Store Buffer does not have any automatic draining
1379 mechanism and therefore a livelock may occur if an external agent
1380 continuously polls a memory location waiting to observe an update.
1381 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1382 written polling loops from denying visibility of updates to memory.
1384 config ARM_ERRATA_364296
1385 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1386 depends on CPU_V6 && !SMP
1388 This options enables the workaround for the 364296 ARM1136
1389 r0p2 erratum (possible cache data corruption with
1390 hit-under-miss enabled). It sets the undocumented bit 31 in
1391 the auxiliary control register and the FI bit in the control
1392 register, thus disabling hit-under-miss without putting the
1393 processor into full low interrupt latency mode. ARM11MPCore
1396 config ARM_ERRATA_764369
1397 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1398 depends on CPU_V7 && SMP
1400 This option enables the workaround for erratum 764369
1401 affecting Cortex-A9 MPCore with two or more processors (all
1402 current revisions). Under certain timing circumstances, a data
1403 cache line maintenance operation by MVA targeting an Inner
1404 Shareable memory region may fail to proceed up to either the
1405 Point of Coherency or to the Point of Unification of the
1406 system. This workaround adds a DSB instruction before the
1407 relevant cache maintenance functions and sets a specific bit
1408 in the diagnostic control register of the SCU.
1410 config PL310_ERRATA_769419
1411 bool "PL310 errata: no automatic Store Buffer drain"
1412 depends on CACHE_L2X0
1414 On revisions of the PL310 prior to r3p2, the Store Buffer does
1415 not automatically drain. This can cause normal, non-cacheable
1416 writes to be retained when the memory system is idle, leading
1417 to suboptimal I/O performance for drivers using coherent DMA.
1418 This option adds a write barrier to the cpu_idle loop so that,
1419 on systems with an outer cache, the store buffer is drained
1424 source "arch/arm/common/Kconfig"
1434 Find out whether you have ISA slots on your motherboard. ISA is the
1435 name of a bus system, i.e. the way the CPU talks to the other stuff
1436 inside your box. Other bus systems are PCI, EISA, MicroChannel
1437 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1438 newer boards don't support it. If you have ISA, say Y, otherwise N.
1440 # Select ISA DMA controller support
1445 # Select ISA DMA interface
1450 bool "PCI support" if MIGHT_HAVE_PCI
1452 Find out whether you have a PCI motherboard. PCI is the name of a
1453 bus system, i.e. the way the CPU talks to the other stuff inside
1454 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1455 VESA. If you have PCI, say Y, otherwise N.
1461 config PCI_NANOENGINE
1462 bool "BSE nanoEngine PCI support"
1463 depends on SA1100_NANOENGINE
1465 Enable PCI on the BSE nanoEngine board.
1470 # Select the host bridge type
1471 config PCI_HOST_VIA82C505
1473 depends on PCI && ARCH_SHARK
1476 config PCI_HOST_ITE8152
1478 depends on PCI && MACH_ARMCORE
1482 source "drivers/pci/Kconfig"
1484 source "drivers/pcmcia/Kconfig"
1488 menu "Kernel Features"
1493 This option should be selected by machines which have an SMP-
1496 The only effect of this option is to make the SMP-related
1497 options available to the user for configuration.
1500 bool "Symmetric Multi-Processing"
1501 depends on CPU_V6K || CPU_V7
1502 depends on GENERIC_CLOCKEVENTS
1505 select USE_GENERIC_SMP_HELPERS
1506 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1508 This enables support for systems with more than one CPU. If you have
1509 a system with only one CPU, like most personal computers, say N. If
1510 you have a system with more than one CPU, say Y.
1512 If you say N here, the kernel will run on single and multiprocessor
1513 machines, but will use only one CPU of a multiprocessor machine. If
1514 you say Y here, the kernel will run on many, but not all, single
1515 processor machines. On a single processor machine, the kernel will
1516 run faster if you say N here.
1518 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1519 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1520 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1522 If you don't know what to do here, say N.
1525 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1526 depends on EXPERIMENTAL
1527 depends on SMP && !XIP_KERNEL
1530 SMP kernels contain instructions which fail on non-SMP processors.
1531 Enabling this option allows the kernel to modify itself to make
1532 these instructions safe. Disabling it allows about 1K of space
1535 If you don't know what to do here, say Y.
1537 config ARM_CPU_TOPOLOGY
1538 bool "Support cpu topology definition"
1539 depends on SMP && CPU_V7
1542 Support ARM cpu topology definition. The MPIDR register defines
1543 affinity between processors which is then used to describe the cpu
1544 topology of an ARM System.
1547 bool "Multi-core scheduler support"
1548 depends on ARM_CPU_TOPOLOGY
1550 Multi-core scheduler support improves the CPU scheduler's decision
1551 making when dealing with multi-core CPU chips at a cost of slightly
1552 increased overhead in some places. If unsure say N here.
1555 bool "SMT scheduler support"
1556 depends on ARM_CPU_TOPOLOGY
1558 Improves the CPU scheduler's decision making when dealing with
1559 MultiThreading at a cost of slightly increased overhead in some
1560 places. If unsure say N here.
1565 This option enables support for the ARM system coherency unit
1567 config ARM_ARCH_TIMER
1568 bool "Architected timer support"
1571 This option enables support for the ARM architected timer
1577 This options enables support for the ARM timer and watchdog unit
1580 prompt "Memory split"
1583 Select the desired split between kernel and user memory.
1585 If you are not absolutely sure what you are doing, leave this
1589 bool "3G/1G user/kernel split"
1591 bool "2G/2G user/kernel split"
1593 bool "1G/3G user/kernel split"
1598 default 0x40000000 if VMSPLIT_1G
1599 default 0x80000000 if VMSPLIT_2G
1603 int "Maximum number of CPUs (2-32)"
1609 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1610 depends on SMP && HOTPLUG && EXPERIMENTAL
1612 Say Y here to experiment with turning CPUs off and on. CPUs
1613 can be controlled through /sys/devices/system/cpu.
1616 bool "Use local timer interrupts"
1619 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1621 Enable support for local timers on SMP platforms, rather then the
1622 legacy IPI broadcast method. Local timers allows the system
1623 accounting to be spread across the timer interval, preventing a
1624 "thundering herd" at every timer tick.
1628 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1629 default 355 if ARCH_U8500
1630 default 264 if MACH_H4700
1631 default 512 if SOC_OMAP5
1634 Maximum number of GPIOs in the system.
1636 If unsure, leave the default value.
1638 source kernel/Kconfig.preempt
1642 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1643 ARCH_S5PV210 || ARCH_EXYNOS4
1644 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1645 default AT91_TIMER_HZ if ARCH_AT91
1646 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1649 config THUMB2_KERNEL
1650 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1651 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1653 select ARM_ASM_UNIFIED
1656 By enabling this option, the kernel will be compiled in
1657 Thumb-2 mode. A compiler/assembler that understand the unified
1658 ARM-Thumb syntax is needed.
1662 config THUMB2_AVOID_R_ARM_THM_JUMP11
1663 bool "Work around buggy Thumb-2 short branch relocations in gas"
1664 depends on THUMB2_KERNEL && MODULES
1667 Various binutils versions can resolve Thumb-2 branches to
1668 locally-defined, preemptible global symbols as short-range "b.n"
1669 branch instructions.
1671 This is a problem, because there's no guarantee the final
1672 destination of the symbol, or any candidate locations for a
1673 trampoline, are within range of the branch. For this reason, the
1674 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1675 relocation in modules at all, and it makes little sense to add
1678 The symptom is that the kernel fails with an "unsupported
1679 relocation" error when loading some modules.
1681 Until fixed tools are available, passing
1682 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1683 code which hits this problem, at the cost of a bit of extra runtime
1684 stack usage in some cases.
1686 The problem is described in more detail at:
1687 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1689 Only Thumb-2 kernels are affected.
1691 Unless you are sure your tools don't have this problem, say Y.
1693 config ARM_ASM_UNIFIED
1697 bool "Use the ARM EABI to compile the kernel"
1699 This option allows for the kernel to be compiled using the latest
1700 ARM ABI (aka EABI). This is only useful if you are using a user
1701 space environment that is also compiled with EABI.
1703 Since there are major incompatibilities between the legacy ABI and
1704 EABI, especially with regard to structure member alignment, this
1705 option also changes the kernel syscall calling convention to
1706 disambiguate both ABIs and allow for backward compatibility support
1707 (selected with CONFIG_OABI_COMPAT).
1709 To use this you need GCC version 4.0.0 or later.
1712 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1713 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1716 This option preserves the old syscall interface along with the
1717 new (ARM EABI) one. It also provides a compatibility layer to
1718 intercept syscalls that have structure arguments which layout
1719 in memory differs between the legacy ABI and the new ARM EABI
1720 (only for non "thumb" binaries). This option adds a tiny
1721 overhead to all syscalls and produces a slightly larger kernel.
1722 If you know you'll be using only pure EABI user space then you
1723 can say N here. If this option is not selected and you attempt
1724 to execute a legacy ABI binary then the result will be
1725 UNPREDICTABLE (in fact it can be predicted that it won't work
1726 at all). If in doubt say Y.
1728 config ARCH_HAS_HOLES_MEMORYMODEL
1731 config ARCH_SPARSEMEM_ENABLE
1734 config ARCH_SPARSEMEM_DEFAULT
1735 def_bool ARCH_SPARSEMEM_ENABLE
1737 config ARCH_SELECT_MEMORY_MODEL
1738 def_bool ARCH_SPARSEMEM_ENABLE
1740 config HAVE_ARCH_PFN_VALID
1741 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1744 bool "High Memory Support"
1747 The address space of ARM processors is only 4 Gigabytes large
1748 and it has to accommodate user address space, kernel address
1749 space as well as some memory mapped IO. That means that, if you
1750 have a large amount of physical memory and/or IO, not all of the
1751 memory can be "permanently mapped" by the kernel. The physical
1752 memory that is not permanently mapped is called "high memory".
1754 Depending on the selected kernel/user memory split, minimum
1755 vmalloc space and actual amount of RAM, you may not need this
1756 option which should result in a slightly faster kernel.
1761 bool "Allocate 2nd-level pagetables from highmem"
1764 config HW_PERF_EVENTS
1765 bool "Enable hardware performance counter support for perf events"
1766 depends on PERF_EVENTS && CPU_HAS_PMU
1769 Enable hardware performance counter support for perf events. If
1770 disabled, perf events will use software events only.
1774 config FORCE_MAX_ZONEORDER
1775 int "Maximum zone order" if ARCH_SHMOBILE
1776 range 11 64 if ARCH_SHMOBILE
1777 default "9" if SA1111
1780 The kernel memory allocator divides physically contiguous memory
1781 blocks into "zones", where each zone is a power of two number of
1782 pages. This option selects the largest power of two that the kernel
1783 keeps in the memory allocator. If you need to allocate very large
1784 blocks of physically contiguous memory, then you may need to
1785 increase this value.
1787 This config option is actually maximum order plus one. For example,
1788 a value of 11 means that the largest free memory block is 2^10 pages.
1790 config ALIGNMENT_TRAP
1792 depends on CPU_CP15_MMU
1793 default y if !ARCH_EBSA110
1794 select HAVE_PROC_CPU if PROC_FS
1796 ARM processors cannot fetch/store information which is not
1797 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1798 address divisible by 4. On 32-bit ARM processors, these non-aligned
1799 fetch/store instructions will be emulated in software if you say
1800 here, which has a severe performance impact. This is necessary for
1801 correct operation of some network protocols. With an IP-only
1802 configuration it is safe to say N, otherwise say Y.
1804 config UACCESS_WITH_MEMCPY
1805 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1806 depends on MMU && EXPERIMENTAL
1807 default y if CPU_FEROCEON
1809 Implement faster copy_to_user and clear_user methods for CPU
1810 cores where a 8-word STM instruction give significantly higher
1811 memory write throughput than a sequence of individual 32bit stores.
1813 A possible side effect is a slight increase in scheduling latency
1814 between threads sharing the same address space if they invoke
1815 such copy operations with large buffers.
1817 However, if the CPU data cache is using a write-allocate mode,
1818 this option is unlikely to provide any performance gain.
1822 prompt "Enable seccomp to safely compute untrusted bytecode"
1824 This kernel feature is useful for number crunching applications
1825 that may need to compute untrusted bytecode during their
1826 execution. By using pipes or other transports made available to
1827 the process as file descriptors supporting the read/write
1828 syscalls, it's possible to isolate those applications in
1829 their own address space using seccomp. Once seccomp is
1830 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1831 and the task is only allowed to execute a few safe syscalls
1832 defined by each seccomp mode.
1834 config CC_STACKPROTECTOR
1835 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1836 depends on EXPERIMENTAL
1838 This option turns on the -fstack-protector GCC feature. This
1839 feature puts, at the beginning of functions, a canary value on
1840 the stack just before the return address, and validates
1841 the value just before actually returning. Stack based buffer
1842 overflows (that need to overwrite this return address) now also
1843 overwrite the canary, which gets detected and the attack is then
1844 neutralized via a kernel panic.
1845 This feature requires gcc version 4.2 or above.
1847 config DEPRECATED_PARAM_STRUCT
1848 bool "Provide old way to pass kernel parameters"
1850 This was deprecated in 2001 and announced to live on for 5 years.
1851 Some old boot loaders still use this way.
1858 bool "Flattened Device Tree support"
1860 select OF_EARLY_FLATTREE
1863 Include support for flattened device tree machine descriptions.
1865 # Compressed boot loader in ROM. Yes, we really want to ask about
1866 # TEXT and BSS so we preserve their values in the config files.
1867 config ZBOOT_ROM_TEXT
1868 hex "Compressed ROM boot loader base address"
1871 The physical address at which the ROM-able zImage is to be
1872 placed in the target. Platforms which normally make use of
1873 ROM-able zImage formats normally set this to a suitable
1874 value in their defconfig file.
1876 If ZBOOT_ROM is not enabled, this has no effect.
1878 config ZBOOT_ROM_BSS
1879 hex "Compressed ROM boot loader BSS address"
1882 The base address of an area of read/write memory in the target
1883 for the ROM-able zImage which must be available while the
1884 decompressor is running. It must be large enough to hold the
1885 entire decompressed kernel plus an additional 128 KiB.
1886 Platforms which normally make use of ROM-able zImage formats
1887 normally set this to a suitable value in their defconfig file.
1889 If ZBOOT_ROM is not enabled, this has no effect.
1892 bool "Compressed boot loader in ROM/flash"
1893 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1895 Say Y here if you intend to execute your compressed kernel image
1896 (zImage) directly from ROM or flash. If unsure, say N.
1899 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1900 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1901 default ZBOOT_ROM_NONE
1903 Include experimental SD/MMC loading code in the ROM-able zImage.
1904 With this enabled it is possible to write the ROM-able zImage
1905 kernel image to an MMC or SD card and boot the kernel straight
1906 from the reset vector. At reset the processor Mask ROM will load
1907 the first part of the ROM-able zImage which in turn loads the
1908 rest the kernel image to RAM.
1910 config ZBOOT_ROM_NONE
1911 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1913 Do not load image from SD or MMC
1915 config ZBOOT_ROM_MMCIF
1916 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1918 Load image from MMCIF hardware block.
1920 config ZBOOT_ROM_SH_MOBILE_SDHI
1921 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1923 Load image from SDHI hardware block
1927 config ARM_APPENDED_DTB
1928 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1929 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1931 With this option, the boot code will look for a device tree binary
1932 (DTB) appended to zImage
1933 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1935 This is meant as a backward compatibility convenience for those
1936 systems with a bootloader that can't be upgraded to accommodate
1937 the documented boot protocol using a device tree.
1939 Beware that there is very little in terms of protection against
1940 this option being confused by leftover garbage in memory that might
1941 look like a DTB header after a reboot if no actual DTB is appended
1942 to zImage. Do not leave this option active in a production kernel
1943 if you don't intend to always append a DTB. Proper passing of the
1944 location into r2 of a bootloader provided DTB is always preferable
1947 config ARM_ATAG_DTB_COMPAT
1948 bool "Supplement the appended DTB with traditional ATAG information"
1949 depends on ARM_APPENDED_DTB
1951 Some old bootloaders can't be updated to a DTB capable one, yet
1952 they provide ATAGs with memory configuration, the ramdisk address,
1953 the kernel cmdline string, etc. Such information is dynamically
1954 provided by the bootloader and can't always be stored in a static
1955 DTB. To allow a device tree enabled kernel to be used with such
1956 bootloaders, this option allows zImage to extract the information
1957 from the ATAG list and store it at run time into the appended DTB.
1960 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1961 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1963 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1964 bool "Use bootloader kernel arguments if available"
1966 Uses the command-line options passed by the boot loader instead of
1967 the device tree bootargs property. If the boot loader doesn't provide
1968 any, the device tree bootargs property will be used.
1970 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1971 bool "Extend with bootloader kernel arguments"
1973 The command-line arguments provided by the boot loader will be
1974 appended to the the device tree bootargs property.
1979 string "Default kernel command string"
1982 On some architectures (EBSA110 and CATS), there is currently no way
1983 for the boot loader to pass arguments to the kernel. For these
1984 architectures, you should supply some command-line options at build
1985 time by entering them here. As a minimum, you should specify the
1986 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1989 prompt "Kernel command line type" if CMDLINE != ""
1990 default CMDLINE_FROM_BOOTLOADER
1992 config CMDLINE_FROM_BOOTLOADER
1993 bool "Use bootloader kernel arguments if available"
1995 Uses the command-line options passed by the boot loader. If
1996 the boot loader doesn't provide any, the default kernel command
1997 string provided in CMDLINE will be used.
1999 config CMDLINE_EXTEND
2000 bool "Extend bootloader kernel arguments"
2002 The command-line arguments provided by the boot loader will be
2003 appended to the default kernel command string.
2005 config CMDLINE_FORCE
2006 bool "Always use the default kernel command string"
2008 Always use the default kernel command string, even if the boot
2009 loader passes other arguments to the kernel.
2010 This is useful if you cannot or don't want to change the
2011 command-line options your boot loader passes to the kernel.
2015 bool "Kernel Execute-In-Place from ROM"
2016 depends on !ZBOOT_ROM && !ARM_LPAE
2018 Execute-In-Place allows the kernel to run from non-volatile storage
2019 directly addressable by the CPU, such as NOR flash. This saves RAM
2020 space since the text section of the kernel is not loaded from flash
2021 to RAM. Read-write sections, such as the data section and stack,
2022 are still copied to RAM. The XIP kernel is not compressed since
2023 it has to run directly from flash, so it will take more space to
2024 store it. The flash address used to link the kernel object files,
2025 and for storing it, is configuration dependent. Therefore, if you
2026 say Y here, you must know the proper physical address where to
2027 store the kernel image depending on your own flash memory usage.
2029 Also note that the make target becomes "make xipImage" rather than
2030 "make zImage" or "make Image". The final kernel binary to put in
2031 ROM memory will be arch/arm/boot/xipImage.
2035 config XIP_PHYS_ADDR
2036 hex "XIP Kernel Physical Location"
2037 depends on XIP_KERNEL
2038 default "0x00080000"
2040 This is the physical address in your flash memory the kernel will
2041 be linked for and stored to. This address is dependent on your
2045 bool "Kexec system call (EXPERIMENTAL)"
2046 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2048 kexec is a system call that implements the ability to shutdown your
2049 current kernel, and to start another kernel. It is like a reboot
2050 but it is independent of the system firmware. And like a reboot
2051 you can start any kernel with it, not just Linux.
2053 It is an ongoing process to be certain the hardware in a machine
2054 is properly shutdown, so do not be surprised if this code does not
2055 initially work for you. It may help to enable device hotplugging
2059 bool "Export atags in procfs"
2063 Should the atags used to boot the kernel be exported in an "atags"
2064 file in procfs. Useful with kexec.
2067 bool "Build kdump crash kernel (EXPERIMENTAL)"
2068 depends on EXPERIMENTAL
2070 Generate crash dump after being started by kexec. This should
2071 be normally only set in special crash dump kernels which are
2072 loaded in the main kernel with kexec-tools into a specially
2073 reserved region and then later executed after a crash by
2074 kdump/kexec. The crash dump kernel must be compiled to a
2075 memory address not used by the main kernel
2077 For more details see Documentation/kdump/kdump.txt
2079 config AUTO_ZRELADDR
2080 bool "Auto calculation of the decompressed kernel image address"
2081 depends on !ZBOOT_ROM && !ARCH_U300
2083 ZRELADDR is the physical address where the decompressed kernel
2084 image will be placed. If AUTO_ZRELADDR is selected, the address
2085 will be determined at run-time by masking the current IP with
2086 0xf8000000. This assumes the zImage being placed in the first 128MB
2087 from start of memory.
2091 menu "CPU Power Management"
2095 source "drivers/cpufreq/Kconfig"
2098 tristate "CPUfreq driver for i.MX CPUs"
2099 depends on ARCH_MXC && CPU_FREQ
2101 This enables the CPUfreq driver for i.MX CPUs.
2103 config CPU_FREQ_SA1100
2106 config CPU_FREQ_SA1110
2109 config CPU_FREQ_INTEGRATOR
2110 tristate "CPUfreq driver for ARM Integrator CPUs"
2111 depends on ARCH_INTEGRATOR && CPU_FREQ
2114 This enables the CPUfreq driver for ARM Integrator CPUs.
2116 For details, take a look at <file:Documentation/cpu-freq>.
2122 depends on CPU_FREQ && ARCH_PXA && PXA25x
2124 select CPU_FREQ_TABLE
2125 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2130 Internal configuration node for common cpufreq on Samsung SoC
2132 config CPU_FREQ_S3C24XX
2133 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2134 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2137 This enables the CPUfreq driver for the Samsung S3C24XX family
2140 For details, take a look at <file:Documentation/cpu-freq>.
2144 config CPU_FREQ_S3C24XX_PLL
2145 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2146 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2148 Compile in support for changing the PLL frequency from the
2149 S3C24XX series CPUfreq driver. The PLL takes time to settle
2150 after a frequency change, so by default it is not enabled.
2152 This also means that the PLL tables for the selected CPU(s) will
2153 be built which may increase the size of the kernel image.
2155 config CPU_FREQ_S3C24XX_DEBUG
2156 bool "Debug CPUfreq Samsung driver core"
2157 depends on CPU_FREQ_S3C24XX
2159 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2161 config CPU_FREQ_S3C24XX_IODEBUG
2162 bool "Debug CPUfreq Samsung driver IO timing"
2163 depends on CPU_FREQ_S3C24XX
2165 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2167 config CPU_FREQ_S3C24XX_DEBUGFS
2168 bool "Export debugfs for CPUFreq"
2169 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2171 Export status information via debugfs.
2175 source "drivers/cpuidle/Kconfig"
2179 menu "Floating point emulation"
2181 comment "At least one emulation must be selected"
2184 bool "NWFPE math emulation"
2185 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2187 Say Y to include the NWFPE floating point emulator in the kernel.
2188 This is necessary to run most binaries. Linux does not currently
2189 support floating point hardware so you need to say Y here even if
2190 your machine has an FPA or floating point co-processor podule.
2192 You may say N here if you are going to load the Acorn FPEmulator
2193 early in the bootup.
2196 bool "Support extended precision"
2197 depends on FPE_NWFPE
2199 Say Y to include 80-bit support in the kernel floating-point
2200 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2201 Note that gcc does not generate 80-bit operations by default,
2202 so in most cases this option only enlarges the size of the
2203 floating point emulator without any good reason.
2205 You almost surely want to say N here.
2208 bool "FastFPE math emulation (EXPERIMENTAL)"
2209 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2211 Say Y here to include the FAST floating point emulator in the kernel.
2212 This is an experimental much faster emulator which now also has full
2213 precision for the mantissa. It does not support any exceptions.
2214 It is very simple, and approximately 3-6 times faster than NWFPE.
2216 It should be sufficient for most programs. It may be not suitable
2217 for scientific calculations, but you have to check this for yourself.
2218 If you do not feel you need a faster FP emulation you should better
2222 bool "VFP-format floating point maths"
2223 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2225 Say Y to include VFP support code in the kernel. This is needed
2226 if your hardware includes a VFP unit.
2228 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2229 release notes and additional status information.
2231 Say N if your target does not have VFP hardware.
2239 bool "Advanced SIMD (NEON) Extension support"
2240 depends on VFPv3 && CPU_V7
2242 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2247 menu "Userspace binary formats"
2249 source "fs/Kconfig.binfmt"
2252 tristate "RISC OS personality"
2255 Say Y here to include the kernel code necessary if you want to run
2256 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2257 experimental; if this sounds frightening, say N and sleep in peace.
2258 You can also say M here to compile this support as a module (which
2259 will be called arthur).
2263 menu "Power management options"
2265 source "kernel/power/Kconfig"
2267 config ARCH_SUSPEND_POSSIBLE
2268 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2269 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2270 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2273 config ARM_CPU_SUSPEND
2278 source "net/Kconfig"
2280 source "drivers/Kconfig"
2284 source "arch/arm/Kconfig.debug"
2286 source "security/Kconfig"
2288 source "crypto/Kconfig"
2290 source "lib/Kconfig"