4 select ARCH_CLOCKSOURCE_DATA
5 select ARCH_HAS_DEBUG_VIRTUAL
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_SET_MEMORY
9 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
10 select ARCH_HAS_STRICT_MODULE_RWX if MMU
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_HAVE_CUSTOM_GPIO_H
13 select ARCH_HAS_GCOV_PROFILE_ALL
14 select ARCH_MIGHT_HAVE_PC_PARPORT
15 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
16 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
17 select ARCH_SUPPORTS_ATOMIC_RMW
18 select ARCH_USE_BUILTIN_BSWAP
19 select ARCH_USE_CMPXCHG_LOCKREF
20 select ARCH_WANT_IPC_PARSE_VERSION
21 select BUILDTIME_EXTABLE_SORT if MMU
22 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
26 select EDAC_ATOMIC_SCRUB
27 select GENERIC_ALLOCATOR
28 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
29 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
30 select GENERIC_CPU_AUTOPROBE
31 select GENERIC_EARLY_IOREMAP
32 select GENERIC_IDLE_POLL_SETUP
33 select GENERIC_IRQ_PROBE
34 select GENERIC_IRQ_SHOW
35 select GENERIC_IRQ_SHOW_LEVEL
36 select GENERIC_PCI_IOMAP
37 select GENERIC_SCHED_CLOCK
38 select GENERIC_SMP_IDLE_THREAD
39 select GENERIC_STRNCPY_FROM_USER
40 select GENERIC_STRNLEN_USER
41 select HANDLE_DOMAIN_IRQ
42 select HARDIRQS_SW_RESEND
43 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
44 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
45 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
46 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
47 select HAVE_ARCH_MMAP_RND_BITS if MMU
48 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
49 select HAVE_ARCH_TRACEHOOK
50 select HAVE_ARM_SMCCC if CPU_V7
52 select HAVE_CC_STACKPROTECTOR
53 select HAVE_CONTEXT_TRACKING
54 select HAVE_C_RECORDMCOUNT
55 select HAVE_DEBUG_KMEMLEAK
56 select HAVE_DMA_API_DEBUG
57 select HAVE_DMA_CONTIGUOUS if MMU
58 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
59 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
60 select HAVE_EXIT_THREAD
61 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
62 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
63 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
64 select HAVE_GCC_PLUGINS
65 select HAVE_GENERIC_DMA_COHERENT
66 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
67 select HAVE_IDE if PCI || ISA || PCMCIA
68 select HAVE_IRQ_TIME_ACCOUNTING
69 select HAVE_KERNEL_GZIP
70 select HAVE_KERNEL_LZ4
71 select HAVE_KERNEL_LZMA
72 select HAVE_KERNEL_LZO
74 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
75 select HAVE_KRETPROBES if (HAVE_KPROBES)
77 select HAVE_MOD_ARCH_SPECIFIC
79 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
80 select HAVE_OPTPROBES if !THUMB2_KERNEL
81 select HAVE_PERF_EVENTS
83 select HAVE_PERF_USER_STACK_DUMP
84 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
85 select HAVE_REGS_AND_STACK_ACCESS_API
86 select HAVE_SYSCALL_TRACEPOINTS
88 select HAVE_VIRT_CPU_ACCOUNTING_GEN
89 select IRQ_FORCED_THREADING
90 select MODULES_USE_ELF_REL
92 select OF_EARLY_FLATTREE if OF
93 select OF_RESERVED_MEM if OF
95 select OLD_SIGSUSPEND3
96 select PERF_USE_VMALLOC
98 select SYS_SUPPORTS_APM_EMULATION
99 # Above selects are sorted alphabetically; please add new ones
100 # according to that. Thanks.
102 The ARM series is a line of low-power-consumption RISC chip designs
103 licensed by ARM Ltd and targeted at embedded applications and
104 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
105 manufactured, but legacy ARM-based PC hardware remains popular in
106 Europe. There is an ARM Linux project with a web page at
107 <http://www.arm.linux.org.uk/>.
109 config ARM_HAS_SG_CHAIN
110 select ARCH_HAS_SG_CHAIN
113 config NEED_SG_DMA_LENGTH
116 config ARM_DMA_USE_IOMMU
118 select ARM_HAS_SG_CHAIN
119 select NEED_SG_DMA_LENGTH
123 config ARM_DMA_IOMMU_ALIGNMENT
124 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
128 DMA mapping framework by default aligns all buffers to the smallest
129 PAGE_SIZE order which is greater than or equal to the requested buffer
130 size. This works well for buffers up to a few hundreds kilobytes, but
131 for larger buffers it just a waste of address space. Drivers which has
132 relatively small addressing window (like 64Mib) might run out of
133 virtual space with just a few allocations.
135 With this parameter you can specify the maximum PAGE_SIZE order for
136 DMA IOMMU buffers. Larger buffers will be aligned only to this
137 specified order. The order is expressed as a power of two multiplied
142 config MIGHT_HAVE_PCI
145 config SYS_SUPPORTS_APM_EMULATION
150 select GENERIC_ALLOCATOR
161 The Extended Industry Standard Architecture (EISA) bus was
162 developed as an open alternative to the IBM MicroChannel bus.
164 The EISA bus provided some of the features of the IBM MicroChannel
165 bus while maintaining backward compatibility with cards made for
166 the older ISA bus. The EISA bus saw limited use between 1988 and
167 1995 when it was made obsolete by the PCI bus.
169 Say Y here if you are building a kernel for an EISA-based machine.
176 config STACKTRACE_SUPPORT
180 config LOCKDEP_SUPPORT
184 config TRACE_IRQFLAGS_SUPPORT
188 config RWSEM_XCHGADD_ALGORITHM
192 config ARCH_HAS_ILOG2_U32
195 config ARCH_HAS_ILOG2_U64
198 config ARCH_HAS_BANDGAP
201 config FIX_EARLYCON_MEM
204 config GENERIC_HWEIGHT
208 config GENERIC_CALIBRATE_DELAY
212 config ARCH_MAY_HAVE_PC_FDC
218 config NEED_DMA_MAP_STATE
221 config ARCH_SUPPORTS_UPROBES
224 config ARCH_HAS_DMA_SET_COHERENT_MASK
227 config GENERIC_ISA_DMA
233 config NEED_RET_TO_USER
241 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
242 default DRAM_BASE if REMAP_VECTORS_TO_RAM
245 The base address of exception vectors. This must be two pages
248 config ARM_PATCH_PHYS_VIRT
249 bool "Patch physical to virtual translations at runtime" if EMBEDDED
251 depends on !XIP_KERNEL && MMU
253 Patch phys-to-virt and virt-to-phys translation functions at
254 boot and module load time according to the position of the
255 kernel in system memory.
257 This can only be used with non-XIP MMU kernels where the base
258 of physical memory is at a 16MB boundary.
260 Only disable this option if you know that you do not require
261 this feature (eg, building a kernel for a single machine) and
262 you need to shrink the kernel to the minimal size.
264 config NEED_MACH_IO_H
267 Select this when mach/io.h is required to provide special
268 definitions for this platform. The need for mach/io.h should
269 be avoided when possible.
271 config NEED_MACH_MEMORY_H
274 Select this when mach/memory.h is required to provide special
275 definitions for this platform. The need for mach/memory.h should
276 be avoided when possible.
279 hex "Physical address of main memory" if MMU
280 depends on !ARM_PATCH_PHYS_VIRT
281 default DRAM_BASE if !MMU
282 default 0x00000000 if ARCH_EBSA110 || \
288 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
289 default 0x20000000 if ARCH_S5PV210
290 default 0xc0000000 if ARCH_SA1100
292 Please provide the physical address corresponding to the
293 location of main memory in your system.
299 config PGTABLE_LEVELS
301 default 3 if ARM_LPAE
304 source "init/Kconfig"
306 source "kernel/Kconfig.freezer"
311 bool "MMU-based Paged Memory Management Support"
314 Select if you want MMU-based virtualised addressing space
315 support by paged memory management. If unsure, say 'Y'.
317 config ARCH_MMAP_RND_BITS_MIN
320 config ARCH_MMAP_RND_BITS_MAX
321 default 14 if PAGE_OFFSET=0x40000000
322 default 15 if PAGE_OFFSET=0x80000000
326 # The "ARM system type" choice list is ordered alphabetically by option
327 # text. Please add new entries in the option alphabetic order.
330 prompt "ARM system type"
331 default ARM_SINGLE_ARMV7M if !MMU
332 default ARCH_MULTIPLATFORM if MMU
334 config ARCH_MULTIPLATFORM
335 bool "Allow multiple platforms to be selected"
337 select ARM_HAS_SG_CHAIN
338 select ARM_PATCH_PHYS_VIRT
342 select GENERIC_CLOCKEVENTS
343 select MIGHT_HAVE_PCI
344 select MULTI_IRQ_HANDLER
345 select PCI_DOMAINS if PCI
349 config ARM_SINGLE_ARMV7M
350 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
357 select GENERIC_CLOCKEVENTS
364 select ARCH_USES_GETTIMEOFFSET
367 select NEED_MACH_IO_H
368 select NEED_MACH_MEMORY_H
371 This is an evaluation board for the StrongARM processor available
372 from Digital. It has limited hardware on-board, including an
373 Ethernet interface, two PCMCIA sockets, two serial ports and a
378 select ARCH_HAS_HOLES_MEMORYMODEL
380 select ARM_PATCH_PHYS_VIRT
386 select GENERIC_CLOCKEVENTS
389 This enables support for the Cirrus EP93xx series of CPUs.
391 config ARCH_FOOTBRIDGE
395 select GENERIC_CLOCKEVENTS
397 select NEED_MACH_IO_H if !MMU
398 select NEED_MACH_MEMORY_H
400 Support for systems based on the DC21285 companion chip
401 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
404 bool "Hilscher NetX based"
408 select GENERIC_CLOCKEVENTS
410 This enables support for systems based on the Hilscher NetX Soc
416 select NEED_MACH_MEMORY_H
417 select NEED_RET_TO_USER
423 Support for Intel's IOP13XX (XScale) family of processors.
431 select NEED_RET_TO_USER
435 Support for Intel's 80219 and IOP32X (XScale) family of
444 select NEED_RET_TO_USER
448 Support for Intel's IOP33X (XScale) family of processors.
453 select ARCH_HAS_DMA_SET_COHERENT_MASK
454 select ARCH_SUPPORTS_BIG_ENDIAN
457 select DMABOUNCE if PCI
458 select GENERIC_CLOCKEVENTS
460 select MIGHT_HAVE_PCI
461 select NEED_MACH_IO_H
462 select USB_EHCI_BIG_ENDIAN_DESC
463 select USB_EHCI_BIG_ENDIAN_MMIO
465 Support for Intel's IXP4XX (XScale) family of processors.
470 select GENERIC_CLOCKEVENTS
472 select MIGHT_HAVE_PCI
473 select MULTI_IRQ_HANDLER
477 select PLAT_ORION_LEGACY
479 select PM_GENERIC_DOMAINS if PM
481 Support for the Marvell Dove SoC 88AP510
484 bool "Micrel/Kendin KS8695"
487 select GENERIC_CLOCKEVENTS
489 select NEED_MACH_MEMORY_H
491 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
492 System-on-Chip devices.
495 bool "Nuvoton W90X900 CPU"
499 select GENERIC_CLOCKEVENTS
502 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
503 At present, the w90x900 has been renamed nuc900, regarding
504 the ARM series product line, you can login the following
505 link address to know more.
507 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
508 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
514 select CLKSRC_LPC32XX
517 select GENERIC_CLOCKEVENTS
519 select MULTI_IRQ_HANDLER
523 Support for the NXP LPC32XX family of processors
526 bool "PXA2xx/PXA3xx-based"
529 select ARM_CPU_SUSPEND if PM
536 select CPU_XSCALE if !CPU_XSC3
537 select GENERIC_CLOCKEVENTS
542 select MULTI_IRQ_HANDLER
546 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
552 select ARCH_MAY_HAVE_PC_FDC
553 select ARCH_SPARSEMEM_ENABLE
554 select ARCH_USES_GETTIMEOFFSET
558 select HAVE_PATA_PLATFORM
560 select NEED_MACH_IO_H
561 select NEED_MACH_MEMORY_H
564 On the Acorn Risc-PC, Linux can support the internal IDE disk and
565 CD-ROM interface, serial and parallel port, and the floppy drive.
570 select ARCH_SPARSEMEM_ENABLE
574 select CLKSRC_OF if OF
577 select GENERIC_CLOCKEVENTS
582 select MULTI_IRQ_HANDLER
583 select NEED_MACH_MEMORY_H
586 Support for StrongARM 11x0 based boards.
589 bool "Samsung S3C24XX SoCs"
592 select CLKSRC_SAMSUNG_PWM
593 select GENERIC_CLOCKEVENTS
596 select HAVE_S3C2410_I2C if I2C
597 select HAVE_S3C2410_WATCHDOG if WATCHDOG
598 select HAVE_S3C_RTC if RTC_CLASS
599 select MULTI_IRQ_HANDLER
600 select NEED_MACH_IO_H
603 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
604 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
605 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
606 Samsung SMDK2410 development board (and derivatives).
610 select ARCH_HAS_HOLES_MEMORYMODEL
613 select GENERIC_ALLOCATOR
614 select GENERIC_CLOCKEVENTS
615 select GENERIC_IRQ_CHIP
621 Support for TI's DaVinci platform.
626 select ARCH_HAS_HOLES_MEMORYMODEL
630 select GENERIC_CLOCKEVENTS
631 select GENERIC_IRQ_CHIP
635 select MULTI_IRQ_HANDLER
636 select NEED_MACH_IO_H if PCCARD
637 select NEED_MACH_MEMORY_H
640 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
644 menu "Multiple platform selection"
645 depends on ARCH_MULTIPLATFORM
647 comment "CPU Core family selection"
650 bool "ARMv4 based platforms (FA526)"
651 depends on !ARCH_MULTI_V6_V7
652 select ARCH_MULTI_V4_V5
655 config ARCH_MULTI_V4T
656 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
657 depends on !ARCH_MULTI_V6_V7
658 select ARCH_MULTI_V4_V5
659 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
660 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
661 CPU_ARM925T || CPU_ARM940T)
664 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
665 depends on !ARCH_MULTI_V6_V7
666 select ARCH_MULTI_V4_V5
667 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
668 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
669 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
671 config ARCH_MULTI_V4_V5
675 bool "ARMv6 based platforms (ARM11)"
676 select ARCH_MULTI_V6_V7
680 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
682 select ARCH_MULTI_V6_V7
686 config ARCH_MULTI_V6_V7
688 select MIGHT_HAVE_CACHE_L2X0
690 config ARCH_MULTI_CPU_AUTO
691 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
697 bool "Dummy Virtual Machine"
698 depends on ARCH_MULTI_V7
701 select ARM_GIC_V2M if PCI
703 select ARM_GIC_V3_ITS if PCI
705 select HAVE_ARM_ARCH_TIMER
708 # This is sorted alphabetically by mach-* pathname. However, plat-*
709 # Kconfigs may be included either alphabetically (according to the
710 # plat- suffix) or along side the corresponding mach-* source.
712 source "arch/arm/mach-mvebu/Kconfig"
714 source "arch/arm/mach-alpine/Kconfig"
716 source "arch/arm/mach-artpec/Kconfig"
718 source "arch/arm/mach-asm9260/Kconfig"
720 source "arch/arm/mach-at91/Kconfig"
722 source "arch/arm/mach-axxia/Kconfig"
724 source "arch/arm/mach-bcm/Kconfig"
726 source "arch/arm/mach-berlin/Kconfig"
728 source "arch/arm/mach-clps711x/Kconfig"
730 source "arch/arm/mach-cns3xxx/Kconfig"
732 source "arch/arm/mach-davinci/Kconfig"
734 source "arch/arm/mach-digicolor/Kconfig"
736 source "arch/arm/mach-dove/Kconfig"
738 source "arch/arm/mach-ep93xx/Kconfig"
740 source "arch/arm/mach-footbridge/Kconfig"
742 source "arch/arm/mach-gemini/Kconfig"
744 source "arch/arm/mach-highbank/Kconfig"
746 source "arch/arm/mach-hisi/Kconfig"
748 source "arch/arm/mach-integrator/Kconfig"
750 source "arch/arm/mach-iop32x/Kconfig"
752 source "arch/arm/mach-iop33x/Kconfig"
754 source "arch/arm/mach-iop13xx/Kconfig"
756 source "arch/arm/mach-ixp4xx/Kconfig"
758 source "arch/arm/mach-keystone/Kconfig"
760 source "arch/arm/mach-ks8695/Kconfig"
762 source "arch/arm/mach-meson/Kconfig"
764 source "arch/arm/mach-moxart/Kconfig"
766 source "arch/arm/mach-aspeed/Kconfig"
768 source "arch/arm/mach-mv78xx0/Kconfig"
770 source "arch/arm/mach-imx/Kconfig"
772 source "arch/arm/mach-mediatek/Kconfig"
774 source "arch/arm/mach-mxs/Kconfig"
776 source "arch/arm/mach-netx/Kconfig"
778 source "arch/arm/mach-nomadik/Kconfig"
780 source "arch/arm/mach-nspire/Kconfig"
782 source "arch/arm/plat-omap/Kconfig"
784 source "arch/arm/mach-omap1/Kconfig"
786 source "arch/arm/mach-omap2/Kconfig"
788 source "arch/arm/mach-orion5x/Kconfig"
790 source "arch/arm/mach-picoxcell/Kconfig"
792 source "arch/arm/mach-pxa/Kconfig"
793 source "arch/arm/plat-pxa/Kconfig"
795 source "arch/arm/mach-mmp/Kconfig"
797 source "arch/arm/mach-oxnas/Kconfig"
799 source "arch/arm/mach-qcom/Kconfig"
801 source "arch/arm/mach-realview/Kconfig"
803 source "arch/arm/mach-rockchip/Kconfig"
805 source "arch/arm/mach-sa1100/Kconfig"
807 source "arch/arm/mach-socfpga/Kconfig"
809 source "arch/arm/mach-spear/Kconfig"
811 source "arch/arm/mach-sti/Kconfig"
813 source "arch/arm/mach-stm32/Kconfig"
815 source "arch/arm/mach-s3c24xx/Kconfig"
817 source "arch/arm/mach-s3c64xx/Kconfig"
819 source "arch/arm/mach-s5pv210/Kconfig"
821 source "arch/arm/mach-exynos/Kconfig"
822 source "arch/arm/plat-samsung/Kconfig"
824 source "arch/arm/mach-shmobile/Kconfig"
826 source "arch/arm/mach-sunxi/Kconfig"
828 source "arch/arm/mach-prima2/Kconfig"
830 source "arch/arm/mach-tango/Kconfig"
832 source "arch/arm/mach-tegra/Kconfig"
834 source "arch/arm/mach-u300/Kconfig"
836 source "arch/arm/mach-uniphier/Kconfig"
838 source "arch/arm/mach-ux500/Kconfig"
840 source "arch/arm/mach-versatile/Kconfig"
842 source "arch/arm/mach-vexpress/Kconfig"
843 source "arch/arm/plat-versatile/Kconfig"
845 source "arch/arm/mach-vt8500/Kconfig"
847 source "arch/arm/mach-w90x900/Kconfig"
849 source "arch/arm/mach-zx/Kconfig"
851 source "arch/arm/mach-zynq/Kconfig"
853 # ARMv7-M architecture
855 bool "Energy Micro efm32"
856 depends on ARM_SINGLE_ARMV7M
859 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
863 bool "NXP LPC18xx/LPC43xx"
864 depends on ARM_SINGLE_ARMV7M
865 select ARCH_HAS_RESET_CONTROLLER
867 select CLKSRC_LPC32XX
870 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
871 high performance microcontrollers.
874 bool "ARM MPS2 platform"
875 depends on ARM_SINGLE_ARMV7M
879 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
880 with a range of available cores like Cortex-M3/M4/M7.
882 Please, note that depends which Application Note is used memory map
883 for the platform may vary, so adjustment of RAM base might be needed.
885 # Definitions to make life easier
891 select GENERIC_CLOCKEVENTS
897 select GENERIC_IRQ_CHIP
900 config PLAT_ORION_LEGACY
907 config PLAT_VERSATILE
910 source "arch/arm/firmware/Kconfig"
912 source arch/arm/mm/Kconfig
915 bool "Enable iWMMXt support"
916 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
917 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
919 Enable support for iWMMXt context switching at run time if
920 running on a CPU that supports it.
922 config MULTI_IRQ_HANDLER
925 Allow each machine to specify it's own IRQ handler at run time.
928 source "arch/arm/Kconfig-nommu"
931 config PJ4B_ERRATA_4742
932 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
933 depends on CPU_PJ4B && MACH_ARMADA_370
936 When coming out of either a Wait for Interrupt (WFI) or a Wait for
937 Event (WFE) IDLE states, a specific timing sensitivity exists between
938 the retiring WFI/WFE instructions and the newly issued subsequent
939 instructions. This sensitivity can result in a CPU hang scenario.
941 The software must insert either a Data Synchronization Barrier (DSB)
942 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
945 config ARM_ERRATA_326103
946 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
949 Executing a SWP instruction to read-only memory does not set bit 11
950 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
951 treat the access as a read, preventing a COW from occurring and
952 causing the faulting task to livelock.
954 config ARM_ERRATA_411920
955 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
956 depends on CPU_V6 || CPU_V6K
958 Invalidation of the Instruction Cache operation can
959 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
960 It does not affect the MPCore. This option enables the ARM Ltd.
961 recommended workaround.
963 config ARM_ERRATA_430973
964 bool "ARM errata: Stale prediction on replaced interworking branch"
967 This option enables the workaround for the 430973 Cortex-A8
968 r1p* erratum. If a code sequence containing an ARM/Thumb
969 interworking branch is replaced with another code sequence at the
970 same virtual address, whether due to self-modifying code or virtual
971 to physical address re-mapping, Cortex-A8 does not recover from the
972 stale interworking branch prediction. This results in Cortex-A8
973 executing the new code sequence in the incorrect ARM or Thumb state.
974 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
975 and also flushes the branch target cache at every context switch.
976 Note that setting specific bits in the ACTLR register may not be
977 available in non-secure mode.
979 config ARM_ERRATA_458693
980 bool "ARM errata: Processor deadlock when a false hazard is created"
982 depends on !ARCH_MULTIPLATFORM
984 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
985 erratum. For very specific sequences of memory operations, it is
986 possible for a hazard condition intended for a cache line to instead
987 be incorrectly associated with a different cache line. This false
988 hazard might then cause a processor deadlock. The workaround enables
989 the L1 caching of the NEON accesses and disables the PLD instruction
990 in the ACTLR register. Note that setting specific bits in the ACTLR
991 register may not be available in non-secure mode.
993 config ARM_ERRATA_460075
994 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
996 depends on !ARCH_MULTIPLATFORM
998 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
999 erratum. Any asynchronous access to the L2 cache may encounter a
1000 situation in which recent store transactions to the L2 cache are lost
1001 and overwritten with stale memory contents from external memory. The
1002 workaround disables the write-allocate mode for the L2 cache via the
1003 ACTLR register. Note that setting specific bits in the ACTLR register
1004 may not be available in non-secure mode.
1006 config ARM_ERRATA_742230
1007 bool "ARM errata: DMB operation may be faulty"
1008 depends on CPU_V7 && SMP
1009 depends on !ARCH_MULTIPLATFORM
1011 This option enables the workaround for the 742230 Cortex-A9
1012 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1013 between two write operations may not ensure the correct visibility
1014 ordering of the two writes. This workaround sets a specific bit in
1015 the diagnostic register of the Cortex-A9 which causes the DMB
1016 instruction to behave as a DSB, ensuring the correct behaviour of
1019 config ARM_ERRATA_742231
1020 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1021 depends on CPU_V7 && SMP
1022 depends on !ARCH_MULTIPLATFORM
1024 This option enables the workaround for the 742231 Cortex-A9
1025 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1026 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1027 accessing some data located in the same cache line, may get corrupted
1028 data due to bad handling of the address hazard when the line gets
1029 replaced from one of the CPUs at the same time as another CPU is
1030 accessing it. This workaround sets specific bits in the diagnostic
1031 register of the Cortex-A9 which reduces the linefill issuing
1032 capabilities of the processor.
1034 config ARM_ERRATA_643719
1035 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1036 depends on CPU_V7 && SMP
1039 This option enables the workaround for the 643719 Cortex-A9 (prior to
1040 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1041 register returns zero when it should return one. The workaround
1042 corrects this value, ensuring cache maintenance operations which use
1043 it behave as intended and avoiding data corruption.
1045 config ARM_ERRATA_720789
1046 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1049 This option enables the workaround for the 720789 Cortex-A9 (prior to
1050 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1051 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1052 As a consequence of this erratum, some TLB entries which should be
1053 invalidated are not, resulting in an incoherency in the system page
1054 tables. The workaround changes the TLB flushing routines to invalidate
1055 entries regardless of the ASID.
1057 config ARM_ERRATA_743622
1058 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1060 depends on !ARCH_MULTIPLATFORM
1062 This option enables the workaround for the 743622 Cortex-A9
1063 (r2p*) erratum. Under very rare conditions, a faulty
1064 optimisation in the Cortex-A9 Store Buffer may lead to data
1065 corruption. This workaround sets a specific bit in the diagnostic
1066 register of the Cortex-A9 which disables the Store Buffer
1067 optimisation, preventing the defect from occurring. This has no
1068 visible impact on the overall performance or power consumption of the
1071 config ARM_ERRATA_751472
1072 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1074 depends on !ARCH_MULTIPLATFORM
1076 This option enables the workaround for the 751472 Cortex-A9 (prior
1077 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1078 completion of a following broadcasted operation if the second
1079 operation is received by a CPU before the ICIALLUIS has completed,
1080 potentially leading to corrupted entries in the cache or TLB.
1082 config ARM_ERRATA_754322
1083 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1086 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1087 r3p*) erratum. A speculative memory access may cause a page table walk
1088 which starts prior to an ASID switch but completes afterwards. This
1089 can populate the micro-TLB with a stale entry which may be hit with
1090 the new ASID. This workaround places two dsb instructions in the mm
1091 switching code so that no page table walks can cross the ASID switch.
1093 config ARM_ERRATA_754327
1094 bool "ARM errata: no automatic Store Buffer drain"
1095 depends on CPU_V7 && SMP
1097 This option enables the workaround for the 754327 Cortex-A9 (prior to
1098 r2p0) erratum. The Store Buffer does not have any automatic draining
1099 mechanism and therefore a livelock may occur if an external agent
1100 continuously polls a memory location waiting to observe an update.
1101 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1102 written polling loops from denying visibility of updates to memory.
1104 config ARM_ERRATA_364296
1105 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1108 This options enables the workaround for the 364296 ARM1136
1109 r0p2 erratum (possible cache data corruption with
1110 hit-under-miss enabled). It sets the undocumented bit 31 in
1111 the auxiliary control register and the FI bit in the control
1112 register, thus disabling hit-under-miss without putting the
1113 processor into full low interrupt latency mode. ARM11MPCore
1116 config ARM_ERRATA_764369
1117 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1118 depends on CPU_V7 && SMP
1120 This option enables the workaround for erratum 764369
1121 affecting Cortex-A9 MPCore with two or more processors (all
1122 current revisions). Under certain timing circumstances, a data
1123 cache line maintenance operation by MVA targeting an Inner
1124 Shareable memory region may fail to proceed up to either the
1125 Point of Coherency or to the Point of Unification of the
1126 system. This workaround adds a DSB instruction before the
1127 relevant cache maintenance functions and sets a specific bit
1128 in the diagnostic control register of the SCU.
1130 config ARM_ERRATA_775420
1131 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1134 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1135 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1136 operation aborts with MMU exception, it might cause the processor
1137 to deadlock. This workaround puts DSB before executing ISB if
1138 an abort may occur on cache maintenance.
1140 config ARM_ERRATA_798181
1141 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1142 depends on CPU_V7 && SMP
1144 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1145 adequately shooting down all use of the old entries. This
1146 option enables the Linux kernel workaround for this erratum
1147 which sends an IPI to the CPUs that are running the same ASID
1148 as the one being invalidated.
1150 config ARM_ERRATA_773022
1151 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1154 This option enables the workaround for the 773022 Cortex-A15
1155 (up to r0p4) erratum. In certain rare sequences of code, the
1156 loop buffer may deliver incorrect instructions. This
1157 workaround disables the loop buffer to avoid the erratum.
1159 config ARM_ERRATA_818325_852422
1160 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1163 This option enables the workaround for:
1164 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1165 instruction might deadlock. Fixed in r0p1.
1166 - Cortex-A12 852422: Execution of a sequence of instructions might
1167 lead to either a data corruption or a CPU deadlock. Not fixed in
1168 any Cortex-A12 cores yet.
1169 This workaround for all both errata involves setting bit[12] of the
1170 Feature Register. This bit disables an optimisation applied to a
1171 sequence of 2 instructions that use opposing condition codes.
1173 config ARM_ERRATA_821420
1174 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1177 This option enables the workaround for the 821420 Cortex-A12
1178 (all revs) erratum. In very rare timing conditions, a sequence
1179 of VMOV to Core registers instructions, for which the second
1180 one is in the shadow of a branch or abort, can lead to a
1181 deadlock when the VMOV instructions are issued out-of-order.
1183 config ARM_ERRATA_825619
1184 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1187 This option enables the workaround for the 825619 Cortex-A12
1188 (all revs) erratum. Within rare timing constraints, executing a
1189 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1190 and Device/Strongly-Ordered loads and stores might cause deadlock
1192 config ARM_ERRATA_852421
1193 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1196 This option enables the workaround for the 852421 Cortex-A17
1197 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1198 execution of a DMB ST instruction might fail to properly order
1199 stores from GroupA and stores from GroupB.
1201 config ARM_ERRATA_852423
1202 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1205 This option enables the workaround for:
1206 - Cortex-A17 852423: Execution of a sequence of instructions might
1207 lead to either a data corruption or a CPU deadlock. Not fixed in
1208 any Cortex-A17 cores yet.
1209 This is identical to Cortex-A12 erratum 852422. It is a separate
1210 config option from the A12 erratum due to the way errata are checked
1215 source "arch/arm/common/Kconfig"
1222 Find out whether you have ISA slots on your motherboard. ISA is the
1223 name of a bus system, i.e. the way the CPU talks to the other stuff
1224 inside your box. Other bus systems are PCI, EISA, MicroChannel
1225 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1226 newer boards don't support it. If you have ISA, say Y, otherwise N.
1228 # Select ISA DMA controller support
1233 # Select ISA DMA interface
1238 bool "PCI support" if MIGHT_HAVE_PCI
1240 Find out whether you have a PCI motherboard. PCI is the name of a
1241 bus system, i.e. the way the CPU talks to the other stuff inside
1242 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1243 VESA. If you have PCI, say Y, otherwise N.
1249 config PCI_DOMAINS_GENERIC
1250 def_bool PCI_DOMAINS
1252 config PCI_NANOENGINE
1253 bool "BSE nanoEngine PCI support"
1254 depends on SA1100_NANOENGINE
1256 Enable PCI on the BSE nanoEngine board.
1261 config PCI_HOST_ITE8152
1263 depends on PCI && MACH_ARMCORE
1267 source "drivers/pci/Kconfig"
1269 source "drivers/pcmcia/Kconfig"
1273 menu "Kernel Features"
1278 This option should be selected by machines which have an SMP-
1281 The only effect of this option is to make the SMP-related
1282 options available to the user for configuration.
1285 bool "Symmetric Multi-Processing"
1286 depends on CPU_V6K || CPU_V7
1287 depends on GENERIC_CLOCKEVENTS
1289 depends on MMU || ARM_MPU
1292 This enables support for systems with more than one CPU. If you have
1293 a system with only one CPU, say N. If you have a system with more
1294 than one CPU, say Y.
1296 If you say N here, the kernel will run on uni- and multiprocessor
1297 machines, but will use only one CPU of a multiprocessor machine. If
1298 you say Y here, the kernel will run on many, but not all,
1299 uniprocessor machines. On a uniprocessor machine, the kernel
1300 will run faster if you say N here.
1302 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1303 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1304 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1306 If you don't know what to do here, say N.
1309 bool "Allow booting SMP kernel on uniprocessor systems"
1310 depends on SMP && !XIP_KERNEL && MMU
1313 SMP kernels contain instructions which fail on non-SMP processors.
1314 Enabling this option allows the kernel to modify itself to make
1315 these instructions safe. Disabling it allows about 1K of space
1318 If you don't know what to do here, say Y.
1320 config ARM_CPU_TOPOLOGY
1321 bool "Support cpu topology definition"
1322 depends on SMP && CPU_V7
1325 Support ARM cpu topology definition. The MPIDR register defines
1326 affinity between processors which is then used to describe the cpu
1327 topology of an ARM System.
1330 bool "Multi-core scheduler support"
1331 depends on ARM_CPU_TOPOLOGY
1333 Multi-core scheduler support improves the CPU scheduler's decision
1334 making when dealing with multi-core CPU chips at a cost of slightly
1335 increased overhead in some places. If unsure say N here.
1338 bool "SMT scheduler support"
1339 depends on ARM_CPU_TOPOLOGY
1341 Improves the CPU scheduler's decision making when dealing with
1342 MultiThreading at a cost of slightly increased overhead in some
1343 places. If unsure say N here.
1348 This option enables support for the ARM system coherency unit
1350 config HAVE_ARM_ARCH_TIMER
1351 bool "Architected timer support"
1353 select ARM_ARCH_TIMER
1354 select GENERIC_CLOCKEVENTS
1356 This option enables support for the ARM architected timer
1360 select CLKSRC_OF if OF
1362 This options enables support for the ARM timer and watchdog unit
1365 bool "Multi-Cluster Power Management"
1366 depends on CPU_V7 && SMP
1368 This option provides the common power management infrastructure
1369 for (multi-)cluster based systems, such as big.LITTLE based
1372 config MCPM_QUAD_CLUSTER
1376 To avoid wasting resources unnecessarily, MCPM only supports up
1377 to 2 clusters by default.
1378 Platforms with 3 or 4 clusters that use MCPM must select this
1379 option to allow the additional clusters to be managed.
1382 bool "big.LITTLE support (Experimental)"
1383 depends on CPU_V7 && SMP
1386 This option enables support selections for the big.LITTLE
1387 system architecture.
1390 bool "big.LITTLE switcher support"
1391 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1394 The big.LITTLE "switcher" provides the core functionality to
1395 transparently handle transition between a cluster of A15's
1396 and a cluster of A7's in a big.LITTLE system.
1398 config BL_SWITCHER_DUMMY_IF
1399 tristate "Simple big.LITTLE switcher user interface"
1400 depends on BL_SWITCHER && DEBUG_KERNEL
1402 This is a simple and dummy char dev interface to control
1403 the big.LITTLE switcher core code. It is meant for
1404 debugging purposes only.
1407 prompt "Memory split"
1411 Select the desired split between kernel and user memory.
1413 If you are not absolutely sure what you are doing, leave this
1417 bool "3G/1G user/kernel split"
1418 config VMSPLIT_3G_OPT
1419 depends on !ARM_LPAE
1420 bool "3G/1G user/kernel split (for full 1G low memory)"
1422 bool "2G/2G user/kernel split"
1424 bool "1G/3G user/kernel split"
1429 default PHYS_OFFSET if !MMU
1430 default 0x40000000 if VMSPLIT_1G
1431 default 0x80000000 if VMSPLIT_2G
1432 default 0xB0000000 if VMSPLIT_3G_OPT
1436 int "Maximum number of CPUs (2-32)"
1442 bool "Support for hot-pluggable CPUs"
1445 Say Y here to experiment with turning CPUs off and on. CPUs
1446 can be controlled through /sys/devices/system/cpu.
1449 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1450 depends on HAVE_ARM_SMCCC
1453 Say Y here if you want Linux to communicate with system firmware
1454 implementing the PSCI specification for CPU-centric power
1455 management operations described in ARM document number ARM DEN
1456 0022A ("Power State Coordination Interface System Software on
1459 # The GPIO number here must be sorted by descending number. In case of
1460 # a multiplatform kernel, we just want the highest value required by the
1461 # selected platforms.
1464 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1466 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1467 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1468 default 416 if ARCH_SUNXI
1469 default 392 if ARCH_U8500
1470 default 352 if ARCH_VT8500
1471 default 288 if ARCH_ROCKCHIP
1472 default 264 if MACH_H4700
1475 Maximum number of GPIOs in the system.
1477 If unsure, leave the default value.
1479 source kernel/Kconfig.preempt
1483 default 200 if ARCH_EBSA110
1484 default 128 if SOC_AT91RM9200
1488 depends on HZ_FIXED = 0
1489 prompt "Timer frequency"
1513 default HZ_FIXED if HZ_FIXED != 0
1514 default 100 if HZ_100
1515 default 200 if HZ_200
1516 default 250 if HZ_250
1517 default 300 if HZ_300
1518 default 500 if HZ_500
1522 def_bool HIGH_RES_TIMERS
1524 config THUMB2_KERNEL
1525 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1526 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1527 default y if CPU_THUMBONLY
1529 select ARM_ASM_UNIFIED
1532 By enabling this option, the kernel will be compiled in
1533 Thumb-2 mode. A compiler/assembler that understand the unified
1534 ARM-Thumb syntax is needed.
1538 config THUMB2_AVOID_R_ARM_THM_JUMP11
1539 bool "Work around buggy Thumb-2 short branch relocations in gas"
1540 depends on THUMB2_KERNEL && MODULES
1543 Various binutils versions can resolve Thumb-2 branches to
1544 locally-defined, preemptible global symbols as short-range "b.n"
1545 branch instructions.
1547 This is a problem, because there's no guarantee the final
1548 destination of the symbol, or any candidate locations for a
1549 trampoline, are within range of the branch. For this reason, the
1550 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1551 relocation in modules at all, and it makes little sense to add
1554 The symptom is that the kernel fails with an "unsupported
1555 relocation" error when loading some modules.
1557 Until fixed tools are available, passing
1558 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1559 code which hits this problem, at the cost of a bit of extra runtime
1560 stack usage in some cases.
1562 The problem is described in more detail at:
1563 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1565 Only Thumb-2 kernels are affected.
1567 Unless you are sure your tools don't have this problem, say Y.
1569 config ARM_ASM_UNIFIED
1572 config ARM_PATCH_IDIV
1573 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1574 depends on CPU_32v7 && !XIP_KERNEL
1577 The ARM compiler inserts calls to __aeabi_idiv() and
1578 __aeabi_uidiv() when it needs to perform division on signed
1579 and unsigned integers. Some v7 CPUs have support for the sdiv
1580 and udiv instructions that can be used to implement those
1583 Enabling this option allows the kernel to modify itself to
1584 replace the first two instructions of these library functions
1585 with the sdiv or udiv plus "bx lr" instructions when the CPU
1586 it is running on supports them. Typically this will be faster
1587 and less power intensive than running the original library
1588 code to do integer division.
1591 bool "Use the ARM EABI to compile the kernel"
1593 This option allows for the kernel to be compiled using the latest
1594 ARM ABI (aka EABI). This is only useful if you are using a user
1595 space environment that is also compiled with EABI.
1597 Since there are major incompatibilities between the legacy ABI and
1598 EABI, especially with regard to structure member alignment, this
1599 option also changes the kernel syscall calling convention to
1600 disambiguate both ABIs and allow for backward compatibility support
1601 (selected with CONFIG_OABI_COMPAT).
1603 To use this you need GCC version 4.0.0 or later.
1606 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1607 depends on AEABI && !THUMB2_KERNEL
1609 This option preserves the old syscall interface along with the
1610 new (ARM EABI) one. It also provides a compatibility layer to
1611 intercept syscalls that have structure arguments which layout
1612 in memory differs between the legacy ABI and the new ARM EABI
1613 (only for non "thumb" binaries). This option adds a tiny
1614 overhead to all syscalls and produces a slightly larger kernel.
1616 The seccomp filter system will not be available when this is
1617 selected, since there is no way yet to sensibly distinguish
1618 between calling conventions during filtering.
1620 If you know you'll be using only pure EABI user space then you
1621 can say N here. If this option is not selected and you attempt
1622 to execute a legacy ABI binary then the result will be
1623 UNPREDICTABLE (in fact it can be predicted that it won't work
1624 at all). If in doubt say N.
1626 config ARCH_HAS_HOLES_MEMORYMODEL
1629 config ARCH_SPARSEMEM_ENABLE
1632 config ARCH_SPARSEMEM_DEFAULT
1633 def_bool ARCH_SPARSEMEM_ENABLE
1635 config ARCH_SELECT_MEMORY_MODEL
1636 def_bool ARCH_SPARSEMEM_ENABLE
1638 config HAVE_ARCH_PFN_VALID
1639 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1641 config HAVE_GENERIC_RCU_GUP
1646 bool "High Memory Support"
1649 The address space of ARM processors is only 4 Gigabytes large
1650 and it has to accommodate user address space, kernel address
1651 space as well as some memory mapped IO. That means that, if you
1652 have a large amount of physical memory and/or IO, not all of the
1653 memory can be "permanently mapped" by the kernel. The physical
1654 memory that is not permanently mapped is called "high memory".
1656 Depending on the selected kernel/user memory split, minimum
1657 vmalloc space and actual amount of RAM, you may not need this
1658 option which should result in a slightly faster kernel.
1663 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1667 The VM uses one page of physical memory for each page table.
1668 For systems with a lot of processes, this can use a lot of
1669 precious low memory, eventually leading to low memory being
1670 consumed by page tables. Setting this option will allow
1671 user-space 2nd level page tables to reside in high memory.
1673 config CPU_SW_DOMAIN_PAN
1674 bool "Enable use of CPU domains to implement privileged no-access"
1675 depends on MMU && !ARM_LPAE
1678 Increase kernel security by ensuring that normal kernel accesses
1679 are unable to access userspace addresses. This can help prevent
1680 use-after-free bugs becoming an exploitable privilege escalation
1681 by ensuring that magic values (such as LIST_POISON) will always
1682 fault when dereferenced.
1684 CPUs with low-vector mappings use a best-efforts implementation.
1685 Their lower 1MB needs to remain accessible for the vectors, but
1686 the remainder of userspace will become appropriately inaccessible.
1688 config HW_PERF_EVENTS
1692 config SYS_SUPPORTS_HUGETLBFS
1696 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1700 config ARCH_WANT_GENERAL_HUGETLB
1703 config ARM_MODULE_PLTS
1704 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1707 Allocate PLTs when loading modules so that jumps and calls whose
1708 targets are too far away for their relative offsets to be encoded
1709 in the instructions themselves can be bounced via veneers in the
1710 module's PLT. This allows modules to be allocated in the generic
1711 vmalloc area after the dedicated module memory area has been
1712 exhausted. The modules will use slightly more memory, but after
1713 rounding up to page size, the actual memory footprint is usually
1716 Say y if you are getting out of memory errors while loading modules
1720 config FORCE_MAX_ZONEORDER
1721 int "Maximum zone order"
1722 default "12" if SOC_AM33XX
1723 default "9" if SA1111 || ARCH_EFM32
1726 The kernel memory allocator divides physically contiguous memory
1727 blocks into "zones", where each zone is a power of two number of
1728 pages. This option selects the largest power of two that the kernel
1729 keeps in the memory allocator. If you need to allocate very large
1730 blocks of physically contiguous memory, then you may need to
1731 increase this value.
1733 This config option is actually maximum order plus one. For example,
1734 a value of 11 means that the largest free memory block is 2^10 pages.
1736 config ALIGNMENT_TRAP
1738 depends on CPU_CP15_MMU
1739 default y if !ARCH_EBSA110
1740 select HAVE_PROC_CPU if PROC_FS
1742 ARM processors cannot fetch/store information which is not
1743 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1744 address divisible by 4. On 32-bit ARM processors, these non-aligned
1745 fetch/store instructions will be emulated in software if you say
1746 here, which has a severe performance impact. This is necessary for
1747 correct operation of some network protocols. With an IP-only
1748 configuration it is safe to say N, otherwise say Y.
1750 config UACCESS_WITH_MEMCPY
1751 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1753 default y if CPU_FEROCEON
1755 Implement faster copy_to_user and clear_user methods for CPU
1756 cores where a 8-word STM instruction give significantly higher
1757 memory write throughput than a sequence of individual 32bit stores.
1759 A possible side effect is a slight increase in scheduling latency
1760 between threads sharing the same address space if they invoke
1761 such copy operations with large buffers.
1763 However, if the CPU data cache is using a write-allocate mode,
1764 this option is unlikely to provide any performance gain.
1768 prompt "Enable seccomp to safely compute untrusted bytecode"
1770 This kernel feature is useful for number crunching applications
1771 that may need to compute untrusted bytecode during their
1772 execution. By using pipes or other transports made available to
1773 the process as file descriptors supporting the read/write
1774 syscalls, it's possible to isolate those applications in
1775 their own address space using seccomp. Once seccomp is
1776 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1777 and the task is only allowed to execute a few safe syscalls
1778 defined by each seccomp mode.
1787 bool "Enable paravirtualization code"
1789 This changes the kernel so it can modify itself when it is run
1790 under a hypervisor, potentially improving performance significantly
1791 over full virtualization.
1793 config PARAVIRT_TIME_ACCOUNTING
1794 bool "Paravirtual steal time accounting"
1798 Select this option to enable fine granularity task steal time
1799 accounting. Time spent executing other tasks in parallel with
1800 the current vCPU is discounted from the vCPU power. To account for
1801 that, there can be a small performance impact.
1803 If in doubt, say N here.
1810 bool "Xen guest support on ARM"
1811 depends on ARM && AEABI && OF
1812 depends on CPU_V7 && !CPU_V6
1813 depends on !GENERIC_ATOMIC64
1815 select ARCH_DMA_ADDR_T_64BIT
1820 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1827 bool "Flattened Device Tree support"
1831 Include support for flattened device tree machine descriptions.
1834 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1837 This is the traditional way of passing data to the kernel at boot
1838 time. If you are solely relying on the flattened device tree (or
1839 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1840 to remove ATAGS support from your kernel binary. If unsure,
1843 config DEPRECATED_PARAM_STRUCT
1844 bool "Provide old way to pass kernel parameters"
1847 This was deprecated in 2001 and announced to live on for 5 years.
1848 Some old boot loaders still use this way.
1850 # Compressed boot loader in ROM. Yes, we really want to ask about
1851 # TEXT and BSS so we preserve their values in the config files.
1852 config ZBOOT_ROM_TEXT
1853 hex "Compressed ROM boot loader base address"
1856 The physical address at which the ROM-able zImage is to be
1857 placed in the target. Platforms which normally make use of
1858 ROM-able zImage formats normally set this to a suitable
1859 value in their defconfig file.
1861 If ZBOOT_ROM is not enabled, this has no effect.
1863 config ZBOOT_ROM_BSS
1864 hex "Compressed ROM boot loader BSS address"
1867 The base address of an area of read/write memory in the target
1868 for the ROM-able zImage which must be available while the
1869 decompressor is running. It must be large enough to hold the
1870 entire decompressed kernel plus an additional 128 KiB.
1871 Platforms which normally make use of ROM-able zImage formats
1872 normally set this to a suitable value in their defconfig file.
1874 If ZBOOT_ROM is not enabled, this has no effect.
1877 bool "Compressed boot loader in ROM/flash"
1878 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1879 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1881 Say Y here if you intend to execute your compressed kernel image
1882 (zImage) directly from ROM or flash. If unsure, say N.
1884 config ARM_APPENDED_DTB
1885 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1888 With this option, the boot code will look for a device tree binary
1889 (DTB) appended to zImage
1890 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1892 This is meant as a backward compatibility convenience for those
1893 systems with a bootloader that can't be upgraded to accommodate
1894 the documented boot protocol using a device tree.
1896 Beware that there is very little in terms of protection against
1897 this option being confused by leftover garbage in memory that might
1898 look like a DTB header after a reboot if no actual DTB is appended
1899 to zImage. Do not leave this option active in a production kernel
1900 if you don't intend to always append a DTB. Proper passing of the
1901 location into r2 of a bootloader provided DTB is always preferable
1904 config ARM_ATAG_DTB_COMPAT
1905 bool "Supplement the appended DTB with traditional ATAG information"
1906 depends on ARM_APPENDED_DTB
1908 Some old bootloaders can't be updated to a DTB capable one, yet
1909 they provide ATAGs with memory configuration, the ramdisk address,
1910 the kernel cmdline string, etc. Such information is dynamically
1911 provided by the bootloader and can't always be stored in a static
1912 DTB. To allow a device tree enabled kernel to be used with such
1913 bootloaders, this option allows zImage to extract the information
1914 from the ATAG list and store it at run time into the appended DTB.
1917 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1918 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1921 bool "Use bootloader kernel arguments if available"
1923 Uses the command-line options passed by the boot loader instead of
1924 the device tree bootargs property. If the boot loader doesn't provide
1925 any, the device tree bootargs property will be used.
1927 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1928 bool "Extend with bootloader kernel arguments"
1930 The command-line arguments provided by the boot loader will be
1931 appended to the the device tree bootargs property.
1936 string "Default kernel command string"
1939 On some architectures (EBSA110 and CATS), there is currently no way
1940 for the boot loader to pass arguments to the kernel. For these
1941 architectures, you should supply some command-line options at build
1942 time by entering them here. As a minimum, you should specify the
1943 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1946 prompt "Kernel command line type" if CMDLINE != ""
1947 default CMDLINE_FROM_BOOTLOADER
1950 config CMDLINE_FROM_BOOTLOADER
1951 bool "Use bootloader kernel arguments if available"
1953 Uses the command-line options passed by the boot loader. If
1954 the boot loader doesn't provide any, the default kernel command
1955 string provided in CMDLINE will be used.
1957 config CMDLINE_EXTEND
1958 bool "Extend bootloader kernel arguments"
1960 The command-line arguments provided by the boot loader will be
1961 appended to the default kernel command string.
1963 config CMDLINE_FORCE
1964 bool "Always use the default kernel command string"
1966 Always use the default kernel command string, even if the boot
1967 loader passes other arguments to the kernel.
1968 This is useful if you cannot or don't want to change the
1969 command-line options your boot loader passes to the kernel.
1973 bool "Kernel Execute-In-Place from ROM"
1974 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1976 Execute-In-Place allows the kernel to run from non-volatile storage
1977 directly addressable by the CPU, such as NOR flash. This saves RAM
1978 space since the text section of the kernel is not loaded from flash
1979 to RAM. Read-write sections, such as the data section and stack,
1980 are still copied to RAM. The XIP kernel is not compressed since
1981 it has to run directly from flash, so it will take more space to
1982 store it. The flash address used to link the kernel object files,
1983 and for storing it, is configuration dependent. Therefore, if you
1984 say Y here, you must know the proper physical address where to
1985 store the kernel image depending on your own flash memory usage.
1987 Also note that the make target becomes "make xipImage" rather than
1988 "make zImage" or "make Image". The final kernel binary to put in
1989 ROM memory will be arch/arm/boot/xipImage.
1993 config XIP_PHYS_ADDR
1994 hex "XIP Kernel Physical Location"
1995 depends on XIP_KERNEL
1996 default "0x00080000"
1998 This is the physical address in your flash memory the kernel will
1999 be linked for and stored to. This address is dependent on your
2003 bool "Kexec system call (EXPERIMENTAL)"
2004 depends on (!SMP || PM_SLEEP_SMP)
2008 kexec is a system call that implements the ability to shutdown your
2009 current kernel, and to start another kernel. It is like a reboot
2010 but it is independent of the system firmware. And like a reboot
2011 you can start any kernel with it, not just Linux.
2013 It is an ongoing process to be certain the hardware in a machine
2014 is properly shutdown, so do not be surprised if this code does not
2015 initially work for you.
2018 bool "Export atags in procfs"
2019 depends on ATAGS && KEXEC
2022 Should the atags used to boot the kernel be exported in an "atags"
2023 file in procfs. Useful with kexec.
2026 bool "Build kdump crash kernel (EXPERIMENTAL)"
2028 Generate crash dump after being started by kexec. This should
2029 be normally only set in special crash dump kernels which are
2030 loaded in the main kernel with kexec-tools into a specially
2031 reserved region and then later executed after a crash by
2032 kdump/kexec. The crash dump kernel must be compiled to a
2033 memory address not used by the main kernel
2035 For more details see Documentation/kdump/kdump.txt
2037 config AUTO_ZRELADDR
2038 bool "Auto calculation of the decompressed kernel image address"
2040 ZRELADDR is the physical address where the decompressed kernel
2041 image will be placed. If AUTO_ZRELADDR is selected, the address
2042 will be determined at run-time by masking the current IP with
2043 0xf8000000. This assumes the zImage being placed in the first 128MB
2044 from start of memory.
2050 bool "UEFI runtime support"
2051 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2053 select EFI_PARAMS_FROM_FDT
2056 select EFI_RUNTIME_WRAPPERS
2058 This option provides support for runtime services provided
2059 by UEFI firmware (such as non-volatile variables, realtime
2060 clock, and platform reset). A UEFI stub is also provided to
2061 allow the kernel to be booted as an EFI application. This
2062 is only useful for kernels that may run on systems that have
2067 menu "CPU Power Management"
2069 source "drivers/cpufreq/Kconfig"
2071 source "drivers/cpuidle/Kconfig"
2075 menu "Floating point emulation"
2077 comment "At least one emulation must be selected"
2080 bool "NWFPE math emulation"
2081 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2083 Say Y to include the NWFPE floating point emulator in the kernel.
2084 This is necessary to run most binaries. Linux does not currently
2085 support floating point hardware so you need to say Y here even if
2086 your machine has an FPA or floating point co-processor podule.
2088 You may say N here if you are going to load the Acorn FPEmulator
2089 early in the bootup.
2092 bool "Support extended precision"
2093 depends on FPE_NWFPE
2095 Say Y to include 80-bit support in the kernel floating-point
2096 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2097 Note that gcc does not generate 80-bit operations by default,
2098 so in most cases this option only enlarges the size of the
2099 floating point emulator without any good reason.
2101 You almost surely want to say N here.
2104 bool "FastFPE math emulation (EXPERIMENTAL)"
2105 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2107 Say Y here to include the FAST floating point emulator in the kernel.
2108 This is an experimental much faster emulator which now also has full
2109 precision for the mantissa. It does not support any exceptions.
2110 It is very simple, and approximately 3-6 times faster than NWFPE.
2112 It should be sufficient for most programs. It may be not suitable
2113 for scientific calculations, but you have to check this for yourself.
2114 If you do not feel you need a faster FP emulation you should better
2118 bool "VFP-format floating point maths"
2119 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2121 Say Y to include VFP support code in the kernel. This is needed
2122 if your hardware includes a VFP unit.
2124 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2125 release notes and additional status information.
2127 Say N if your target does not have VFP hardware.
2135 bool "Advanced SIMD (NEON) Extension support"
2136 depends on VFPv3 && CPU_V7
2138 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2141 config KERNEL_MODE_NEON
2142 bool "Support for NEON in kernel mode"
2143 depends on NEON && AEABI
2145 Say Y to include support for NEON in kernel mode.
2149 menu "Userspace binary formats"
2151 source "fs/Kconfig.binfmt"
2155 menu "Power management options"
2157 source "kernel/power/Kconfig"
2159 config ARCH_SUSPEND_POSSIBLE
2160 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2161 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2164 config ARM_CPU_SUSPEND
2165 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2166 depends on ARCH_SUSPEND_POSSIBLE
2168 config ARCH_HIBERNATION_POSSIBLE
2171 default y if ARCH_SUSPEND_POSSIBLE
2175 source "net/Kconfig"
2177 source "drivers/Kconfig"
2179 source "drivers/firmware/Kconfig"
2183 source "arch/arm/Kconfig.debug"
2185 source "security/Kconfig"
2187 source "crypto/Kconfig"
2189 source "arch/arm/crypto/Kconfig"
2192 source "lib/Kconfig"
2194 source "arch/arm/kvm/Kconfig"