arch/arm/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0
   2 config ARM
   3         bool
   4         default y
   5         select ARCH_32BIT_OFF_T
   6         select ARCH_CLOCKSOURCE_DATA
   7         select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
   8         select ARCH_HAS_DEBUG_VIRTUAL if MMU
   9         select ARCH_HAS_DEVMEM_IS_ALLOWED
  10         select ARCH_HAS_ELF_RANDOMIZE
  11         select ARCH_HAS_FORTIFY_SOURCE
  12         select ARCH_HAS_KCOV
  13         select ARCH_HAS_MEMBARRIER_SYNC_CORE
  14         select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
  15         select ARCH_HAS_PHYS_TO_DMA
  16         select ARCH_HAS_SETUP_DMA_OPS
  17         select ARCH_HAS_SET_MEMORY
  18         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  19         select ARCH_HAS_STRICT_MODULE_RWX if MMU
  20         select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
  21         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  22         select ARCH_HAVE_CUSTOM_GPIO_H
  23         select ARCH_HAS_GCOV_PROFILE_ALL
  24         select ARCH_MIGHT_HAVE_PC_PARPORT
  25         select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
  26         select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  27         select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  28         select ARCH_SUPPORTS_ATOMIC_RMW
  29         select ARCH_USE_BUILTIN_BSWAP
  30         select ARCH_USE_CMPXCHG_LOCKREF
  31         select ARCH_WANT_IPC_PARSE_VERSION
  32         select BUILDTIME_EXTABLE_SORT if MMU
  33         select CLONE_BACKWARDS
  34         select CPU_PM if SUSPEND || CPU_IDLE
  35         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  36         select DMA_DECLARE_COHERENT
  37         select DMA_REMAP if MMU
  38         select EDAC_SUPPORT
  39         select EDAC_ATOMIC_SCRUB
  40         select GENERIC_ALLOCATOR
  41         select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  42         select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
  43         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  44         select GENERIC_CPU_AUTOPROBE
  45         select GENERIC_EARLY_IOREMAP
  46         select GENERIC_IDLE_POLL_SETUP
  47         select GENERIC_IRQ_PROBE
  48         select GENERIC_IRQ_SHOW
  49         select GENERIC_IRQ_SHOW_LEVEL
  50         select GENERIC_PCI_IOMAP
  51         select GENERIC_SCHED_CLOCK
  52         select GENERIC_SMP_IDLE_THREAD
  53         select GENERIC_STRNCPY_FROM_USER
  54         select GENERIC_STRNLEN_USER
  55         select HANDLE_DOMAIN_IRQ
  56         select HARDIRQS_SW_RESEND
  57         select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
  58         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  59         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  60         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  61         select HAVE_ARCH_MMAP_RND_BITS if MMU
  62         select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
  63         select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  64         select HAVE_ARCH_TRACEHOOK
  65         select HAVE_ARM_SMCCC if CPU_V7
  66         select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  67         select HAVE_CONTEXT_TRACKING
  68         select HAVE_C_RECORDMCOUNT
  69         select HAVE_DEBUG_KMEMLEAK
  70         select HAVE_DMA_CONTIGUOUS if MMU
  71         select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  72         select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  73         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  74         select HAVE_EXIT_THREAD
  75         select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
  76         select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL
  77         select HAVE_FUNCTION_TRACER if !XIP_KERNEL
  78         select HAVE_GCC_PLUGINS
  79         select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
  80         select HAVE_IDE if PCI || ISA || PCMCIA
  81         select HAVE_IRQ_TIME_ACCOUNTING
  82         select HAVE_KERNEL_GZIP
  83         select HAVE_KERNEL_LZ4
  84         select HAVE_KERNEL_LZMA
  85         select HAVE_KERNEL_LZO
  86         select HAVE_KERNEL_XZ
  87         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  88         select HAVE_KRETPROBES if HAVE_KPROBES
  89         select HAVE_MOD_ARCH_SPECIFIC
  90         select HAVE_NMI
  91         select HAVE_OPROFILE if HAVE_PERF_EVENTS
  92         select HAVE_OPTPROBES if !THUMB2_KERNEL
  93         select HAVE_PERF_EVENTS
  94         select HAVE_PERF_REGS
  95         select HAVE_PERF_USER_STACK_DUMP
  96         select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
  97         select HAVE_REGS_AND_STACK_ACCESS_API
  98         select HAVE_RSEQ
  99         select HAVE_STACKPROTECTOR
 100         select HAVE_SYSCALL_TRACEPOINTS
 101         select HAVE_UID16
 102         select HAVE_VIRT_CPU_ACCOUNTING_GEN
 103         select IRQ_FORCED_THREADING
 104         select MODULES_USE_ELF_REL
 105         select NEED_DMA_MAP_STATE
 106         select OF_EARLY_FLATTREE if OF
 107         select OLD_SIGACTION
 108         select OLD_SIGSUSPEND3
 109         select PCI_SYSCALL if PCI
 110         select PERF_USE_VMALLOC
 111         select REFCOUNT_FULL
 112         select RTC_LIB
 113         select SYS_SUPPORTS_APM_EMULATION
 114         # Above selects are sorted alphabetically; please add new ones
 115         # according to that.  Thanks.
 116         help
 117           The ARM series is a line of low-power-consumption RISC chip designs
 118           licensed by ARM Ltd and targeted at embedded applications and
 119           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 120           manufactured, but legacy ARM-based PC hardware remains popular in
 121           Europe.  There is an ARM Linux project with a web page at
 122           <http://www.arm.linux.org.uk/>.
 123
 124 config ARM_HAS_SG_CHAIN
 125         bool
 126
 127 config ARM_DMA_USE_IOMMU
 128         bool
 129         select ARM_HAS_SG_CHAIN
 130         select NEED_SG_DMA_LENGTH
 131
 132 if ARM_DMA_USE_IOMMU
 133
 134 config ARM_DMA_IOMMU_ALIGNMENT
 135         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 136         range 4 9
 137         default 8
 138         help
 139           DMA mapping framework by default aligns all buffers to the smallest
 140           PAGE_SIZE order which is greater than or equal to the requested buffer
 141           size. This works well for buffers up to a few hundreds kilobytes, but
 142           for larger buffers it just a waste of address space. Drivers which has
 143           relatively small addressing window (like 64Mib) might run out of
 144           virtual space with just a few allocations.
 145
 146           With this parameter you can specify the maximum PAGE_SIZE order for
 147           DMA IOMMU buffers. Larger buffers will be aligned only to this
 148           specified order. The order is expressed as a power of two multiplied
 149           by the PAGE_SIZE.
 150
 151 endif
 152
 153 config SYS_SUPPORTS_APM_EMULATION
 154         bool
 155
 156 config HAVE_TCM
 157         bool
 158         select GENERIC_ALLOCATOR
 159
 160 config HAVE_PROC_CPU
 161         bool
 162
 163 config NO_IOPORT_MAP
 164         bool
 165
 166 config SBUS
 167         bool
 168
 169 config STACKTRACE_SUPPORT
 170         bool
 171         default y
 172
 173 config LOCKDEP_SUPPORT
 174         bool
 175         default y
 176
 177 config TRACE_IRQFLAGS_SUPPORT
 178         bool
 179         default !CPU_V7M
 180
 181 config RWSEM_XCHGADD_ALGORITHM
 182         bool
 183         default y
 184
 185 config ARCH_HAS_ILOG2_U32
 186         bool
 187
 188 config ARCH_HAS_ILOG2_U64
 189         bool
 190
 191 config ARCH_HAS_BANDGAP
 192         bool
 193
 194 config FIX_EARLYCON_MEM
 195         def_bool y if MMU
 196
 197 config GENERIC_HWEIGHT
 198         bool
 199         default y
 200
 201 config GENERIC_CALIBRATE_DELAY
 202         bool
 203         default y
 204
 205 config ARCH_MAY_HAVE_PC_FDC
 206         bool
 207
 208 config ZONE_DMA
 209         bool
 210
 211 config ARCH_SUPPORTS_UPROBES
 212         def_bool y
 213
 214 config ARCH_HAS_DMA_SET_COHERENT_MASK
 215         bool
 216
 217 config GENERIC_ISA_DMA
 218         bool
 219
 220 config FIQ
 221         bool
 222
 223 config NEED_RET_TO_USER
 224         bool
 225
 226 config ARCH_MTD_XIP
 227         bool
 228
 229 config ARM_PATCH_PHYS_VIRT
 230         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 231         default y
 232         depends on !XIP_KERNEL && MMU
 233         help
 234           Patch phys-to-virt and virt-to-phys translation functions at
 235           boot and module load time according to the position of the
 236           kernel in system memory.
 237
 238           This can only be used with non-XIP MMU kernels where the base
 239           of physical memory is at a 16MB boundary.
 240
 241           Only disable this option if you know that you do not require
 242           this feature (eg, building a kernel for a single machine) and
 243           you need to shrink the kernel to the minimal size.
 244
 245 config NEED_MACH_IO_H
 246         bool
 247         help
 248           Select this when mach/io.h is required to provide special
 249           definitions for this platform.  The need for mach/io.h should
 250           be avoided when possible.
 251
 252 config NEED_MACH_MEMORY_H
 253         bool
 254         help
 255           Select this when mach/memory.h is required to provide special
 256           definitions for this platform.  The need for mach/memory.h should
 257           be avoided when possible.
 258
 259 config PHYS_OFFSET
 260         hex "Physical address of main memory" if MMU
 261         depends on !ARM_PATCH_PHYS_VIRT
 262         default DRAM_BASE if !MMU
 263         default 0x00000000 if ARCH_EBSA110 || \
 264                         ARCH_FOOTBRIDGE || \
 265                         ARCH_INTEGRATOR || \
 266                         ARCH_IOP13XX || \
 267                         ARCH_KS8695 || \
 268                         ARCH_REALVIEW
 269         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 270         default 0x20000000 if ARCH_S5PV210
 271         default 0xc0000000 if ARCH_SA1100
 272         help
 273           Please provide the physical address corresponding to the
 274           location of main memory in your system.
 275
 276 config GENERIC_BUG
 277         def_bool y
 278         depends on BUG
 279
 280 config PGTABLE_LEVELS
 281         int
 282         default 3 if ARM_LPAE
 283         default 2
 284
 285 menu "System Type"
 286
 287 config MMU
 288         bool "MMU-based Paged Memory Management Support"
 289         default y
 290         help
 291           Select if you want MMU-based virtualised addressing space
 292           support by paged memory management. If unsure, say 'Y'.
 293
 294 config ARCH_MMAP_RND_BITS_MIN
 295         default 8
 296
 297 config ARCH_MMAP_RND_BITS_MAX
 298         default 14 if PAGE_OFFSET=0x40000000
 299         default 15 if PAGE_OFFSET=0x80000000
 300         default 16
 301
 302 #
 303 # The "ARM system type" choice list is ordered alphabetically by option
 304 # text.  Please add new entries in the option alphabetic order.
 305 #
 306 choice
 307         prompt "ARM system type"
 308         default ARM_SINGLE_ARMV7M if !MMU
 309         default ARCH_MULTIPLATFORM if MMU
 310
 311 config ARCH_MULTIPLATFORM
 312         bool "Allow multiple platforms to be selected"
 313         depends on MMU
 314         select ARM_HAS_SG_CHAIN
 315         select ARM_PATCH_PHYS_VIRT
 316         select AUTO_ZRELADDR
 317         select TIMER_OF
 318         select COMMON_CLK
 319         select GENERIC_CLOCKEVENTS
 320         select GENERIC_IRQ_MULTI_HANDLER
 321         select HAVE_PCI
 322         select PCI_DOMAINS_GENERIC if PCI
 323         select SPARSE_IRQ
 324         select USE_OF
 325
 326 config ARM_SINGLE_ARMV7M
 327         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 328         depends on !MMU
 329         select ARM_NVIC
 330         select AUTO_ZRELADDR
 331         select TIMER_OF
 332         select COMMON_CLK
 333         select CPU_V7M
 334         select GENERIC_CLOCKEVENTS
 335         select NO_IOPORT_MAP
 336         select SPARSE_IRQ
 337         select USE_OF
 338
 339 config ARCH_EBSA110
 340         bool "EBSA-110"
 341         select ARCH_USES_GETTIMEOFFSET
 342         select CPU_SA110
 343         select ISA
 344         select NEED_MACH_IO_H
 345         select NEED_MACH_MEMORY_H
 346         select NO_IOPORT_MAP
 347         help
 348           This is an evaluation board for the StrongARM processor available
 349           from Digital. It has limited hardware on-board, including an
 350           Ethernet interface, two PCMCIA sockets, two serial ports and a
 351           parallel port.
 352
 353 config ARCH_EP93XX
 354         bool "EP93xx-based"
 355         select ARCH_SPARSEMEM_ENABLE
 356         select ARM_AMBA
 357         imply ARM_PATCH_PHYS_VIRT
 358         select ARM_VIC
 359         select AUTO_ZRELADDR
 360         select CLKDEV_LOOKUP
 361         select CLKSRC_MMIO
 362         select CPU_ARM920T
 363         select GENERIC_CLOCKEVENTS
 364         select GPIOLIB
 365         help
 366           This enables support for the Cirrus EP93xx series of CPUs.
 367
 368 config ARCH_FOOTBRIDGE
 369         bool "FootBridge"
 370         select CPU_SA110
 371         select FOOTBRIDGE
 372         select GENERIC_CLOCKEVENTS
 373         select HAVE_IDE
 374         select NEED_MACH_IO_H if !MMU
 375         select NEED_MACH_MEMORY_H
 376         help
 377           Support for systems based on the DC21285 companion chip
 378           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 379
 380 config ARCH_NETX
 381         bool "Hilscher NetX based"
 382         select ARM_VIC
 383         select CLKSRC_MMIO
 384         select CPU_ARM926T
 385         select GENERIC_CLOCKEVENTS
 386         help
 387           This enables support for systems based on the Hilscher NetX Soc
 388
 389 config ARCH_IOP13XX
 390         bool "IOP13xx-based"
 391         depends on MMU
 392         select CPU_XSC3
 393         select NEED_MACH_MEMORY_H
 394         select NEED_RET_TO_USER
 395         select FORCE_PCI
 396         select PLAT_IOP
 397         select VMSPLIT_1G
 398         select SPARSE_IRQ
 399         help
 400           Support for Intel's IOP13XX (XScale) family of processors.
 401
 402 config ARCH_IOP32X
 403         bool "IOP32x-based"
 404         depends on MMU
 405         select CPU_XSCALE
 406         select GPIO_IOP
 407         select GPIOLIB
 408         select NEED_RET_TO_USER
 409         select FORCE_PCI
 410         select PLAT_IOP
 411         help
 412           Support for Intel's 80219 and IOP32X (XScale) family of
 413           processors.
 414
 415 config ARCH_IOP33X
 416         bool "IOP33x-based"
 417         depends on MMU
 418         select CPU_XSCALE
 419         select GPIO_IOP
 420         select GPIOLIB
 421         select NEED_RET_TO_USER
 422         select FORCE_PCI
 423         select PLAT_IOP
 424         help
 425           Support for Intel's IOP33X (XScale) family of processors.
 426
 427 config ARCH_IXP4XX
 428         bool "IXP4xx-based"
 429         depends on MMU
 430         select ARCH_HAS_DMA_SET_COHERENT_MASK
 431         select ARCH_SUPPORTS_BIG_ENDIAN
 432         select CPU_XSCALE
 433         select DMABOUNCE if PCI
 434         select GENERIC_CLOCKEVENTS
 435         select GENERIC_IRQ_MULTI_HANDLER
 436         select GPIO_IXP4XX
 437         select GPIOLIB
 438         select HAVE_PCI
 439         select IXP4XX_IRQ
 440         select IXP4XX_TIMER
 441         select NEED_MACH_IO_H
 442         select USB_EHCI_BIG_ENDIAN_DESC
 443         select USB_EHCI_BIG_ENDIAN_MMIO
 444         help
 445           Support for Intel's IXP4XX (XScale) family of processors.
 446
 447 config ARCH_DOVE
 448         bool "Marvell Dove"
 449         select CPU_PJ4
 450         select GENERIC_CLOCKEVENTS
 451         select GENERIC_IRQ_MULTI_HANDLER
 452         select GPIOLIB
 453         select HAVE_PCI
 454         select MVEBU_MBUS
 455         select PINCTRL
 456         select PINCTRL_DOVE
 457         select PLAT_ORION_LEGACY
 458         select SPARSE_IRQ
 459         select PM_GENERIC_DOMAINS if PM
 460         help
 461           Support for the Marvell Dove SoC 88AP510
 462
 463 config ARCH_KS8695
 464         bool "Micrel/Kendin KS8695"
 465         select CLKSRC_MMIO
 466         select CPU_ARM922T
 467         select GENERIC_CLOCKEVENTS
 468         select GPIOLIB
 469         select NEED_MACH_MEMORY_H
 470         help
 471           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 472           System-on-Chip devices.
 473
 474 config ARCH_W90X900
 475         bool "Nuvoton W90X900 CPU"
 476         select CLKDEV_LOOKUP
 477         select CLKSRC_MMIO
 478         select CPU_ARM926T
 479         select GENERIC_CLOCKEVENTS
 480         select GPIOLIB
 481         help
 482           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 483           At present, the w90x900 has been renamed nuc900, regarding
 484           the ARM series product line, you can login the following
 485           link address to know more.
 486
 487           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 488                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 489
 490 config ARCH_LPC32XX
 491         bool "NXP LPC32XX"
 492         select ARM_AMBA
 493         select CLKDEV_LOOKUP
 494         select CLKSRC_LPC32XX
 495         select COMMON_CLK
 496         select CPU_ARM926T
 497         select GENERIC_CLOCKEVENTS
 498         select GENERIC_IRQ_MULTI_HANDLER
 499         select GPIOLIB
 500         select SPARSE_IRQ
 501         select USE_OF
 502         help
 503           Support for the NXP LPC32XX family of processors
 504
 505 config ARCH_PXA
 506         bool "PXA2xx/PXA3xx-based"
 507         depends on MMU
 508         select ARCH_MTD_XIP
 509         select ARM_CPU_SUSPEND if PM
 510         select AUTO_ZRELADDR
 511         select COMMON_CLK
 512         select CLKDEV_LOOKUP
 513         select CLKSRC_PXA
 514         select CLKSRC_MMIO
 515         select TIMER_OF
 516         select CPU_XSCALE if !CPU_XSC3
 517         select GENERIC_CLOCKEVENTS
 518         select GENERIC_IRQ_MULTI_HANDLER
 519         select GPIO_PXA
 520         select GPIOLIB
 521         select HAVE_IDE
 522         select IRQ_DOMAIN
 523         select PLAT_PXA
 524         select SPARSE_IRQ
 525         help
 526           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 527
 528 config ARCH_RPC
 529         bool "RiscPC"
 530         depends on MMU
 531         select ARCH_ACORN
 532         select ARCH_MAY_HAVE_PC_FDC
 533         select ARCH_SPARSEMEM_ENABLE
 534         select ARCH_USES_GETTIMEOFFSET
 535         select CPU_SA110
 536         select FIQ
 537         select HAVE_IDE
 538         select HAVE_PATA_PLATFORM
 539         select ISA_DMA_API
 540         select NEED_MACH_IO_H
 541         select NEED_MACH_MEMORY_H
 542         select NO_IOPORT_MAP
 543         help
 544           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 545           CD-ROM interface, serial and parallel port, and the floppy drive.
 546
 547 config ARCH_SA1100
 548         bool "SA1100-based"
 549         select ARCH_MTD_XIP
 550         select ARCH_SPARSEMEM_ENABLE
 551         select CLKDEV_LOOKUP
 552         select CLKSRC_MMIO
 553         select CLKSRC_PXA
 554         select TIMER_OF if OF
 555         select CPU_FREQ
 556         select CPU_SA1100
 557         select GENERIC_CLOCKEVENTS
 558         select GENERIC_IRQ_MULTI_HANDLER
 559         select GPIOLIB
 560         select HAVE_IDE
 561         select IRQ_DOMAIN
 562         select ISA
 563         select NEED_MACH_MEMORY_H
 564         select SPARSE_IRQ
 565         help
 566           Support for StrongARM 11x0 based boards.
 567
 568 config ARCH_S3C24XX
 569         bool "Samsung S3C24XX SoCs"
 570         select ATAGS
 571         select CLKDEV_LOOKUP
 572         select CLKSRC_SAMSUNG_PWM
 573         select GENERIC_CLOCKEVENTS
 574         select GPIO_SAMSUNG
 575         select GPIOLIB
 576         select GENERIC_IRQ_MULTI_HANDLER
 577         select HAVE_S3C2410_I2C if I2C
 578         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 579         select HAVE_S3C_RTC if RTC_CLASS
 580         select NEED_MACH_IO_H
 581         select SAMSUNG_ATAGS
 582         select USE_OF
 583         help
 584           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 585           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 586           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 587           Samsung SMDK2410 development board (and derivatives).
 588
 589 config ARCH_DAVINCI
 590         bool "TI DaVinci"
 591         select ARCH_HAS_HOLES_MEMORYMODEL
 592         select COMMON_CLK
 593         select CPU_ARM926T
 594         select GENERIC_ALLOCATOR
 595         select GENERIC_CLOCKEVENTS
 596         select GENERIC_IRQ_CHIP
 597         select GENERIC_IRQ_MULTI_HANDLER
 598         select GPIOLIB
 599         select HAVE_IDE
 600         select PM_GENERIC_DOMAINS if PM
 601         select PM_GENERIC_DOMAINS_OF if PM && OF
 602         select RESET_CONTROLLER
 603         select SPARSE_IRQ
 604         select USE_OF
 605         select ZONE_DMA
 606         help
 607           Support for TI's DaVinci platform.
 608
 609 config ARCH_OMAP1
 610         bool "TI OMAP1"
 611         depends on MMU
 612         select ARCH_HAS_HOLES_MEMORYMODEL
 613         select ARCH_OMAP
 614         select CLKDEV_LOOKUP
 615         select CLKSRC_MMIO
 616         select GENERIC_CLOCKEVENTS
 617         select GENERIC_IRQ_CHIP
 618         select GENERIC_IRQ_MULTI_HANDLER
 619         select GPIOLIB
 620         select HAVE_IDE
 621         select IRQ_DOMAIN
 622         select NEED_MACH_IO_H if PCCARD
 623         select NEED_MACH_MEMORY_H
 624         select SPARSE_IRQ
 625         help
 626           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 627
 628 endchoice
 629
 630 menu "Multiple platform selection"
 631         depends on ARCH_MULTIPLATFORM
 632
 633 comment "CPU Core family selection"
 634
 635 config ARCH_MULTI_V4
 636         bool "ARMv4 based platforms (FA526)"
 637         depends on !ARCH_MULTI_V6_V7
 638         select ARCH_MULTI_V4_V5
 639         select CPU_FA526
 640
 641 config ARCH_MULTI_V4T
 642         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 643         depends on !ARCH_MULTI_V6_V7
 644         select ARCH_MULTI_V4_V5
 645         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 646                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 647                 CPU_ARM925T || CPU_ARM940T)
 648
 649 config ARCH_MULTI_V5
 650         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 651         depends on !ARCH_MULTI_V6_V7
 652         select ARCH_MULTI_V4_V5
 653         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 654                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 655                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 656
 657 config ARCH_MULTI_V4_V5
 658         bool
 659
 660 config ARCH_MULTI_V6
 661         bool "ARMv6 based platforms (ARM11)"
 662         select ARCH_MULTI_V6_V7
 663         select CPU_V6K
 664
 665 config ARCH_MULTI_V7
 666         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 667         default y
 668         select ARCH_MULTI_V6_V7
 669         select CPU_V7
 670         select HAVE_SMP
 671
 672 config ARCH_MULTI_V6_V7
 673         bool
 674         select MIGHT_HAVE_CACHE_L2X0
 675
 676 config ARCH_MULTI_CPU_AUTO
 677         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 678         select ARCH_MULTI_V5
 679
 680 endmenu
 681
 682 config ARCH_VIRT
 683         bool "Dummy Virtual Machine"
 684         depends on ARCH_MULTI_V7
 685         select ARM_AMBA
 686         select ARM_GIC
 687         select ARM_GIC_V2M if PCI
 688         select ARM_GIC_V3
 689         select ARM_GIC_V3_ITS if PCI
 690         select ARM_PSCI
 691         select HAVE_ARM_ARCH_TIMER
 692         select ARCH_SUPPORTS_BIG_ENDIAN
 693
 694 #
 695 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 696 # Kconfigs may be included either alphabetically (according to the
 697 # plat- suffix) or along side the corresponding mach-* source.
 698 #
 699 source "arch/arm/mach-actions/Kconfig"
 700
 701 source "arch/arm/mach-alpine/Kconfig"
 702
 703 source "arch/arm/mach-artpec/Kconfig"
 704
 705 source "arch/arm/mach-asm9260/Kconfig"
 706
 707 source "arch/arm/mach-aspeed/Kconfig"
 708
 709 source "arch/arm/mach-at91/Kconfig"
 710
 711 source "arch/arm/mach-axxia/Kconfig"
 712
 713 source "arch/arm/mach-bcm/Kconfig"
 714
 715 source "arch/arm/mach-berlin/Kconfig"
 716
 717 source "arch/arm/mach-clps711x/Kconfig"
 718
 719 source "arch/arm/mach-cns3xxx/Kconfig"
 720
 721 source "arch/arm/mach-davinci/Kconfig"
 722
 723 source "arch/arm/mach-digicolor/Kconfig"
 724
 725 source "arch/arm/mach-dove/Kconfig"
 726
 727 source "arch/arm/mach-ep93xx/Kconfig"
 728
 729 source "arch/arm/mach-exynos/Kconfig"
 730 source "arch/arm/plat-samsung/Kconfig"
 731
 732 source "arch/arm/mach-footbridge/Kconfig"
 733
 734 source "arch/arm/mach-gemini/Kconfig"
 735
 736 source "arch/arm/mach-highbank/Kconfig"
 737
 738 source "arch/arm/mach-hisi/Kconfig"
 739
 740 source "arch/arm/mach-imx/Kconfig"
 741
 742 source "arch/arm/mach-integrator/Kconfig"
 743
 744 source "arch/arm/mach-iop13xx/Kconfig"
 745
 746 source "arch/arm/mach-iop32x/Kconfig"
 747
 748 source "arch/arm/mach-iop33x/Kconfig"
 749
 750 source "arch/arm/mach-ixp4xx/Kconfig"
 751
 752 source "arch/arm/mach-keystone/Kconfig"
 753
 754 source "arch/arm/mach-ks8695/Kconfig"
 755
 756 source "arch/arm/mach-mediatek/Kconfig"
 757
 758 source "arch/arm/mach-meson/Kconfig"
 759
 760 source "arch/arm/mach-milbeaut/Kconfig"
 761
 762 source "arch/arm/mach-mmp/Kconfig"
 763
 764 source "arch/arm/mach-moxart/Kconfig"
 765
 766 source "arch/arm/mach-mv78xx0/Kconfig"
 767
 768 source "arch/arm/mach-mvebu/Kconfig"
 769
 770 source "arch/arm/mach-mxs/Kconfig"
 771
 772 source "arch/arm/mach-netx/Kconfig"
 773
 774 source "arch/arm/mach-nomadik/Kconfig"
 775
 776 source "arch/arm/mach-npcm/Kconfig"
 777
 778 source "arch/arm/mach-nspire/Kconfig"
 779
 780 source "arch/arm/plat-omap/Kconfig"
 781
 782 source "arch/arm/mach-omap1/Kconfig"
 783
 784 source "arch/arm/mach-omap2/Kconfig"
 785
 786 source "arch/arm/mach-orion5x/Kconfig"
 787
 788 source "arch/arm/mach-oxnas/Kconfig"
 789
 790 source "arch/arm/mach-picoxcell/Kconfig"
 791
 792 source "arch/arm/mach-prima2/Kconfig"
 793
 794 source "arch/arm/mach-pxa/Kconfig"
 795 source "arch/arm/plat-pxa/Kconfig"
 796
 797 source "arch/arm/mach-qcom/Kconfig"
 798
 799 source "arch/arm/mach-rda/Kconfig"
 800
 801 source "arch/arm/mach-realview/Kconfig"
 802
 803 source "arch/arm/mach-rockchip/Kconfig"
 804
 805 source "arch/arm/mach-s3c24xx/Kconfig"
 806
 807 source "arch/arm/mach-s3c64xx/Kconfig"
 808
 809 source "arch/arm/mach-s5pv210/Kconfig"
 810
 811 source "arch/arm/mach-sa1100/Kconfig"
 812
 813 source "arch/arm/mach-shmobile/Kconfig"
 814
 815 source "arch/arm/mach-socfpga/Kconfig"
 816
 817 source "arch/arm/mach-spear/Kconfig"
 818
 819 source "arch/arm/mach-sti/Kconfig"
 820
 821 source "arch/arm/mach-stm32/Kconfig"
 822
 823 source "arch/arm/mach-sunxi/Kconfig"
 824
 825 source "arch/arm/mach-tango/Kconfig"
 826
 827 source "arch/arm/mach-tegra/Kconfig"
 828
 829 source "arch/arm/mach-u300/Kconfig"
 830
 831 source "arch/arm/mach-uniphier/Kconfig"
 832
 833 source "arch/arm/mach-ux500/Kconfig"
 834
 835 source "arch/arm/mach-versatile/Kconfig"
 836
 837 source "arch/arm/mach-vexpress/Kconfig"
 838 source "arch/arm/plat-versatile/Kconfig"
 839
 840 source "arch/arm/mach-vt8500/Kconfig"
 841
 842 source "arch/arm/mach-w90x900/Kconfig"
 843
 844 source "arch/arm/mach-zx/Kconfig"
 845
 846 source "arch/arm/mach-zynq/Kconfig"
 847
 848 # ARMv7-M architecture
 849 config ARCH_EFM32
 850         bool "Energy Micro efm32"
 851         depends on ARM_SINGLE_ARMV7M
 852         select GPIOLIB
 853         help
 854           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 855           processors.
 856
 857 config ARCH_LPC18XX
 858         bool "NXP LPC18xx/LPC43xx"
 859         depends on ARM_SINGLE_ARMV7M
 860         select ARCH_HAS_RESET_CONTROLLER
 861         select ARM_AMBA
 862         select CLKSRC_LPC32XX
 863         select PINCTRL
 864         help
 865           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 866           high performance microcontrollers.
 867
 868 config ARCH_MPS2
 869         bool "ARM MPS2 platform"
 870         depends on ARM_SINGLE_ARMV7M
 871         select ARM_AMBA
 872         select CLKSRC_MPS2
 873         help
 874           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 875           with a range of available cores like Cortex-M3/M4/M7.
 876
 877           Please, note that depends which Application Note is used memory map
 878           for the platform may vary, so adjustment of RAM base might be needed.
 879
 880 # Definitions to make life easier
 881 config ARCH_ACORN
 882         bool
 883
 884 config PLAT_IOP
 885         bool
 886         select GENERIC_CLOCKEVENTS
 887
 888 config PLAT_ORION
 889         bool
 890         select CLKSRC_MMIO
 891         select COMMON_CLK
 892         select GENERIC_IRQ_CHIP
 893         select IRQ_DOMAIN
 894
 895 config PLAT_ORION_LEGACY
 896         bool
 897         select PLAT_ORION
 898
 899 config PLAT_PXA
 900         bool
 901
 902 config PLAT_VERSATILE
 903         bool
 904
 905 source "arch/arm/firmware/Kconfig"
 906
 907 source "arch/arm/mm/Kconfig"
 908
 909 config IWMMXT
 910         bool "Enable iWMMXt support"
 911         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 912         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 913         help
 914           Enable support for iWMMXt context switching at run time if
 915           running on a CPU that supports it.
 916
 917 if !MMU
 918 source "arch/arm/Kconfig-nommu"
 919 endif
 920
 921 config PJ4B_ERRATA_4742
 922         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 923         depends on CPU_PJ4B && MACH_ARMADA_370
 924         default y
 925         help
 926           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 927           Event (WFE) IDLE states, a specific timing sensitivity exists between
 928           the retiring WFI/WFE instructions and the newly issued subsequent
 929           instructions.  This sensitivity can result in a CPU hang scenario.
 930           Workaround:
 931           The software must insert either a Data Synchronization Barrier (DSB)
 932           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 933           instruction
 934
 935 config ARM_ERRATA_326103
 936         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 937         depends on CPU_V6
 938         help
 939           Executing a SWP instruction to read-only memory does not set bit 11
 940           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 941           treat the access as a read, preventing a COW from occurring and
 942           causing the faulting task to livelock.
 943
 944 config ARM_ERRATA_411920
 945         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 946         depends on CPU_V6 || CPU_V6K
 947         help
 948           Invalidation of the Instruction Cache operation can
 949           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 950           It does not affect the MPCore. This option enables the ARM Ltd.
 951           recommended workaround.
 952
 953 config ARM_ERRATA_430973
 954         bool "ARM errata: Stale prediction on replaced interworking branch"
 955         depends on CPU_V7
 956         help
 957           This option enables the workaround for the 430973 Cortex-A8
 958           r1p* erratum. If a code sequence containing an ARM/Thumb
 959           interworking branch is replaced with another code sequence at the
 960           same virtual address, whether due to self-modifying code or virtual
 961           to physical address re-mapping, Cortex-A8 does not recover from the
 962           stale interworking branch prediction. This results in Cortex-A8
 963           executing the new code sequence in the incorrect ARM or Thumb state.
 964           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 965           and also flushes the branch target cache at every context switch.
 966           Note that setting specific bits in the ACTLR register may not be
 967           available in non-secure mode.
 968
 969 config ARM_ERRATA_458693
 970         bool "ARM errata: Processor deadlock when a false hazard is created"
 971         depends on CPU_V7
 972         depends on !ARCH_MULTIPLATFORM
 973         help
 974           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 975           erratum. For very specific sequences of memory operations, it is
 976           possible for a hazard condition intended for a cache line to instead
 977           be incorrectly associated with a different cache line. This false
 978           hazard might then cause a processor deadlock. The workaround enables
 979           the L1 caching of the NEON accesses and disables the PLD instruction
 980           in the ACTLR register. Note that setting specific bits in the ACTLR
 981           register may not be available in non-secure mode.
 982
 983 config ARM_ERRATA_460075
 984         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
 985         depends on CPU_V7
 986         depends on !ARCH_MULTIPLATFORM
 987         help
 988           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
 989           erratum. Any asynchronous access to the L2 cache may encounter a
 990           situation in which recent store transactions to the L2 cache are lost
 991           and overwritten with stale memory contents from external memory. The
 992           workaround disables the write-allocate mode for the L2 cache via the
 993           ACTLR register. Note that setting specific bits in the ACTLR register
 994           may not be available in non-secure mode.
 995
 996 config ARM_ERRATA_742230
 997         bool "ARM errata: DMB operation may be faulty"
 998         depends on CPU_V7 && SMP
 999         depends on !ARCH_MULTIPLATFORM
1000         help
1001           This option enables the workaround for the 742230 Cortex-A9
1002           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1003           between two write operations may not ensure the correct visibility
1004           ordering of the two writes. This workaround sets a specific bit in
1005           the diagnostic register of the Cortex-A9 which causes the DMB
1006           instruction to behave as a DSB, ensuring the correct behaviour of
1007           the two writes.
1008
1009 config ARM_ERRATA_742231
1010         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1011         depends on CPU_V7 && SMP
1012         depends on !ARCH_MULTIPLATFORM
1013         help
1014           This option enables the workaround for the 742231 Cortex-A9
1015           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1016           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1017           accessing some data located in the same cache line, may get corrupted
1018           data due to bad handling of the address hazard when the line gets
1019           replaced from one of the CPUs at the same time as another CPU is
1020           accessing it. This workaround sets specific bits in the diagnostic
1021           register of the Cortex-A9 which reduces the linefill issuing
1022           capabilities of the processor.
1023
1024 config ARM_ERRATA_643719
1025         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1026         depends on CPU_V7 && SMP
1027         default y
1028         help
1029           This option enables the workaround for the 643719 Cortex-A9 (prior to
1030           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1031           register returns zero when it should return one. The workaround
1032           corrects this value, ensuring cache maintenance operations which use
1033           it behave as intended and avoiding data corruption.
1034
1035 config ARM_ERRATA_720789
1036         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1037         depends on CPU_V7
1038         help
1039           This option enables the workaround for the 720789 Cortex-A9 (prior to
1040           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1041           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1042           As a consequence of this erratum, some TLB entries which should be
1043           invalidated are not, resulting in an incoherency in the system page
1044           tables. The workaround changes the TLB flushing routines to invalidate
1045           entries regardless of the ASID.
1046
1047 config ARM_ERRATA_743622
1048         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1049         depends on CPU_V7
1050         depends on !ARCH_MULTIPLATFORM
1051         help
1052           This option enables the workaround for the 743622 Cortex-A9
1053           (r2p*) erratum. Under very rare conditions, a faulty
1054           optimisation in the Cortex-A9 Store Buffer may lead to data
1055           corruption. This workaround sets a specific bit in the diagnostic
1056           register of the Cortex-A9 which disables the Store Buffer
1057           optimisation, preventing the defect from occurring. This has no
1058           visible impact on the overall performance or power consumption of the
1059           processor.
1060
1061 config ARM_ERRATA_751472
1062         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1063         depends on CPU_V7
1064         depends on !ARCH_MULTIPLATFORM
1065         help
1066           This option enables the workaround for the 751472 Cortex-A9 (prior
1067           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1068           completion of a following broadcasted operation if the second
1069           operation is received by a CPU before the ICIALLUIS has completed,
1070           potentially leading to corrupted entries in the cache or TLB.
1071
1072 config ARM_ERRATA_754322
1073         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1074         depends on CPU_V7
1075         help
1076           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1077           r3p*) erratum. A speculative memory access may cause a page table walk
1078           which starts prior to an ASID switch but completes afterwards. This
1079           can populate the micro-TLB with a stale entry which may be hit with
1080           the new ASID. This workaround places two dsb instructions in the mm
1081           switching code so that no page table walks can cross the ASID switch.
1082
1083 config ARM_ERRATA_754327
1084         bool "ARM errata: no automatic Store Buffer drain"
1085         depends on CPU_V7 && SMP
1086         help
1087           This option enables the workaround for the 754327 Cortex-A9 (prior to
1088           r2p0) erratum. The Store Buffer does not have any automatic draining
1089           mechanism and therefore a livelock may occur if an external agent
1090           continuously polls a memory location waiting to observe an update.
1091           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1092           written polling loops from denying visibility of updates to memory.
1093
1094 config ARM_ERRATA_364296
1095         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1096         depends on CPU_V6
1097         help
1098           This options enables the workaround for the 364296 ARM1136
1099           r0p2 erratum (possible cache data corruption with
1100           hit-under-miss enabled). It sets the undocumented bit 31 in
1101           the auxiliary control register and the FI bit in the control
1102           register, thus disabling hit-under-miss without putting the
1103           processor into full low interrupt latency mode. ARM11MPCore
1104           is not affected.
1105
1106 config ARM_ERRATA_764369
1107         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1108         depends on CPU_V7 && SMP
1109         help
1110           This option enables the workaround for erratum 764369
1111           affecting Cortex-A9 MPCore with two or more processors (all
1112           current revisions). Under certain timing circumstances, a data
1113           cache line maintenance operation by MVA targeting an Inner
1114           Shareable memory region may fail to proceed up to either the
1115           Point of Coherency or to the Point of Unification of the
1116           system. This workaround adds a DSB instruction before the
1117           relevant cache maintenance functions and sets a specific bit
1118           in the diagnostic control register of the SCU.
1119
1120 config ARM_ERRATA_775420
1121        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1122        depends on CPU_V7
1123        help
1124          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1125          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1126          operation aborts with MMU exception, it might cause the processor
1127          to deadlock. This workaround puts DSB before executing ISB if
1128          an abort may occur on cache maintenance.
1129
1130 config ARM_ERRATA_798181
1131         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1132         depends on CPU_V7 && SMP
1133         help
1134           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1135           adequately shooting down all use of the old entries. This
1136           option enables the Linux kernel workaround for this erratum
1137           which sends an IPI to the CPUs that are running the same ASID
1138           as the one being invalidated.
1139
1140 config ARM_ERRATA_773022
1141         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1142         depends on CPU_V7
1143         help
1144           This option enables the workaround for the 773022 Cortex-A15
1145           (up to r0p4) erratum. In certain rare sequences of code, the
1146           loop buffer may deliver incorrect instructions. This
1147           workaround disables the loop buffer to avoid the erratum.
1148
1149 config ARM_ERRATA_818325_852422
1150         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1151         depends on CPU_V7
1152         help
1153           This option enables the workaround for:
1154           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1155             instruction might deadlock.  Fixed in r0p1.
1156           - Cortex-A12 852422: Execution of a sequence of instructions might
1157             lead to either a data corruption or a CPU deadlock.  Not fixed in
1158             any Cortex-A12 cores yet.
1159           This workaround for all both errata involves setting bit[12] of the
1160           Feature Register. This bit disables an optimisation applied to a
1161           sequence of 2 instructions that use opposing condition codes.
1162
1163 config ARM_ERRATA_821420
1164         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1165         depends on CPU_V7
1166         help
1167           This option enables the workaround for the 821420 Cortex-A12
1168           (all revs) erratum. In very rare timing conditions, a sequence
1169           of VMOV to Core registers instructions, for which the second
1170           one is in the shadow of a branch or abort, can lead to a
1171           deadlock when the VMOV instructions are issued out-of-order.
1172
1173 config ARM_ERRATA_825619
1174         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1175         depends on CPU_V7
1176         help
1177           This option enables the workaround for the 825619 Cortex-A12
1178           (all revs) erratum. Within rare timing constraints, executing a
1179           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1180           and Device/Strongly-Ordered loads and stores might cause deadlock
1181
1182 config ARM_ERRATA_852421
1183         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1184         depends on CPU_V7
1185         help
1186           This option enables the workaround for the 852421 Cortex-A17
1187           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1188           execution of a DMB ST instruction might fail to properly order
1189           stores from GroupA and stores from GroupB.
1190
1191 config ARM_ERRATA_852423
1192         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1193         depends on CPU_V7
1194         help
1195           This option enables the workaround for:
1196           - Cortex-A17 852423: Execution of a sequence of instructions might
1197             lead to either a data corruption or a CPU deadlock.  Not fixed in
1198             any Cortex-A17 cores yet.
1199           This is identical to Cortex-A12 erratum 852422.  It is a separate
1200           config option from the A12 erratum due to the way errata are checked
1201           for and handled.
1202
1203 endmenu
1204
1205 source "arch/arm/common/Kconfig"
1206
1207 menu "Bus support"
1208
1209 config ISA
1210         bool
1211         help
1212           Find out whether you have ISA slots on your motherboard.  ISA is the
1213           name of a bus system, i.e. the way the CPU talks to the other stuff
1214           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1215           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1216           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1217
1218 # Select ISA DMA controller support
1219 config ISA_DMA
1220         bool
1221         select ISA_DMA_API
1222
1223 # Select ISA DMA interface
1224 config ISA_DMA_API
1225         bool
1226
1227 config PCI_NANOENGINE
1228         bool "BSE nanoEngine PCI support"
1229         depends on SA1100_NANOENGINE
1230         help
1231           Enable PCI on the BSE nanoEngine board.
1232
1233 config PCI_HOST_ITE8152
1234         bool
1235         depends on PCI && MACH_ARMCORE
1236         default y
1237         select DMABOUNCE
1238
1239 endmenu
1240
1241 menu "Kernel Features"
1242
1243 config HAVE_SMP
1244         bool
1245         help
1246           This option should be selected by machines which have an SMP-
1247           capable CPU.
1248
1249           The only effect of this option is to make the SMP-related
1250           options available to the user for configuration.
1251
1252 config SMP
1253         bool "Symmetric Multi-Processing"
1254         depends on CPU_V6K || CPU_V7
1255         depends on GENERIC_CLOCKEVENTS
1256         depends on HAVE_SMP
1257         depends on MMU || ARM_MPU
1258         select IRQ_WORK
1259         help
1260           This enables support for systems with more than one CPU. If you have
1261           a system with only one CPU, say N. If you have a system with more
1262           than one CPU, say Y.
1263
1264           If you say N here, the kernel will run on uni- and multiprocessor
1265           machines, but will use only one CPU of a multiprocessor machine. If
1266           you say Y here, the kernel will run on many, but not all,
1267           uniprocessor machines. On a uniprocessor machine, the kernel
1268           will run faster if you say N here.
1269
1270           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1271           <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1272           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1273
1274           If you don't know what to do here, say N.
1275
1276 config SMP_ON_UP
1277         bool "Allow booting SMP kernel on uniprocessor systems"
1278         depends on SMP && !XIP_KERNEL && MMU
1279         default y
1280         help
1281           SMP kernels contain instructions which fail on non-SMP processors.
1282           Enabling this option allows the kernel to modify itself to make
1283           these instructions safe.  Disabling it allows about 1K of space
1284           savings.
1285
1286           If you don't know what to do here, say Y.
1287
1288 config ARM_CPU_TOPOLOGY
1289         bool "Support cpu topology definition"
1290         depends on SMP && CPU_V7
1291         default y
1292         help
1293           Support ARM cpu topology definition. The MPIDR register defines
1294           affinity between processors which is then used to describe the cpu
1295           topology of an ARM System.
1296
1297 config SCHED_MC
1298         bool "Multi-core scheduler support"
1299         depends on ARM_CPU_TOPOLOGY
1300         help
1301           Multi-core scheduler support improves the CPU scheduler's decision
1302           making when dealing with multi-core CPU chips at a cost of slightly
1303           increased overhead in some places. If unsure say N here.
1304
1305 config SCHED_SMT
1306         bool "SMT scheduler support"
1307         depends on ARM_CPU_TOPOLOGY
1308         help
1309           Improves the CPU scheduler's decision making when dealing with
1310           MultiThreading at a cost of slightly increased overhead in some
1311           places. If unsure say N here.
1312
1313 config HAVE_ARM_SCU
1314         bool
1315         help
1316           This option enables support for the ARM snoop control unit
1317
1318 config HAVE_ARM_ARCH_TIMER
1319         bool "Architected timer support"
1320         depends on CPU_V7
1321         select ARM_ARCH_TIMER
1322         select GENERIC_CLOCKEVENTS
1323         help
1324           This option enables support for the ARM architected timer
1325
1326 config HAVE_ARM_TWD
1327         bool
1328         help
1329           This options enables support for the ARM timer and watchdog unit
1330
1331 config MCPM
1332         bool "Multi-Cluster Power Management"
1333         depends on CPU_V7 && SMP
1334         help
1335           This option provides the common power management infrastructure
1336           for (multi-)cluster based systems, such as big.LITTLE based
1337           systems.
1338
1339 config MCPM_QUAD_CLUSTER
1340         bool
1341         depends on MCPM
1342         help
1343           To avoid wasting resources unnecessarily, MCPM only supports up
1344           to 2 clusters by default.
1345           Platforms with 3 or 4 clusters that use MCPM must select this
1346           option to allow the additional clusters to be managed.
1347
1348 config BIG_LITTLE
1349         bool "big.LITTLE support (Experimental)"
1350         depends on CPU_V7 && SMP
1351         select MCPM
1352         help
1353           This option enables support selections for the big.LITTLE
1354           system architecture.
1355
1356 config BL_SWITCHER
1357         bool "big.LITTLE switcher support"
1358         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1359         select CPU_PM
1360         help
1361           The big.LITTLE "switcher" provides the core functionality to
1362           transparently handle transition between a cluster of A15's
1363           and a cluster of A7's in a big.LITTLE system.
1364
1365 config BL_SWITCHER_DUMMY_IF
1366         tristate "Simple big.LITTLE switcher user interface"
1367         depends on BL_SWITCHER && DEBUG_KERNEL
1368         help
1369           This is a simple and dummy char dev interface to control
1370           the big.LITTLE switcher core code.  It is meant for
1371           debugging purposes only.
1372
1373 choice
1374         prompt "Memory split"
1375         depends on MMU
1376         default VMSPLIT_3G
1377         help
1378           Select the desired split between kernel and user memory.
1379
1380           If you are not absolutely sure what you are doing, leave this
1381           option alone!
1382
1383         config VMSPLIT_3G
1384                 bool "3G/1G user/kernel split"
1385         config VMSPLIT_3G_OPT
1386                 depends on !ARM_LPAE
1387                 bool "3G/1G user/kernel split (for full 1G low memory)"
1388         config VMSPLIT_2G
1389                 bool "2G/2G user/kernel split"
1390         config VMSPLIT_1G
1391                 bool "1G/3G user/kernel split"
1392 endchoice
1393
1394 config PAGE_OFFSET
1395         hex
1396         default PHYS_OFFSET if !MMU
1397         default 0x40000000 if VMSPLIT_1G
1398         default 0x80000000 if VMSPLIT_2G
1399         default 0xB0000000 if VMSPLIT_3G_OPT
1400         default 0xC0000000
1401
1402 config NR_CPUS
1403         int "Maximum number of CPUs (2-32)"
1404         range 2 32
1405         depends on SMP
1406         default "4"
1407
1408 config HOTPLUG_CPU
1409         bool "Support for hot-pluggable CPUs"
1410         depends on SMP
1411         select GENERIC_IRQ_MIGRATION
1412         help
1413           Say Y here to experiment with turning CPUs off and on.  CPUs
1414           can be controlled through /sys/devices/system/cpu.
1415
1416 config ARM_PSCI
1417         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1418         depends on HAVE_ARM_SMCCC
1419         select ARM_PSCI_FW
1420         help
1421           Say Y here if you want Linux to communicate with system firmware
1422           implementing the PSCI specification for CPU-centric power
1423           management operations described in ARM document number ARM DEN
1424           0022A ("Power State Coordination Interface System Software on
1425           ARM processors").
1426
1427 # The GPIO number here must be sorted by descending number. In case of
1428 # a multiplatform kernel, we just want the highest value required by the
1429 # selected platforms.
1430 config ARCH_NR_GPIO
1431         int
1432         default 2048 if ARCH_SOCFPGA
1433         default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1434                 ARCH_ZYNQ
1435         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1436                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1437         default 416 if ARCH_SUNXI
1438         default 392 if ARCH_U8500
1439         default 352 if ARCH_VT8500
1440         default 288 if ARCH_ROCKCHIP
1441         default 264 if MACH_H4700
1442         default 0
1443         help
1444           Maximum number of GPIOs in the system.
1445
1446           If unsure, leave the default value.
1447
1448 config HZ_FIXED
1449         int
1450         default 200 if ARCH_EBSA110
1451         default 128 if SOC_AT91RM9200
1452         default 0
1453
1454 choice
1455         depends on HZ_FIXED = 0
1456         prompt "Timer frequency"
1457
1458 config HZ_100
1459         bool "100 Hz"
1460
1461 config HZ_200
1462         bool "200 Hz"
1463
1464 config HZ_250
1465         bool "250 Hz"
1466
1467 config HZ_300
1468         bool "300 Hz"
1469
1470 config HZ_500
1471         bool "500 Hz"
1472
1473 config HZ_1000
1474         bool "1000 Hz"
1475
1476 endchoice
1477
1478 config HZ
1479         int
1480         default HZ_FIXED if HZ_FIXED != 0
1481         default 100 if HZ_100
1482         default 200 if HZ_200
1483         default 250 if HZ_250
1484         default 300 if HZ_300
1485         default 500 if HZ_500
1486         default 1000
1487
1488 config SCHED_HRTICK
1489         def_bool HIGH_RES_TIMERS
1490
1491 config THUMB2_KERNEL
1492         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1493         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1494         default y if CPU_THUMBONLY
1495         select ARM_UNWIND
1496         help
1497           By enabling this option, the kernel will be compiled in
1498           Thumb-2 mode.
1499
1500           If unsure, say N.
1501
1502 config THUMB2_AVOID_R_ARM_THM_JUMP11
1503         bool "Work around buggy Thumb-2 short branch relocations in gas"
1504         depends on THUMB2_KERNEL && MODULES
1505         default y
1506         help
1507           Various binutils versions can resolve Thumb-2 branches to
1508           locally-defined, preemptible global symbols as short-range "b.n"
1509           branch instructions.
1510
1511           This is a problem, because there's no guarantee the final
1512           destination of the symbol, or any candidate locations for a
1513           trampoline, are within range of the branch.  For this reason, the
1514           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1515           relocation in modules at all, and it makes little sense to add
1516           support.
1517
1518           The symptom is that the kernel fails with an "unsupported
1519           relocation" error when loading some modules.
1520
1521           Until fixed tools are available, passing
1522           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1523           code which hits this problem, at the cost of a bit of extra runtime
1524           stack usage in some cases.
1525
1526           The problem is described in more detail at:
1527               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1528
1529           Only Thumb-2 kernels are affected.
1530
1531           Unless you are sure your tools don't have this problem, say Y.
1532
1533 config ARM_PATCH_IDIV
1534         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1535         depends on CPU_32v7 && !XIP_KERNEL
1536         default y
1537         help
1538           The ARM compiler inserts calls to __aeabi_idiv() and
1539           __aeabi_uidiv() when it needs to perform division on signed
1540           and unsigned integers. Some v7 CPUs have support for the sdiv
1541           and udiv instructions that can be used to implement those
1542           functions.
1543
1544           Enabling this option allows the kernel to modify itself to
1545           replace the first two instructions of these library functions
1546           with the sdiv or udiv plus "bx lr" instructions when the CPU
1547           it is running on supports them. Typically this will be faster
1548           and less power intensive than running the original library
1549           code to do integer division.
1550
1551 config AEABI
1552         bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1553         default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1554         help
1555           This option allows for the kernel to be compiled using the latest
1556           ARM ABI (aka EABI).  This is only useful if you are using a user
1557           space environment that is also compiled with EABI.
1558
1559           Since there are major incompatibilities between the legacy ABI and
1560           EABI, especially with regard to structure member alignment, this
1561           option also changes the kernel syscall calling convention to
1562           disambiguate both ABIs and allow for backward compatibility support
1563           (selected with CONFIG_OABI_COMPAT).
1564
1565           To use this you need GCC version 4.0.0 or later.
1566
1567 config OABI_COMPAT
1568         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1569         depends on AEABI && !THUMB2_KERNEL
1570         help
1571           This option preserves the old syscall interface along with the
1572           new (ARM EABI) one. It also provides a compatibility layer to
1573           intercept syscalls that have structure arguments which layout
1574           in memory differs between the legacy ABI and the new ARM EABI
1575           (only for non "thumb" binaries). This option adds a tiny
1576           overhead to all syscalls and produces a slightly larger kernel.
1577
1578           The seccomp filter system will not be available when this is
1579           selected, since there is no way yet to sensibly distinguish
1580           between calling conventions during filtering.
1581
1582           If you know you'll be using only pure EABI user space then you
1583           can say N here. If this option is not selected and you attempt
1584           to execute a legacy ABI binary then the result will be
1585           UNPREDICTABLE (in fact it can be predicted that it won't work
1586           at all). If in doubt say N.
1587
1588 config ARCH_HAS_HOLES_MEMORYMODEL
1589         bool
1590
1591 config ARCH_SPARSEMEM_ENABLE
1592         bool
1593
1594 config ARCH_SPARSEMEM_DEFAULT
1595         def_bool ARCH_SPARSEMEM_ENABLE
1596
1597 config ARCH_SELECT_MEMORY_MODEL
1598         def_bool ARCH_SPARSEMEM_ENABLE
1599
1600 config HAVE_ARCH_PFN_VALID
1601         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1602
1603 config HAVE_GENERIC_GUP
1604         def_bool y
1605         depends on ARM_LPAE
1606
1607 config HIGHMEM
1608         bool "High Memory Support"
1609         depends on MMU
1610         help
1611           The address space of ARM processors is only 4 Gigabytes large
1612           and it has to accommodate user address space, kernel address
1613           space as well as some memory mapped IO. That means that, if you
1614           have a large amount of physical memory and/or IO, not all of the
1615           memory can be "permanently mapped" by the kernel. The physical
1616           memory that is not permanently mapped is called "high memory".
1617
1618           Depending on the selected kernel/user memory split, minimum
1619           vmalloc space and actual amount of RAM, you may not need this
1620           option which should result in a slightly faster kernel.
1621
1622           If unsure, say n.
1623
1624 config HIGHPTE
1625         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1626         depends on HIGHMEM
1627         default y
1628         help
1629           The VM uses one page of physical memory for each page table.
1630           For systems with a lot of processes, this can use a lot of
1631           precious low memory, eventually leading to low memory being
1632           consumed by page tables.  Setting this option will allow
1633           user-space 2nd level page tables to reside in high memory.
1634
1635 config CPU_SW_DOMAIN_PAN
1636         bool "Enable use of CPU domains to implement privileged no-access"
1637         depends on MMU && !ARM_LPAE
1638         default y
1639         help
1640           Increase kernel security by ensuring that normal kernel accesses
1641           are unable to access userspace addresses.  This can help prevent
1642           use-after-free bugs becoming an exploitable privilege escalation
1643           by ensuring that magic values (such as LIST_POISON) will always
1644           fault when dereferenced.
1645
1646           CPUs with low-vector mappings use a best-efforts implementation.
1647           Their lower 1MB needs to remain accessible for the vectors, but
1648           the remainder of userspace will become appropriately inaccessible.
1649
1650 config HW_PERF_EVENTS
1651         def_bool y
1652         depends on ARM_PMU
1653
1654 config SYS_SUPPORTS_HUGETLBFS
1655        def_bool y
1656        depends on ARM_LPAE
1657
1658 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1659        def_bool y
1660        depends on ARM_LPAE
1661
1662 config ARCH_WANT_GENERAL_HUGETLB
1663         def_bool y
1664
1665 config ARM_MODULE_PLTS
1666         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1667         depends on MODULES
1668         default y
1669         help
1670           Allocate PLTs when loading modules so that jumps and calls whose
1671           targets are too far away for their relative offsets to be encoded
1672           in the instructions themselves can be bounced via veneers in the
1673           module's PLT. This allows modules to be allocated in the generic
1674           vmalloc area after the dedicated module memory area has been
1675           exhausted. The modules will use slightly more memory, but after
1676           rounding up to page size, the actual memory footprint is usually
1677           the same.
1678
1679           Disabling this is usually safe for small single-platform
1680           configurations. If unsure, say y.
1681
1682 config FORCE_MAX_ZONEORDER
1683         int "Maximum zone order"
1684         default "12" if SOC_AM33XX
1685         default "9" if SA1111 || ARCH_EFM32
1686         default "11"
1687         help
1688           The kernel memory allocator divides physically contiguous memory
1689           blocks into "zones", where each zone is a power of two number of
1690           pages.  This option selects the largest power of two that the kernel
1691           keeps in the memory allocator.  If you need to allocate very large
1692           blocks of physically contiguous memory, then you may need to
1693           increase this value.
1694
1695           This config option is actually maximum order plus one. For example,
1696           a value of 11 means that the largest free memory block is 2^10 pages.
1697
1698 config ALIGNMENT_TRAP
1699         bool
1700         depends on CPU_CP15_MMU
1701         default y if !ARCH_EBSA110
1702         select HAVE_PROC_CPU if PROC_FS
1703         help
1704           ARM processors cannot fetch/store information which is not
1705           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1706           address divisible by 4. On 32-bit ARM processors, these non-aligned
1707           fetch/store instructions will be emulated in software if you say
1708           here, which has a severe performance impact. This is necessary for
1709           correct operation of some network protocols. With an IP-only
1710           configuration it is safe to say N, otherwise say Y.
1711
1712 config UACCESS_WITH_MEMCPY
1713         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1714         depends on MMU
1715         default y if CPU_FEROCEON
1716         help
1717           Implement faster copy_to_user and clear_user methods for CPU
1718           cores where a 8-word STM instruction give significantly higher
1719           memory write throughput than a sequence of individual 32bit stores.
1720
1721           A possible side effect is a slight increase in scheduling latency
1722           between threads sharing the same address space if they invoke
1723           such copy operations with large buffers.
1724
1725           However, if the CPU data cache is using a write-allocate mode,
1726           this option is unlikely to provide any performance gain.
1727
1728 config SECCOMP
1729         bool
1730         prompt "Enable seccomp to safely compute untrusted bytecode"
1731         ---help---
1732           This kernel feature is useful for number crunching applications
1733           that may need to compute untrusted bytecode during their
1734           execution. By using pipes or other transports made available to
1735           the process as file descriptors supporting the read/write
1736           syscalls, it's possible to isolate those applications in
1737           their own address space using seccomp. Once seccomp is
1738           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1739           and the task is only allowed to execute a few safe syscalls
1740           defined by each seccomp mode.
1741
1742 config PARAVIRT
1743         bool "Enable paravirtualization code"
1744         help
1745           This changes the kernel so it can modify itself when it is run
1746           under a hypervisor, potentially improving performance significantly
1747           over full virtualization.
1748
1749 config PARAVIRT_TIME_ACCOUNTING
1750         bool "Paravirtual steal time accounting"
1751         select PARAVIRT
1752         help
1753           Select this option to enable fine granularity task steal time
1754           accounting. Time spent executing other tasks in parallel with
1755           the current vCPU is discounted from the vCPU power. To account for
1756           that, there can be a small performance impact.
1757
1758           If in doubt, say N here.
1759
1760 config XEN_DOM0
1761         def_bool y
1762         depends on XEN
1763
1764 config XEN
1765         bool "Xen guest support on ARM"
1766         depends on ARM && AEABI && OF
1767         depends on CPU_V7 && !CPU_V6
1768         depends on !GENERIC_ATOMIC64
1769         depends on MMU
1770         select ARCH_DMA_ADDR_T_64BIT
1771         select ARM_PSCI
1772         select SWIOTLB
1773         select SWIOTLB_XEN
1774         select PARAVIRT
1775         help
1776           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1777
1778 config STACKPROTECTOR_PER_TASK
1779         bool "Use a unique stack canary value for each task"
1780         depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1781         select GCC_PLUGIN_ARM_SSP_PER_TASK
1782         default y
1783         help
1784           Due to the fact that GCC uses an ordinary symbol reference from
1785           which to load the value of the stack canary, this value can only
1786           change at reboot time on SMP systems, and all tasks running in the
1787           kernel's address space are forced to use the same canary value for
1788           the entire duration that the system is up.
1789
1790           Enable this option to switch to a different method that uses a
1791           different canary value for each task.
1792
1793 endmenu
1794
1795 menu "Boot options"
1796
1797 config USE_OF
1798         bool "Flattened Device Tree support"
1799         select IRQ_DOMAIN
1800         select OF
1801         help
1802           Include support for flattened device tree machine descriptions.
1803
1804 config ATAGS
1805         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1806         default y
1807         help
1808           This is the traditional way of passing data to the kernel at boot
1809           time. If you are solely relying on the flattened device tree (or
1810           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1811           to remove ATAGS support from your kernel binary.  If unsure,
1812           leave this to y.
1813
1814 config DEPRECATED_PARAM_STRUCT
1815         bool "Provide old way to pass kernel parameters"
1816         depends on ATAGS
1817         help
1818           This was deprecated in 2001 and announced to live on for 5 years.
1819           Some old boot loaders still use this way.
1820
1821 # Compressed boot loader in ROM.  Yes, we really want to ask about
1822 # TEXT and BSS so we preserve their values in the config files.
1823 config ZBOOT_ROM_TEXT
1824         hex "Compressed ROM boot loader base address"
1825         default "0"
1826         help
1827           The physical address at which the ROM-able zImage is to be
1828           placed in the target.  Platforms which normally make use of
1829           ROM-able zImage formats normally set this to a suitable
1830           value in their defconfig file.
1831
1832           If ZBOOT_ROM is not enabled, this has no effect.
1833
1834 config ZBOOT_ROM_BSS
1835         hex "Compressed ROM boot loader BSS address"
1836         default "0"
1837         help
1838           The base address of an area of read/write memory in the target
1839           for the ROM-able zImage which must be available while the
1840           decompressor is running. It must be large enough to hold the
1841           entire decompressed kernel plus an additional 128 KiB.
1842           Platforms which normally make use of ROM-able zImage formats
1843           normally set this to a suitable value in their defconfig file.
1844
1845           If ZBOOT_ROM is not enabled, this has no effect.
1846
1847 config ZBOOT_ROM
1848         bool "Compressed boot loader in ROM/flash"
1849         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1850         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1851         help
1852           Say Y here if you intend to execute your compressed kernel image
1853           (zImage) directly from ROM or flash.  If unsure, say N.
1854
1855 config ARM_APPENDED_DTB
1856         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1857         depends on OF
1858         help
1859           With this option, the boot code will look for a device tree binary
1860           (DTB) appended to zImage
1861           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1862
1863           This is meant as a backward compatibility convenience for those
1864           systems with a bootloader that can't be upgraded to accommodate
1865           the documented boot protocol using a device tree.
1866
1867           Beware that there is very little in terms of protection against
1868           this option being confused by leftover garbage in memory that might
1869           look like a DTB header after a reboot if no actual DTB is appended
1870           to zImage.  Do not leave this option active in a production kernel
1871           if you don't intend to always append a DTB.  Proper passing of the
1872           location into r2 of a bootloader provided DTB is always preferable
1873           to this option.
1874
1875 config ARM_ATAG_DTB_COMPAT
1876         bool "Supplement the appended DTB with traditional ATAG information"
1877         depends on ARM_APPENDED_DTB
1878         help
1879           Some old bootloaders can't be updated to a DTB capable one, yet
1880           they provide ATAGs with memory configuration, the ramdisk address,
1881           the kernel cmdline string, etc.  Such information is dynamically
1882           provided by the bootloader and can't always be stored in a static
1883           DTB.  To allow a device tree enabled kernel to be used with such
1884           bootloaders, this option allows zImage to extract the information
1885           from the ATAG list and store it at run time into the appended DTB.
1886
1887 choice
1888         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1889         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1890
1891 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1892         bool "Use bootloader kernel arguments if available"
1893         help
1894           Uses the command-line options passed by the boot loader instead of
1895           the device tree bootargs property. If the boot loader doesn't provide
1896           any, the device tree bootargs property will be used.
1897
1898 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1899         bool "Extend with bootloader kernel arguments"
1900         help
1901           The command-line arguments provided by the boot loader will be
1902           appended to the the device tree bootargs property.
1903
1904 endchoice
1905
1906 config CMDLINE
1907         string "Default kernel command string"
1908         default ""
1909         help
1910           On some architectures (EBSA110 and CATS), there is currently no way
1911           for the boot loader to pass arguments to the kernel. For these
1912           architectures, you should supply some command-line options at build
1913           time by entering them here. As a minimum, you should specify the
1914           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1915
1916 choice
1917         prompt "Kernel command line type" if CMDLINE != ""
1918         default CMDLINE_FROM_BOOTLOADER
1919         depends on ATAGS
1920
1921 config CMDLINE_FROM_BOOTLOADER
1922         bool "Use bootloader kernel arguments if available"
1923         help
1924           Uses the command-line options passed by the boot loader. If
1925           the boot loader doesn't provide any, the default kernel command
1926           string provided in CMDLINE will be used.
1927
1928 config CMDLINE_EXTEND
1929         bool "Extend bootloader kernel arguments"
1930         help
1931           The command-line arguments provided by the boot loader will be
1932           appended to the default kernel command string.
1933
1934 config CMDLINE_FORCE
1935         bool "Always use the default kernel command string"
1936         help
1937           Always use the default kernel command string, even if the boot
1938           loader passes other arguments to the kernel.
1939           This is useful if you cannot or don't want to change the
1940           command-line options your boot loader passes to the kernel.
1941 endchoice
1942
1943 config XIP_KERNEL
1944         bool "Kernel Execute-In-Place from ROM"
1945         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1946         help
1947           Execute-In-Place allows the kernel to run from non-volatile storage
1948           directly addressable by the CPU, such as NOR flash. This saves RAM
1949           space since the text section of the kernel is not loaded from flash
1950           to RAM.  Read-write sections, such as the data section and stack,
1951           are still copied to RAM.  The XIP kernel is not compressed since
1952           it has to run directly from flash, so it will take more space to
1953           store it.  The flash address used to link the kernel object files,
1954           and for storing it, is configuration dependent. Therefore, if you
1955           say Y here, you must know the proper physical address where to
1956           store the kernel image depending on your own flash memory usage.
1957
1958           Also note that the make target becomes "make xipImage" rather than
1959           "make zImage" or "make Image".  The final kernel binary to put in
1960           ROM memory will be arch/arm/boot/xipImage.
1961
1962           If unsure, say N.
1963
1964 config XIP_PHYS_ADDR
1965         hex "XIP Kernel Physical Location"
1966         depends on XIP_KERNEL
1967         default "0x00080000"
1968         help
1969           This is the physical address in your flash memory the kernel will
1970           be linked for and stored to.  This address is dependent on your
1971           own flash usage.
1972
1973 config XIP_DEFLATED_DATA
1974         bool "Store kernel .data section compressed in ROM"
1975         depends on XIP_KERNEL
1976         select ZLIB_INFLATE
1977         help
1978           Before the kernel is actually executed, its .data section has to be
1979           copied to RAM from ROM. This option allows for storing that data
1980           in compressed form and decompressed to RAM rather than merely being
1981           copied, saving some precious ROM space. A possible drawback is a
1982           slightly longer boot delay.
1983
1984 config KEXEC
1985         bool "Kexec system call (EXPERIMENTAL)"
1986         depends on (!SMP || PM_SLEEP_SMP)
1987         depends on !CPU_V7M
1988         select KEXEC_CORE
1989         help
1990           kexec is a system call that implements the ability to shutdown your
1991           current kernel, and to start another kernel.  It is like a reboot
1992           but it is independent of the system firmware.   And like a reboot
1993           you can start any kernel with it, not just Linux.
1994
1995           It is an ongoing process to be certain the hardware in a machine
1996           is properly shutdown, so do not be surprised if this code does not
1997           initially work for you.
1998
1999 config ATAGS_PROC
2000         bool "Export atags in procfs"
2001         depends on ATAGS && KEXEC
2002         default y
2003         help
2004           Should the atags used to boot the kernel be exported in an "atags"
2005           file in procfs. Useful with kexec.
2006
2007 config CRASH_DUMP
2008         bool "Build kdump crash kernel (EXPERIMENTAL)"
2009         help
2010           Generate crash dump after being started by kexec. This should
2011           be normally only set in special crash dump kernels which are
2012           loaded in the main kernel with kexec-tools into a specially
2013           reserved region and then later executed after a crash by
2014           kdump/kexec. The crash dump kernel must be compiled to a
2015           memory address not used by the main kernel
2016
2017           For more details see Documentation/kdump/kdump.txt
2018
2019 config AUTO_ZRELADDR
2020         bool "Auto calculation of the decompressed kernel image address"
2021         help
2022           ZRELADDR is the physical address where the decompressed kernel
2023           image will be placed. If AUTO_ZRELADDR is selected, the address
2024           will be determined at run-time by masking the current IP with
2025           0xf8000000. This assumes the zImage being placed in the first 128MB
2026           from start of memory.
2027
2028 config EFI_STUB
2029         bool
2030
2031 config EFI
2032         bool "UEFI runtime support"
2033         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2034         select UCS2_STRING
2035         select EFI_PARAMS_FROM_FDT
2036         select EFI_STUB
2037         select EFI_ARMSTUB
2038         select EFI_RUNTIME_WRAPPERS
2039         ---help---
2040           This option provides support for runtime services provided
2041           by UEFI firmware (such as non-volatile variables, realtime
2042           clock, and platform reset). A UEFI stub is also provided to
2043           allow the kernel to be booted as an EFI application. This
2044           is only useful for kernels that may run on systems that have
2045           UEFI firmware.
2046
2047 config DMI
2048         bool "Enable support for SMBIOS (DMI) tables"
2049         depends on EFI
2050         default y
2051         help
2052           This enables SMBIOS/DMI feature for systems.
2053
2054           This option is only useful on systems that have UEFI firmware.
2055           However, even with this option, the resultant kernel should
2056           continue to boot on existing non-UEFI platforms.
2057
2058           NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2059           i.e., the the practice of identifying the platform via DMI to
2060           decide whether certain workarounds for buggy hardware and/or
2061           firmware need to be enabled. This would require the DMI subsystem
2062           to be enabled much earlier than we do on ARM, which is non-trivial.
2063
2064 endmenu
2065
2066 menu "CPU Power Management"
2067
2068 source "drivers/cpufreq/Kconfig"
2069
2070 source "drivers/cpuidle/Kconfig"
2071
2072 endmenu
2073
2074 menu "Floating point emulation"
2075
2076 comment "At least one emulation must be selected"
2077
2078 config FPE_NWFPE
2079         bool "NWFPE math emulation"
2080         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2081         ---help---
2082           Say Y to include the NWFPE floating point emulator in the kernel.
2083           This is necessary to run most binaries. Linux does not currently
2084           support floating point hardware so you need to say Y here even if
2085           your machine has an FPA or floating point co-processor podule.
2086
2087           You may say N here if you are going to load the Acorn FPEmulator
2088           early in the bootup.
2089
2090 config FPE_NWFPE_XP
2091         bool "Support extended precision"
2092         depends on FPE_NWFPE
2093         help
2094           Say Y to include 80-bit support in the kernel floating-point
2095           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2096           Note that gcc does not generate 80-bit operations by default,
2097           so in most cases this option only enlarges the size of the
2098           floating point emulator without any good reason.
2099
2100           You almost surely want to say N here.
2101
2102 config FPE_FASTFPE
2103         bool "FastFPE math emulation (EXPERIMENTAL)"
2104         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2105         ---help---
2106           Say Y here to include the FAST floating point emulator in the kernel.
2107           This is an experimental much faster emulator which now also has full
2108           precision for the mantissa.  It does not support any exceptions.
2109           It is very simple, and approximately 3-6 times faster than NWFPE.
2110
2111           It should be sufficient for most programs.  It may be not suitable
2112           for scientific calculations, but you have to check this for yourself.
2113           If you do not feel you need a faster FP emulation you should better
2114           choose NWFPE.
2115
2116 config VFP
2117         bool "VFP-format floating point maths"
2118         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2119         help
2120           Say Y to include VFP support code in the kernel. This is needed
2121           if your hardware includes a VFP unit.
2122
2123           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2124           release notes and additional status information.
2125
2126           Say N if your target does not have VFP hardware.
2127
2128 config VFPv3
2129         bool
2130         depends on VFP
2131         default y if CPU_V7
2132
2133 config NEON
2134         bool "Advanced SIMD (NEON) Extension support"
2135         depends on VFPv3 && CPU_V7
2136         help
2137           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2138           Extension.
2139
2140 config KERNEL_MODE_NEON
2141         bool "Support for NEON in kernel mode"
2142         depends on NEON && AEABI
2143         help
2144           Say Y to include support for NEON in kernel mode.
2145
2146 endmenu
2147
2148 menu "Power management options"
2149
2150 source "kernel/power/Kconfig"
2151
2152 config ARCH_SUSPEND_POSSIBLE
2153         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2154                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2155         def_bool y
2156
2157 config ARM_CPU_SUSPEND
2158         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2159         depends on ARCH_SUSPEND_POSSIBLE
2160
2161 config ARCH_HIBERNATION_POSSIBLE
2162         bool
2163         depends on MMU
2164         default y if ARCH_SUSPEND_POSSIBLE
2165
2166 endmenu
2167
2168 source "drivers/firmware/Kconfig"
2169
2170 if CRYPTO
2171 source "arch/arm/crypto/Kconfig"
2172 endif
2173
2174 source "arch/arm/kvm/Kconfig"