arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_CLOCKSOURCE_DATA
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_HARDENED_USERCOPY
  39         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  41         select HAVE_ARCH_MMAP_RND_BITS if MMU
  42         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  43         select HAVE_ARCH_TRACEHOOK
  44         select HAVE_ARM_SMCCC if CPU_V7
  45         select HAVE_CBPF_JIT
  46         select HAVE_CC_STACKPROTECTOR
  47         select HAVE_CONTEXT_TRACKING
  48         select HAVE_C_RECORDMCOUNT
  49         select HAVE_DEBUG_KMEMLEAK
  50         select HAVE_DMA_API_DEBUG
  51         select HAVE_DMA_CONTIGUOUS if MMU
  52         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  53         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  54         select HAVE_EXIT_THREAD
  55         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  56         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  57         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  58         select HAVE_GCC_PLUGINS
  59         select HAVE_GENERIC_DMA_COHERENT
  60         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  61         select HAVE_IDE if PCI || ISA || PCMCIA
  62         select HAVE_IRQ_TIME_ACCOUNTING
  63         select HAVE_KERNEL_GZIP
  64         select HAVE_KERNEL_LZ4
  65         select HAVE_KERNEL_LZMA
  66         select HAVE_KERNEL_LZO
  67         select HAVE_KERNEL_XZ
  68         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  69         select HAVE_KRETPROBES if (HAVE_KPROBES)
  70         select HAVE_MEMBLOCK
  71         select HAVE_MOD_ARCH_SPECIFIC
  72         select HAVE_NMI
  73         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  74         select HAVE_OPTPROBES if !THUMB2_KERNEL
  75         select HAVE_PERF_EVENTS
  76         select HAVE_PERF_REGS
  77         select HAVE_PERF_USER_STACK_DUMP
  78         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  79         select HAVE_REGS_AND_STACK_ACCESS_API
  80         select HAVE_SYSCALL_TRACEPOINTS
  81         select HAVE_UID16
  82         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  83         select IRQ_FORCED_THREADING
  84         select MODULES_USE_ELF_REL
  85         select NO_BOOTMEM
  86         select OF_EARLY_FLATTREE if OF
  87         select OF_RESERVED_MEM if OF
  88         select OLD_SIGACTION
  89         select OLD_SIGSUSPEND3
  90         select PERF_USE_VMALLOC
  91         select RTC_LIB
  92         select SYS_SUPPORTS_APM_EMULATION
  93         # Above selects are sorted alphabetically; please add new ones
  94         # according to that.  Thanks.
  95         help
  96           The ARM series is a line of low-power-consumption RISC chip designs
  97           licensed by ARM Ltd and targeted at embedded applications and
  98           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  99           manufactured, but legacy ARM-based PC hardware remains popular in
 100           Europe.  There is an ARM Linux project with a web page at
 101           <http://www.arm.linux.org.uk/>.
 102
 103 config ARM_HAS_SG_CHAIN
 104         select ARCH_HAS_SG_CHAIN
 105         bool
 106
 107 config NEED_SG_DMA_LENGTH
 108         bool
 109
 110 config ARM_DMA_USE_IOMMU
 111         bool
 112         select ARM_HAS_SG_CHAIN
 113         select NEED_SG_DMA_LENGTH
 114
 115 if ARM_DMA_USE_IOMMU
 116
 117 config ARM_DMA_IOMMU_ALIGNMENT
 118         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 119         range 4 9
 120         default 8
 121         help
 122           DMA mapping framework by default aligns all buffers to the smallest
 123           PAGE_SIZE order which is greater than or equal to the requested buffer
 124           size. This works well for buffers up to a few hundreds kilobytes, but
 125           for larger buffers it just a waste of address space. Drivers which has
 126           relatively small addressing window (like 64Mib) might run out of
 127           virtual space with just a few allocations.
 128
 129           With this parameter you can specify the maximum PAGE_SIZE order for
 130           DMA IOMMU buffers. Larger buffers will be aligned only to this
 131           specified order. The order is expressed as a power of two multiplied
 132           by the PAGE_SIZE.
 133
 134 endif
 135
 136 config MIGHT_HAVE_PCI
 137         bool
 138
 139 config SYS_SUPPORTS_APM_EMULATION
 140         bool
 141
 142 config HAVE_TCM
 143         bool
 144         select GENERIC_ALLOCATOR
 145
 146 config HAVE_PROC_CPU
 147         bool
 148
 149 config NO_IOPORT_MAP
 150         bool
 151
 152 config EISA
 153         bool
 154         ---help---
 155           The Extended Industry Standard Architecture (EISA) bus was
 156           developed as an open alternative to the IBM MicroChannel bus.
 157
 158           The EISA bus provided some of the features of the IBM MicroChannel
 159           bus while maintaining backward compatibility with cards made for
 160           the older ISA bus.  The EISA bus saw limited use between 1988 and
 161           1995 when it was made obsolete by the PCI bus.
 162
 163           Say Y here if you are building a kernel for an EISA-based machine.
 164
 165           Otherwise, say N.
 166
 167 config SBUS
 168         bool
 169
 170 config STACKTRACE_SUPPORT
 171         bool
 172         default y
 173
 174 config LOCKDEP_SUPPORT
 175         bool
 176         default y
 177
 178 config TRACE_IRQFLAGS_SUPPORT
 179         bool
 180         default !CPU_V7M
 181
 182 config RWSEM_XCHGADD_ALGORITHM
 183         bool
 184         default y
 185
 186 config ARCH_HAS_ILOG2_U32
 187         bool
 188
 189 config ARCH_HAS_ILOG2_U64
 190         bool
 191
 192 config ARCH_HAS_BANDGAP
 193         bool
 194
 195 config FIX_EARLYCON_MEM
 196         def_bool y if MMU
 197
 198 config GENERIC_HWEIGHT
 199         bool
 200         default y
 201
 202 config GENERIC_CALIBRATE_DELAY
 203         bool
 204         default y
 205
 206 config ARCH_MAY_HAVE_PC_FDC
 207         bool
 208
 209 config ZONE_DMA
 210         bool
 211
 212 config NEED_DMA_MAP_STATE
 213        def_bool y
 214
 215 config ARCH_SUPPORTS_UPROBES
 216         def_bool y
 217
 218 config ARCH_HAS_DMA_SET_COHERENT_MASK
 219         bool
 220
 221 config GENERIC_ISA_DMA
 222         bool
 223
 224 config FIQ
 225         bool
 226
 227 config NEED_RET_TO_USER
 228         bool
 229
 230 config ARCH_MTD_XIP
 231         bool
 232
 233 config VECTORS_BASE
 234         hex
 235         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 236         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 237         default 0x00000000
 238         help
 239           The base address of exception vectors.  This must be two pages
 240           in size.
 241
 242 config ARM_PATCH_PHYS_VIRT
 243         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 244         default y
 245         depends on !XIP_KERNEL && MMU
 246         help
 247           Patch phys-to-virt and virt-to-phys translation functions at
 248           boot and module load time according to the position of the
 249           kernel in system memory.
 250
 251           This can only be used with non-XIP MMU kernels where the base
 252           of physical memory is at a 16MB boundary.
 253
 254           Only disable this option if you know that you do not require
 255           this feature (eg, building a kernel for a single machine) and
 256           you need to shrink the kernel to the minimal size.
 257
 258 config NEED_MACH_IO_H
 259         bool
 260         help
 261           Select this when mach/io.h is required to provide special
 262           definitions for this platform.  The need for mach/io.h should
 263           be avoided when possible.
 264
 265 config NEED_MACH_MEMORY_H
 266         bool
 267         help
 268           Select this when mach/memory.h is required to provide special
 269           definitions for this platform.  The need for mach/memory.h should
 270           be avoided when possible.
 271
 272 config PHYS_OFFSET
 273         hex "Physical address of main memory" if MMU
 274         depends on !ARM_PATCH_PHYS_VIRT
 275         default DRAM_BASE if !MMU
 276         default 0x00000000 if ARCH_EBSA110 || \
 277                         ARCH_FOOTBRIDGE || \
 278                         ARCH_INTEGRATOR || \
 279                         ARCH_IOP13XX || \
 280                         ARCH_KS8695 || \
 281                         ARCH_REALVIEW
 282         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 283         default 0x20000000 if ARCH_S5PV210
 284         default 0xc0000000 if ARCH_SA1100
 285         help
 286           Please provide the physical address corresponding to the
 287           location of main memory in your system.
 288
 289 config GENERIC_BUG
 290         def_bool y
 291         depends on BUG
 292
 293 config PGTABLE_LEVELS
 294         int
 295         default 3 if ARM_LPAE
 296         default 2
 297
 298 source "init/Kconfig"
 299
 300 source "kernel/Kconfig.freezer"
 301
 302 menu "System Type"
 303
 304 config MMU
 305         bool "MMU-based Paged Memory Management Support"
 306         default y
 307         help
 308           Select if you want MMU-based virtualised addressing space
 309           support by paged memory management. If unsure, say 'Y'.
 310
 311 config ARCH_MMAP_RND_BITS_MIN
 312         default 8
 313
 314 config ARCH_MMAP_RND_BITS_MAX
 315         default 14 if PAGE_OFFSET=0x40000000
 316         default 15 if PAGE_OFFSET=0x80000000
 317         default 16
 318
 319 #
 320 # The "ARM system type" choice list is ordered alphabetically by option
 321 # text.  Please add new entries in the option alphabetic order.
 322 #
 323 choice
 324         prompt "ARM system type"
 325         default ARM_SINGLE_ARMV7M if !MMU
 326         default ARCH_MULTIPLATFORM if MMU
 327
 328 config ARCH_MULTIPLATFORM
 329         bool "Allow multiple platforms to be selected"
 330         depends on MMU
 331         select ARM_HAS_SG_CHAIN
 332         select ARM_PATCH_PHYS_VIRT
 333         select AUTO_ZRELADDR
 334         select CLKSRC_OF
 335         select COMMON_CLK
 336         select GENERIC_CLOCKEVENTS
 337         select MIGHT_HAVE_PCI
 338         select MULTI_IRQ_HANDLER
 339         select PCI_DOMAINS if PCI
 340         select SPARSE_IRQ
 341         select USE_OF
 342
 343 config ARM_SINGLE_ARMV7M
 344         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 345         depends on !MMU
 346         select ARM_NVIC
 347         select AUTO_ZRELADDR
 348         select CLKSRC_OF
 349         select COMMON_CLK
 350         select CPU_V7M
 351         select GENERIC_CLOCKEVENTS
 352         select NO_IOPORT_MAP
 353         select SPARSE_IRQ
 354         select USE_OF
 355
 356 config ARCH_GEMINI
 357         bool "Cortina Systems Gemini"
 358         select CLKSRC_MMIO
 359         select CPU_FA526
 360         select GENERIC_CLOCKEVENTS
 361         select GPIOLIB
 362         help
 363           Support for the Cortina Systems Gemini family SoCs
 364
 365 config ARCH_EBSA110
 366         bool "EBSA-110"
 367         select ARCH_USES_GETTIMEOFFSET
 368         select CPU_SA110
 369         select ISA
 370         select NEED_MACH_IO_H
 371         select NEED_MACH_MEMORY_H
 372         select NO_IOPORT_MAP
 373         help
 374           This is an evaluation board for the StrongARM processor available
 375           from Digital. It has limited hardware on-board, including an
 376           Ethernet interface, two PCMCIA sockets, two serial ports and a
 377           parallel port.
 378
 379 config ARCH_EP93XX
 380         bool "EP93xx-based"
 381         select ARCH_HAS_HOLES_MEMORYMODEL
 382         select ARM_AMBA
 383         select ARM_PATCH_PHYS_VIRT
 384         select ARM_VIC
 385         select AUTO_ZRELADDR
 386         select CLKDEV_LOOKUP
 387         select CLKSRC_MMIO
 388         select CPU_ARM920T
 389         select GENERIC_CLOCKEVENTS
 390         select GPIOLIB
 391         help
 392           This enables support for the Cirrus EP93xx series of CPUs.
 393
 394 config ARCH_FOOTBRIDGE
 395         bool "FootBridge"
 396         select CPU_SA110
 397         select FOOTBRIDGE
 398         select GENERIC_CLOCKEVENTS
 399         select HAVE_IDE
 400         select NEED_MACH_IO_H if !MMU
 401         select NEED_MACH_MEMORY_H
 402         help
 403           Support for systems based on the DC21285 companion chip
 404           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 405
 406 config ARCH_NETX
 407         bool "Hilscher NetX based"
 408         select ARM_VIC
 409         select CLKSRC_MMIO
 410         select CPU_ARM926T
 411         select GENERIC_CLOCKEVENTS
 412         help
 413           This enables support for systems based on the Hilscher NetX Soc
 414
 415 config ARCH_IOP13XX
 416         bool "IOP13xx-based"
 417         depends on MMU
 418         select CPU_XSC3
 419         select NEED_MACH_MEMORY_H
 420         select NEED_RET_TO_USER
 421         select PCI
 422         select PLAT_IOP
 423         select VMSPLIT_1G
 424         select SPARSE_IRQ
 425         help
 426           Support for Intel's IOP13XX (XScale) family of processors.
 427
 428 config ARCH_IOP32X
 429         bool "IOP32x-based"
 430         depends on MMU
 431         select CPU_XSCALE
 432         select GPIO_IOP
 433         select GPIOLIB
 434         select NEED_RET_TO_USER
 435         select PCI
 436         select PLAT_IOP
 437         help
 438           Support for Intel's 80219 and IOP32X (XScale) family of
 439           processors.
 440
 441 config ARCH_IOP33X
 442         bool "IOP33x-based"
 443         depends on MMU
 444         select CPU_XSCALE
 445         select GPIO_IOP
 446         select GPIOLIB
 447         select NEED_RET_TO_USER
 448         select PCI
 449         select PLAT_IOP
 450         help
 451           Support for Intel's IOP33X (XScale) family of processors.
 452
 453 config ARCH_IXP4XX
 454         bool "IXP4xx-based"
 455         depends on MMU
 456         select ARCH_HAS_DMA_SET_COHERENT_MASK
 457         select ARCH_SUPPORTS_BIG_ENDIAN
 458         select CLKSRC_MMIO
 459         select CPU_XSCALE
 460         select DMABOUNCE if PCI
 461         select GENERIC_CLOCKEVENTS
 462         select GPIOLIB
 463         select MIGHT_HAVE_PCI
 464         select NEED_MACH_IO_H
 465         select USB_EHCI_BIG_ENDIAN_DESC
 466         select USB_EHCI_BIG_ENDIAN_MMIO
 467         help
 468           Support for Intel's IXP4XX (XScale) family of processors.
 469
 470 config ARCH_DOVE
 471         bool "Marvell Dove"
 472         select CPU_PJ4
 473         select GENERIC_CLOCKEVENTS
 474         select GPIOLIB
 475         select MIGHT_HAVE_PCI
 476         select MULTI_IRQ_HANDLER
 477         select MVEBU_MBUS
 478         select PINCTRL
 479         select PINCTRL_DOVE
 480         select PLAT_ORION_LEGACY
 481         select SPARSE_IRQ
 482         select PM_GENERIC_DOMAINS if PM
 483         help
 484           Support for the Marvell Dove SoC 88AP510
 485
 486 config ARCH_KS8695
 487         bool "Micrel/Kendin KS8695"
 488         select CLKSRC_MMIO
 489         select CPU_ARM922T
 490         select GENERIC_CLOCKEVENTS
 491         select GPIOLIB
 492         select NEED_MACH_MEMORY_H
 493         help
 494           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 495           System-on-Chip devices.
 496
 497 config ARCH_W90X900
 498         bool "Nuvoton W90X900 CPU"
 499         select CLKDEV_LOOKUP
 500         select CLKSRC_MMIO
 501         select CPU_ARM926T
 502         select GENERIC_CLOCKEVENTS
 503         select GPIOLIB
 504         help
 505           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 506           At present, the w90x900 has been renamed nuc900, regarding
 507           the ARM series product line, you can login the following
 508           link address to know more.
 509
 510           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 511                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 512
 513 config ARCH_LPC32XX
 514         bool "NXP LPC32XX"
 515         select ARM_AMBA
 516         select CLKDEV_LOOKUP
 517         select CLKSRC_LPC32XX
 518         select COMMON_CLK
 519         select CPU_ARM926T
 520         select GENERIC_CLOCKEVENTS
 521         select GPIOLIB
 522         select MULTI_IRQ_HANDLER
 523         select SPARSE_IRQ
 524         select USE_OF
 525         help
 526           Support for the NXP LPC32XX family of processors
 527
 528 config ARCH_PXA
 529         bool "PXA2xx/PXA3xx-based"
 530         depends on MMU
 531         select ARCH_MTD_XIP
 532         select ARM_CPU_SUSPEND if PM
 533         select AUTO_ZRELADDR
 534         select COMMON_CLK
 535         select CLKDEV_LOOKUP
 536         select CLKSRC_PXA
 537         select CLKSRC_MMIO
 538         select CLKSRC_OF
 539         select CPU_XSCALE if !CPU_XSC3
 540         select GENERIC_CLOCKEVENTS
 541         select GPIO_PXA
 542         select GPIOLIB
 543         select HAVE_IDE
 544         select IRQ_DOMAIN
 545         select MULTI_IRQ_HANDLER
 546         select PLAT_PXA
 547         select SPARSE_IRQ
 548         help
 549           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 550
 551 config ARCH_RPC
 552         bool "RiscPC"
 553         depends on MMU
 554         select ARCH_ACORN
 555         select ARCH_MAY_HAVE_PC_FDC
 556         select ARCH_SPARSEMEM_ENABLE
 557         select ARCH_USES_GETTIMEOFFSET
 558         select CPU_SA110
 559         select FIQ
 560         select HAVE_IDE
 561         select HAVE_PATA_PLATFORM
 562         select ISA_DMA_API
 563         select NEED_MACH_IO_H
 564         select NEED_MACH_MEMORY_H
 565         select NO_IOPORT_MAP
 566         help
 567           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 568           CD-ROM interface, serial and parallel port, and the floppy drive.
 569
 570 config ARCH_SA1100
 571         bool "SA1100-based"
 572         select ARCH_MTD_XIP
 573         select ARCH_SPARSEMEM_ENABLE
 574         select CLKDEV_LOOKUP
 575         select CLKSRC_MMIO
 576         select CLKSRC_PXA
 577         select CLKSRC_OF if OF
 578         select CPU_FREQ
 579         select CPU_SA1100
 580         select GENERIC_CLOCKEVENTS
 581         select GPIOLIB
 582         select HAVE_IDE
 583         select IRQ_DOMAIN
 584         select ISA
 585         select MULTI_IRQ_HANDLER
 586         select NEED_MACH_MEMORY_H
 587         select SPARSE_IRQ
 588         help
 589           Support for StrongARM 11x0 based boards.
 590
 591 config ARCH_S3C24XX
 592         bool "Samsung S3C24XX SoCs"
 593         select ATAGS
 594         select CLKDEV_LOOKUP
 595         select CLKSRC_SAMSUNG_PWM
 596         select GENERIC_CLOCKEVENTS
 597         select GPIO_SAMSUNG
 598         select GPIOLIB
 599         select HAVE_S3C2410_I2C if I2C
 600         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 601         select HAVE_S3C_RTC if RTC_CLASS
 602         select MULTI_IRQ_HANDLER
 603         select NEED_MACH_IO_H
 604         select SAMSUNG_ATAGS
 605         help
 606           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 607           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 608           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 609           Samsung SMDK2410 development board (and derivatives).
 610
 611 config ARCH_DAVINCI
 612         bool "TI DaVinci"
 613         select ARCH_HAS_HOLES_MEMORYMODEL
 614         select CLKDEV_LOOKUP
 615         select CPU_ARM926T
 616         select GENERIC_ALLOCATOR
 617         select GENERIC_CLOCKEVENTS
 618         select GENERIC_IRQ_CHIP
 619         select GPIOLIB
 620         select HAVE_IDE
 621         select USE_OF
 622         select ZONE_DMA
 623         help
 624           Support for TI's DaVinci platform.
 625
 626 config ARCH_OMAP1
 627         bool "TI OMAP1"
 628         depends on MMU
 629         select ARCH_HAS_HOLES_MEMORYMODEL
 630         select ARCH_OMAP
 631         select CLKDEV_LOOKUP
 632         select CLKSRC_MMIO
 633         select GENERIC_CLOCKEVENTS
 634         select GENERIC_IRQ_CHIP
 635         select GPIOLIB
 636         select HAVE_IDE
 637         select IRQ_DOMAIN
 638         select MULTI_IRQ_HANDLER
 639         select NEED_MACH_IO_H if PCCARD
 640         select NEED_MACH_MEMORY_H
 641         select SPARSE_IRQ
 642         help
 643           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 644
 645 endchoice
 646
 647 menu "Multiple platform selection"
 648         depends on ARCH_MULTIPLATFORM
 649
 650 comment "CPU Core family selection"
 651
 652 config ARCH_MULTI_V4
 653         bool "ARMv4 based platforms (FA526)"
 654         depends on !ARCH_MULTI_V6_V7
 655         select ARCH_MULTI_V4_V5
 656         select CPU_FA526
 657
 658 config ARCH_MULTI_V4T
 659         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 660         depends on !ARCH_MULTI_V6_V7
 661         select ARCH_MULTI_V4_V5
 662         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 663                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 664                 CPU_ARM925T || CPU_ARM940T)
 665
 666 config ARCH_MULTI_V5
 667         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 668         depends on !ARCH_MULTI_V6_V7
 669         select ARCH_MULTI_V4_V5
 670         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 671                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 672                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 673
 674 config ARCH_MULTI_V4_V5
 675         bool
 676
 677 config ARCH_MULTI_V6
 678         bool "ARMv6 based platforms (ARM11)"
 679         select ARCH_MULTI_V6_V7
 680         select CPU_V6K
 681
 682 config ARCH_MULTI_V7
 683         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 684         default y
 685         select ARCH_MULTI_V6_V7
 686         select CPU_V7
 687         select HAVE_SMP
 688
 689 config ARCH_MULTI_V6_V7
 690         bool
 691         select MIGHT_HAVE_CACHE_L2X0
 692
 693 config ARCH_MULTI_CPU_AUTO
 694         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 695         select ARCH_MULTI_V5
 696
 697 endmenu
 698
 699 config ARCH_VIRT
 700         bool "Dummy Virtual Machine"
 701         depends on ARCH_MULTI_V7
 702         select ARM_AMBA
 703         select ARM_GIC
 704         select ARM_GIC_V2M if PCI
 705         select ARM_GIC_V3
 706         select ARM_GIC_V3_ITS if PCI
 707         select ARM_PSCI
 708         select HAVE_ARM_ARCH_TIMER
 709
 710 #
 711 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 712 # Kconfigs may be included either alphabetically (according to the
 713 # plat- suffix) or along side the corresponding mach-* source.
 714 #
 715 source "arch/arm/mach-mvebu/Kconfig"
 716
 717 source "arch/arm/mach-alpine/Kconfig"
 718
 719 source "arch/arm/mach-artpec/Kconfig"
 720
 721 source "arch/arm/mach-asm9260/Kconfig"
 722
 723 source "arch/arm/mach-at91/Kconfig"
 724
 725 source "arch/arm/mach-axxia/Kconfig"
 726
 727 source "arch/arm/mach-bcm/Kconfig"
 728
 729 source "arch/arm/mach-berlin/Kconfig"
 730
 731 source "arch/arm/mach-clps711x/Kconfig"
 732
 733 source "arch/arm/mach-cns3xxx/Kconfig"
 734
 735 source "arch/arm/mach-davinci/Kconfig"
 736
 737 source "arch/arm/mach-digicolor/Kconfig"
 738
 739 source "arch/arm/mach-dove/Kconfig"
 740
 741 source "arch/arm/mach-ep93xx/Kconfig"
 742
 743 source "arch/arm/mach-footbridge/Kconfig"
 744
 745 source "arch/arm/mach-gemini/Kconfig"
 746
 747 source "arch/arm/mach-highbank/Kconfig"
 748
 749 source "arch/arm/mach-hisi/Kconfig"
 750
 751 source "arch/arm/mach-integrator/Kconfig"
 752
 753 source "arch/arm/mach-iop32x/Kconfig"
 754
 755 source "arch/arm/mach-iop33x/Kconfig"
 756
 757 source "arch/arm/mach-iop13xx/Kconfig"
 758
 759 source "arch/arm/mach-ixp4xx/Kconfig"
 760
 761 source "arch/arm/mach-keystone/Kconfig"
 762
 763 source "arch/arm/mach-ks8695/Kconfig"
 764
 765 source "arch/arm/mach-meson/Kconfig"
 766
 767 source "arch/arm/mach-moxart/Kconfig"
 768
 769 source "arch/arm/mach-aspeed/Kconfig"
 770
 771 source "arch/arm/mach-mv78xx0/Kconfig"
 772
 773 source "arch/arm/mach-imx/Kconfig"
 774
 775 source "arch/arm/mach-mediatek/Kconfig"
 776
 777 source "arch/arm/mach-mxs/Kconfig"
 778
 779 source "arch/arm/mach-netx/Kconfig"
 780
 781 source "arch/arm/mach-nomadik/Kconfig"
 782
 783 source "arch/arm/mach-nspire/Kconfig"
 784
 785 source "arch/arm/plat-omap/Kconfig"
 786
 787 source "arch/arm/mach-omap1/Kconfig"
 788
 789 source "arch/arm/mach-omap2/Kconfig"
 790
 791 source "arch/arm/mach-orion5x/Kconfig"
 792
 793 source "arch/arm/mach-picoxcell/Kconfig"
 794
 795 source "arch/arm/mach-pxa/Kconfig"
 796 source "arch/arm/plat-pxa/Kconfig"
 797
 798 source "arch/arm/mach-mmp/Kconfig"
 799
 800 source "arch/arm/mach-oxnas/Kconfig"
 801
 802 source "arch/arm/mach-qcom/Kconfig"
 803
 804 source "arch/arm/mach-realview/Kconfig"
 805
 806 source "arch/arm/mach-rockchip/Kconfig"
 807
 808 source "arch/arm/mach-sa1100/Kconfig"
 809
 810 source "arch/arm/mach-socfpga/Kconfig"
 811
 812 source "arch/arm/mach-spear/Kconfig"
 813
 814 source "arch/arm/mach-sti/Kconfig"
 815
 816 source "arch/arm/mach-s3c24xx/Kconfig"
 817
 818 source "arch/arm/mach-s3c64xx/Kconfig"
 819
 820 source "arch/arm/mach-s5pv210/Kconfig"
 821
 822 source "arch/arm/mach-exynos/Kconfig"
 823 source "arch/arm/plat-samsung/Kconfig"
 824
 825 source "arch/arm/mach-shmobile/Kconfig"
 826
 827 source "arch/arm/mach-sunxi/Kconfig"
 828
 829 source "arch/arm/mach-prima2/Kconfig"
 830
 831 source "arch/arm/mach-tango/Kconfig"
 832
 833 source "arch/arm/mach-tegra/Kconfig"
 834
 835 source "arch/arm/mach-u300/Kconfig"
 836
 837 source "arch/arm/mach-uniphier/Kconfig"
 838
 839 source "arch/arm/mach-ux500/Kconfig"
 840
 841 source "arch/arm/mach-versatile/Kconfig"
 842
 843 source "arch/arm/mach-vexpress/Kconfig"
 844 source "arch/arm/plat-versatile/Kconfig"
 845
 846 source "arch/arm/mach-vt8500/Kconfig"
 847
 848 source "arch/arm/mach-w90x900/Kconfig"
 849
 850 source "arch/arm/mach-zx/Kconfig"
 851
 852 source "arch/arm/mach-zynq/Kconfig"
 853
 854 # ARMv7-M architecture
 855 config ARCH_EFM32
 856         bool "Energy Micro efm32"
 857         depends on ARM_SINGLE_ARMV7M
 858         select GPIOLIB
 859         help
 860           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 861           processors.
 862
 863 config ARCH_LPC18XX
 864         bool "NXP LPC18xx/LPC43xx"
 865         depends on ARM_SINGLE_ARMV7M
 866         select ARCH_HAS_RESET_CONTROLLER
 867         select ARM_AMBA
 868         select CLKSRC_LPC32XX
 869         select PINCTRL
 870         help
 871           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 872           high performance microcontrollers.
 873
 874 config ARCH_STM32
 875         bool "STMicrolectronics STM32"
 876         depends on ARM_SINGLE_ARMV7M
 877         select ARCH_HAS_RESET_CONTROLLER
 878         select ARMV7M_SYSTICK
 879         select CLKSRC_STM32
 880         select PINCTRL
 881         select RESET_CONTROLLER
 882         select STM32_EXTI
 883         help
 884           Support for STMicroelectronics STM32 processors.
 885
 886 config MACH_STM32F429
 887         bool "STMicrolectronics STM32F429"
 888         depends on ARCH_STM32
 889         default y
 890
 891 config ARCH_MPS2
 892         bool "ARM MPS2 platform"
 893         depends on ARM_SINGLE_ARMV7M
 894         select ARM_AMBA
 895         select CLKSRC_MPS2
 896         help
 897           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 898           with a range of available cores like Cortex-M3/M4/M7.
 899
 900           Please, note that depends which Application Note is used memory map
 901           for the platform may vary, so adjustment of RAM base might be needed.
 902
 903 # Definitions to make life easier
 904 config ARCH_ACORN
 905         bool
 906
 907 config PLAT_IOP
 908         bool
 909         select GENERIC_CLOCKEVENTS
 910
 911 config PLAT_ORION
 912         bool
 913         select CLKSRC_MMIO
 914         select COMMON_CLK
 915         select GENERIC_IRQ_CHIP
 916         select IRQ_DOMAIN
 917
 918 config PLAT_ORION_LEGACY
 919         bool
 920         select PLAT_ORION
 921
 922 config PLAT_PXA
 923         bool
 924
 925 config PLAT_VERSATILE
 926         bool
 927
 928 source "arch/arm/firmware/Kconfig"
 929
 930 source arch/arm/mm/Kconfig
 931
 932 config IWMMXT
 933         bool "Enable iWMMXt support"
 934         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 935         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 936         help
 937           Enable support for iWMMXt context switching at run time if
 938           running on a CPU that supports it.
 939
 940 config MULTI_IRQ_HANDLER
 941         bool
 942         help
 943           Allow each machine to specify it's own IRQ handler at run time.
 944
 945 if !MMU
 946 source "arch/arm/Kconfig-nommu"
 947 endif
 948
 949 config PJ4B_ERRATA_4742
 950         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 951         depends on CPU_PJ4B && MACH_ARMADA_370
 952         default y
 953         help
 954           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 955           Event (WFE) IDLE states, a specific timing sensitivity exists between
 956           the retiring WFI/WFE instructions and the newly issued subsequent
 957           instructions.  This sensitivity can result in a CPU hang scenario.
 958           Workaround:
 959           The software must insert either a Data Synchronization Barrier (DSB)
 960           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 961           instruction
 962
 963 config ARM_ERRATA_326103
 964         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 965         depends on CPU_V6
 966         help
 967           Executing a SWP instruction to read-only memory does not set bit 11
 968           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 969           treat the access as a read, preventing a COW from occurring and
 970           causing the faulting task to livelock.
 971
 972 config ARM_ERRATA_411920
 973         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 974         depends on CPU_V6 || CPU_V6K
 975         help
 976           Invalidation of the Instruction Cache operation can
 977           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 978           It does not affect the MPCore. This option enables the ARM Ltd.
 979           recommended workaround.
 980
 981 config ARM_ERRATA_430973
 982         bool "ARM errata: Stale prediction on replaced interworking branch"
 983         depends on CPU_V7
 984         help
 985           This option enables the workaround for the 430973 Cortex-A8
 986           r1p* erratum. If a code sequence containing an ARM/Thumb
 987           interworking branch is replaced with another code sequence at the
 988           same virtual address, whether due to self-modifying code or virtual
 989           to physical address re-mapping, Cortex-A8 does not recover from the
 990           stale interworking branch prediction. This results in Cortex-A8
 991           executing the new code sequence in the incorrect ARM or Thumb state.
 992           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 993           and also flushes the branch target cache at every context switch.
 994           Note that setting specific bits in the ACTLR register may not be
 995           available in non-secure mode.
 996
 997 config ARM_ERRATA_458693
 998         bool "ARM errata: Processor deadlock when a false hazard is created"
 999         depends on CPU_V7
1000         depends on !ARCH_MULTIPLATFORM
1001         help
1002           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1003           erratum. For very specific sequences of memory operations, it is
1004           possible for a hazard condition intended for a cache line to instead
1005           be incorrectly associated with a different cache line. This false
1006           hazard might then cause a processor deadlock. The workaround enables
1007           the L1 caching of the NEON accesses and disables the PLD instruction
1008           in the ACTLR register. Note that setting specific bits in the ACTLR
1009           register may not be available in non-secure mode.
1010
1011 config ARM_ERRATA_460075
1012         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1013         depends on CPU_V7
1014         depends on !ARCH_MULTIPLATFORM
1015         help
1016           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1017           erratum. Any asynchronous access to the L2 cache may encounter a
1018           situation in which recent store transactions to the L2 cache are lost
1019           and overwritten with stale memory contents from external memory. The
1020           workaround disables the write-allocate mode for the L2 cache via the
1021           ACTLR register. Note that setting specific bits in the ACTLR register
1022           may not be available in non-secure mode.
1023
1024 config ARM_ERRATA_742230
1025         bool "ARM errata: DMB operation may be faulty"
1026         depends on CPU_V7 && SMP
1027         depends on !ARCH_MULTIPLATFORM
1028         help
1029           This option enables the workaround for the 742230 Cortex-A9
1030           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1031           between two write operations may not ensure the correct visibility
1032           ordering of the two writes. This workaround sets a specific bit in
1033           the diagnostic register of the Cortex-A9 which causes the DMB
1034           instruction to behave as a DSB, ensuring the correct behaviour of
1035           the two writes.
1036
1037 config ARM_ERRATA_742231
1038         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1039         depends on CPU_V7 && SMP
1040         depends on !ARCH_MULTIPLATFORM
1041         help
1042           This option enables the workaround for the 742231 Cortex-A9
1043           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1044           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1045           accessing some data located in the same cache line, may get corrupted
1046           data due to bad handling of the address hazard when the line gets
1047           replaced from one of the CPUs at the same time as another CPU is
1048           accessing it. This workaround sets specific bits in the diagnostic
1049           register of the Cortex-A9 which reduces the linefill issuing
1050           capabilities of the processor.
1051
1052 config ARM_ERRATA_643719
1053         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1054         depends on CPU_V7 && SMP
1055         default y
1056         help
1057           This option enables the workaround for the 643719 Cortex-A9 (prior to
1058           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1059           register returns zero when it should return one. The workaround
1060           corrects this value, ensuring cache maintenance operations which use
1061           it behave as intended and avoiding data corruption.
1062
1063 config ARM_ERRATA_720789
1064         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1065         depends on CPU_V7
1066         help
1067           This option enables the workaround for the 720789 Cortex-A9 (prior to
1068           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1069           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1070           As a consequence of this erratum, some TLB entries which should be
1071           invalidated are not, resulting in an incoherency in the system page
1072           tables. The workaround changes the TLB flushing routines to invalidate
1073           entries regardless of the ASID.
1074
1075 config ARM_ERRATA_743622
1076         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1077         depends on CPU_V7
1078         depends on !ARCH_MULTIPLATFORM
1079         help
1080           This option enables the workaround for the 743622 Cortex-A9
1081           (r2p*) erratum. Under very rare conditions, a faulty
1082           optimisation in the Cortex-A9 Store Buffer may lead to data
1083           corruption. This workaround sets a specific bit in the diagnostic
1084           register of the Cortex-A9 which disables the Store Buffer
1085           optimisation, preventing the defect from occurring. This has no
1086           visible impact on the overall performance or power consumption of the
1087           processor.
1088
1089 config ARM_ERRATA_751472
1090         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1091         depends on CPU_V7
1092         depends on !ARCH_MULTIPLATFORM
1093         help
1094           This option enables the workaround for the 751472 Cortex-A9 (prior
1095           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1096           completion of a following broadcasted operation if the second
1097           operation is received by a CPU before the ICIALLUIS has completed,
1098           potentially leading to corrupted entries in the cache or TLB.
1099
1100 config ARM_ERRATA_754322
1101         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1102         depends on CPU_V7
1103         help
1104           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1105           r3p*) erratum. A speculative memory access may cause a page table walk
1106           which starts prior to an ASID switch but completes afterwards. This
1107           can populate the micro-TLB with a stale entry which may be hit with
1108           the new ASID. This workaround places two dsb instructions in the mm
1109           switching code so that no page table walks can cross the ASID switch.
1110
1111 config ARM_ERRATA_754327
1112         bool "ARM errata: no automatic Store Buffer drain"
1113         depends on CPU_V7 && SMP
1114         help
1115           This option enables the workaround for the 754327 Cortex-A9 (prior to
1116           r2p0) erratum. The Store Buffer does not have any automatic draining
1117           mechanism and therefore a livelock may occur if an external agent
1118           continuously polls a memory location waiting to observe an update.
1119           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1120           written polling loops from denying visibility of updates to memory.
1121
1122 config ARM_ERRATA_364296
1123         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1124         depends on CPU_V6
1125         help
1126           This options enables the workaround for the 364296 ARM1136
1127           r0p2 erratum (possible cache data corruption with
1128           hit-under-miss enabled). It sets the undocumented bit 31 in
1129           the auxiliary control register and the FI bit in the control
1130           register, thus disabling hit-under-miss without putting the
1131           processor into full low interrupt latency mode. ARM11MPCore
1132           is not affected.
1133
1134 config ARM_ERRATA_764369
1135         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1136         depends on CPU_V7 && SMP
1137         help
1138           This option enables the workaround for erratum 764369
1139           affecting Cortex-A9 MPCore with two or more processors (all
1140           current revisions). Under certain timing circumstances, a data
1141           cache line maintenance operation by MVA targeting an Inner
1142           Shareable memory region may fail to proceed up to either the
1143           Point of Coherency or to the Point of Unification of the
1144           system. This workaround adds a DSB instruction before the
1145           relevant cache maintenance functions and sets a specific bit
1146           in the diagnostic control register of the SCU.
1147
1148 config ARM_ERRATA_775420
1149        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1150        depends on CPU_V7
1151        help
1152          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1153          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1154          operation aborts with MMU exception, it might cause the processor
1155          to deadlock. This workaround puts DSB before executing ISB if
1156          an abort may occur on cache maintenance.
1157
1158 config ARM_ERRATA_798181
1159         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1160         depends on CPU_V7 && SMP
1161         help
1162           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1163           adequately shooting down all use of the old entries. This
1164           option enables the Linux kernel workaround for this erratum
1165           which sends an IPI to the CPUs that are running the same ASID
1166           as the one being invalidated.
1167
1168 config ARM_ERRATA_773022
1169         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1170         depends on CPU_V7
1171         help
1172           This option enables the workaround for the 773022 Cortex-A15
1173           (up to r0p4) erratum. In certain rare sequences of code, the
1174           loop buffer may deliver incorrect instructions. This
1175           workaround disables the loop buffer to avoid the erratum.
1176
1177 config ARM_ERRATA_818325_852422
1178         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1179         depends on CPU_V7
1180         help
1181           This option enables the workaround for:
1182           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1183             instruction might deadlock.  Fixed in r0p1.
1184           - Cortex-A12 852422: Execution of a sequence of instructions might
1185             lead to either a data corruption or a CPU deadlock.  Not fixed in
1186             any Cortex-A12 cores yet.
1187           This workaround for all both errata involves setting bit[12] of the
1188           Feature Register. This bit disables an optimisation applied to a
1189           sequence of 2 instructions that use opposing condition codes.
1190
1191 config ARM_ERRATA_821420
1192         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1193         depends on CPU_V7
1194         help
1195           This option enables the workaround for the 821420 Cortex-A12
1196           (all revs) erratum. In very rare timing conditions, a sequence
1197           of VMOV to Core registers instructions, for which the second
1198           one is in the shadow of a branch or abort, can lead to a
1199           deadlock when the VMOV instructions are issued out-of-order.
1200
1201 config ARM_ERRATA_825619
1202         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1203         depends on CPU_V7
1204         help
1205           This option enables the workaround for the 825619 Cortex-A12
1206           (all revs) erratum. Within rare timing constraints, executing a
1207           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1208           and Device/Strongly-Ordered loads and stores might cause deadlock
1209
1210 config ARM_ERRATA_852421
1211         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1212         depends on CPU_V7
1213         help
1214           This option enables the workaround for the 852421 Cortex-A17
1215           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1216           execution of a DMB ST instruction might fail to properly order
1217           stores from GroupA and stores from GroupB.
1218
1219 config ARM_ERRATA_852423
1220         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1221         depends on CPU_V7
1222         help
1223           This option enables the workaround for:
1224           - Cortex-A17 852423: Execution of a sequence of instructions might
1225             lead to either a data corruption or a CPU deadlock.  Not fixed in
1226             any Cortex-A17 cores yet.
1227           This is identical to Cortex-A12 erratum 852422.  It is a separate
1228           config option from the A12 erratum due to the way errata are checked
1229           for and handled.
1230
1231 endmenu
1232
1233 source "arch/arm/common/Kconfig"
1234
1235 menu "Bus support"
1236
1237 config ISA
1238         bool
1239         help
1240           Find out whether you have ISA slots on your motherboard.  ISA is the
1241           name of a bus system, i.e. the way the CPU talks to the other stuff
1242           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1243           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1244           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1245
1246 # Select ISA DMA controller support
1247 config ISA_DMA
1248         bool
1249         select ISA_DMA_API
1250
1251 # Select ISA DMA interface
1252 config ISA_DMA_API
1253         bool
1254
1255 config PCI
1256         bool "PCI support" if MIGHT_HAVE_PCI
1257         help
1258           Find out whether you have a PCI motherboard. PCI is the name of a
1259           bus system, i.e. the way the CPU talks to the other stuff inside
1260           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1261           VESA. If you have PCI, say Y, otherwise N.
1262
1263 config PCI_DOMAINS
1264         bool
1265         depends on PCI
1266
1267 config PCI_DOMAINS_GENERIC
1268         def_bool PCI_DOMAINS
1269
1270 config PCI_NANOENGINE
1271         bool "BSE nanoEngine PCI support"
1272         depends on SA1100_NANOENGINE
1273         help
1274           Enable PCI on the BSE nanoEngine board.
1275
1276 config PCI_SYSCALL
1277         def_bool PCI
1278
1279 config PCI_HOST_ITE8152
1280         bool
1281         depends on PCI && MACH_ARMCORE
1282         default y
1283         select DMABOUNCE
1284
1285 source "drivers/pci/Kconfig"
1286
1287 source "drivers/pcmcia/Kconfig"
1288
1289 endmenu
1290
1291 menu "Kernel Features"
1292
1293 config HAVE_SMP
1294         bool
1295         help
1296           This option should be selected by machines which have an SMP-
1297           capable CPU.
1298
1299           The only effect of this option is to make the SMP-related
1300           options available to the user for configuration.
1301
1302 config SMP
1303         bool "Symmetric Multi-Processing"
1304         depends on CPU_V6K || CPU_V7
1305         depends on GENERIC_CLOCKEVENTS
1306         depends on HAVE_SMP
1307         depends on MMU || ARM_MPU
1308         select IRQ_WORK
1309         help
1310           This enables support for systems with more than one CPU. If you have
1311           a system with only one CPU, say N. If you have a system with more
1312           than one CPU, say Y.
1313
1314           If you say N here, the kernel will run on uni- and multiprocessor
1315           machines, but will use only one CPU of a multiprocessor machine. If
1316           you say Y here, the kernel will run on many, but not all,
1317           uniprocessor machines. On a uniprocessor machine, the kernel
1318           will run faster if you say N here.
1319
1320           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1321           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1322           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1323
1324           If you don't know what to do here, say N.
1325
1326 config SMP_ON_UP
1327         bool "Allow booting SMP kernel on uniprocessor systems"
1328         depends on SMP && !XIP_KERNEL && MMU
1329         default y
1330         help
1331           SMP kernels contain instructions which fail on non-SMP processors.
1332           Enabling this option allows the kernel to modify itself to make
1333           these instructions safe.  Disabling it allows about 1K of space
1334           savings.
1335
1336           If you don't know what to do here, say Y.
1337
1338 config ARM_CPU_TOPOLOGY
1339         bool "Support cpu topology definition"
1340         depends on SMP && CPU_V7
1341         default y
1342         help
1343           Support ARM cpu topology definition. The MPIDR register defines
1344           affinity between processors which is then used to describe the cpu
1345           topology of an ARM System.
1346
1347 config SCHED_MC
1348         bool "Multi-core scheduler support"
1349         depends on ARM_CPU_TOPOLOGY
1350         help
1351           Multi-core scheduler support improves the CPU scheduler's decision
1352           making when dealing with multi-core CPU chips at a cost of slightly
1353           increased overhead in some places. If unsure say N here.
1354
1355 config SCHED_SMT
1356         bool "SMT scheduler support"
1357         depends on ARM_CPU_TOPOLOGY
1358         help
1359           Improves the CPU scheduler's decision making when dealing with
1360           MultiThreading at a cost of slightly increased overhead in some
1361           places. If unsure say N here.
1362
1363 config HAVE_ARM_SCU
1364         bool
1365         help
1366           This option enables support for the ARM system coherency unit
1367
1368 config HAVE_ARM_ARCH_TIMER
1369         bool "Architected timer support"
1370         depends on CPU_V7
1371         select ARM_ARCH_TIMER
1372         select GENERIC_CLOCKEVENTS
1373         help
1374           This option enables support for the ARM architected timer
1375
1376 config HAVE_ARM_TWD
1377         bool
1378         select CLKSRC_OF if OF
1379         help
1380           This options enables support for the ARM timer and watchdog unit
1381
1382 config MCPM
1383         bool "Multi-Cluster Power Management"
1384         depends on CPU_V7 && SMP
1385         help
1386           This option provides the common power management infrastructure
1387           for (multi-)cluster based systems, such as big.LITTLE based
1388           systems.
1389
1390 config MCPM_QUAD_CLUSTER
1391         bool
1392         depends on MCPM
1393         help
1394           To avoid wasting resources unnecessarily, MCPM only supports up
1395           to 2 clusters by default.
1396           Platforms with 3 or 4 clusters that use MCPM must select this
1397           option to allow the additional clusters to be managed.
1398
1399 config BIG_LITTLE
1400         bool "big.LITTLE support (Experimental)"
1401         depends on CPU_V7 && SMP
1402         select MCPM
1403         help
1404           This option enables support selections for the big.LITTLE
1405           system architecture.
1406
1407 config BL_SWITCHER
1408         bool "big.LITTLE switcher support"
1409         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1410         select CPU_PM
1411         help
1412           The big.LITTLE "switcher" provides the core functionality to
1413           transparently handle transition between a cluster of A15's
1414           and a cluster of A7's in a big.LITTLE system.
1415
1416 config BL_SWITCHER_DUMMY_IF
1417         tristate "Simple big.LITTLE switcher user interface"
1418         depends on BL_SWITCHER && DEBUG_KERNEL
1419         help
1420           This is a simple and dummy char dev interface to control
1421           the big.LITTLE switcher core code.  It is meant for
1422           debugging purposes only.
1423
1424 choice
1425         prompt "Memory split"
1426         depends on MMU
1427         default VMSPLIT_3G
1428         help
1429           Select the desired split between kernel and user memory.
1430
1431           If you are not absolutely sure what you are doing, leave this
1432           option alone!
1433
1434         config VMSPLIT_3G
1435                 bool "3G/1G user/kernel split"
1436         config VMSPLIT_3G_OPT
1437                 bool "3G/1G user/kernel split (for full 1G low memory)"
1438         config VMSPLIT_2G
1439                 bool "2G/2G user/kernel split"
1440         config VMSPLIT_1G
1441                 bool "1G/3G user/kernel split"
1442 endchoice
1443
1444 config PAGE_OFFSET
1445         hex
1446         default PHYS_OFFSET if !MMU
1447         default 0x40000000 if VMSPLIT_1G
1448         default 0x80000000 if VMSPLIT_2G
1449         default 0xB0000000 if VMSPLIT_3G_OPT
1450         default 0xC0000000
1451
1452 config NR_CPUS
1453         int "Maximum number of CPUs (2-32)"
1454         range 2 32
1455         depends on SMP
1456         default "4"
1457
1458 config HOTPLUG_CPU
1459         bool "Support for hot-pluggable CPUs"
1460         depends on SMP
1461         help
1462           Say Y here to experiment with turning CPUs off and on.  CPUs
1463           can be controlled through /sys/devices/system/cpu.
1464
1465 config ARM_PSCI
1466         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1467         depends on HAVE_ARM_SMCCC
1468         select ARM_PSCI_FW
1469         help
1470           Say Y here if you want Linux to communicate with system firmware
1471           implementing the PSCI specification for CPU-centric power
1472           management operations described in ARM document number ARM DEN
1473           0022A ("Power State Coordination Interface System Software on
1474           ARM processors").
1475
1476 # The GPIO number here must be sorted by descending number. In case of
1477 # a multiplatform kernel, we just want the highest value required by the
1478 # selected platforms.
1479 config ARCH_NR_GPIO
1480         int
1481         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1482                 ARCH_ZYNQ
1483         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1484                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1485         default 416 if ARCH_SUNXI
1486         default 392 if ARCH_U8500
1487         default 352 if ARCH_VT8500
1488         default 288 if ARCH_ROCKCHIP
1489         default 264 if MACH_H4700
1490         default 0
1491         help
1492           Maximum number of GPIOs in the system.
1493
1494           If unsure, leave the default value.
1495
1496 source kernel/Kconfig.preempt
1497
1498 config HZ_FIXED
1499         int
1500         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1501                 ARCH_S5PV210 || ARCH_EXYNOS4
1502         default 128 if SOC_AT91RM9200
1503         default 0
1504
1505 choice
1506         depends on HZ_FIXED = 0
1507         prompt "Timer frequency"
1508
1509 config HZ_100
1510         bool "100 Hz"
1511
1512 config HZ_200
1513         bool "200 Hz"
1514
1515 config HZ_250
1516         bool "250 Hz"
1517
1518 config HZ_300
1519         bool "300 Hz"
1520
1521 config HZ_500
1522         bool "500 Hz"
1523
1524 config HZ_1000
1525         bool "1000 Hz"
1526
1527 endchoice
1528
1529 config HZ
1530         int
1531         default HZ_FIXED if HZ_FIXED != 0
1532         default 100 if HZ_100
1533         default 200 if HZ_200
1534         default 250 if HZ_250
1535         default 300 if HZ_300
1536         default 500 if HZ_500
1537         default 1000
1538
1539 config SCHED_HRTICK
1540         def_bool HIGH_RES_TIMERS
1541
1542 config THUMB2_KERNEL
1543         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1544         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1545         default y if CPU_THUMBONLY
1546         select AEABI
1547         select ARM_ASM_UNIFIED
1548         select ARM_UNWIND
1549         help
1550           By enabling this option, the kernel will be compiled in
1551           Thumb-2 mode. A compiler/assembler that understand the unified
1552           ARM-Thumb syntax is needed.
1553
1554           If unsure, say N.
1555
1556 config THUMB2_AVOID_R_ARM_THM_JUMP11
1557         bool "Work around buggy Thumb-2 short branch relocations in gas"
1558         depends on THUMB2_KERNEL && MODULES
1559         default y
1560         help
1561           Various binutils versions can resolve Thumb-2 branches to
1562           locally-defined, preemptible global symbols as short-range "b.n"
1563           branch instructions.
1564
1565           This is a problem, because there's no guarantee the final
1566           destination of the symbol, or any candidate locations for a
1567           trampoline, are within range of the branch.  For this reason, the
1568           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1569           relocation in modules at all, and it makes little sense to add
1570           support.
1571
1572           The symptom is that the kernel fails with an "unsupported
1573           relocation" error when loading some modules.
1574
1575           Until fixed tools are available, passing
1576           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1577           code which hits this problem, at the cost of a bit of extra runtime
1578           stack usage in some cases.
1579
1580           The problem is described in more detail at:
1581               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1582
1583           Only Thumb-2 kernels are affected.
1584
1585           Unless you are sure your tools don't have this problem, say Y.
1586
1587 config ARM_ASM_UNIFIED
1588         bool
1589
1590 config ARM_PATCH_IDIV
1591         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1592         depends on CPU_32v7 && !XIP_KERNEL
1593         default y
1594         help
1595           The ARM compiler inserts calls to __aeabi_idiv() and
1596           __aeabi_uidiv() when it needs to perform division on signed
1597           and unsigned integers. Some v7 CPUs have support for the sdiv
1598           and udiv instructions that can be used to implement those
1599           functions.
1600
1601           Enabling this option allows the kernel to modify itself to
1602           replace the first two instructions of these library functions
1603           with the sdiv or udiv plus "bx lr" instructions when the CPU
1604           it is running on supports them. Typically this will be faster
1605           and less power intensive than running the original library
1606           code to do integer division.
1607
1608 config AEABI
1609         bool "Use the ARM EABI to compile the kernel"
1610         help
1611           This option allows for the kernel to be compiled using the latest
1612           ARM ABI (aka EABI).  This is only useful if you are using a user
1613           space environment that is also compiled with EABI.
1614
1615           Since there are major incompatibilities between the legacy ABI and
1616           EABI, especially with regard to structure member alignment, this
1617           option also changes the kernel syscall calling convention to
1618           disambiguate both ABIs and allow for backward compatibility support
1619           (selected with CONFIG_OABI_COMPAT).
1620
1621           To use this you need GCC version 4.0.0 or later.
1622
1623 config OABI_COMPAT
1624         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1625         depends on AEABI && !THUMB2_KERNEL
1626         help
1627           This option preserves the old syscall interface along with the
1628           new (ARM EABI) one. It also provides a compatibility layer to
1629           intercept syscalls that have structure arguments which layout
1630           in memory differs between the legacy ABI and the new ARM EABI
1631           (only for non "thumb" binaries). This option adds a tiny
1632           overhead to all syscalls and produces a slightly larger kernel.
1633
1634           The seccomp filter system will not be available when this is
1635           selected, since there is no way yet to sensibly distinguish
1636           between calling conventions during filtering.
1637
1638           If you know you'll be using only pure EABI user space then you
1639           can say N here. If this option is not selected and you attempt
1640           to execute a legacy ABI binary then the result will be
1641           UNPREDICTABLE (in fact it can be predicted that it won't work
1642           at all). If in doubt say N.
1643
1644 config ARCH_HAS_HOLES_MEMORYMODEL
1645         bool
1646
1647 config ARCH_SPARSEMEM_ENABLE
1648         bool
1649
1650 config ARCH_SPARSEMEM_DEFAULT
1651         def_bool ARCH_SPARSEMEM_ENABLE
1652
1653 config ARCH_SELECT_MEMORY_MODEL
1654         def_bool ARCH_SPARSEMEM_ENABLE
1655
1656 config HAVE_ARCH_PFN_VALID
1657         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1658
1659 config HAVE_GENERIC_RCU_GUP
1660         def_bool y
1661         depends on ARM_LPAE
1662
1663 config HIGHMEM
1664         bool "High Memory Support"
1665         depends on MMU
1666         help
1667           The address space of ARM processors is only 4 Gigabytes large
1668           and it has to accommodate user address space, kernel address
1669           space as well as some memory mapped IO. That means that, if you
1670           have a large amount of physical memory and/or IO, not all of the
1671           memory can be "permanently mapped" by the kernel. The physical
1672           memory that is not permanently mapped is called "high memory".
1673
1674           Depending on the selected kernel/user memory split, minimum
1675           vmalloc space and actual amount of RAM, you may not need this
1676           option which should result in a slightly faster kernel.
1677
1678           If unsure, say n.
1679
1680 config HIGHPTE
1681         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1682         depends on HIGHMEM
1683         default y
1684         help
1685           The VM uses one page of physical memory for each page table.
1686           For systems with a lot of processes, this can use a lot of
1687           precious low memory, eventually leading to low memory being
1688           consumed by page tables.  Setting this option will allow
1689           user-space 2nd level page tables to reside in high memory.
1690
1691 config CPU_SW_DOMAIN_PAN
1692         bool "Enable use of CPU domains to implement privileged no-access"
1693         depends on MMU && !ARM_LPAE
1694         default y
1695         help
1696           Increase kernel security by ensuring that normal kernel accesses
1697           are unable to access userspace addresses.  This can help prevent
1698           use-after-free bugs becoming an exploitable privilege escalation
1699           by ensuring that magic values (such as LIST_POISON) will always
1700           fault when dereferenced.
1701
1702           CPUs with low-vector mappings use a best-efforts implementation.
1703           Their lower 1MB needs to remain accessible for the vectors, but
1704           the remainder of userspace will become appropriately inaccessible.
1705
1706 config HW_PERF_EVENTS
1707         def_bool y
1708         depends on ARM_PMU
1709
1710 config SYS_SUPPORTS_HUGETLBFS
1711        def_bool y
1712        depends on ARM_LPAE
1713
1714 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1715        def_bool y
1716        depends on ARM_LPAE
1717
1718 config ARCH_WANT_GENERAL_HUGETLB
1719         def_bool y
1720
1721 config ARM_MODULE_PLTS
1722         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1723         depends on MODULES
1724         help
1725           Allocate PLTs when loading modules so that jumps and calls whose
1726           targets are too far away for their relative offsets to be encoded
1727           in the instructions themselves can be bounced via veneers in the
1728           module's PLT. This allows modules to be allocated in the generic
1729           vmalloc area after the dedicated module memory area has been
1730           exhausted. The modules will use slightly more memory, but after
1731           rounding up to page size, the actual memory footprint is usually
1732           the same.
1733
1734           Say y if you are getting out of memory errors while loading modules
1735
1736 source "mm/Kconfig"
1737
1738 config FORCE_MAX_ZONEORDER
1739         int "Maximum zone order"
1740         default "12" if SOC_AM33XX
1741         default "9" if SA1111 || ARCH_EFM32
1742         default "11"
1743         help
1744           The kernel memory allocator divides physically contiguous memory
1745           blocks into "zones", where each zone is a power of two number of
1746           pages.  This option selects the largest power of two that the kernel
1747           keeps in the memory allocator.  If you need to allocate very large
1748           blocks of physically contiguous memory, then you may need to
1749           increase this value.
1750
1751           This config option is actually maximum order plus one. For example,
1752           a value of 11 means that the largest free memory block is 2^10 pages.
1753
1754 config ALIGNMENT_TRAP
1755         bool
1756         depends on CPU_CP15_MMU
1757         default y if !ARCH_EBSA110
1758         select HAVE_PROC_CPU if PROC_FS
1759         help
1760           ARM processors cannot fetch/store information which is not
1761           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1762           address divisible by 4. On 32-bit ARM processors, these non-aligned
1763           fetch/store instructions will be emulated in software if you say
1764           here, which has a severe performance impact. This is necessary for
1765           correct operation of some network protocols. With an IP-only
1766           configuration it is safe to say N, otherwise say Y.
1767
1768 config UACCESS_WITH_MEMCPY
1769         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1770         depends on MMU
1771         default y if CPU_FEROCEON
1772         help
1773           Implement faster copy_to_user and clear_user methods for CPU
1774           cores where a 8-word STM instruction give significantly higher
1775           memory write throughput than a sequence of individual 32bit stores.
1776
1777           A possible side effect is a slight increase in scheduling latency
1778           between threads sharing the same address space if they invoke
1779           such copy operations with large buffers.
1780
1781           However, if the CPU data cache is using a write-allocate mode,
1782           this option is unlikely to provide any performance gain.
1783
1784 config SECCOMP
1785         bool
1786         prompt "Enable seccomp to safely compute untrusted bytecode"
1787         ---help---
1788           This kernel feature is useful for number crunching applications
1789           that may need to compute untrusted bytecode during their
1790           execution. By using pipes or other transports made available to
1791           the process as file descriptors supporting the read/write
1792           syscalls, it's possible to isolate those applications in
1793           their own address space using seccomp. Once seccomp is
1794           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1795           and the task is only allowed to execute a few safe syscalls
1796           defined by each seccomp mode.
1797
1798 config SWIOTLB
1799         def_bool y
1800
1801 config IOMMU_HELPER
1802         def_bool SWIOTLB
1803
1804 config PARAVIRT
1805         bool "Enable paravirtualization code"
1806         help
1807           This changes the kernel so it can modify itself when it is run
1808           under a hypervisor, potentially improving performance significantly
1809           over full virtualization.
1810
1811 config PARAVIRT_TIME_ACCOUNTING
1812         bool "Paravirtual steal time accounting"
1813         select PARAVIRT
1814         default n
1815         help
1816           Select this option to enable fine granularity task steal time
1817           accounting. Time spent executing other tasks in parallel with
1818           the current vCPU is discounted from the vCPU power. To account for
1819           that, there can be a small performance impact.
1820
1821           If in doubt, say N here.
1822
1823 config XEN_DOM0
1824         def_bool y
1825         depends on XEN
1826
1827 config XEN
1828         bool "Xen guest support on ARM"
1829         depends on ARM && AEABI && OF
1830         depends on CPU_V7 && !CPU_V6
1831         depends on !GENERIC_ATOMIC64
1832         depends on MMU
1833         select ARCH_DMA_ADDR_T_64BIT
1834         select ARM_PSCI
1835         select SWIOTLB_XEN
1836         select PARAVIRT
1837         help
1838           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1839
1840 endmenu
1841
1842 menu "Boot options"
1843
1844 config USE_OF
1845         bool "Flattened Device Tree support"
1846         select IRQ_DOMAIN
1847         select OF
1848         help
1849           Include support for flattened device tree machine descriptions.
1850
1851 config ATAGS
1852         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1853         default y
1854         help
1855           This is the traditional way of passing data to the kernel at boot
1856           time. If you are solely relying on the flattened device tree (or
1857           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1858           to remove ATAGS support from your kernel binary.  If unsure,
1859           leave this to y.
1860
1861 config DEPRECATED_PARAM_STRUCT
1862         bool "Provide old way to pass kernel parameters"
1863         depends on ATAGS
1864         help
1865           This was deprecated in 2001 and announced to live on for 5 years.
1866           Some old boot loaders still use this way.
1867
1868 # Compressed boot loader in ROM.  Yes, we really want to ask about
1869 # TEXT and BSS so we preserve their values in the config files.
1870 config ZBOOT_ROM_TEXT
1871         hex "Compressed ROM boot loader base address"
1872         default "0"
1873         help
1874           The physical address at which the ROM-able zImage is to be
1875           placed in the target.  Platforms which normally make use of
1876           ROM-able zImage formats normally set this to a suitable
1877           value in their defconfig file.
1878
1879           If ZBOOT_ROM is not enabled, this has no effect.
1880
1881 config ZBOOT_ROM_BSS
1882         hex "Compressed ROM boot loader BSS address"
1883         default "0"
1884         help
1885           The base address of an area of read/write memory in the target
1886           for the ROM-able zImage which must be available while the
1887           decompressor is running. It must be large enough to hold the
1888           entire decompressed kernel plus an additional 128 KiB.
1889           Platforms which normally make use of ROM-able zImage formats
1890           normally set this to a suitable value in their defconfig file.
1891
1892           If ZBOOT_ROM is not enabled, this has no effect.
1893
1894 config ZBOOT_ROM
1895         bool "Compressed boot loader in ROM/flash"
1896         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1897         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1898         help
1899           Say Y here if you intend to execute your compressed kernel image
1900           (zImage) directly from ROM or flash.  If unsure, say N.
1901
1902 config ARM_APPENDED_DTB
1903         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1904         depends on OF
1905         help
1906           With this option, the boot code will look for a device tree binary
1907           (DTB) appended to zImage
1908           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1909
1910           This is meant as a backward compatibility convenience for those
1911           systems with a bootloader that can't be upgraded to accommodate
1912           the documented boot protocol using a device tree.
1913
1914           Beware that there is very little in terms of protection against
1915           this option being confused by leftover garbage in memory that might
1916           look like a DTB header after a reboot if no actual DTB is appended
1917           to zImage.  Do not leave this option active in a production kernel
1918           if you don't intend to always append a DTB.  Proper passing of the
1919           location into r2 of a bootloader provided DTB is always preferable
1920           to this option.
1921
1922 config ARM_ATAG_DTB_COMPAT
1923         bool "Supplement the appended DTB with traditional ATAG information"
1924         depends on ARM_APPENDED_DTB
1925         help
1926           Some old bootloaders can't be updated to a DTB capable one, yet
1927           they provide ATAGs with memory configuration, the ramdisk address,
1928           the kernel cmdline string, etc.  Such information is dynamically
1929           provided by the bootloader and can't always be stored in a static
1930           DTB.  To allow a device tree enabled kernel to be used with such
1931           bootloaders, this option allows zImage to extract the information
1932           from the ATAG list and store it at run time into the appended DTB.
1933
1934 choice
1935         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1936         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1937
1938 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1939         bool "Use bootloader kernel arguments if available"
1940         help
1941           Uses the command-line options passed by the boot loader instead of
1942           the device tree bootargs property. If the boot loader doesn't provide
1943           any, the device tree bootargs property will be used.
1944
1945 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1946         bool "Extend with bootloader kernel arguments"
1947         help
1948           The command-line arguments provided by the boot loader will be
1949           appended to the the device tree bootargs property.
1950
1951 endchoice
1952
1953 config CMDLINE
1954         string "Default kernel command string"
1955         default ""
1956         help
1957           On some architectures (EBSA110 and CATS), there is currently no way
1958           for the boot loader to pass arguments to the kernel. For these
1959           architectures, you should supply some command-line options at build
1960           time by entering them here. As a minimum, you should specify the
1961           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1962
1963 choice
1964         prompt "Kernel command line type" if CMDLINE != ""
1965         default CMDLINE_FROM_BOOTLOADER
1966         depends on ATAGS
1967
1968 config CMDLINE_FROM_BOOTLOADER
1969         bool "Use bootloader kernel arguments if available"
1970         help
1971           Uses the command-line options passed by the boot loader. If
1972           the boot loader doesn't provide any, the default kernel command
1973           string provided in CMDLINE will be used.
1974
1975 config CMDLINE_EXTEND
1976         bool "Extend bootloader kernel arguments"
1977         help
1978           The command-line arguments provided by the boot loader will be
1979           appended to the default kernel command string.
1980
1981 config CMDLINE_FORCE
1982         bool "Always use the default kernel command string"
1983         help
1984           Always use the default kernel command string, even if the boot
1985           loader passes other arguments to the kernel.
1986           This is useful if you cannot or don't want to change the
1987           command-line options your boot loader passes to the kernel.
1988 endchoice
1989
1990 config XIP_KERNEL
1991         bool "Kernel Execute-In-Place from ROM"
1992         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1993         help
1994           Execute-In-Place allows the kernel to run from non-volatile storage
1995           directly addressable by the CPU, such as NOR flash. This saves RAM
1996           space since the text section of the kernel is not loaded from flash
1997           to RAM.  Read-write sections, such as the data section and stack,
1998           are still copied to RAM.  The XIP kernel is not compressed since
1999           it has to run directly from flash, so it will take more space to
2000           store it.  The flash address used to link the kernel object files,
2001           and for storing it, is configuration dependent. Therefore, if you
2002           say Y here, you must know the proper physical address where to
2003           store the kernel image depending on your own flash memory usage.
2004
2005           Also note that the make target becomes "make xipImage" rather than
2006           "make zImage" or "make Image".  The final kernel binary to put in
2007           ROM memory will be arch/arm/boot/xipImage.
2008
2009           If unsure, say N.
2010
2011 config XIP_PHYS_ADDR
2012         hex "XIP Kernel Physical Location"
2013         depends on XIP_KERNEL
2014         default "0x00080000"
2015         help
2016           This is the physical address in your flash memory the kernel will
2017           be linked for and stored to.  This address is dependent on your
2018           own flash usage.
2019
2020 config KEXEC
2021         bool "Kexec system call (EXPERIMENTAL)"
2022         depends on (!SMP || PM_SLEEP_SMP)
2023         depends on !CPU_V7M
2024         select KEXEC_CORE
2025         help
2026           kexec is a system call that implements the ability to shutdown your
2027           current kernel, and to start another kernel.  It is like a reboot
2028           but it is independent of the system firmware.   And like a reboot
2029           you can start any kernel with it, not just Linux.
2030
2031           It is an ongoing process to be certain the hardware in a machine
2032           is properly shutdown, so do not be surprised if this code does not
2033           initially work for you.
2034
2035 config ATAGS_PROC
2036         bool "Export atags in procfs"
2037         depends on ATAGS && KEXEC
2038         default y
2039         help
2040           Should the atags used to boot the kernel be exported in an "atags"
2041           file in procfs. Useful with kexec.
2042
2043 config CRASH_DUMP
2044         bool "Build kdump crash kernel (EXPERIMENTAL)"
2045         help
2046           Generate crash dump after being started by kexec. This should
2047           be normally only set in special crash dump kernels which are
2048           loaded in the main kernel with kexec-tools into a specially
2049           reserved region and then later executed after a crash by
2050           kdump/kexec. The crash dump kernel must be compiled to a
2051           memory address not used by the main kernel
2052
2053           For more details see Documentation/kdump/kdump.txt
2054
2055 config AUTO_ZRELADDR
2056         bool "Auto calculation of the decompressed kernel image address"
2057         help
2058           ZRELADDR is the physical address where the decompressed kernel
2059           image will be placed. If AUTO_ZRELADDR is selected, the address
2060           will be determined at run-time by masking the current IP with
2061           0xf8000000. This assumes the zImage being placed in the first 128MB
2062           from start of memory.
2063
2064 config EFI_STUB
2065         bool
2066
2067 config EFI
2068         bool "UEFI runtime support"
2069         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2070         select UCS2_STRING
2071         select EFI_PARAMS_FROM_FDT
2072         select EFI_STUB
2073         select EFI_ARMSTUB
2074         select EFI_RUNTIME_WRAPPERS
2075         ---help---
2076           This option provides support for runtime services provided
2077           by UEFI firmware (such as non-volatile variables, realtime
2078           clock, and platform reset). A UEFI stub is also provided to
2079           allow the kernel to be booted as an EFI application. This
2080           is only useful for kernels that may run on systems that have
2081           UEFI firmware.
2082
2083 endmenu
2084
2085 menu "CPU Power Management"
2086
2087 source "drivers/cpufreq/Kconfig"
2088
2089 source "drivers/cpuidle/Kconfig"
2090
2091 endmenu
2092
2093 menu "Floating point emulation"
2094
2095 comment "At least one emulation must be selected"
2096
2097 config FPE_NWFPE
2098         bool "NWFPE math emulation"
2099         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2100         ---help---
2101           Say Y to include the NWFPE floating point emulator in the kernel.
2102           This is necessary to run most binaries. Linux does not currently
2103           support floating point hardware so you need to say Y here even if
2104           your machine has an FPA or floating point co-processor podule.
2105
2106           You may say N here if you are going to load the Acorn FPEmulator
2107           early in the bootup.
2108
2109 config FPE_NWFPE_XP
2110         bool "Support extended precision"
2111         depends on FPE_NWFPE
2112         help
2113           Say Y to include 80-bit support in the kernel floating-point
2114           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2115           Note that gcc does not generate 80-bit operations by default,
2116           so in most cases this option only enlarges the size of the
2117           floating point emulator without any good reason.
2118
2119           You almost surely want to say N here.
2120
2121 config FPE_FASTFPE
2122         bool "FastFPE math emulation (EXPERIMENTAL)"
2123         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2124         ---help---
2125           Say Y here to include the FAST floating point emulator in the kernel.
2126           This is an experimental much faster emulator which now also has full
2127           precision for the mantissa.  It does not support any exceptions.
2128           It is very simple, and approximately 3-6 times faster than NWFPE.
2129
2130           It should be sufficient for most programs.  It may be not suitable
2131           for scientific calculations, but you have to check this for yourself.
2132           If you do not feel you need a faster FP emulation you should better
2133           choose NWFPE.
2134
2135 config VFP
2136         bool "VFP-format floating point maths"
2137         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2138         help
2139           Say Y to include VFP support code in the kernel. This is needed
2140           if your hardware includes a VFP unit.
2141
2142           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2143           release notes and additional status information.
2144
2145           Say N if your target does not have VFP hardware.
2146
2147 config VFPv3
2148         bool
2149         depends on VFP
2150         default y if CPU_V7
2151
2152 config NEON
2153         bool "Advanced SIMD (NEON) Extension support"
2154         depends on VFPv3 && CPU_V7
2155         help
2156           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2157           Extension.
2158
2159 config KERNEL_MODE_NEON
2160         bool "Support for NEON in kernel mode"
2161         depends on NEON && AEABI
2162         help
2163           Say Y to include support for NEON in kernel mode.
2164
2165 endmenu
2166
2167 menu "Userspace binary formats"
2168
2169 source "fs/Kconfig.binfmt"
2170
2171 endmenu
2172
2173 menu "Power management options"
2174
2175 source "kernel/power/Kconfig"
2176
2177 config ARCH_SUSPEND_POSSIBLE
2178         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2179                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2180         def_bool y
2181
2182 config ARM_CPU_SUSPEND
2183         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2184         depends on ARCH_SUSPEND_POSSIBLE
2185
2186 config ARCH_HIBERNATION_POSSIBLE
2187         bool
2188         depends on MMU
2189         default y if ARCH_SUSPEND_POSSIBLE
2190
2191 endmenu
2192
2193 source "net/Kconfig"
2194
2195 source "drivers/Kconfig"
2196
2197 source "drivers/firmware/Kconfig"
2198
2199 source "fs/Kconfig"
2200
2201 source "arch/arm/Kconfig.debug"
2202
2203 source "security/Kconfig"
2204
2205 source "crypto/Kconfig"
2206 if CRYPTO
2207 source "arch/arm/crypto/Kconfig"
2208 endif
2209
2210 source "lib/Kconfig"
2211
2212 source "arch/arm/kvm/Kconfig"