4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
61 select OLD_SIGSUSPEND3
63 select HAVE_CONTEXT_TRACKING
65 The ARM series is a line of low-power-consumption RISC chip designs
66 licensed by ARM Ltd and targeted at embedded applications and
67 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
68 manufactured, but legacy ARM-based PC hardware remains popular in
69 Europe. There is an ARM Linux project with a web page at
70 <http://www.arm.linux.org.uk/>.
72 config ARM_HAS_SG_CHAIN
75 config NEED_SG_DMA_LENGTH
78 config ARM_DMA_USE_IOMMU
80 select ARM_HAS_SG_CHAIN
81 select NEED_SG_DMA_LENGTH
85 config ARM_DMA_IOMMU_ALIGNMENT
86 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
90 DMA mapping framework by default aligns all buffers to the smallest
91 PAGE_SIZE order which is greater than or equal to the requested buffer
92 size. This works well for buffers up to a few hundreds kilobytes, but
93 for larger buffers it just a waste of address space. Drivers which has
94 relatively small addressing window (like 64Mib) might run out of
95 virtual space with just a few allocations.
97 With this parameter you can specify the maximum PAGE_SIZE order for
98 DMA IOMMU buffers. Larger buffers will be aligned only to this
99 specified order. The order is expressed as a power of two multiplied
107 config MIGHT_HAVE_PCI
110 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARM_PATCH_PHYS_VIRT
296 select MULTI_IRQ_HANDLER
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
313 select VERSATILE_FPGA_IRQ
315 Support for ARM's Integrator platform.
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_TIMER_SP804
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
348 This enables support for ARM Ltd Versatile board.
352 select ARCH_REQUIRE_GPIOLIB
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
359 select PINCTRL_AT91 if USE_OF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
366 select ARCH_REQUIRE_GPIOLIB
372 select GENERIC_CLOCKEVENTS
374 select MULTI_IRQ_HANDLER
377 Support for Cirrus Logic 711x/721x/731x based boards.
380 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
383 select NEED_MACH_GPIO_H
386 Support for the Cortina Systems Gemini family SoCs
390 select ARCH_USES_GETTIMEOFFSET
393 select NEED_MACH_IO_H
394 select NEED_MACH_MEMORY_H
397 This is an evaluation board for the StrongARM processor available
398 from Digital. It has limited hardware on-board, including an
399 Ethernet interface, two PCMCIA sockets, two serial ports and a
404 select ARCH_HAS_HOLES_MEMORYMODEL
405 select ARCH_REQUIRE_GPIOLIB
406 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_MEMORY_H
413 This enables support for the Cirrus EP93xx series of CPUs.
415 config ARCH_FOOTBRIDGE
419 select GENERIC_CLOCKEVENTS
421 select NEED_MACH_IO_H if !MMU
422 select NEED_MACH_MEMORY_H
424 Support for systems based on the DC21285 companion chip
425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
428 bool "Hilscher NetX based"
432 select GENERIC_CLOCKEVENTS
434 This enables support for systems based on the Hilscher NetX Soc
439 select ARCH_SUPPORTS_MSI
441 select NEED_MACH_MEMORY_H
442 select NEED_RET_TO_USER
447 Support for Intel's IOP13XX (XScale) family of processors.
452 select ARCH_REQUIRE_GPIOLIB
454 select NEED_MACH_GPIO_H
455 select NEED_RET_TO_USER
459 Support for Intel's 80219 and IOP32X (XScale) family of
465 select ARCH_REQUIRE_GPIOLIB
467 select NEED_MACH_GPIO_H
468 select NEED_RET_TO_USER
472 Support for Intel's IOP33X (XScale) family of processors.
477 select ARCH_HAS_DMA_SET_COHERENT_MASK
478 select ARCH_REQUIRE_GPIOLIB
481 select DMABOUNCE if PCI
482 select GENERIC_CLOCKEVENTS
483 select MIGHT_HAVE_PCI
484 select NEED_MACH_IO_H
485 select USB_EHCI_BIG_ENDIAN_MMIO
486 select USB_EHCI_BIG_ENDIAN_DESC
488 Support for Intel's IXP4XX (XScale) family of processors.
492 select ARCH_REQUIRE_GPIOLIB
494 select GENERIC_CLOCKEVENTS
495 select MIGHT_HAVE_PCI
498 select PLAT_ORION_LEGACY
499 select USB_ARCH_HAS_EHCI
502 Support for the Marvell Dove SoC 88AP510
505 bool "Marvell Kirkwood"
506 select ARCH_HAS_CPUFREQ
507 select ARCH_REQUIRE_GPIOLIB
509 select GENERIC_CLOCKEVENTS
513 select PINCTRL_KIRKWOOD
514 select PLAT_ORION_LEGACY
517 Support for the following Marvell Kirkwood series SoCs:
518 88F6180, 88F6192 and 88F6281.
521 bool "Marvell MV78xx0"
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
526 select PLAT_ORION_LEGACY
529 Support for the following Marvell MV78xx0 series SoCs:
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
539 select PLAT_ORION_LEGACY
542 Support for the following Marvell Orion 5x series SoCs:
543 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
544 Orion-2 (5281), Orion-1-90 (6183).
547 bool "Marvell PXA168/910/MMP2"
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_ALLOCATOR
552 select GENERIC_CLOCKEVENTS
555 select NEED_MACH_GPIO_H
560 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
563 bool "Micrel/Kendin KS8695"
564 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_CLOCKEVENTS
568 select NEED_MACH_MEMORY_H
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
574 bool "Nuvoton W90X900 CPU"
575 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
591 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
599 select USB_ARCH_HAS_OHCI
602 Support for the NXP LPC32XX family of processors
605 bool "PXA2xx/PXA3xx-based"
607 select ARCH_HAS_CPUFREQ
609 select ARCH_REQUIRE_GPIOLIB
610 select ARM_CPU_SUSPEND if PM
614 select GENERIC_CLOCKEVENTS
617 select MULTI_IRQ_HANDLER
618 select NEED_MACH_GPIO_H
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
626 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory
633 interface to the modem processor which runs the baseband
634 stack and controls some vital subsystems
635 (clock and power control, etc).
638 bool "Renesas SH-Mobile / R-Mobile"
639 select ARM_PATCH_PHYS_VIRT
641 select GENERIC_CLOCKEVENTS
642 select HAVE_ARM_SCU if SMP
643 select HAVE_ARM_TWD if LOCAL_TIMERS
645 select HAVE_MACH_CLKDEV
647 select MIGHT_HAVE_CACHE_L2X0
648 select MULTI_IRQ_HANDLER
651 select PM_GENERIC_DOMAINS if PM
654 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
659 select ARCH_MAY_HAVE_PC_FDC
660 select ARCH_SPARSEMEM_ENABLE
661 select ARCH_USES_GETTIMEOFFSET
664 select HAVE_PATA_PLATFORM
666 select NEED_MACH_IO_H
667 select NEED_MACH_MEMORY_H
671 On the Acorn Risc-PC, Linux can support the internal IDE disk and
672 CD-ROM interface, serial and parallel port, and the floppy drive.
676 select ARCH_HAS_CPUFREQ
678 select ARCH_REQUIRE_GPIOLIB
679 select ARCH_SPARSEMEM_ENABLE
684 select GENERIC_CLOCKEVENTS
687 select NEED_MACH_GPIO_H
688 select NEED_MACH_MEMORY_H
691 Support for StrongARM 11x0 based boards.
694 bool "Samsung S3C24XX SoCs"
695 select ARCH_HAS_CPUFREQ
696 select ARCH_REQUIRE_GPIOLIB
699 select GENERIC_CLOCKEVENTS
702 select HAVE_S3C2410_I2C if I2C
703 select HAVE_S3C2410_WATCHDOG if WATCHDOG
704 select HAVE_S3C_RTC if RTC_CLASS
705 select MULTI_IRQ_HANDLER
706 select NEED_MACH_GPIO_H
707 select NEED_MACH_IO_H
710 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
711 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
712 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
713 Samsung SMDK2410 development board (and derivatives).
716 bool "Samsung S3C64XX"
717 select ARCH_HAS_CPUFREQ
718 select ARCH_REQUIRE_GPIOLIB
723 select GENERIC_CLOCKEVENTS
726 select HAVE_S3C2410_I2C if I2C
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
729 select NEED_MACH_GPIO_H
733 select S3C_GPIO_TRACK
735 select SAMSUNG_CLKSRC
736 select SAMSUNG_GPIOLIB_4BIT
737 select SAMSUNG_IRQ_VIC_TIMER
738 select SAMSUNG_WDT_RESET
739 select USB_ARCH_HAS_OHCI
741 Samsung S3C64XX series based systems
744 bool "Samsung S5P6440 S5P6450"
748 select GENERIC_CLOCKEVENTS
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
753 select HAVE_S3C_RTC if RTC_CLASS
754 select NEED_MACH_GPIO_H
755 select SAMSUNG_WDT_RESET
758 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
762 bool "Samsung S5PC100"
763 select ARCH_REQUIRE_GPIOLIB
767 select GENERIC_CLOCKEVENTS
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select HAVE_S3C_RTC if RTC_CLASS
773 select NEED_MACH_GPIO_H
774 select SAMSUNG_WDT_RESET
777 Samsung S5PC100 series based systems
780 bool "Samsung S5PV210/S5PC110"
781 select ARCH_HAS_CPUFREQ
782 select ARCH_HAS_HOLES_MEMORYMODEL
783 select ARCH_SPARSEMEM_ENABLE
787 select GENERIC_CLOCKEVENTS
790 select HAVE_S3C2410_I2C if I2C
791 select HAVE_S3C2410_WATCHDOG if WATCHDOG
792 select HAVE_S3C_RTC if RTC_CLASS
793 select NEED_MACH_GPIO_H
794 select NEED_MACH_MEMORY_H
797 Samsung S5PV210/S5PC110 series based systems
800 bool "Samsung EXYNOS"
801 select ARCH_HAS_CPUFREQ
802 select ARCH_HAS_HOLES_MEMORYMODEL
803 select ARCH_REQUIRE_GPIOLIB
804 select ARCH_SPARSEMEM_ENABLE
809 select GENERIC_CLOCKEVENTS
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select HAVE_S3C_RTC if RTC_CLASS
814 select NEED_MACH_MEMORY_H
818 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
822 select ARCH_USES_GETTIMEOFFSET
826 select NEED_MACH_MEMORY_H
831 Support for the StrongARM based Digital DNARD machine, also known
832 as "Shark" (<http://www.shark-linux.de/shark.html>).
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_REQUIRE_GPIOLIB
839 select GENERIC_ALLOCATOR
840 select GENERIC_CLOCKEVENTS
841 select GENERIC_IRQ_CHIP
843 select NEED_MACH_GPIO_H
848 Support for TI's DaVinci platform.
853 select ARCH_HAS_CPUFREQ
854 select ARCH_HAS_HOLES_MEMORYMODEL
856 select ARCH_REQUIRE_GPIOLIB
859 select GENERIC_CLOCKEVENTS
860 select GENERIC_IRQ_CHIP
864 select NEED_MACH_IO_H if PCCARD
865 select NEED_MACH_MEMORY_H
867 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
871 menu "Multiple platform selection"
872 depends on ARCH_MULTIPLATFORM
874 comment "CPU Core family selection"
876 config ARCH_MULTI_V4T
877 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
878 depends on !ARCH_MULTI_V6_V7
879 select ARCH_MULTI_V4_V5
880 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
881 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
882 CPU_ARM925T || CPU_ARM940T)
885 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
888 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
889 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
890 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
892 config ARCH_MULTI_V4_V5
896 bool "ARMv6 based platforms (ARM11)"
897 select ARCH_MULTI_V6_V7
901 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
903 select ARCH_MULTI_V6_V7
906 config ARCH_MULTI_V6_V7
909 config ARCH_MULTI_CPU_AUTO
910 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
916 # This is sorted alphabetically by mach-* pathname. However, plat-*
917 # Kconfigs may be included either alphabetically (according to the
918 # plat- suffix) or along side the corresponding mach-* source.
920 source "arch/arm/mach-mvebu/Kconfig"
922 source "arch/arm/mach-at91/Kconfig"
924 source "arch/arm/mach-bcm/Kconfig"
926 source "arch/arm/mach-bcm2835/Kconfig"
928 source "arch/arm/mach-clps711x/Kconfig"
930 source "arch/arm/mach-cns3xxx/Kconfig"
932 source "arch/arm/mach-davinci/Kconfig"
934 source "arch/arm/mach-dove/Kconfig"
936 source "arch/arm/mach-ep93xx/Kconfig"
938 source "arch/arm/mach-footbridge/Kconfig"
940 source "arch/arm/mach-gemini/Kconfig"
942 source "arch/arm/mach-highbank/Kconfig"
944 source "arch/arm/mach-integrator/Kconfig"
946 source "arch/arm/mach-iop32x/Kconfig"
948 source "arch/arm/mach-iop33x/Kconfig"
950 source "arch/arm/mach-iop13xx/Kconfig"
952 source "arch/arm/mach-ixp4xx/Kconfig"
954 source "arch/arm/mach-keystone/Kconfig"
956 source "arch/arm/mach-kirkwood/Kconfig"
958 source "arch/arm/mach-ks8695/Kconfig"
960 source "arch/arm/mach-msm/Kconfig"
962 source "arch/arm/mach-mv78xx0/Kconfig"
964 source "arch/arm/mach-imx/Kconfig"
966 source "arch/arm/mach-mxs/Kconfig"
968 source "arch/arm/mach-netx/Kconfig"
970 source "arch/arm/mach-nomadik/Kconfig"
972 source "arch/arm/mach-nspire/Kconfig"
974 source "arch/arm/plat-omap/Kconfig"
976 source "arch/arm/mach-omap1/Kconfig"
978 source "arch/arm/mach-omap2/Kconfig"
980 source "arch/arm/mach-orion5x/Kconfig"
982 source "arch/arm/mach-picoxcell/Kconfig"
984 source "arch/arm/mach-pxa/Kconfig"
985 source "arch/arm/plat-pxa/Kconfig"
987 source "arch/arm/mach-mmp/Kconfig"
989 source "arch/arm/mach-realview/Kconfig"
991 source "arch/arm/mach-rockchip/Kconfig"
993 source "arch/arm/mach-sa1100/Kconfig"
995 source "arch/arm/plat-samsung/Kconfig"
997 source "arch/arm/mach-socfpga/Kconfig"
999 source "arch/arm/mach-spear/Kconfig"
1001 source "arch/arm/mach-sti/Kconfig"
1003 source "arch/arm/mach-s3c24xx/Kconfig"
1006 source "arch/arm/mach-s3c64xx/Kconfig"
1009 source "arch/arm/mach-s5p64x0/Kconfig"
1011 source "arch/arm/mach-s5pc100/Kconfig"
1013 source "arch/arm/mach-s5pv210/Kconfig"
1015 source "arch/arm/mach-exynos/Kconfig"
1017 source "arch/arm/mach-shmobile/Kconfig"
1019 source "arch/arm/mach-sunxi/Kconfig"
1021 source "arch/arm/mach-prima2/Kconfig"
1023 source "arch/arm/mach-tegra/Kconfig"
1025 source "arch/arm/mach-u300/Kconfig"
1027 source "arch/arm/mach-ux500/Kconfig"
1029 source "arch/arm/mach-versatile/Kconfig"
1031 source "arch/arm/mach-vexpress/Kconfig"
1032 source "arch/arm/plat-versatile/Kconfig"
1034 source "arch/arm/mach-virt/Kconfig"
1036 source "arch/arm/mach-vt8500/Kconfig"
1038 source "arch/arm/mach-w90x900/Kconfig"
1040 source "arch/arm/mach-zynq/Kconfig"
1042 # Definitions to make life easier
1048 select GENERIC_CLOCKEVENTS
1054 select GENERIC_IRQ_CHIP
1057 config PLAT_ORION_LEGACY
1064 config PLAT_VERSATILE
1067 config ARM_TIMER_SP804
1070 select CLKSRC_OF if OF
1072 source arch/arm/mm/Kconfig
1076 default 16 if ARCH_EP93XX
1080 bool "Enable iWMMXt support" if !CPU_PJ4
1081 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1082 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1084 Enable support for iWMMXt context switching at run time if
1085 running on a CPU that supports it.
1089 depends on CPU_XSCALE
1092 config MULTI_IRQ_HANDLER
1095 Allow each machine to specify it's own IRQ handler at run time.
1098 source "arch/arm/Kconfig-nommu"
1101 config PJ4B_ERRATA_4742
1102 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1103 depends on CPU_PJ4B && MACH_ARMADA_370
1106 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1107 Event (WFE) IDLE states, a specific timing sensitivity exists between
1108 the retiring WFI/WFE instructions and the newly issued subsequent
1109 instructions. This sensitivity can result in a CPU hang scenario.
1111 The software must insert either a Data Synchronization Barrier (DSB)
1112 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1115 config ARM_ERRATA_326103
1116 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1119 Executing a SWP instruction to read-only memory does not set bit 11
1120 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1121 treat the access as a read, preventing a COW from occurring and
1122 causing the faulting task to livelock.
1124 config ARM_ERRATA_411920
1125 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1126 depends on CPU_V6 || CPU_V6K
1128 Invalidation of the Instruction Cache operation can
1129 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1130 It does not affect the MPCore. This option enables the ARM Ltd.
1131 recommended workaround.
1133 config ARM_ERRATA_430973
1134 bool "ARM errata: Stale prediction on replaced interworking branch"
1137 This option enables the workaround for the 430973 Cortex-A8
1138 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1139 interworking branch is replaced with another code sequence at the
1140 same virtual address, whether due to self-modifying code or virtual
1141 to physical address re-mapping, Cortex-A8 does not recover from the
1142 stale interworking branch prediction. This results in Cortex-A8
1143 executing the new code sequence in the incorrect ARM or Thumb state.
1144 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1145 and also flushes the branch target cache at every context switch.
1146 Note that setting specific bits in the ACTLR register may not be
1147 available in non-secure mode.
1149 config ARM_ERRATA_458693
1150 bool "ARM errata: Processor deadlock when a false hazard is created"
1152 depends on !ARCH_MULTIPLATFORM
1154 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1155 erratum. For very specific sequences of memory operations, it is
1156 possible for a hazard condition intended for a cache line to instead
1157 be incorrectly associated with a different cache line. This false
1158 hazard might then cause a processor deadlock. The workaround enables
1159 the L1 caching of the NEON accesses and disables the PLD instruction
1160 in the ACTLR register. Note that setting specific bits in the ACTLR
1161 register may not be available in non-secure mode.
1163 config ARM_ERRATA_460075
1164 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1166 depends on !ARCH_MULTIPLATFORM
1168 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1169 erratum. Any asynchronous access to the L2 cache may encounter a
1170 situation in which recent store transactions to the L2 cache are lost
1171 and overwritten with stale memory contents from external memory. The
1172 workaround disables the write-allocate mode for the L2 cache via the
1173 ACTLR register. Note that setting specific bits in the ACTLR register
1174 may not be available in non-secure mode.
1176 config ARM_ERRATA_742230
1177 bool "ARM errata: DMB operation may be faulty"
1178 depends on CPU_V7 && SMP
1179 depends on !ARCH_MULTIPLATFORM
1181 This option enables the workaround for the 742230 Cortex-A9
1182 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1183 between two write operations may not ensure the correct visibility
1184 ordering of the two writes. This workaround sets a specific bit in
1185 the diagnostic register of the Cortex-A9 which causes the DMB
1186 instruction to behave as a DSB, ensuring the correct behaviour of
1189 config ARM_ERRATA_742231
1190 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1191 depends on CPU_V7 && SMP
1192 depends on !ARCH_MULTIPLATFORM
1194 This option enables the workaround for the 742231 Cortex-A9
1195 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1196 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1197 accessing some data located in the same cache line, may get corrupted
1198 data due to bad handling of the address hazard when the line gets
1199 replaced from one of the CPUs at the same time as another CPU is
1200 accessing it. This workaround sets specific bits in the diagnostic
1201 register of the Cortex-A9 which reduces the linefill issuing
1202 capabilities of the processor.
1204 config PL310_ERRATA_588369
1205 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1206 depends on CACHE_L2X0
1208 The PL310 L2 cache controller implements three types of Clean &
1209 Invalidate maintenance operations: by Physical Address
1210 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1211 They are architecturally defined to behave as the execution of a
1212 clean operation followed immediately by an invalidate operation,
1213 both performing to the same memory location. This functionality
1214 is not correctly implemented in PL310 as clean lines are not
1215 invalidated as a result of these operations.
1217 config ARM_ERRATA_643719
1218 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1219 depends on CPU_V7 && SMP
1221 This option enables the workaround for the 643719 Cortex-A9 (prior to
1222 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1223 register returns zero when it should return one. The workaround
1224 corrects this value, ensuring cache maintenance operations which use
1225 it behave as intended and avoiding data corruption.
1227 config ARM_ERRATA_720789
1228 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1231 This option enables the workaround for the 720789 Cortex-A9 (prior to
1232 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1233 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1234 As a consequence of this erratum, some TLB entries which should be
1235 invalidated are not, resulting in an incoherency in the system page
1236 tables. The workaround changes the TLB flushing routines to invalidate
1237 entries regardless of the ASID.
1239 config PL310_ERRATA_727915
1240 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1241 depends on CACHE_L2X0
1243 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1244 operation (offset 0x7FC). This operation runs in background so that
1245 PL310 can handle normal accesses while it is in progress. Under very
1246 rare circumstances, due to this erratum, write data can be lost when
1247 PL310 treats a cacheable write transaction during a Clean &
1248 Invalidate by Way operation.
1250 config ARM_ERRATA_743622
1251 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1253 depends on !ARCH_MULTIPLATFORM
1255 This option enables the workaround for the 743622 Cortex-A9
1256 (r2p*) erratum. Under very rare conditions, a faulty
1257 optimisation in the Cortex-A9 Store Buffer may lead to data
1258 corruption. This workaround sets a specific bit in the diagnostic
1259 register of the Cortex-A9 which disables the Store Buffer
1260 optimisation, preventing the defect from occurring. This has no
1261 visible impact on the overall performance or power consumption of the
1264 config ARM_ERRATA_751472
1265 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1267 depends on !ARCH_MULTIPLATFORM
1269 This option enables the workaround for the 751472 Cortex-A9 (prior
1270 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1271 completion of a following broadcasted operation if the second
1272 operation is received by a CPU before the ICIALLUIS has completed,
1273 potentially leading to corrupted entries in the cache or TLB.
1275 config PL310_ERRATA_753970
1276 bool "PL310 errata: cache sync operation may be faulty"
1277 depends on CACHE_PL310
1279 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1281 Under some condition the effect of cache sync operation on
1282 the store buffer still remains when the operation completes.
1283 This means that the store buffer is always asked to drain and
1284 this prevents it from merging any further writes. The workaround
1285 is to replace the normal offset of cache sync operation (0x730)
1286 by another offset targeting an unmapped PL310 register 0x740.
1287 This has the same effect as the cache sync operation: store buffer
1288 drain and waiting for all buffers empty.
1290 config ARM_ERRATA_754322
1291 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1294 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1295 r3p*) erratum. A speculative memory access may cause a page table walk
1296 which starts prior to an ASID switch but completes afterwards. This
1297 can populate the micro-TLB with a stale entry which may be hit with
1298 the new ASID. This workaround places two dsb instructions in the mm
1299 switching code so that no page table walks can cross the ASID switch.
1301 config ARM_ERRATA_754327
1302 bool "ARM errata: no automatic Store Buffer drain"
1303 depends on CPU_V7 && SMP
1305 This option enables the workaround for the 754327 Cortex-A9 (prior to
1306 r2p0) erratum. The Store Buffer does not have any automatic draining
1307 mechanism and therefore a livelock may occur if an external agent
1308 continuously polls a memory location waiting to observe an update.
1309 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1310 written polling loops from denying visibility of updates to memory.
1312 config ARM_ERRATA_364296
1313 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1314 depends on CPU_V6 && !SMP
1316 This options enables the workaround for the 364296 ARM1136
1317 r0p2 erratum (possible cache data corruption with
1318 hit-under-miss enabled). It sets the undocumented bit 31 in
1319 the auxiliary control register and the FI bit in the control
1320 register, thus disabling hit-under-miss without putting the
1321 processor into full low interrupt latency mode. ARM11MPCore
1324 config ARM_ERRATA_764369
1325 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1326 depends on CPU_V7 && SMP
1328 This option enables the workaround for erratum 764369
1329 affecting Cortex-A9 MPCore with two or more processors (all
1330 current revisions). Under certain timing circumstances, a data
1331 cache line maintenance operation by MVA targeting an Inner
1332 Shareable memory region may fail to proceed up to either the
1333 Point of Coherency or to the Point of Unification of the
1334 system. This workaround adds a DSB instruction before the
1335 relevant cache maintenance functions and sets a specific bit
1336 in the diagnostic control register of the SCU.
1338 config PL310_ERRATA_769419
1339 bool "PL310 errata: no automatic Store Buffer drain"
1340 depends on CACHE_L2X0
1342 On revisions of the PL310 prior to r3p2, the Store Buffer does
1343 not automatically drain. This can cause normal, non-cacheable
1344 writes to be retained when the memory system is idle, leading
1345 to suboptimal I/O performance for drivers using coherent DMA.
1346 This option adds a write barrier to the cpu_idle loop so that,
1347 on systems with an outer cache, the store buffer is drained
1350 config ARM_ERRATA_775420
1351 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1354 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1355 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1356 operation aborts with MMU exception, it might cause the processor
1357 to deadlock. This workaround puts DSB before executing ISB if
1358 an abort may occur on cache maintenance.
1360 config ARM_ERRATA_798181
1361 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1362 depends on CPU_V7 && SMP
1364 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1365 adequately shooting down all use of the old entries. This
1366 option enables the Linux kernel workaround for this erratum
1367 which sends an IPI to the CPUs that are running the same ASID
1368 as the one being invalidated.
1372 source "arch/arm/common/Kconfig"
1382 Find out whether you have ISA slots on your motherboard. ISA is the
1383 name of a bus system, i.e. the way the CPU talks to the other stuff
1384 inside your box. Other bus systems are PCI, EISA, MicroChannel
1385 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1386 newer boards don't support it. If you have ISA, say Y, otherwise N.
1388 # Select ISA DMA controller support
1393 # Select ISA DMA interface
1398 bool "PCI support" if MIGHT_HAVE_PCI
1400 Find out whether you have a PCI motherboard. PCI is the name of a
1401 bus system, i.e. the way the CPU talks to the other stuff inside
1402 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1403 VESA. If you have PCI, say Y, otherwise N.
1409 config PCI_NANOENGINE
1410 bool "BSE nanoEngine PCI support"
1411 depends on SA1100_NANOENGINE
1413 Enable PCI on the BSE nanoEngine board.
1418 # Select the host bridge type
1419 config PCI_HOST_VIA82C505
1421 depends on PCI && ARCH_SHARK
1424 config PCI_HOST_ITE8152
1426 depends on PCI && MACH_ARMCORE
1430 source "drivers/pci/Kconfig"
1431 source "drivers/pci/pcie/Kconfig"
1433 source "drivers/pcmcia/Kconfig"
1437 menu "Kernel Features"
1442 This option should be selected by machines which have an SMP-
1445 The only effect of this option is to make the SMP-related
1446 options available to the user for configuration.
1449 bool "Symmetric Multi-Processing"
1450 depends on CPU_V6K || CPU_V7
1451 depends on GENERIC_CLOCKEVENTS
1454 select USE_GENERIC_SMP_HELPERS
1456 This enables support for systems with more than one CPU. If you have
1457 a system with only one CPU, like most personal computers, say N. If
1458 you have a system with more than one CPU, say Y.
1460 If you say N here, the kernel will run on single and multiprocessor
1461 machines, but will use only one CPU of a multiprocessor machine. If
1462 you say Y here, the kernel will run on many, but not all, single
1463 processor machines. On a single processor machine, the kernel will
1464 run faster if you say N here.
1466 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1467 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1468 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1470 If you don't know what to do here, say N.
1473 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1474 depends on SMP && !XIP_KERNEL
1477 SMP kernels contain instructions which fail on non-SMP processors.
1478 Enabling this option allows the kernel to modify itself to make
1479 these instructions safe. Disabling it allows about 1K of space
1482 If you don't know what to do here, say Y.
1484 config ARM_CPU_TOPOLOGY
1485 bool "Support cpu topology definition"
1486 depends on SMP && CPU_V7
1489 Support ARM cpu topology definition. The MPIDR register defines
1490 affinity between processors which is then used to describe the cpu
1491 topology of an ARM System.
1494 bool "Multi-core scheduler support"
1495 depends on ARM_CPU_TOPOLOGY
1497 Multi-core scheduler support improves the CPU scheduler's decision
1498 making when dealing with multi-core CPU chips at a cost of slightly
1499 increased overhead in some places. If unsure say N here.
1502 bool "SMT scheduler support"
1503 depends on ARM_CPU_TOPOLOGY
1505 Improves the CPU scheduler's decision making when dealing with
1506 MultiThreading at a cost of slightly increased overhead in some
1507 places. If unsure say N here.
1512 This option enables support for the ARM system coherency unit
1514 config HAVE_ARM_ARCH_TIMER
1515 bool "Architected timer support"
1517 select ARM_ARCH_TIMER
1519 This option enables support for the ARM architected timer
1524 select CLKSRC_OF if OF
1526 This options enables support for the ARM timer and watchdog unit
1529 bool "Multi-Cluster Power Management"
1530 depends on CPU_V7 && SMP
1532 This option provides the common power management infrastructure
1533 for (multi-)cluster based systems, such as big.LITTLE based
1537 prompt "Memory split"
1540 Select the desired split between kernel and user memory.
1542 If you are not absolutely sure what you are doing, leave this
1546 bool "3G/1G user/kernel split"
1548 bool "2G/2G user/kernel split"
1550 bool "1G/3G user/kernel split"
1555 default 0x40000000 if VMSPLIT_1G
1556 default 0x80000000 if VMSPLIT_2G
1560 int "Maximum number of CPUs (2-32)"
1566 bool "Support for hot-pluggable CPUs"
1569 Say Y here to experiment with turning CPUs off and on. CPUs
1570 can be controlled through /sys/devices/system/cpu.
1573 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1576 Say Y here if you want Linux to communicate with system firmware
1577 implementing the PSCI specification for CPU-centric power
1578 management operations described in ARM document number ARM DEN
1579 0022A ("Power State Coordination Interface System Software on
1583 bool "Use local timer interrupts"
1587 Enable support for local timers on SMP platforms, rather then the
1588 legacy IPI broadcast method. Local timers allows the system
1589 accounting to be spread across the timer interval, preventing a
1590 "thundering herd" at every timer tick.
1592 # The GPIO number here must be sorted by descending number. In case of
1593 # a multiplatform kernel, we just want the highest value required by the
1594 # selected platforms.
1597 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1598 default 512 if SOC_OMAP5
1599 default 512 if ARCH_KEYSTONE
1600 default 392 if ARCH_U8500
1601 default 352 if ARCH_VT8500
1602 default 288 if ARCH_SUNXI
1603 default 264 if MACH_H4700
1606 Maximum number of GPIOs in the system.
1608 If unsure, leave the default value.
1610 source kernel/Kconfig.preempt
1614 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1615 ARCH_S5PV210 || ARCH_EXYNOS4
1616 default AT91_TIMER_HZ if ARCH_AT91
1617 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1621 def_bool HIGH_RES_TIMERS
1623 config THUMB2_KERNEL
1624 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1625 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1626 default y if CPU_THUMBONLY
1628 select ARM_ASM_UNIFIED
1631 By enabling this option, the kernel will be compiled in
1632 Thumb-2 mode. A compiler/assembler that understand the unified
1633 ARM-Thumb syntax is needed.
1637 config THUMB2_AVOID_R_ARM_THM_JUMP11
1638 bool "Work around buggy Thumb-2 short branch relocations in gas"
1639 depends on THUMB2_KERNEL && MODULES
1642 Various binutils versions can resolve Thumb-2 branches to
1643 locally-defined, preemptible global symbols as short-range "b.n"
1644 branch instructions.
1646 This is a problem, because there's no guarantee the final
1647 destination of the symbol, or any candidate locations for a
1648 trampoline, are within range of the branch. For this reason, the
1649 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1650 relocation in modules at all, and it makes little sense to add
1653 The symptom is that the kernel fails with an "unsupported
1654 relocation" error when loading some modules.
1656 Until fixed tools are available, passing
1657 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1658 code which hits this problem, at the cost of a bit of extra runtime
1659 stack usage in some cases.
1661 The problem is described in more detail at:
1662 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1664 Only Thumb-2 kernels are affected.
1666 Unless you are sure your tools don't have this problem, say Y.
1668 config ARM_ASM_UNIFIED
1672 bool "Use the ARM EABI to compile the kernel"
1674 This option allows for the kernel to be compiled using the latest
1675 ARM ABI (aka EABI). This is only useful if you are using a user
1676 space environment that is also compiled with EABI.
1678 Since there are major incompatibilities between the legacy ABI and
1679 EABI, especially with regard to structure member alignment, this
1680 option also changes the kernel syscall calling convention to
1681 disambiguate both ABIs and allow for backward compatibility support
1682 (selected with CONFIG_OABI_COMPAT).
1684 To use this you need GCC version 4.0.0 or later.
1687 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1688 depends on AEABI && !THUMB2_KERNEL
1691 This option preserves the old syscall interface along with the
1692 new (ARM EABI) one. It also provides a compatibility layer to
1693 intercept syscalls that have structure arguments which layout
1694 in memory differs between the legacy ABI and the new ARM EABI
1695 (only for non "thumb" binaries). This option adds a tiny
1696 overhead to all syscalls and produces a slightly larger kernel.
1697 If you know you'll be using only pure EABI user space then you
1698 can say N here. If this option is not selected and you attempt
1699 to execute a legacy ABI binary then the result will be
1700 UNPREDICTABLE (in fact it can be predicted that it won't work
1701 at all). If in doubt say Y.
1703 config ARCH_HAS_HOLES_MEMORYMODEL
1706 config ARCH_SPARSEMEM_ENABLE
1709 config ARCH_SPARSEMEM_DEFAULT
1710 def_bool ARCH_SPARSEMEM_ENABLE
1712 config ARCH_SELECT_MEMORY_MODEL
1713 def_bool ARCH_SPARSEMEM_ENABLE
1715 config HAVE_ARCH_PFN_VALID
1716 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1719 bool "High Memory Support"
1722 The address space of ARM processors is only 4 Gigabytes large
1723 and it has to accommodate user address space, kernel address
1724 space as well as some memory mapped IO. That means that, if you
1725 have a large amount of physical memory and/or IO, not all of the
1726 memory can be "permanently mapped" by the kernel. The physical
1727 memory that is not permanently mapped is called "high memory".
1729 Depending on the selected kernel/user memory split, minimum
1730 vmalloc space and actual amount of RAM, you may not need this
1731 option which should result in a slightly faster kernel.
1736 bool "Allocate 2nd-level pagetables from highmem"
1739 config HW_PERF_EVENTS
1740 bool "Enable hardware performance counter support for perf events"
1741 depends on PERF_EVENTS
1744 Enable hardware performance counter support for perf events. If
1745 disabled, perf events will use software events only.
1749 config FORCE_MAX_ZONEORDER
1750 int "Maximum zone order" if ARCH_SHMOBILE
1751 range 11 64 if ARCH_SHMOBILE
1752 default "12" if SOC_AM33XX
1753 default "9" if SA1111
1756 The kernel memory allocator divides physically contiguous memory
1757 blocks into "zones", where each zone is a power of two number of
1758 pages. This option selects the largest power of two that the kernel
1759 keeps in the memory allocator. If you need to allocate very large
1760 blocks of physically contiguous memory, then you may need to
1761 increase this value.
1763 This config option is actually maximum order plus one. For example,
1764 a value of 11 means that the largest free memory block is 2^10 pages.
1766 config ALIGNMENT_TRAP
1768 depends on CPU_CP15_MMU
1769 default y if !ARCH_EBSA110
1770 select HAVE_PROC_CPU if PROC_FS
1772 ARM processors cannot fetch/store information which is not
1773 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1774 address divisible by 4. On 32-bit ARM processors, these non-aligned
1775 fetch/store instructions will be emulated in software if you say
1776 here, which has a severe performance impact. This is necessary for
1777 correct operation of some network protocols. With an IP-only
1778 configuration it is safe to say N, otherwise say Y.
1780 config UACCESS_WITH_MEMCPY
1781 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1783 default y if CPU_FEROCEON
1785 Implement faster copy_to_user and clear_user methods for CPU
1786 cores where a 8-word STM instruction give significantly higher
1787 memory write throughput than a sequence of individual 32bit stores.
1789 A possible side effect is a slight increase in scheduling latency
1790 between threads sharing the same address space if they invoke
1791 such copy operations with large buffers.
1793 However, if the CPU data cache is using a write-allocate mode,
1794 this option is unlikely to provide any performance gain.
1798 prompt "Enable seccomp to safely compute untrusted bytecode"
1800 This kernel feature is useful for number crunching applications
1801 that may need to compute untrusted bytecode during their
1802 execution. By using pipes or other transports made available to
1803 the process as file descriptors supporting the read/write
1804 syscalls, it's possible to isolate those applications in
1805 their own address space using seccomp. Once seccomp is
1806 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1807 and the task is only allowed to execute a few safe syscalls
1808 defined by each seccomp mode.
1810 config CC_STACKPROTECTOR
1811 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1813 This option turns on the -fstack-protector GCC feature. This
1814 feature puts, at the beginning of functions, a canary value on
1815 the stack just before the return address, and validates
1816 the value just before actually returning. Stack based buffer
1817 overflows (that need to overwrite this return address) now also
1818 overwrite the canary, which gets detected and the attack is then
1819 neutralized via a kernel panic.
1820 This feature requires gcc version 4.2 or above.
1827 bool "Xen guest support on ARM (EXPERIMENTAL)"
1828 depends on ARM && AEABI && OF
1829 depends on CPU_V7 && !CPU_V6
1830 depends on !GENERIC_ATOMIC64
1833 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1840 bool "Flattened Device Tree support"
1843 select OF_EARLY_FLATTREE
1845 Include support for flattened device tree machine descriptions.
1848 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1851 This is the traditional way of passing data to the kernel at boot
1852 time. If you are solely relying on the flattened device tree (or
1853 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1854 to remove ATAGS support from your kernel binary. If unsure,
1857 config DEPRECATED_PARAM_STRUCT
1858 bool "Provide old way to pass kernel parameters"
1861 This was deprecated in 2001 and announced to live on for 5 years.
1862 Some old boot loaders still use this way.
1864 # Compressed boot loader in ROM. Yes, we really want to ask about
1865 # TEXT and BSS so we preserve their values in the config files.
1866 config ZBOOT_ROM_TEXT
1867 hex "Compressed ROM boot loader base address"
1870 The physical address at which the ROM-able zImage is to be
1871 placed in the target. Platforms which normally make use of
1872 ROM-able zImage formats normally set this to a suitable
1873 value in their defconfig file.
1875 If ZBOOT_ROM is not enabled, this has no effect.
1877 config ZBOOT_ROM_BSS
1878 hex "Compressed ROM boot loader BSS address"
1881 The base address of an area of read/write memory in the target
1882 for the ROM-able zImage which must be available while the
1883 decompressor is running. It must be large enough to hold the
1884 entire decompressed kernel plus an additional 128 KiB.
1885 Platforms which normally make use of ROM-able zImage formats
1886 normally set this to a suitable value in their defconfig file.
1888 If ZBOOT_ROM is not enabled, this has no effect.
1891 bool "Compressed boot loader in ROM/flash"
1892 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1894 Say Y here if you intend to execute your compressed kernel image
1895 (zImage) directly from ROM or flash. If unsure, say N.
1898 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1899 depends on ZBOOT_ROM && ARCH_SH7372
1900 default ZBOOT_ROM_NONE
1902 Include experimental SD/MMC loading code in the ROM-able zImage.
1903 With this enabled it is possible to write the ROM-able zImage
1904 kernel image to an MMC or SD card and boot the kernel straight
1905 from the reset vector. At reset the processor Mask ROM will load
1906 the first part of the ROM-able zImage which in turn loads the
1907 rest the kernel image to RAM.
1909 config ZBOOT_ROM_NONE
1910 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1912 Do not load image from SD or MMC
1914 config ZBOOT_ROM_MMCIF
1915 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1917 Load image from MMCIF hardware block.
1919 config ZBOOT_ROM_SH_MOBILE_SDHI
1920 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1922 Load image from SDHI hardware block
1926 config ARM_APPENDED_DTB
1927 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1928 depends on OF && !ZBOOT_ROM
1930 With this option, the boot code will look for a device tree binary
1931 (DTB) appended to zImage
1932 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1934 This is meant as a backward compatibility convenience for those
1935 systems with a bootloader that can't be upgraded to accommodate
1936 the documented boot protocol using a device tree.
1938 Beware that there is very little in terms of protection against
1939 this option being confused by leftover garbage in memory that might
1940 look like a DTB header after a reboot if no actual DTB is appended
1941 to zImage. Do not leave this option active in a production kernel
1942 if you don't intend to always append a DTB. Proper passing of the
1943 location into r2 of a bootloader provided DTB is always preferable
1946 config ARM_ATAG_DTB_COMPAT
1947 bool "Supplement the appended DTB with traditional ATAG information"
1948 depends on ARM_APPENDED_DTB
1950 Some old bootloaders can't be updated to a DTB capable one, yet
1951 they provide ATAGs with memory configuration, the ramdisk address,
1952 the kernel cmdline string, etc. Such information is dynamically
1953 provided by the bootloader and can't always be stored in a static
1954 DTB. To allow a device tree enabled kernel to be used with such
1955 bootloaders, this option allows zImage to extract the information
1956 from the ATAG list and store it at run time into the appended DTB.
1959 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1960 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1962 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1963 bool "Use bootloader kernel arguments if available"
1965 Uses the command-line options passed by the boot loader instead of
1966 the device tree bootargs property. If the boot loader doesn't provide
1967 any, the device tree bootargs property will be used.
1969 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1970 bool "Extend with bootloader kernel arguments"
1972 The command-line arguments provided by the boot loader will be
1973 appended to the the device tree bootargs property.
1978 string "Default kernel command string"
1981 On some architectures (EBSA110 and CATS), there is currently no way
1982 for the boot loader to pass arguments to the kernel. For these
1983 architectures, you should supply some command-line options at build
1984 time by entering them here. As a minimum, you should specify the
1985 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1988 prompt "Kernel command line type" if CMDLINE != ""
1989 default CMDLINE_FROM_BOOTLOADER
1992 config CMDLINE_FROM_BOOTLOADER
1993 bool "Use bootloader kernel arguments if available"
1995 Uses the command-line options passed by the boot loader. If
1996 the boot loader doesn't provide any, the default kernel command
1997 string provided in CMDLINE will be used.
1999 config CMDLINE_EXTEND
2000 bool "Extend bootloader kernel arguments"
2002 The command-line arguments provided by the boot loader will be
2003 appended to the default kernel command string.
2005 config CMDLINE_FORCE
2006 bool "Always use the default kernel command string"
2008 Always use the default kernel command string, even if the boot
2009 loader passes other arguments to the kernel.
2010 This is useful if you cannot or don't want to change the
2011 command-line options your boot loader passes to the kernel.
2015 bool "Kernel Execute-In-Place from ROM"
2016 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2018 Execute-In-Place allows the kernel to run from non-volatile storage
2019 directly addressable by the CPU, such as NOR flash. This saves RAM
2020 space since the text section of the kernel is not loaded from flash
2021 to RAM. Read-write sections, such as the data section and stack,
2022 are still copied to RAM. The XIP kernel is not compressed since
2023 it has to run directly from flash, so it will take more space to
2024 store it. The flash address used to link the kernel object files,
2025 and for storing it, is configuration dependent. Therefore, if you
2026 say Y here, you must know the proper physical address where to
2027 store the kernel image depending on your own flash memory usage.
2029 Also note that the make target becomes "make xipImage" rather than
2030 "make zImage" or "make Image". The final kernel binary to put in
2031 ROM memory will be arch/arm/boot/xipImage.
2035 config XIP_PHYS_ADDR
2036 hex "XIP Kernel Physical Location"
2037 depends on XIP_KERNEL
2038 default "0x00080000"
2040 This is the physical address in your flash memory the kernel will
2041 be linked for and stored to. This address is dependent on your
2045 bool "Kexec system call (EXPERIMENTAL)"
2046 depends on (!SMP || PM_SLEEP_SMP)
2048 kexec is a system call that implements the ability to shutdown your
2049 current kernel, and to start another kernel. It is like a reboot
2050 but it is independent of the system firmware. And like a reboot
2051 you can start any kernel with it, not just Linux.
2053 It is an ongoing process to be certain the hardware in a machine
2054 is properly shutdown, so do not be surprised if this code does not
2055 initially work for you. It may help to enable device hotplugging
2059 bool "Export atags in procfs"
2060 depends on ATAGS && KEXEC
2063 Should the atags used to boot the kernel be exported in an "atags"
2064 file in procfs. Useful with kexec.
2067 bool "Build kdump crash kernel (EXPERIMENTAL)"
2069 Generate crash dump after being started by kexec. This should
2070 be normally only set in special crash dump kernels which are
2071 loaded in the main kernel with kexec-tools into a specially
2072 reserved region and then later executed after a crash by
2073 kdump/kexec. The crash dump kernel must be compiled to a
2074 memory address not used by the main kernel
2076 For more details see Documentation/kdump/kdump.txt
2078 config AUTO_ZRELADDR
2079 bool "Auto calculation of the decompressed kernel image address"
2080 depends on !ZBOOT_ROM
2082 ZRELADDR is the physical address where the decompressed kernel
2083 image will be placed. If AUTO_ZRELADDR is selected, the address
2084 will be determined at run-time by masking the current IP with
2085 0xf8000000. This assumes the zImage being placed in the first 128MB
2086 from start of memory.
2090 menu "CPU Power Management"
2093 source "drivers/cpufreq/Kconfig"
2096 source "drivers/cpuidle/Kconfig"
2100 menu "Floating point emulation"
2102 comment "At least one emulation must be selected"
2105 bool "NWFPE math emulation"
2106 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2108 Say Y to include the NWFPE floating point emulator in the kernel.
2109 This is necessary to run most binaries. Linux does not currently
2110 support floating point hardware so you need to say Y here even if
2111 your machine has an FPA or floating point co-processor podule.
2113 You may say N here if you are going to load the Acorn FPEmulator
2114 early in the bootup.
2117 bool "Support extended precision"
2118 depends on FPE_NWFPE
2120 Say Y to include 80-bit support in the kernel floating-point
2121 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2122 Note that gcc does not generate 80-bit operations by default,
2123 so in most cases this option only enlarges the size of the
2124 floating point emulator without any good reason.
2126 You almost surely want to say N here.
2129 bool "FastFPE math emulation (EXPERIMENTAL)"
2130 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2132 Say Y here to include the FAST floating point emulator in the kernel.
2133 This is an experimental much faster emulator which now also has full
2134 precision for the mantissa. It does not support any exceptions.
2135 It is very simple, and approximately 3-6 times faster than NWFPE.
2137 It should be sufficient for most programs. It may be not suitable
2138 for scientific calculations, but you have to check this for yourself.
2139 If you do not feel you need a faster FP emulation you should better
2143 bool "VFP-format floating point maths"
2144 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2146 Say Y to include VFP support code in the kernel. This is needed
2147 if your hardware includes a VFP unit.
2149 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2150 release notes and additional status information.
2152 Say N if your target does not have VFP hardware.
2160 bool "Advanced SIMD (NEON) Extension support"
2161 depends on VFPv3 && CPU_V7
2163 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2168 menu "Userspace binary formats"
2170 source "fs/Kconfig.binfmt"
2173 tristate "RISC OS personality"
2176 Say Y here to include the kernel code necessary if you want to run
2177 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2178 experimental; if this sounds frightening, say N and sleep in peace.
2179 You can also say M here to compile this support as a module (which
2180 will be called arthur).
2184 menu "Power management options"
2186 source "kernel/power/Kconfig"
2188 config ARCH_SUSPEND_POSSIBLE
2189 depends on !ARCH_S5PC100
2190 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2191 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2194 config ARM_CPU_SUSPEND
2199 source "net/Kconfig"
2201 source "drivers/Kconfig"
2205 source "arch/arm/Kconfig.debug"
2207 source "security/Kconfig"
2209 source "crypto/Kconfig"
2211 source "lib/Kconfig"
2213 source "arch/arm/kvm/Kconfig"