arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAVE_CUSTOM_GPIO_H
   5         select HAVE_AOUT
   6         select HAVE_DMA_API_DEBUG
   7         select HAVE_IDE if PCI || ISA || PCMCIA
   8         select HAVE_DMA_ATTRS
   9         select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
  10         select HAVE_MEMBLOCK
  11         select RTC_LIB
  12         select SYS_SUPPORTS_APM_EMULATION
  13         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  15         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  16         select HAVE_ARCH_KGDB
  17         select HAVE_ARCH_TRACEHOOK
  18         select HAVE_KPROBES if !XIP_KERNEL
  19         select HAVE_KRETPROBES if (HAVE_KPROBES)
  20         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  21         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  22         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  23         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  24         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  25         select HAVE_GENERIC_DMA_COHERENT
  26         select HAVE_KERNEL_GZIP
  27         select HAVE_KERNEL_LZO
  28         select HAVE_KERNEL_LZMA
  29         select HAVE_KERNEL_XZ
  30         select HAVE_IRQ_WORK
  31         select HAVE_PERF_EVENTS
  32         select PERF_USE_VMALLOC
  33         select HAVE_REGS_AND_STACK_ACCESS_API
  34         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  35         select HAVE_C_RECORDMCOUNT
  36         select HAVE_GENERIC_HARDIRQS
  37         select HARDIRQS_SW_RESEND
  38         select GENERIC_IRQ_PROBE
  39         select GENERIC_IRQ_SHOW
  40         select GENERIC_IRQ_PROBE
  41         select HARDIRQS_SW_RESEND
  42         select CPU_PM if (SUSPEND || CPU_IDLE)
  43         select GENERIC_PCI_IOMAP
  44         select HAVE_BPF_JIT
  45         select GENERIC_SMP_IDLE_THREAD
  46         select KTIME_SCALAR
  47         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  48         help
  49           The ARM series is a line of low-power-consumption RISC chip designs
  50           licensed by ARM Ltd and targeted at embedded applications and
  51           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  52           manufactured, but legacy ARM-based PC hardware remains popular in
  53           Europe.  There is an ARM Linux project with a web page at
  54           <http://www.arm.linux.org.uk/>.
  55
  56 config ARM_HAS_SG_CHAIN
  57         bool
  58
  59 config NEED_SG_DMA_LENGTH
  60         bool
  61
  62 config ARM_DMA_USE_IOMMU
  63         select NEED_SG_DMA_LENGTH
  64         select ARM_HAS_SG_CHAIN
  65         bool
  66
  67 config HAVE_PWM
  68         bool
  69
  70 config MIGHT_HAVE_PCI
  71         bool
  72
  73 config SYS_SUPPORTS_APM_EMULATION
  74         bool
  75
  76 config GENERIC_GPIO
  77         bool
  78
  79 config HAVE_TCM
  80         bool
  81         select GENERIC_ALLOCATOR
  82
  83 config HAVE_PROC_CPU
  84         bool
  85
  86 config NO_IOPORT
  87         bool
  88
  89 config EISA
  90         bool
  91         ---help---
  92           The Extended Industry Standard Architecture (EISA) bus was
  93           developed as an open alternative to the IBM MicroChannel bus.
  94
  95           The EISA bus provided some of the features of the IBM MicroChannel
  96           bus while maintaining backward compatibility with cards made for
  97           the older ISA bus.  The EISA bus saw limited use between 1988 and
  98           1995 when it was made obsolete by the PCI bus.
  99
 100           Say Y here if you are building a kernel for an EISA-based machine.
 101
 102           Otherwise, say N.
 103
 104 config SBUS
 105         bool
 106
 107 config STACKTRACE_SUPPORT
 108         bool
 109         default y
 110
 111 config HAVE_LATENCYTOP_SUPPORT
 112         bool
 113         depends on !SMP
 114         default y
 115
 116 config LOCKDEP_SUPPORT
 117         bool
 118         default y
 119
 120 config TRACE_IRQFLAGS_SUPPORT
 121         bool
 122         default y
 123
 124 config GENERIC_LOCKBREAK
 125         bool
 126         default y
 127         depends on SMP && PREEMPT
 128
 129 config RWSEM_GENERIC_SPINLOCK
 130         bool
 131         default y
 132
 133 config RWSEM_XCHGADD_ALGORITHM
 134         bool
 135
 136 config ARCH_HAS_ILOG2_U32
 137         bool
 138
 139 config ARCH_HAS_ILOG2_U64
 140         bool
 141
 142 config ARCH_HAS_CPUFREQ
 143         bool
 144         help
 145           Internal node to signify that the ARCH has CPUFREQ support
 146           and that the relevant menu configurations are displayed for
 147           it.
 148
 149 config GENERIC_HWEIGHT
 150         bool
 151         default y
 152
 153 config GENERIC_CALIBRATE_DELAY
 154         bool
 155         default y
 156
 157 config ARCH_MAY_HAVE_PC_FDC
 158         bool
 159
 160 config ZONE_DMA
 161         bool
 162
 163 config NEED_DMA_MAP_STATE
 164        def_bool y
 165
 166 config ARCH_HAS_DMA_SET_COHERENT_MASK
 167         bool
 168
 169 config GENERIC_ISA_DMA
 170         bool
 171
 172 config FIQ
 173         bool
 174
 175 config NEED_RET_TO_USER
 176         bool
 177
 178 config ARCH_MTD_XIP
 179         bool
 180
 181 config VECTORS_BASE
 182         hex
 183         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 184         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 185         default 0x00000000
 186         help
 187           The base address of exception vectors.
 188
 189 config ARM_PATCH_PHYS_VIRT
 190         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 191         default y
 192         depends on !XIP_KERNEL && MMU
 193         depends on !ARCH_REALVIEW || !SPARSEMEM
 194         help
 195           Patch phys-to-virt and virt-to-phys translation functions at
 196           boot and module load time according to the position of the
 197           kernel in system memory.
 198
 199           This can only be used with non-XIP MMU kernels where the base
 200           of physical memory is at a 16MB boundary.
 201
 202           Only disable this option if you know that you do not require
 203           this feature (eg, building a kernel for a single machine) and
 204           you need to shrink the kernel to the minimal size.
 205
 206 config NEED_MACH_IO_H
 207         bool
 208         help
 209           Select this when mach/io.h is required to provide special
 210           definitions for this platform.  The need for mach/io.h should
 211           be avoided when possible.
 212
 213 config NEED_MACH_MEMORY_H
 214         bool
 215         help
 216           Select this when mach/memory.h is required to provide special
 217           definitions for this platform.  The need for mach/memory.h should
 218           be avoided when possible.
 219
 220 config PHYS_OFFSET
 221         hex "Physical address of main memory" if MMU
 222         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 223         default DRAM_BASE if !MMU
 224         help
 225           Please provide the physical address corresponding to the
 226           location of main memory in your system.
 227
 228 config GENERIC_BUG
 229         def_bool y
 230         depends on BUG
 231
 232 source "init/Kconfig"
 233
 234 source "kernel/Kconfig.freezer"
 235
 236 menu "System Type"
 237
 238 config MMU
 239         bool "MMU-based Paged Memory Management Support"
 240         default y
 241         help
 242           Select if you want MMU-based virtualised addressing space
 243           support by paged memory management. If unsure, say 'Y'.
 244
 245 #
 246 # The "ARM system type" choice list is ordered alphabetically by option
 247 # text.  Please add new entries in the option alphabetic order.
 248 #
 249 choice
 250         prompt "ARM system type"
 251         default ARCH_VERSATILE
 252
 253 config ARCH_SOCFPGA
 254         bool "Altera SOCFPGA family"
 255         select ARCH_WANT_OPTIONAL_GPIOLIB
 256         select ARM_AMBA
 257         select ARM_GIC
 258         select CACHE_L2X0
 259         select CLKDEV_LOOKUP
 260         select COMMON_CLK
 261         select CPU_V7
 262         select DW_APB_TIMER
 263         select DW_APB_TIMER_OF
 264         select GENERIC_CLOCKEVENTS
 265         select GPIO_PL061 if GPIOLIB
 266         select HAVE_ARM_SCU
 267         select SPARSE_IRQ
 268         select USE_OF
 269         help
 270           This enables support for Altera SOCFPGA Cyclone V platform
 271
 272 config ARCH_INTEGRATOR
 273         bool "ARM Ltd. Integrator family"
 274         select ARM_AMBA
 275         select ARCH_HAS_CPUFREQ
 276         select CLKDEV_LOOKUP
 277         select HAVE_MACH_CLKDEV
 278         select HAVE_TCM
 279         select ICST
 280         select GENERIC_CLOCKEVENTS
 281         select PLAT_VERSATILE
 282         select PLAT_VERSATILE_FPGA_IRQ
 283         select NEED_MACH_IO_H
 284         select NEED_MACH_MEMORY_H
 285         select SPARSE_IRQ
 286         select MULTI_IRQ_HANDLER
 287         help
 288           Support for ARM's Integrator platform.
 289
 290 config ARCH_REALVIEW
 291         bool "ARM Ltd. RealView family"
 292         select ARM_AMBA
 293         select CLKDEV_LOOKUP
 294         select HAVE_MACH_CLKDEV
 295         select ICST
 296         select GENERIC_CLOCKEVENTS
 297         select ARCH_WANT_OPTIONAL_GPIOLIB
 298         select PLAT_VERSATILE
 299         select PLAT_VERSATILE_CLCD
 300         select ARM_TIMER_SP804
 301         select GPIO_PL061 if GPIOLIB
 302         select NEED_MACH_MEMORY_H
 303         help
 304           This enables support for ARM Ltd RealView boards.
 305
 306 config ARCH_VERSATILE
 307         bool "ARM Ltd. Versatile family"
 308         select ARM_AMBA
 309         select ARM_VIC
 310         select CLKDEV_LOOKUP
 311         select HAVE_MACH_CLKDEV
 312         select ICST
 313         select GENERIC_CLOCKEVENTS
 314         select ARCH_WANT_OPTIONAL_GPIOLIB
 315         select NEED_MACH_IO_H if PCI
 316         select PLAT_VERSATILE
 317         select PLAT_VERSATILE_CLCD
 318         select PLAT_VERSATILE_FPGA_IRQ
 319         select ARM_TIMER_SP804
 320         help
 321           This enables support for ARM Ltd Versatile board.
 322
 323 config ARCH_VEXPRESS
 324         bool "ARM Ltd. Versatile Express family"
 325         select ARCH_WANT_OPTIONAL_GPIOLIB
 326         select ARM_AMBA
 327         select ARM_TIMER_SP804
 328         select CLKDEV_LOOKUP
 329         select HAVE_MACH_CLKDEV
 330         select GENERIC_CLOCKEVENTS
 331         select HAVE_CLK
 332         select HAVE_PATA_PLATFORM
 333         select ICST
 334         select NO_IOPORT
 335         select PLAT_VERSATILE
 336         select PLAT_VERSATILE_CLCD
 337         help
 338           This enables support for the ARM Ltd Versatile Express boards.
 339
 340 config ARCH_AT91
 341         bool "Atmel AT91"
 342         select ARCH_REQUIRE_GPIOLIB
 343         select HAVE_CLK
 344         select CLKDEV_LOOKUP
 345         select IRQ_DOMAIN
 346         select NEED_MACH_IO_H if PCCARD
 347         help
 348           This enables support for systems based on Atmel
 349           AT91RM9200 and AT91SAM9* processors.
 350
 351 config ARCH_BCMRING
 352         bool "Broadcom BCMRING"
 353         depends on MMU
 354         select CPU_V6
 355         select ARM_AMBA
 356         select ARM_TIMER_SP804
 357         select CLKDEV_LOOKUP
 358         select GENERIC_CLOCKEVENTS
 359         select ARCH_WANT_OPTIONAL_GPIOLIB
 360         help
 361           Support for Broadcom's BCMRing platform.
 362
 363 config ARCH_HIGHBANK
 364         bool "Calxeda Highbank-based"
 365         select ARCH_WANT_OPTIONAL_GPIOLIB
 366         select ARM_AMBA
 367         select ARM_GIC
 368         select ARM_TIMER_SP804
 369         select CACHE_L2X0
 370         select CLKDEV_LOOKUP
 371         select CPU_V7
 372         select GENERIC_CLOCKEVENTS
 373         select HAVE_ARM_SCU
 374         select HAVE_SMP
 375         select SPARSE_IRQ
 376         select USE_OF
 377         help
 378           Support for the Calxeda Highbank SoC based boards.
 379
 380 config ARCH_CLPS711X
 381         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 382         select CPU_ARM720T
 383         select ARCH_USES_GETTIMEOFFSET
 384         select NEED_MACH_MEMORY_H
 385         help
 386           Support for Cirrus Logic 711x/721x/731x based boards.
 387
 388 config ARCH_CNS3XXX
 389         bool "Cavium Networks CNS3XXX family"
 390         select CPU_V6K
 391         select GENERIC_CLOCKEVENTS
 392         select ARM_GIC
 393         select MIGHT_HAVE_CACHE_L2X0
 394         select MIGHT_HAVE_PCI
 395         select PCI_DOMAINS if PCI
 396         help
 397           Support for Cavium Networks CNS3XXX platform.
 398
 399 config ARCH_GEMINI
 400         bool "Cortina Systems Gemini"
 401         select CPU_FA526
 402         select ARCH_REQUIRE_GPIOLIB
 403         select ARCH_USES_GETTIMEOFFSET
 404         help
 405           Support for the Cortina Systems Gemini family SoCs
 406
 407 config ARCH_PRIMA2
 408         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 409         select CPU_V7
 410         select NO_IOPORT
 411         select GENERIC_CLOCKEVENTS
 412         select CLKDEV_LOOKUP
 413         select GENERIC_IRQ_CHIP
 414         select MIGHT_HAVE_CACHE_L2X0
 415         select PINCTRL
 416         select PINCTRL_SIRF
 417         select USE_OF
 418         select ZONE_DMA
 419         help
 420           Support for CSR SiRFSoC ARM Cortex A9 Platform
 421
 422 config ARCH_EBSA110
 423         bool "EBSA-110"
 424         select CPU_SA110
 425         select ISA
 426         select NO_IOPORT
 427         select ARCH_USES_GETTIMEOFFSET
 428         select NEED_MACH_IO_H
 429         select NEED_MACH_MEMORY_H
 430         help
 431           This is an evaluation board for the StrongARM processor available
 432           from Digital. It has limited hardware on-board, including an
 433           Ethernet interface, two PCMCIA sockets, two serial ports and a
 434           parallel port.
 435
 436 config ARCH_EP93XX
 437         bool "EP93xx-based"
 438         select CPU_ARM920T
 439         select ARM_AMBA
 440         select ARM_VIC
 441         select CLKDEV_LOOKUP
 442         select ARCH_REQUIRE_GPIOLIB
 443         select ARCH_HAS_HOLES_MEMORYMODEL
 444         select ARCH_USES_GETTIMEOFFSET
 445         select NEED_MACH_MEMORY_H
 446         help
 447           This enables support for the Cirrus EP93xx series of CPUs.
 448
 449 config ARCH_FOOTBRIDGE
 450         bool "FootBridge"
 451         select CPU_SA110
 452         select FOOTBRIDGE
 453         select GENERIC_CLOCKEVENTS
 454         select HAVE_IDE
 455         select NEED_MACH_IO_H
 456         select NEED_MACH_MEMORY_H
 457         help
 458           Support for systems based on the DC21285 companion chip
 459           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 460
 461 config ARCH_MXC
 462         bool "Freescale MXC/iMX-based"
 463         select GENERIC_CLOCKEVENTS
 464         select ARCH_REQUIRE_GPIOLIB
 465         select CLKDEV_LOOKUP
 466         select CLKSRC_MMIO
 467         select GENERIC_IRQ_CHIP
 468         select MULTI_IRQ_HANDLER
 469         help
 470           Support for Freescale MXC/iMX-based family of processors
 471
 472 config ARCH_MXS
 473         bool "Freescale MXS-based"
 474         select GENERIC_CLOCKEVENTS
 475         select ARCH_REQUIRE_GPIOLIB
 476         select CLKDEV_LOOKUP
 477         select CLKSRC_MMIO
 478         select COMMON_CLK
 479         select HAVE_CLK_PREPARE
 480         select PINCTRL
 481         select USE_OF
 482         help
 483           Support for Freescale MXS-based family of processors
 484
 485 config ARCH_NETX
 486         bool "Hilscher NetX based"
 487         select CLKSRC_MMIO
 488         select CPU_ARM926T
 489         select ARM_VIC
 490         select GENERIC_CLOCKEVENTS
 491         help
 492           This enables support for systems based on the Hilscher NetX Soc
 493
 494 config ARCH_H720X
 495         bool "Hynix HMS720x-based"
 496         select CPU_ARM720T
 497         select ISA_DMA_API
 498         select ARCH_USES_GETTIMEOFFSET
 499         help
 500           This enables support for systems based on the Hynix HMS720x
 501
 502 config ARCH_IOP13XX
 503         bool "IOP13xx-based"
 504         depends on MMU
 505         select CPU_XSC3
 506         select PLAT_IOP
 507         select PCI
 508         select ARCH_SUPPORTS_MSI
 509         select VMSPLIT_1G
 510         select NEED_MACH_IO_H
 511         select NEED_MACH_MEMORY_H
 512         select NEED_RET_TO_USER
 513         help
 514           Support for Intel's IOP13XX (XScale) family of processors.
 515
 516 config ARCH_IOP32X
 517         bool "IOP32x-based"
 518         depends on MMU
 519         select CPU_XSCALE
 520         select NEED_MACH_IO_H
 521         select NEED_RET_TO_USER
 522         select PLAT_IOP
 523         select PCI
 524         select ARCH_REQUIRE_GPIOLIB
 525         help
 526           Support for Intel's 80219 and IOP32X (XScale) family of
 527           processors.
 528
 529 config ARCH_IOP33X
 530         bool "IOP33x-based"
 531         depends on MMU
 532         select CPU_XSCALE
 533         select NEED_MACH_IO_H
 534         select NEED_RET_TO_USER
 535         select PLAT_IOP
 536         select PCI
 537         select ARCH_REQUIRE_GPIOLIB
 538         help
 539           Support for Intel's IOP33X (XScale) family of processors.
 540
 541 config ARCH_IXP4XX
 542         bool "IXP4xx-based"
 543         depends on MMU
 544         select ARCH_HAS_DMA_SET_COHERENT_MASK
 545         select CLKSRC_MMIO
 546         select CPU_XSCALE
 547         select ARCH_REQUIRE_GPIOLIB
 548         select GENERIC_CLOCKEVENTS
 549         select MIGHT_HAVE_PCI
 550         select NEED_MACH_IO_H
 551         select DMABOUNCE if PCI
 552         help
 553           Support for Intel's IXP4XX (XScale) family of processors.
 554
 555 config ARCH_MVEBU
 556         bool "Marvell SOCs with Device Tree support"
 557         select GENERIC_CLOCKEVENTS
 558         select MULTI_IRQ_HANDLER
 559         select SPARSE_IRQ
 560         select CLKSRC_MMIO
 561         select GENERIC_IRQ_CHIP
 562         select IRQ_DOMAIN
 563         select COMMON_CLK
 564         help
 565           Support for the Marvell SoC Family with device tree support
 566
 567 config ARCH_DOVE
 568         bool "Marvell Dove"
 569         select CPU_V7
 570         select PCI
 571         select ARCH_REQUIRE_GPIOLIB
 572         select GENERIC_CLOCKEVENTS
 573         select NEED_MACH_IO_H
 574         select PLAT_ORION
 575         help
 576           Support for the Marvell Dove SoC 88AP510
 577
 578 config ARCH_KIRKWOOD
 579         bool "Marvell Kirkwood"
 580         select CPU_FEROCEON
 581         select PCI
 582         select ARCH_REQUIRE_GPIOLIB
 583         select GENERIC_CLOCKEVENTS
 584         select NEED_MACH_IO_H
 585         select PLAT_ORION
 586         help
 587           Support for the following Marvell Kirkwood series SoCs:
 588           88F6180, 88F6192 and 88F6281.
 589
 590 config ARCH_LPC32XX
 591         bool "NXP LPC32XX"
 592         select CLKSRC_MMIO
 593         select CPU_ARM926T
 594         select ARCH_REQUIRE_GPIOLIB
 595         select HAVE_IDE
 596         select ARM_AMBA
 597         select USB_ARCH_HAS_OHCI
 598         select CLKDEV_LOOKUP
 599         select GENERIC_CLOCKEVENTS
 600         select USE_OF
 601         help
 602           Support for the NXP LPC32XX family of processors
 603
 604 config ARCH_MV78XX0
 605         bool "Marvell MV78xx0"
 606         select CPU_FEROCEON
 607         select PCI
 608         select ARCH_REQUIRE_GPIOLIB
 609         select GENERIC_CLOCKEVENTS
 610         select NEED_MACH_IO_H
 611         select PLAT_ORION
 612         help
 613           Support for the following Marvell MV78xx0 series SoCs:
 614           MV781x0, MV782x0.
 615
 616 config ARCH_ORION5X
 617         bool "Marvell Orion"
 618         depends on MMU
 619         select CPU_FEROCEON
 620         select PCI
 621         select ARCH_REQUIRE_GPIOLIB
 622         select GENERIC_CLOCKEVENTS
 623         select NEED_MACH_IO_H
 624         select PLAT_ORION
 625         help
 626           Support for the following Marvell Orion 5x series SoCs:
 627           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 628           Orion-2 (5281), Orion-1-90 (6183).
 629
 630 config ARCH_MMP
 631         bool "Marvell PXA168/910/MMP2"
 632         depends on MMU
 633         select ARCH_REQUIRE_GPIOLIB
 634         select CLKDEV_LOOKUP
 635         select GENERIC_CLOCKEVENTS
 636         select GPIO_PXA
 637         select IRQ_DOMAIN
 638         select PLAT_PXA
 639         select SPARSE_IRQ
 640         select GENERIC_ALLOCATOR
 641         help
 642           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 643
 644 config ARCH_KS8695
 645         bool "Micrel/Kendin KS8695"
 646         select CPU_ARM922T
 647         select ARCH_REQUIRE_GPIOLIB
 648         select ARCH_USES_GETTIMEOFFSET
 649         select NEED_MACH_MEMORY_H
 650         help
 651           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 652           System-on-Chip devices.
 653
 654 config ARCH_W90X900
 655         bool "Nuvoton W90X900 CPU"
 656         select CPU_ARM926T
 657         select ARCH_REQUIRE_GPIOLIB
 658         select CLKDEV_LOOKUP
 659         select CLKSRC_MMIO
 660         select GENERIC_CLOCKEVENTS
 661         help
 662           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 663           At present, the w90x900 has been renamed nuc900, regarding
 664           the ARM series product line, you can login the following
 665           link address to know more.
 666
 667           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 668                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 669
 670 config ARCH_TEGRA
 671         bool "NVIDIA Tegra"
 672         select CLKDEV_LOOKUP
 673         select CLKSRC_MMIO
 674         select GENERIC_CLOCKEVENTS
 675         select GENERIC_GPIO
 676         select HAVE_CLK
 677         select HAVE_SMP
 678         select MIGHT_HAVE_CACHE_L2X0
 679         select NEED_MACH_IO_H if PCI
 680         select ARCH_HAS_CPUFREQ
 681         help
 682           This enables support for NVIDIA Tegra based systems (Tegra APX,
 683           Tegra 6xx and Tegra 2 series).
 684
 685 config ARCH_PICOXCELL
 686         bool "Picochip picoXcell"
 687         select ARCH_REQUIRE_GPIOLIB
 688         select ARM_PATCH_PHYS_VIRT
 689         select ARM_VIC
 690         select CPU_V6K
 691         select DW_APB_TIMER
 692         select GENERIC_CLOCKEVENTS
 693         select GENERIC_GPIO
 694         select HAVE_TCM
 695         select NO_IOPORT
 696         select SPARSE_IRQ
 697         select USE_OF
 698         help
 699           This enables support for systems based on the Picochip picoXcell
 700           family of Femtocell devices.  The picoxcell support requires device tree
 701           for all boards.
 702
 703 config ARCH_PNX4008
 704         bool "Philips Nexperia PNX4008 Mobile"
 705         select CPU_ARM926T
 706         select CLKDEV_LOOKUP
 707         select ARCH_USES_GETTIMEOFFSET
 708         help
 709           This enables support for Philips PNX4008 mobile platform.
 710
 711 config ARCH_PXA
 712         bool "PXA2xx/PXA3xx-based"
 713         depends on MMU
 714         select ARCH_MTD_XIP
 715         select ARCH_HAS_CPUFREQ
 716         select CLKDEV_LOOKUP
 717         select CLKSRC_MMIO
 718         select ARCH_REQUIRE_GPIOLIB
 719         select GENERIC_CLOCKEVENTS
 720         select GPIO_PXA
 721         select PLAT_PXA
 722         select SPARSE_IRQ
 723         select AUTO_ZRELADDR
 724         select MULTI_IRQ_HANDLER
 725         select ARM_CPU_SUSPEND if PM
 726         select HAVE_IDE
 727         help
 728           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 729
 730 config ARCH_MSM
 731         bool "Qualcomm MSM"
 732         select HAVE_CLK
 733         select GENERIC_CLOCKEVENTS
 734         select ARCH_REQUIRE_GPIOLIB
 735         select CLKDEV_LOOKUP
 736         help
 737           Support for Qualcomm MSM/QSD based systems.  This runs on the
 738           apps processor of the MSM/QSD and depends on a shared memory
 739           interface to the modem processor which runs the baseband
 740           stack and controls some vital subsystems
 741           (clock and power control, etc).
 742
 743 config ARCH_SHMOBILE
 744         bool "Renesas SH-Mobile / R-Mobile"
 745         select HAVE_CLK
 746         select CLKDEV_LOOKUP
 747         select HAVE_MACH_CLKDEV
 748         select HAVE_SMP
 749         select GENERIC_CLOCKEVENTS
 750         select MIGHT_HAVE_CACHE_L2X0
 751         select NO_IOPORT
 752         select SPARSE_IRQ
 753         select MULTI_IRQ_HANDLER
 754         select PM_GENERIC_DOMAINS if PM
 755         select NEED_MACH_MEMORY_H
 756         help
 757           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 758
 759 config ARCH_RPC
 760         bool "RiscPC"
 761         select ARCH_ACORN
 762         select FIQ
 763         select ARCH_MAY_HAVE_PC_FDC
 764         select HAVE_PATA_PLATFORM
 765         select ISA_DMA_API
 766         select NO_IOPORT
 767         select ARCH_SPARSEMEM_ENABLE
 768         select ARCH_USES_GETTIMEOFFSET
 769         select HAVE_IDE
 770         select NEED_MACH_IO_H
 771         select NEED_MACH_MEMORY_H
 772         help
 773           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 774           CD-ROM interface, serial and parallel port, and the floppy drive.
 775
 776 config ARCH_SA1100
 777         bool "SA1100-based"
 778         select CLKSRC_MMIO
 779         select CPU_SA1100
 780         select ISA
 781         select ARCH_SPARSEMEM_ENABLE
 782         select ARCH_MTD_XIP
 783         select ARCH_HAS_CPUFREQ
 784         select CPU_FREQ
 785         select GENERIC_CLOCKEVENTS
 786         select CLKDEV_LOOKUP
 787         select ARCH_REQUIRE_GPIOLIB
 788         select HAVE_IDE
 789         select NEED_MACH_MEMORY_H
 790         select SPARSE_IRQ
 791         help
 792           Support for StrongARM 11x0 based boards.
 793
 794 config ARCH_S3C24XX
 795         bool "Samsung S3C24XX SoCs"
 796         select GENERIC_GPIO
 797         select ARCH_HAS_CPUFREQ
 798         select HAVE_CLK
 799         select CLKDEV_LOOKUP
 800         select ARCH_USES_GETTIMEOFFSET
 801         select HAVE_S3C2410_I2C if I2C
 802         select HAVE_S3C_RTC if RTC_CLASS
 803         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 804         select NEED_MACH_IO_H
 805         help
 806           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 807           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 808           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 809           Samsung SMDK2410 development board (and derivatives).
 810
 811 config ARCH_S3C64XX
 812         bool "Samsung S3C64XX"
 813         select PLAT_SAMSUNG
 814         select CPU_V6
 815         select ARM_VIC
 816         select HAVE_CLK
 817         select HAVE_TCM
 818         select CLKDEV_LOOKUP
 819         select NO_IOPORT
 820         select ARCH_USES_GETTIMEOFFSET
 821         select ARCH_HAS_CPUFREQ
 822         select ARCH_REQUIRE_GPIOLIB
 823         select SAMSUNG_CLKSRC
 824         select SAMSUNG_IRQ_VIC_TIMER
 825         select S3C_GPIO_TRACK
 826         select S3C_DEV_NAND
 827         select USB_ARCH_HAS_OHCI
 828         select SAMSUNG_GPIOLIB_4BIT
 829         select HAVE_S3C2410_I2C if I2C
 830         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 831         help
 832           Samsung S3C64XX series based systems
 833
 834 config ARCH_S5P64X0
 835         bool "Samsung S5P6440 S5P6450"
 836         select CPU_V6
 837         select GENERIC_GPIO
 838         select HAVE_CLK
 839         select CLKDEV_LOOKUP
 840         select CLKSRC_MMIO
 841         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 842         select GENERIC_CLOCKEVENTS
 843         select HAVE_S3C2410_I2C if I2C
 844         select HAVE_S3C_RTC if RTC_CLASS
 845         help
 846           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 847           SMDK6450.
 848
 849 config ARCH_S5PC100
 850         bool "Samsung S5PC100"
 851         select GENERIC_GPIO
 852         select HAVE_CLK
 853         select CLKDEV_LOOKUP
 854         select CPU_V7
 855         select ARCH_USES_GETTIMEOFFSET
 856         select HAVE_S3C2410_I2C if I2C
 857         select HAVE_S3C_RTC if RTC_CLASS
 858         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 859         help
 860           Samsung S5PC100 series based systems
 861
 862 config ARCH_S5PV210
 863         bool "Samsung S5PV210/S5PC110"
 864         select CPU_V7
 865         select ARCH_SPARSEMEM_ENABLE
 866         select ARCH_HAS_HOLES_MEMORYMODEL
 867         select GENERIC_GPIO
 868         select HAVE_CLK
 869         select CLKDEV_LOOKUP
 870         select CLKSRC_MMIO
 871         select ARCH_HAS_CPUFREQ
 872         select GENERIC_CLOCKEVENTS
 873         select HAVE_S3C2410_I2C if I2C
 874         select HAVE_S3C_RTC if RTC_CLASS
 875         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 876         select NEED_MACH_MEMORY_H
 877         help
 878           Samsung S5PV210/S5PC110 series based systems
 879
 880 config ARCH_EXYNOS
 881         bool "SAMSUNG EXYNOS"
 882         select CPU_V7
 883         select ARCH_SPARSEMEM_ENABLE
 884         select ARCH_HAS_HOLES_MEMORYMODEL
 885         select GENERIC_GPIO
 886         select HAVE_CLK
 887         select CLKDEV_LOOKUP
 888         select ARCH_HAS_CPUFREQ
 889         select GENERIC_CLOCKEVENTS
 890         select HAVE_S3C_RTC if RTC_CLASS
 891         select HAVE_S3C2410_I2C if I2C
 892         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 893         select NEED_MACH_MEMORY_H
 894         help
 895           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 896
 897 config ARCH_SHARK
 898         bool "Shark"
 899         select CPU_SA110
 900         select ISA
 901         select ISA_DMA
 902         select ZONE_DMA
 903         select PCI
 904         select ARCH_USES_GETTIMEOFFSET
 905         select NEED_MACH_MEMORY_H
 906         select NEED_MACH_IO_H
 907         help
 908           Support for the StrongARM based Digital DNARD machine, also known
 909           as "Shark" (<http://www.shark-linux.de/shark.html>).
 910
 911 config ARCH_U300
 912         bool "ST-Ericsson U300 Series"
 913         depends on MMU
 914         select CLKSRC_MMIO
 915         select CPU_ARM926T
 916         select HAVE_TCM
 917         select ARM_AMBA
 918         select ARM_PATCH_PHYS_VIRT
 919         select ARM_VIC
 920         select GENERIC_CLOCKEVENTS
 921         select CLKDEV_LOOKUP
 922         select HAVE_MACH_CLKDEV
 923         select GENERIC_GPIO
 924         select ARCH_REQUIRE_GPIOLIB
 925         help
 926           Support for ST-Ericsson U300 series mobile platforms.
 927
 928 config ARCH_U8500
 929         bool "ST-Ericsson U8500 Series"
 930         depends on MMU
 931         select CPU_V7
 932         select ARM_AMBA
 933         select GENERIC_CLOCKEVENTS
 934         select CLKDEV_LOOKUP
 935         select ARCH_REQUIRE_GPIOLIB
 936         select ARCH_HAS_CPUFREQ
 937         select HAVE_SMP
 938         select MIGHT_HAVE_CACHE_L2X0
 939         help
 940           Support for ST-Ericsson's Ux500 architecture
 941
 942 config ARCH_NOMADIK
 943         bool "STMicroelectronics Nomadik"
 944         select ARM_AMBA
 945         select ARM_VIC
 946         select CPU_ARM926T
 947         select CLKDEV_LOOKUP
 948         select GENERIC_CLOCKEVENTS
 949         select PINCTRL
 950         select MIGHT_HAVE_CACHE_L2X0
 951         select ARCH_REQUIRE_GPIOLIB
 952         help
 953           Support for the Nomadik platform by ST-Ericsson
 954
 955 config ARCH_DAVINCI
 956         bool "TI DaVinci"
 957         select GENERIC_CLOCKEVENTS
 958         select ARCH_REQUIRE_GPIOLIB
 959         select ZONE_DMA
 960         select HAVE_IDE
 961         select CLKDEV_LOOKUP
 962         select GENERIC_ALLOCATOR
 963         select GENERIC_IRQ_CHIP
 964         select ARCH_HAS_HOLES_MEMORYMODEL
 965         help
 966           Support for TI's DaVinci platform.
 967
 968 config ARCH_OMAP
 969         bool "TI OMAP"
 970         select HAVE_CLK
 971         select ARCH_REQUIRE_GPIOLIB
 972         select ARCH_HAS_CPUFREQ
 973         select CLKSRC_MMIO
 974         select GENERIC_CLOCKEVENTS
 975         select ARCH_HAS_HOLES_MEMORYMODEL
 976         help
 977           Support for TI's OMAP platform (OMAP1/2/3/4).
 978
 979 config PLAT_SPEAR
 980         bool "ST SPEAr"
 981         select ARM_AMBA
 982         select ARCH_REQUIRE_GPIOLIB
 983         select CLKDEV_LOOKUP
 984         select COMMON_CLK
 985         select CLKSRC_MMIO
 986         select GENERIC_CLOCKEVENTS
 987         select HAVE_CLK
 988         help
 989           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 990
 991 config ARCH_VT8500
 992         bool "VIA/WonderMedia 85xx"
 993         select CPU_ARM926T
 994         select GENERIC_GPIO
 995         select ARCH_HAS_CPUFREQ
 996         select GENERIC_CLOCKEVENTS
 997         select ARCH_REQUIRE_GPIOLIB
 998         select HAVE_PWM
 999         help
1000           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1001
1002 config ARCH_ZYNQ
1003         bool "Xilinx Zynq ARM Cortex A9 Platform"
1004         select CPU_V7
1005         select GENERIC_CLOCKEVENTS
1006         select CLKDEV_LOOKUP
1007         select ARM_GIC
1008         select ARM_AMBA
1009         select ICST
1010         select MIGHT_HAVE_CACHE_L2X0
1011         select USE_OF
1012         help
1013           Support for Xilinx Zynq ARM Cortex A9 Platform
1014 endchoice
1015
1016 #
1017 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1018 # Kconfigs may be included either alphabetically (according to the
1019 # plat- suffix) or along side the corresponding mach-* source.
1020 #
1021 source "arch/arm/mach-mvebu/Kconfig"
1022
1023 source "arch/arm/mach-at91/Kconfig"
1024
1025 source "arch/arm/mach-bcmring/Kconfig"
1026
1027 source "arch/arm/mach-clps711x/Kconfig"
1028
1029 source "arch/arm/mach-cns3xxx/Kconfig"
1030
1031 source "arch/arm/mach-davinci/Kconfig"
1032
1033 source "arch/arm/mach-dove/Kconfig"
1034
1035 source "arch/arm/mach-ep93xx/Kconfig"
1036
1037 source "arch/arm/mach-footbridge/Kconfig"
1038
1039 source "arch/arm/mach-gemini/Kconfig"
1040
1041 source "arch/arm/mach-h720x/Kconfig"
1042
1043 source "arch/arm/mach-integrator/Kconfig"
1044
1045 source "arch/arm/mach-iop32x/Kconfig"
1046
1047 source "arch/arm/mach-iop33x/Kconfig"
1048
1049 source "arch/arm/mach-iop13xx/Kconfig"
1050
1051 source "arch/arm/mach-ixp4xx/Kconfig"
1052
1053 source "arch/arm/mach-kirkwood/Kconfig"
1054
1055 source "arch/arm/mach-ks8695/Kconfig"
1056
1057 source "arch/arm/mach-lpc32xx/Kconfig"
1058
1059 source "arch/arm/mach-msm/Kconfig"
1060
1061 source "arch/arm/mach-mv78xx0/Kconfig"
1062
1063 source "arch/arm/plat-mxc/Kconfig"
1064
1065 source "arch/arm/mach-mxs/Kconfig"
1066
1067 source "arch/arm/mach-netx/Kconfig"
1068
1069 source "arch/arm/mach-nomadik/Kconfig"
1070 source "arch/arm/plat-nomadik/Kconfig"
1071
1072 source "arch/arm/plat-omap/Kconfig"
1073
1074 source "arch/arm/mach-omap1/Kconfig"
1075
1076 source "arch/arm/mach-omap2/Kconfig"
1077
1078 source "arch/arm/mach-orion5x/Kconfig"
1079
1080 source "arch/arm/mach-pxa/Kconfig"
1081 source "arch/arm/plat-pxa/Kconfig"
1082
1083 source "arch/arm/mach-mmp/Kconfig"
1084
1085 source "arch/arm/mach-realview/Kconfig"
1086
1087 source "arch/arm/mach-sa1100/Kconfig"
1088
1089 source "arch/arm/plat-samsung/Kconfig"
1090 source "arch/arm/plat-s3c24xx/Kconfig"
1091
1092 source "arch/arm/plat-spear/Kconfig"
1093
1094 source "arch/arm/mach-s3c24xx/Kconfig"
1095 if ARCH_S3C24XX
1096 source "arch/arm/mach-s3c2412/Kconfig"
1097 source "arch/arm/mach-s3c2440/Kconfig"
1098 endif
1099
1100 if ARCH_S3C64XX
1101 source "arch/arm/mach-s3c64xx/Kconfig"
1102 endif
1103
1104 source "arch/arm/mach-s5p64x0/Kconfig"
1105
1106 source "arch/arm/mach-s5pc100/Kconfig"
1107
1108 source "arch/arm/mach-s5pv210/Kconfig"
1109
1110 source "arch/arm/mach-exynos/Kconfig"
1111
1112 source "arch/arm/mach-shmobile/Kconfig"
1113
1114 source "arch/arm/mach-tegra/Kconfig"
1115
1116 source "arch/arm/mach-u300/Kconfig"
1117
1118 source "arch/arm/mach-ux500/Kconfig"
1119
1120 source "arch/arm/mach-versatile/Kconfig"
1121
1122 source "arch/arm/mach-vexpress/Kconfig"
1123 source "arch/arm/plat-versatile/Kconfig"
1124
1125 source "arch/arm/mach-vt8500/Kconfig"
1126
1127 source "arch/arm/mach-w90x900/Kconfig"
1128
1129 # Definitions to make life easier
1130 config ARCH_ACORN
1131         bool
1132
1133 config PLAT_IOP
1134         bool
1135         select GENERIC_CLOCKEVENTS
1136
1137 config PLAT_ORION
1138         bool
1139         select CLKSRC_MMIO
1140         select GENERIC_IRQ_CHIP
1141         select COMMON_CLK
1142
1143 config PLAT_PXA
1144         bool
1145
1146 config PLAT_VERSATILE
1147         bool
1148
1149 config ARM_TIMER_SP804
1150         bool
1151         select CLKSRC_MMIO
1152         select HAVE_SCHED_CLOCK
1153
1154 source arch/arm/mm/Kconfig
1155
1156 config ARM_NR_BANKS
1157         int
1158         default 16 if ARCH_EP93XX
1159         default 8
1160
1161 config IWMMXT
1162         bool "Enable iWMMXt support"
1163         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1164         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1165         help
1166           Enable support for iWMMXt context switching at run time if
1167           running on a CPU that supports it.
1168
1169 config XSCALE_PMU
1170         bool
1171         depends on CPU_XSCALE
1172         default y
1173
1174 config CPU_HAS_PMU
1175         depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1176                    (!ARCH_OMAP3 || OMAP3_EMU)
1177         default y
1178         bool
1179
1180 config MULTI_IRQ_HANDLER
1181         bool
1182         help
1183           Allow each machine to specify it's own IRQ handler at run time.
1184
1185 if !MMU
1186 source "arch/arm/Kconfig-nommu"
1187 endif
1188
1189 config ARM_ERRATA_326103
1190         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1191         depends on CPU_V6
1192         help
1193           Executing a SWP instruction to read-only memory does not set bit 11
1194           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1195           treat the access as a read, preventing a COW from occurring and
1196           causing the faulting task to livelock.
1197
1198 config ARM_ERRATA_411920
1199         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1200         depends on CPU_V6 || CPU_V6K
1201         help
1202           Invalidation of the Instruction Cache operation can
1203           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1204           It does not affect the MPCore. This option enables the ARM Ltd.
1205           recommended workaround.
1206
1207 config ARM_ERRATA_430973
1208         bool "ARM errata: Stale prediction on replaced interworking branch"
1209         depends on CPU_V7
1210         help
1211           This option enables the workaround for the 430973 Cortex-A8
1212           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1213           interworking branch is replaced with another code sequence at the
1214           same virtual address, whether due to self-modifying code or virtual
1215           to physical address re-mapping, Cortex-A8 does not recover from the
1216           stale interworking branch prediction. This results in Cortex-A8
1217           executing the new code sequence in the incorrect ARM or Thumb state.
1218           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1219           and also flushes the branch target cache at every context switch.
1220           Note that setting specific bits in the ACTLR register may not be
1221           available in non-secure mode.
1222
1223 config ARM_ERRATA_458693
1224         bool "ARM errata: Processor deadlock when a false hazard is created"
1225         depends on CPU_V7
1226         help
1227           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1228           erratum. For very specific sequences of memory operations, it is
1229           possible for a hazard condition intended for a cache line to instead
1230           be incorrectly associated with a different cache line. This false
1231           hazard might then cause a processor deadlock. The workaround enables
1232           the L1 caching of the NEON accesses and disables the PLD instruction
1233           in the ACTLR register. Note that setting specific bits in the ACTLR
1234           register may not be available in non-secure mode.
1235
1236 config ARM_ERRATA_460075
1237         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1238         depends on CPU_V7
1239         help
1240           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1241           erratum. Any asynchronous access to the L2 cache may encounter a
1242           situation in which recent store transactions to the L2 cache are lost
1243           and overwritten with stale memory contents from external memory. The
1244           workaround disables the write-allocate mode for the L2 cache via the
1245           ACTLR register. Note that setting specific bits in the ACTLR register
1246           may not be available in non-secure mode.
1247
1248 config ARM_ERRATA_742230
1249         bool "ARM errata: DMB operation may be faulty"
1250         depends on CPU_V7 && SMP
1251         help
1252           This option enables the workaround for the 742230 Cortex-A9
1253           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1254           between two write operations may not ensure the correct visibility
1255           ordering of the two writes. This workaround sets a specific bit in
1256           the diagnostic register of the Cortex-A9 which causes the DMB
1257           instruction to behave as a DSB, ensuring the correct behaviour of
1258           the two writes.
1259
1260 config ARM_ERRATA_742231
1261         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1262         depends on CPU_V7 && SMP
1263         help
1264           This option enables the workaround for the 742231 Cortex-A9
1265           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1266           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1267           accessing some data located in the same cache line, may get corrupted
1268           data due to bad handling of the address hazard when the line gets
1269           replaced from one of the CPUs at the same time as another CPU is
1270           accessing it. This workaround sets specific bits in the diagnostic
1271           register of the Cortex-A9 which reduces the linefill issuing
1272           capabilities of the processor.
1273
1274 config PL310_ERRATA_588369
1275         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1276         depends on CACHE_L2X0
1277         help
1278            The PL310 L2 cache controller implements three types of Clean &
1279            Invalidate maintenance operations: by Physical Address
1280            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1281            They are architecturally defined to behave as the execution of a
1282            clean operation followed immediately by an invalidate operation,
1283            both performing to the same memory location. This functionality
1284            is not correctly implemented in PL310 as clean lines are not
1285            invalidated as a result of these operations.
1286
1287 config ARM_ERRATA_720789
1288         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1289         depends on CPU_V7
1290         help
1291           This option enables the workaround for the 720789 Cortex-A9 (prior to
1292           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1293           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1294           As a consequence of this erratum, some TLB entries which should be
1295           invalidated are not, resulting in an incoherency in the system page
1296           tables. The workaround changes the TLB flushing routines to invalidate
1297           entries regardless of the ASID.
1298
1299 config PL310_ERRATA_727915
1300         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1301         depends on CACHE_L2X0
1302         help
1303           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1304           operation (offset 0x7FC). This operation runs in background so that
1305           PL310 can handle normal accesses while it is in progress. Under very
1306           rare circumstances, due to this erratum, write data can be lost when
1307           PL310 treats a cacheable write transaction during a Clean &
1308           Invalidate by Way operation.
1309
1310 config ARM_ERRATA_743622
1311         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1312         depends on CPU_V7
1313         help
1314           This option enables the workaround for the 743622 Cortex-A9
1315           (r2p*) erratum. Under very rare conditions, a faulty
1316           optimisation in the Cortex-A9 Store Buffer may lead to data
1317           corruption. This workaround sets a specific bit in the diagnostic
1318           register of the Cortex-A9 which disables the Store Buffer
1319           optimisation, preventing the defect from occurring. This has no
1320           visible impact on the overall performance or power consumption of the
1321           processor.
1322
1323 config ARM_ERRATA_751472
1324         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1325         depends on CPU_V7
1326         help
1327           This option enables the workaround for the 751472 Cortex-A9 (prior
1328           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1329           completion of a following broadcasted operation if the second
1330           operation is received by a CPU before the ICIALLUIS has completed,
1331           potentially leading to corrupted entries in the cache or TLB.
1332
1333 config PL310_ERRATA_753970
1334         bool "PL310 errata: cache sync operation may be faulty"
1335         depends on CACHE_PL310
1336         help
1337           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1338
1339           Under some condition the effect of cache sync operation on
1340           the store buffer still remains when the operation completes.
1341           This means that the store buffer is always asked to drain and
1342           this prevents it from merging any further writes. The workaround
1343           is to replace the normal offset of cache sync operation (0x730)
1344           by another offset targeting an unmapped PL310 register 0x740.
1345           This has the same effect as the cache sync operation: store buffer
1346           drain and waiting for all buffers empty.
1347
1348 config ARM_ERRATA_754322
1349         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1350         depends on CPU_V7
1351         help
1352           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1353           r3p*) erratum. A speculative memory access may cause a page table walk
1354           which starts prior to an ASID switch but completes afterwards. This
1355           can populate the micro-TLB with a stale entry which may be hit with
1356           the new ASID. This workaround places two dsb instructions in the mm
1357           switching code so that no page table walks can cross the ASID switch.
1358
1359 config ARM_ERRATA_754327
1360         bool "ARM errata: no automatic Store Buffer drain"
1361         depends on CPU_V7 && SMP
1362         help
1363           This option enables the workaround for the 754327 Cortex-A9 (prior to
1364           r2p0) erratum. The Store Buffer does not have any automatic draining
1365           mechanism and therefore a livelock may occur if an external agent
1366           continuously polls a memory location waiting to observe an update.
1367           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1368           written polling loops from denying visibility of updates to memory.
1369
1370 config ARM_ERRATA_364296
1371         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1372         depends on CPU_V6 && !SMP
1373         help
1374           This options enables the workaround for the 364296 ARM1136
1375           r0p2 erratum (possible cache data corruption with
1376           hit-under-miss enabled). It sets the undocumented bit 31 in
1377           the auxiliary control register and the FI bit in the control
1378           register, thus disabling hit-under-miss without putting the
1379           processor into full low interrupt latency mode. ARM11MPCore
1380           is not affected.
1381
1382 config ARM_ERRATA_764369
1383         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1384         depends on CPU_V7 && SMP
1385         help
1386           This option enables the workaround for erratum 764369
1387           affecting Cortex-A9 MPCore with two or more processors (all
1388           current revisions). Under certain timing circumstances, a data
1389           cache line maintenance operation by MVA targeting an Inner
1390           Shareable memory region may fail to proceed up to either the
1391           Point of Coherency or to the Point of Unification of the
1392           system. This workaround adds a DSB instruction before the
1393           relevant cache maintenance functions and sets a specific bit
1394           in the diagnostic control register of the SCU.
1395
1396 config PL310_ERRATA_769419
1397         bool "PL310 errata: no automatic Store Buffer drain"
1398         depends on CACHE_L2X0
1399         help
1400           On revisions of the PL310 prior to r3p2, the Store Buffer does
1401           not automatically drain. This can cause normal, non-cacheable
1402           writes to be retained when the memory system is idle, leading
1403           to suboptimal I/O performance for drivers using coherent DMA.
1404           This option adds a write barrier to the cpu_idle loop so that,
1405           on systems with an outer cache, the store buffer is drained
1406           explicitly.
1407
1408 endmenu
1409
1410 source "arch/arm/common/Kconfig"
1411
1412 menu "Bus support"
1413
1414 config ARM_AMBA
1415         bool
1416
1417 config ISA
1418         bool
1419         help
1420           Find out whether you have ISA slots on your motherboard.  ISA is the
1421           name of a bus system, i.e. the way the CPU talks to the other stuff
1422           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1423           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1424           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1425
1426 # Select ISA DMA controller support
1427 config ISA_DMA
1428         bool
1429         select ISA_DMA_API
1430
1431 # Select ISA DMA interface
1432 config ISA_DMA_API
1433         bool
1434
1435 config PCI
1436         bool "PCI support" if MIGHT_HAVE_PCI
1437         help
1438           Find out whether you have a PCI motherboard. PCI is the name of a
1439           bus system, i.e. the way the CPU talks to the other stuff inside
1440           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1441           VESA. If you have PCI, say Y, otherwise N.
1442
1443 config PCI_DOMAINS
1444         bool
1445         depends on PCI
1446
1447 config PCI_NANOENGINE
1448         bool "BSE nanoEngine PCI support"
1449         depends on SA1100_NANOENGINE
1450         help
1451           Enable PCI on the BSE nanoEngine board.
1452
1453 config PCI_SYSCALL
1454         def_bool PCI
1455
1456 # Select the host bridge type
1457 config PCI_HOST_VIA82C505
1458         bool
1459         depends on PCI && ARCH_SHARK
1460         default y
1461
1462 config PCI_HOST_ITE8152
1463         bool
1464         depends on PCI && MACH_ARMCORE
1465         default y
1466         select DMABOUNCE
1467
1468 source "drivers/pci/Kconfig"
1469
1470 source "drivers/pcmcia/Kconfig"
1471
1472 endmenu
1473
1474 menu "Kernel Features"
1475
1476 config HAVE_SMP
1477         bool
1478         help
1479           This option should be selected by machines which have an SMP-
1480           capable CPU.
1481
1482           The only effect of this option is to make the SMP-related
1483           options available to the user for configuration.
1484
1485 config SMP
1486         bool "Symmetric Multi-Processing"
1487         depends on CPU_V6K || CPU_V7
1488         depends on GENERIC_CLOCKEVENTS
1489         depends on HAVE_SMP
1490         depends on MMU
1491         select USE_GENERIC_SMP_HELPERS
1492         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1493         help
1494           This enables support for systems with more than one CPU. If you have
1495           a system with only one CPU, like most personal computers, say N. If
1496           you have a system with more than one CPU, say Y.
1497
1498           If you say N here, the kernel will run on single and multiprocessor
1499           machines, but will use only one CPU of a multiprocessor machine. If
1500           you say Y here, the kernel will run on many, but not all, single
1501           processor machines. On a single processor machine, the kernel will
1502           run faster if you say N here.
1503
1504           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1505           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1506           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1507
1508           If you don't know what to do here, say N.
1509
1510 config SMP_ON_UP
1511         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1512         depends on EXPERIMENTAL
1513         depends on SMP && !XIP_KERNEL
1514         default y
1515         help
1516           SMP kernels contain instructions which fail on non-SMP processors.
1517           Enabling this option allows the kernel to modify itself to make
1518           these instructions safe.  Disabling it allows about 1K of space
1519           savings.
1520
1521           If you don't know what to do here, say Y.
1522
1523 config ARM_CPU_TOPOLOGY
1524         bool "Support cpu topology definition"
1525         depends on SMP && CPU_V7
1526         default y
1527         help
1528           Support ARM cpu topology definition. The MPIDR register defines
1529           affinity between processors which is then used to describe the cpu
1530           topology of an ARM System.
1531
1532 config SCHED_MC
1533         bool "Multi-core scheduler support"
1534         depends on ARM_CPU_TOPOLOGY
1535         help
1536           Multi-core scheduler support improves the CPU scheduler's decision
1537           making when dealing with multi-core CPU chips at a cost of slightly
1538           increased overhead in some places. If unsure say N here.
1539
1540 config SCHED_SMT
1541         bool "SMT scheduler support"
1542         depends on ARM_CPU_TOPOLOGY
1543         help
1544           Improves the CPU scheduler's decision making when dealing with
1545           MultiThreading at a cost of slightly increased overhead in some
1546           places. If unsure say N here.
1547
1548 config HAVE_ARM_SCU
1549         bool
1550         help
1551           This option enables support for the ARM system coherency unit
1552
1553 config ARM_ARCH_TIMER
1554         bool "Architected timer support"
1555         depends on CPU_V7
1556         help
1557           This option enables support for the ARM architected timer
1558
1559 config HAVE_ARM_TWD
1560         bool
1561         depends on SMP
1562         help
1563           This options enables support for the ARM timer and watchdog unit
1564
1565 choice
1566         prompt "Memory split"
1567         default VMSPLIT_3G
1568         help
1569           Select the desired split between kernel and user memory.
1570
1571           If you are not absolutely sure what you are doing, leave this
1572           option alone!
1573
1574         config VMSPLIT_3G
1575                 bool "3G/1G user/kernel split"
1576         config VMSPLIT_2G
1577                 bool "2G/2G user/kernel split"
1578         config VMSPLIT_1G
1579                 bool "1G/3G user/kernel split"
1580 endchoice
1581
1582 config PAGE_OFFSET
1583         hex
1584         default 0x40000000 if VMSPLIT_1G
1585         default 0x80000000 if VMSPLIT_2G
1586         default 0xC0000000
1587
1588 config NR_CPUS
1589         int "Maximum number of CPUs (2-32)"
1590         range 2 32
1591         depends on SMP
1592         default "4"
1593
1594 config HOTPLUG_CPU
1595         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1596         depends on SMP && HOTPLUG && EXPERIMENTAL
1597         help
1598           Say Y here to experiment with turning CPUs off and on.  CPUs
1599           can be controlled through /sys/devices/system/cpu.
1600
1601 config LOCAL_TIMERS
1602         bool "Use local timer interrupts"
1603         depends on SMP
1604         default y
1605         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1606         help
1607           Enable support for local timers on SMP platforms, rather then the
1608           legacy IPI broadcast method.  Local timers allows the system
1609           accounting to be spread across the timer interval, preventing a
1610           "thundering herd" at every timer tick.
1611
1612 config ARCH_NR_GPIO
1613         int
1614         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1615         default 355 if ARCH_U8500
1616         default 264 if MACH_H4700
1617         default 512 if SOC_OMAP5
1618         default 0
1619         help
1620           Maximum number of GPIOs in the system.
1621
1622           If unsure, leave the default value.
1623
1624 source kernel/Kconfig.preempt
1625
1626 config HZ
1627         int
1628         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1629                 ARCH_S5PV210 || ARCH_EXYNOS4
1630         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1631         default AT91_TIMER_HZ if ARCH_AT91
1632         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1633         default 100
1634
1635 config THUMB2_KERNEL
1636         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1637         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1638         select AEABI
1639         select ARM_ASM_UNIFIED
1640         select ARM_UNWIND
1641         help
1642           By enabling this option, the kernel will be compiled in
1643           Thumb-2 mode. A compiler/assembler that understand the unified
1644           ARM-Thumb syntax is needed.
1645
1646           If unsure, say N.
1647
1648 config THUMB2_AVOID_R_ARM_THM_JUMP11
1649         bool "Work around buggy Thumb-2 short branch relocations in gas"
1650         depends on THUMB2_KERNEL && MODULES
1651         default y
1652         help
1653           Various binutils versions can resolve Thumb-2 branches to
1654           locally-defined, preemptible global symbols as short-range "b.n"
1655           branch instructions.
1656
1657           This is a problem, because there's no guarantee the final
1658           destination of the symbol, or any candidate locations for a
1659           trampoline, are within range of the branch.  For this reason, the
1660           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1661           relocation in modules at all, and it makes little sense to add
1662           support.
1663
1664           The symptom is that the kernel fails with an "unsupported
1665           relocation" error when loading some modules.
1666
1667           Until fixed tools are available, passing
1668           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1669           code which hits this problem, at the cost of a bit of extra runtime
1670           stack usage in some cases.
1671
1672           The problem is described in more detail at:
1673               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1674
1675           Only Thumb-2 kernels are affected.
1676
1677           Unless you are sure your tools don't have this problem, say Y.
1678
1679 config ARM_ASM_UNIFIED
1680         bool
1681
1682 config AEABI
1683         bool "Use the ARM EABI to compile the kernel"
1684         help
1685           This option allows for the kernel to be compiled using the latest
1686           ARM ABI (aka EABI).  This is only useful if you are using a user
1687           space environment that is also compiled with EABI.
1688
1689           Since there are major incompatibilities between the legacy ABI and
1690           EABI, especially with regard to structure member alignment, this
1691           option also changes the kernel syscall calling convention to
1692           disambiguate both ABIs and allow for backward compatibility support
1693           (selected with CONFIG_OABI_COMPAT).
1694
1695           To use this you need GCC version 4.0.0 or later.
1696
1697 config OABI_COMPAT
1698         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1699         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1700         default y
1701         help
1702           This option preserves the old syscall interface along with the
1703           new (ARM EABI) one. It also provides a compatibility layer to
1704           intercept syscalls that have structure arguments which layout
1705           in memory differs between the legacy ABI and the new ARM EABI
1706           (only for non "thumb" binaries). This option adds a tiny
1707           overhead to all syscalls and produces a slightly larger kernel.
1708           If you know you'll be using only pure EABI user space then you
1709           can say N here. If this option is not selected and you attempt
1710           to execute a legacy ABI binary then the result will be
1711           UNPREDICTABLE (in fact it can be predicted that it won't work
1712           at all). If in doubt say Y.
1713
1714 config ARCH_HAS_HOLES_MEMORYMODEL
1715         bool
1716
1717 config ARCH_SPARSEMEM_ENABLE
1718         bool
1719
1720 config ARCH_SPARSEMEM_DEFAULT
1721         def_bool ARCH_SPARSEMEM_ENABLE
1722
1723 config ARCH_SELECT_MEMORY_MODEL
1724         def_bool ARCH_SPARSEMEM_ENABLE
1725
1726 config HAVE_ARCH_PFN_VALID
1727         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1728
1729 config HIGHMEM
1730         bool "High Memory Support"
1731         depends on MMU
1732         help
1733           The address space of ARM processors is only 4 Gigabytes large
1734           and it has to accommodate user address space, kernel address
1735           space as well as some memory mapped IO. That means that, if you
1736           have a large amount of physical memory and/or IO, not all of the
1737           memory can be "permanently mapped" by the kernel. The physical
1738           memory that is not permanently mapped is called "high memory".
1739
1740           Depending on the selected kernel/user memory split, minimum
1741           vmalloc space and actual amount of RAM, you may not need this
1742           option which should result in a slightly faster kernel.
1743
1744           If unsure, say n.
1745
1746 config HIGHPTE
1747         bool "Allocate 2nd-level pagetables from highmem"
1748         depends on HIGHMEM
1749
1750 config HW_PERF_EVENTS
1751         bool "Enable hardware performance counter support for perf events"
1752         depends on PERF_EVENTS && CPU_HAS_PMU
1753         default y
1754         help
1755           Enable hardware performance counter support for perf events. If
1756           disabled, perf events will use software events only.
1757
1758 source "mm/Kconfig"
1759
1760 config FORCE_MAX_ZONEORDER
1761         int "Maximum zone order" if ARCH_SHMOBILE
1762         range 11 64 if ARCH_SHMOBILE
1763         default "9" if SA1111
1764         default "11"
1765         help
1766           The kernel memory allocator divides physically contiguous memory
1767           blocks into "zones", where each zone is a power of two number of
1768           pages.  This option selects the largest power of two that the kernel
1769           keeps in the memory allocator.  If you need to allocate very large
1770           blocks of physically contiguous memory, then you may need to
1771           increase this value.
1772
1773           This config option is actually maximum order plus one. For example,
1774           a value of 11 means that the largest free memory block is 2^10 pages.
1775
1776 config LEDS
1777         bool "Timer and CPU usage LEDs"
1778         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1779                    ARCH_EBSA285 || ARCH_INTEGRATOR || \
1780                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1781                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1782                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1783                    ARCH_AT91 || ARCH_DAVINCI || \
1784                    ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1785         help
1786           If you say Y here, the LEDs on your machine will be used
1787           to provide useful information about your current system status.
1788
1789           If you are compiling a kernel for a NetWinder or EBSA-285, you will
1790           be able to select which LEDs are active using the options below. If
1791           you are compiling a kernel for the EBSA-110 or the LART however, the
1792           red LED will simply flash regularly to indicate that the system is
1793           still functional. It is safe to say Y here if you have a CATS
1794           system, but the driver will do nothing.
1795
1796 config LEDS_TIMER
1797         bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1798                             OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1799                             || MACH_OMAP_PERSEUS2
1800         depends on LEDS
1801         depends on !GENERIC_CLOCKEVENTS
1802         default y if ARCH_EBSA110
1803         help
1804           If you say Y here, one of the system LEDs (the green one on the
1805           NetWinder, the amber one on the EBSA285, or the red one on the LART)
1806           will flash regularly to indicate that the system is still
1807           operational. This is mainly useful to kernel hackers who are
1808           debugging unstable kernels.
1809
1810           The LART uses the same LED for both Timer LED and CPU usage LED
1811           functions. You may choose to use both, but the Timer LED function
1812           will overrule the CPU usage LED.
1813
1814 config LEDS_CPU
1815         bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1816                         !ARCH_OMAP) \
1817                         || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1818                         || MACH_OMAP_PERSEUS2
1819         depends on LEDS
1820         help
1821           If you say Y here, the red LED will be used to give a good real
1822           time indication of CPU usage, by lighting whenever the idle task
1823           is not currently executing.
1824
1825           The LART uses the same LED for both Timer LED and CPU usage LED
1826           functions. You may choose to use both, but the Timer LED function
1827           will overrule the CPU usage LED.
1828
1829 config ALIGNMENT_TRAP
1830         bool
1831         depends on CPU_CP15_MMU
1832         default y if !ARCH_EBSA110
1833         select HAVE_PROC_CPU if PROC_FS
1834         help
1835           ARM processors cannot fetch/store information which is not
1836           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1837           address divisible by 4. On 32-bit ARM processors, these non-aligned
1838           fetch/store instructions will be emulated in software if you say
1839           here, which has a severe performance impact. This is necessary for
1840           correct operation of some network protocols. With an IP-only
1841           configuration it is safe to say N, otherwise say Y.
1842
1843 config UACCESS_WITH_MEMCPY
1844         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1845         depends on MMU && EXPERIMENTAL
1846         default y if CPU_FEROCEON
1847         help
1848           Implement faster copy_to_user and clear_user methods for CPU
1849           cores where a 8-word STM instruction give significantly higher
1850           memory write throughput than a sequence of individual 32bit stores.
1851
1852           A possible side effect is a slight increase in scheduling latency
1853           between threads sharing the same address space if they invoke
1854           such copy operations with large buffers.
1855
1856           However, if the CPU data cache is using a write-allocate mode,
1857           this option is unlikely to provide any performance gain.
1858
1859 config SECCOMP
1860         bool
1861         prompt "Enable seccomp to safely compute untrusted bytecode"
1862         ---help---
1863           This kernel feature is useful for number crunching applications
1864           that may need to compute untrusted bytecode during their
1865           execution. By using pipes or other transports made available to
1866           the process as file descriptors supporting the read/write
1867           syscalls, it's possible to isolate those applications in
1868           their own address space using seccomp. Once seccomp is
1869           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1870           and the task is only allowed to execute a few safe syscalls
1871           defined by each seccomp mode.
1872
1873 config CC_STACKPROTECTOR
1874         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1875         depends on EXPERIMENTAL
1876         help
1877           This option turns on the -fstack-protector GCC feature. This
1878           feature puts, at the beginning of functions, a canary value on
1879           the stack just before the return address, and validates
1880           the value just before actually returning.  Stack based buffer
1881           overflows (that need to overwrite this return address) now also
1882           overwrite the canary, which gets detected and the attack is then
1883           neutralized via a kernel panic.
1884           This feature requires gcc version 4.2 or above.
1885
1886 config DEPRECATED_PARAM_STRUCT
1887         bool "Provide old way to pass kernel parameters"
1888         help
1889           This was deprecated in 2001 and announced to live on for 5 years.
1890           Some old boot loaders still use this way.
1891
1892 endmenu
1893
1894 menu "Boot options"
1895
1896 config USE_OF
1897         bool "Flattened Device Tree support"
1898         select OF
1899         select OF_EARLY_FLATTREE
1900         select IRQ_DOMAIN
1901         help
1902           Include support for flattened device tree machine descriptions.
1903
1904 # Compressed boot loader in ROM.  Yes, we really want to ask about
1905 # TEXT and BSS so we preserve their values in the config files.
1906 config ZBOOT_ROM_TEXT
1907         hex "Compressed ROM boot loader base address"
1908         default "0"
1909         help
1910           The physical address at which the ROM-able zImage is to be
1911           placed in the target.  Platforms which normally make use of
1912           ROM-able zImage formats normally set this to a suitable
1913           value in their defconfig file.
1914
1915           If ZBOOT_ROM is not enabled, this has no effect.
1916
1917 config ZBOOT_ROM_BSS
1918         hex "Compressed ROM boot loader BSS address"
1919         default "0"
1920         help
1921           The base address of an area of read/write memory in the target
1922           for the ROM-able zImage which must be available while the
1923           decompressor is running. It must be large enough to hold the
1924           entire decompressed kernel plus an additional 128 KiB.
1925           Platforms which normally make use of ROM-able zImage formats
1926           normally set this to a suitable value in their defconfig file.
1927
1928           If ZBOOT_ROM is not enabled, this has no effect.
1929
1930 config ZBOOT_ROM
1931         bool "Compressed boot loader in ROM/flash"
1932         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1933         help
1934           Say Y here if you intend to execute your compressed kernel image
1935           (zImage) directly from ROM or flash.  If unsure, say N.
1936
1937 choice
1938         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1939         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1940         default ZBOOT_ROM_NONE
1941         help
1942           Include experimental SD/MMC loading code in the ROM-able zImage.
1943           With this enabled it is possible to write the ROM-able zImage
1944           kernel image to an MMC or SD card and boot the kernel straight
1945           from the reset vector. At reset the processor Mask ROM will load
1946           the first part of the ROM-able zImage which in turn loads the
1947           rest the kernel image to RAM.
1948
1949 config ZBOOT_ROM_NONE
1950         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1951         help
1952           Do not load image from SD or MMC
1953
1954 config ZBOOT_ROM_MMCIF
1955         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1956         help
1957           Load image from MMCIF hardware block.
1958
1959 config ZBOOT_ROM_SH_MOBILE_SDHI
1960         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1961         help
1962           Load image from SDHI hardware block
1963
1964 endchoice
1965
1966 config ARM_APPENDED_DTB
1967         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1968         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1969         help
1970           With this option, the boot code will look for a device tree binary
1971           (DTB) appended to zImage
1972           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1973
1974           This is meant as a backward compatibility convenience for those
1975           systems with a bootloader that can't be upgraded to accommodate
1976           the documented boot protocol using a device tree.
1977
1978           Beware that there is very little in terms of protection against
1979           this option being confused by leftover garbage in memory that might
1980           look like a DTB header after a reboot if no actual DTB is appended
1981           to zImage.  Do not leave this option active in a production kernel
1982           if you don't intend to always append a DTB.  Proper passing of the
1983           location into r2 of a bootloader provided DTB is always preferable
1984           to this option.
1985
1986 config ARM_ATAG_DTB_COMPAT
1987         bool "Supplement the appended DTB with traditional ATAG information"
1988         depends on ARM_APPENDED_DTB
1989         help
1990           Some old bootloaders can't be updated to a DTB capable one, yet
1991           they provide ATAGs with memory configuration, the ramdisk address,
1992           the kernel cmdline string, etc.  Such information is dynamically
1993           provided by the bootloader and can't always be stored in a static
1994           DTB.  To allow a device tree enabled kernel to be used with such
1995           bootloaders, this option allows zImage to extract the information
1996           from the ATAG list and store it at run time into the appended DTB.
1997
1998 config CMDLINE
1999         string "Default kernel command string"
2000         default ""
2001         help
2002           On some architectures (EBSA110 and CATS), there is currently no way
2003           for the boot loader to pass arguments to the kernel. For these
2004           architectures, you should supply some command-line options at build
2005           time by entering them here. As a minimum, you should specify the
2006           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2007
2008 choice
2009         prompt "Kernel command line type" if CMDLINE != ""
2010         default CMDLINE_FROM_BOOTLOADER
2011
2012 config CMDLINE_FROM_BOOTLOADER
2013         bool "Use bootloader kernel arguments if available"
2014         help
2015           Uses the command-line options passed by the boot loader. If
2016           the boot loader doesn't provide any, the default kernel command
2017           string provided in CMDLINE will be used.
2018
2019 config CMDLINE_EXTEND
2020         bool "Extend bootloader kernel arguments"
2021         help
2022           The command-line arguments provided by the boot loader will be
2023           appended to the default kernel command string.
2024
2025 config CMDLINE_FORCE
2026         bool "Always use the default kernel command string"
2027         help
2028           Always use the default kernel command string, even if the boot
2029           loader passes other arguments to the kernel.
2030           This is useful if you cannot or don't want to change the
2031           command-line options your boot loader passes to the kernel.
2032 endchoice
2033
2034 config XIP_KERNEL
2035         bool "Kernel Execute-In-Place from ROM"
2036         depends on !ZBOOT_ROM && !ARM_LPAE
2037         help
2038           Execute-In-Place allows the kernel to run from non-volatile storage
2039           directly addressable by the CPU, such as NOR flash. This saves RAM
2040           space since the text section of the kernel is not loaded from flash
2041           to RAM.  Read-write sections, such as the data section and stack,
2042           are still copied to RAM.  The XIP kernel is not compressed since
2043           it has to run directly from flash, so it will take more space to
2044           store it.  The flash address used to link the kernel object files,
2045           and for storing it, is configuration dependent. Therefore, if you
2046           say Y here, you must know the proper physical address where to
2047           store the kernel image depending on your own flash memory usage.
2048
2049           Also note that the make target becomes "make xipImage" rather than
2050           "make zImage" or "make Image".  The final kernel binary to put in
2051           ROM memory will be arch/arm/boot/xipImage.
2052
2053           If unsure, say N.
2054
2055 config XIP_PHYS_ADDR
2056         hex "XIP Kernel Physical Location"
2057         depends on XIP_KERNEL
2058         default "0x00080000"
2059         help
2060           This is the physical address in your flash memory the kernel will
2061           be linked for and stored to.  This address is dependent on your
2062           own flash usage.
2063
2064 config KEXEC
2065         bool "Kexec system call (EXPERIMENTAL)"
2066         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2067         help
2068           kexec is a system call that implements the ability to shutdown your
2069           current kernel, and to start another kernel.  It is like a reboot
2070           but it is independent of the system firmware.   And like a reboot
2071           you can start any kernel with it, not just Linux.
2072
2073           It is an ongoing process to be certain the hardware in a machine
2074           is properly shutdown, so do not be surprised if this code does not
2075           initially work for you.  It may help to enable device hotplugging
2076           support.
2077
2078 config ATAGS_PROC
2079         bool "Export atags in procfs"
2080         depends on KEXEC
2081         default y
2082         help
2083           Should the atags used to boot the kernel be exported in an "atags"
2084           file in procfs. Useful with kexec.
2085
2086 config CRASH_DUMP
2087         bool "Build kdump crash kernel (EXPERIMENTAL)"
2088         depends on EXPERIMENTAL
2089         help
2090           Generate crash dump after being started by kexec. This should
2091           be normally only set in special crash dump kernels which are
2092           loaded in the main kernel with kexec-tools into a specially
2093           reserved region and then later executed after a crash by
2094           kdump/kexec. The crash dump kernel must be compiled to a
2095           memory address not used by the main kernel
2096
2097           For more details see Documentation/kdump/kdump.txt
2098
2099 config AUTO_ZRELADDR
2100         bool "Auto calculation of the decompressed kernel image address"
2101         depends on !ZBOOT_ROM && !ARCH_U300
2102         help
2103           ZRELADDR is the physical address where the decompressed kernel
2104           image will be placed. If AUTO_ZRELADDR is selected, the address
2105           will be determined at run-time by masking the current IP with
2106           0xf8000000. This assumes the zImage being placed in the first 128MB
2107           from start of memory.
2108
2109 endmenu
2110
2111 menu "CPU Power Management"
2112
2113 if ARCH_HAS_CPUFREQ
2114
2115 source "drivers/cpufreq/Kconfig"
2116
2117 config CPU_FREQ_IMX
2118         tristate "CPUfreq driver for i.MX CPUs"
2119         depends on ARCH_MXC && CPU_FREQ
2120         help
2121           This enables the CPUfreq driver for i.MX CPUs.
2122
2123 config CPU_FREQ_SA1100
2124         bool
2125
2126 config CPU_FREQ_SA1110
2127         bool
2128
2129 config CPU_FREQ_INTEGRATOR
2130         tristate "CPUfreq driver for ARM Integrator CPUs"
2131         depends on ARCH_INTEGRATOR && CPU_FREQ
2132         default y
2133         help
2134           This enables the CPUfreq driver for ARM Integrator CPUs.
2135
2136           For details, take a look at <file:Documentation/cpu-freq>.
2137
2138           If in doubt, say Y.
2139
2140 config CPU_FREQ_PXA
2141         bool
2142         depends on CPU_FREQ && ARCH_PXA && PXA25x
2143         default y
2144         select CPU_FREQ_TABLE
2145         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2146
2147 config CPU_FREQ_S3C
2148         bool
2149         help
2150           Internal configuration node for common cpufreq on Samsung SoC
2151
2152 config CPU_FREQ_S3C24XX
2153         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2154         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2155         select CPU_FREQ_S3C
2156         help
2157           This enables the CPUfreq driver for the Samsung S3C24XX family
2158           of CPUs.
2159
2160           For details, take a look at <file:Documentation/cpu-freq>.
2161
2162           If in doubt, say N.
2163
2164 config CPU_FREQ_S3C24XX_PLL
2165         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2166         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2167         help
2168           Compile in support for changing the PLL frequency from the
2169           S3C24XX series CPUfreq driver. The PLL takes time to settle
2170           after a frequency change, so by default it is not enabled.
2171
2172           This also means that the PLL tables for the selected CPU(s) will
2173           be built which may increase the size of the kernel image.
2174
2175 config CPU_FREQ_S3C24XX_DEBUG
2176         bool "Debug CPUfreq Samsung driver core"
2177         depends on CPU_FREQ_S3C24XX
2178         help
2179           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2180
2181 config CPU_FREQ_S3C24XX_IODEBUG
2182         bool "Debug CPUfreq Samsung driver IO timing"
2183         depends on CPU_FREQ_S3C24XX
2184         help
2185           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2186
2187 config CPU_FREQ_S3C24XX_DEBUGFS
2188         bool "Export debugfs for CPUFreq"
2189         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2190         help
2191           Export status information via debugfs.
2192
2193 endif
2194
2195 source "drivers/cpuidle/Kconfig"
2196
2197 endmenu
2198
2199 menu "Floating point emulation"
2200
2201 comment "At least one emulation must be selected"
2202
2203 config FPE_NWFPE
2204         bool "NWFPE math emulation"
2205         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2206         ---help---
2207           Say Y to include the NWFPE floating point emulator in the kernel.
2208           This is necessary to run most binaries. Linux does not currently
2209           support floating point hardware so you need to say Y here even if
2210           your machine has an FPA or floating point co-processor podule.
2211
2212           You may say N here if you are going to load the Acorn FPEmulator
2213           early in the bootup.
2214
2215 config FPE_NWFPE_XP
2216         bool "Support extended precision"
2217         depends on FPE_NWFPE
2218         help
2219           Say Y to include 80-bit support in the kernel floating-point
2220           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2221           Note that gcc does not generate 80-bit operations by default,
2222           so in most cases this option only enlarges the size of the
2223           floating point emulator without any good reason.
2224
2225           You almost surely want to say N here.
2226
2227 config FPE_FASTFPE
2228         bool "FastFPE math emulation (EXPERIMENTAL)"
2229         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2230         ---help---
2231           Say Y here to include the FAST floating point emulator in the kernel.
2232           This is an experimental much faster emulator which now also has full
2233           precision for the mantissa.  It does not support any exceptions.
2234           It is very simple, and approximately 3-6 times faster than NWFPE.
2235
2236           It should be sufficient for most programs.  It may be not suitable
2237           for scientific calculations, but you have to check this for yourself.
2238           If you do not feel you need a faster FP emulation you should better
2239           choose NWFPE.
2240
2241 config VFP
2242         bool "VFP-format floating point maths"
2243         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2244         help
2245           Say Y to include VFP support code in the kernel. This is needed
2246           if your hardware includes a VFP unit.
2247
2248           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2249           release notes and additional status information.
2250
2251           Say N if your target does not have VFP hardware.
2252
2253 config VFPv3
2254         bool
2255         depends on VFP
2256         default y if CPU_V7
2257
2258 config NEON
2259         bool "Advanced SIMD (NEON) Extension support"
2260         depends on VFPv3 && CPU_V7
2261         help
2262           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2263           Extension.
2264
2265 endmenu
2266
2267 menu "Userspace binary formats"
2268
2269 source "fs/Kconfig.binfmt"
2270
2271 config ARTHUR
2272         tristate "RISC OS personality"
2273         depends on !AEABI
2274         help
2275           Say Y here to include the kernel code necessary if you want to run
2276           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2277           experimental; if this sounds frightening, say N and sleep in peace.
2278           You can also say M here to compile this support as a module (which
2279           will be called arthur).
2280
2281 endmenu
2282
2283 menu "Power management options"
2284
2285 source "kernel/power/Kconfig"
2286
2287 config ARCH_SUSPEND_POSSIBLE
2288         depends on !ARCH_S5PC100 && !ARCH_TEGRA
2289         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2290                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2291         def_bool y
2292
2293 config ARM_CPU_SUSPEND
2294         def_bool PM_SLEEP
2295
2296 endmenu
2297
2298 source "net/Kconfig"
2299
2300 source "drivers/Kconfig"
2301
2302 source "fs/Kconfig"
2303
2304 source "arch/arm/Kconfig.debug"
2305
2306 source "security/Kconfig"
2307
2308 source "crypto/Kconfig"
2309
2310 source "lib/Kconfig"