4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_IRQ_PROBE
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select HARDIRQS_SW_RESEND
44 select CPU_PM if (SUSPEND || CPU_IDLE)
45 select GENERIC_PCI_IOMAP
47 select GENERIC_SMP_IDLE_THREAD
49 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
54 The ARM series is a line of low-power-consumption RISC chip designs
55 licensed by ARM Ltd and targeted at embedded applications and
56 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
57 manufactured, but legacy ARM-based PC hardware remains popular in
58 Europe. There is an ARM Linux project with a web page at
59 <http://www.arm.linux.org.uk/>.
61 config ARM_HAS_SG_CHAIN
64 config NEED_SG_DMA_LENGTH
67 config ARM_DMA_USE_IOMMU
68 select NEED_SG_DMA_LENGTH
69 select ARM_HAS_SG_CHAIN
78 config SYS_SUPPORTS_APM_EMULATION
86 select GENERIC_ALLOCATOR
97 The Extended Industry Standard Architecture (EISA) bus was
98 developed as an open alternative to the IBM MicroChannel bus.
100 The EISA bus provided some of the features of the IBM MicroChannel
101 bus while maintaining backward compatibility with cards made for
102 the older ISA bus. The EISA bus saw limited use between 1988 and
103 1995 when it was made obsolete by the PCI bus.
105 Say Y here if you are building a kernel for an EISA-based machine.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config GENERIC_LOCKBREAK
132 depends on SMP && PREEMPT
134 config RWSEM_GENERIC_SPINLOCK
138 config RWSEM_XCHGADD_ALGORITHM
141 config ARCH_HAS_ILOG2_U32
144 config ARCH_HAS_ILOG2_U64
147 config ARCH_HAS_CPUFREQ
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
154 config GENERIC_HWEIGHT
158 config GENERIC_CALIBRATE_DELAY
162 config ARCH_MAY_HAVE_PC_FDC
168 config NEED_DMA_MAP_STATE
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
174 config GENERIC_ISA_DMA
180 config NEED_RET_TO_USER
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_IO_H
214 Select this when mach/io.h is required to provide special
215 definitions for this platform. The need for mach/io.h should
216 be avoided when possible.
218 config NEED_MACH_MEMORY_H
221 Select this when mach/memory.h is required to provide special
222 definitions for this platform. The need for mach/memory.h should
223 be avoided when possible.
226 hex "Physical address of main memory" if MMU
227 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
228 default DRAM_BASE if !MMU
230 Please provide the physical address corresponding to the
231 location of main memory in your system.
237 source "init/Kconfig"
239 source "kernel/Kconfig.freezer"
244 bool "MMU-based Paged Memory Management Support"
247 Select if you want MMU-based virtualised addressing space
248 support by paged memory management. If unsure, say 'Y'.
251 # The "ARM system type" choice list is ordered alphabetically by option
252 # text. Please add new entries in the option alphabetic order.
255 prompt "ARM system type"
256 default ARCH_VERSATILE
259 bool "Altera SOCFPGA family"
260 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select DW_APB_TIMER_OF
269 select GENERIC_CLOCKEVENTS
270 select GPIO_PL061 if GPIOLIB
275 This enables support for Altera SOCFPGA Cyclone V platform
277 config ARCH_INTEGRATOR
278 bool "ARM Ltd. Integrator family"
280 select ARCH_HAS_CPUFREQ
285 select GENERIC_CLOCKEVENTS
286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_FPGA_IRQ
288 select NEED_MACH_MEMORY_H
290 select MULTI_IRQ_HANDLER
292 Support for ARM's Integrator platform.
295 bool "ARM Ltd. RealView family"
298 select HAVE_MACH_CLKDEV
300 select GENERIC_CLOCKEVENTS
301 select ARCH_WANT_OPTIONAL_GPIOLIB
302 select PLAT_VERSATILE
303 select PLAT_VERSATILE_CLOCK
304 select PLAT_VERSATILE_CLCD
305 select ARM_TIMER_SP804
306 select GPIO_PL061 if GPIOLIB
307 select NEED_MACH_MEMORY_H
309 This enables support for ARM Ltd RealView boards.
311 config ARCH_VERSATILE
312 bool "ARM Ltd. Versatile family"
316 select HAVE_MACH_CLKDEV
318 select GENERIC_CLOCKEVENTS
319 select ARCH_WANT_OPTIONAL_GPIOLIB
320 select PLAT_VERSATILE
321 select PLAT_VERSATILE_CLOCK
322 select PLAT_VERSATILE_CLCD
323 select PLAT_VERSATILE_FPGA_IRQ
324 select ARM_TIMER_SP804
326 This enables support for ARM Ltd Versatile board.
329 bool "ARM Ltd. Versatile Express family"
330 select ARCH_WANT_OPTIONAL_GPIOLIB
332 select ARM_TIMER_SP804
335 select GENERIC_CLOCKEVENTS
337 select HAVE_PATA_PLATFORM
340 select PLAT_VERSATILE
341 select PLAT_VERSATILE_CLCD
342 select REGULATOR_FIXED_VOLTAGE if REGULATOR
344 This enables support for the ARM Ltd Versatile Express boards.
348 select ARCH_REQUIRE_GPIOLIB
352 select NEED_MACH_IO_H if PCCARD
354 This enables support for systems based on Atmel
355 AT91RM9200 and AT91SAM9* processors.
358 bool "Broadcom BCMRING"
362 select ARM_TIMER_SP804
364 select GENERIC_CLOCKEVENTS
365 select ARCH_WANT_OPTIONAL_GPIOLIB
367 Support for Broadcom's BCMRing platform.
370 bool "Calxeda Highbank-based"
371 select ARCH_WANT_OPTIONAL_GPIOLIB
374 select ARM_TIMER_SP804
379 select GENERIC_CLOCKEVENTS
385 Support for the Calxeda Highbank SoC based boards.
388 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
390 select ARCH_USES_GETTIMEOFFSET
391 select NEED_MACH_MEMORY_H
393 Support for Cirrus Logic 711x/721x/731x based boards.
396 bool "Cavium Networks CNS3XXX family"
398 select GENERIC_CLOCKEVENTS
400 select MIGHT_HAVE_CACHE_L2X0
401 select MIGHT_HAVE_PCI
402 select PCI_DOMAINS if PCI
404 Support for Cavium Networks CNS3XXX platform.
407 bool "Cortina Systems Gemini"
409 select ARCH_REQUIRE_GPIOLIB
410 select ARCH_USES_GETTIMEOFFSET
412 Support for the Cortina Systems Gemini family SoCs
415 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
418 select ARCH_REQUIRE_GPIOLIB
419 select GENERIC_CLOCKEVENTS
421 select GENERIC_IRQ_CHIP
422 select MIGHT_HAVE_CACHE_L2X0
428 Support for CSR SiRFSoC ARM Cortex A9 Platform
435 select ARCH_USES_GETTIMEOFFSET
436 select NEED_MACH_IO_H
437 select NEED_MACH_MEMORY_H
439 This is an evaluation board for the StrongARM processor available
440 from Digital. It has limited hardware on-board, including an
441 Ethernet interface, two PCMCIA sockets, two serial ports and a
450 select ARCH_REQUIRE_GPIOLIB
451 select ARCH_HAS_HOLES_MEMORYMODEL
452 select ARCH_USES_GETTIMEOFFSET
453 select NEED_MACH_MEMORY_H
455 This enables support for the Cirrus EP93xx series of CPUs.
457 config ARCH_FOOTBRIDGE
461 select GENERIC_CLOCKEVENTS
463 select NEED_MACH_IO_H if !MMU
464 select NEED_MACH_MEMORY_H
466 Support for systems based on the DC21285 companion chip
467 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
470 bool "Freescale MXC/iMX-based"
471 select GENERIC_CLOCKEVENTS
472 select ARCH_REQUIRE_GPIOLIB
475 select GENERIC_IRQ_CHIP
476 select MULTI_IRQ_HANDLER
480 Support for Freescale MXC/iMX-based family of processors
483 bool "Freescale MXS-based"
484 select GENERIC_CLOCKEVENTS
485 select ARCH_REQUIRE_GPIOLIB
489 select HAVE_CLK_PREPARE
493 Support for Freescale MXS-based family of processors
496 bool "Hilscher NetX based"
500 select GENERIC_CLOCKEVENTS
502 This enables support for systems based on the Hilscher NetX Soc
505 bool "Hynix HMS720x-based"
508 select ARCH_USES_GETTIMEOFFSET
510 This enables support for systems based on the Hynix HMS720x
518 select ARCH_SUPPORTS_MSI
520 select NEED_MACH_MEMORY_H
521 select NEED_RET_TO_USER
523 Support for Intel's IOP13XX (XScale) family of processors.
529 select NEED_RET_TO_USER
532 select ARCH_REQUIRE_GPIOLIB
534 Support for Intel's 80219 and IOP32X (XScale) family of
541 select NEED_RET_TO_USER
544 select ARCH_REQUIRE_GPIOLIB
546 Support for Intel's IOP33X (XScale) family of processors.
551 select ARCH_HAS_DMA_SET_COHERENT_MASK
554 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
556 select MIGHT_HAVE_PCI
557 select NEED_MACH_IO_H
558 select DMABOUNCE if PCI
560 Support for Intel's IXP4XX (XScale) family of processors.
563 bool "Marvell SOCs with Device Tree support"
564 select GENERIC_CLOCKEVENTS
565 select MULTI_IRQ_HANDLER
568 select GENERIC_IRQ_CHIP
572 Support for the Marvell SoC Family with device tree support
578 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
582 Support for the Marvell Dove SoC 88AP510
585 bool "Marvell Kirkwood"
588 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
592 Support for the following Marvell Kirkwood series SoCs:
593 88F6180, 88F6192 and 88F6281.
599 select ARCH_REQUIRE_GPIOLIB
602 select USB_ARCH_HAS_OHCI
604 select GENERIC_CLOCKEVENTS
608 Support for the NXP LPC32XX family of processors
611 bool "Marvell MV78xx0"
614 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
618 Support for the following Marvell MV78xx0 series SoCs:
626 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
630 Support for the following Marvell Orion 5x series SoCs:
631 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
632 Orion-2 (5281), Orion-1-90 (6183).
635 bool "Marvell PXA168/910/MMP2"
637 select ARCH_REQUIRE_GPIOLIB
639 select GENERIC_CLOCKEVENTS
644 select GENERIC_ALLOCATOR
646 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
649 bool "Micrel/Kendin KS8695"
651 select ARCH_REQUIRE_GPIOLIB
652 select ARCH_USES_GETTIMEOFFSET
653 select NEED_MACH_MEMORY_H
655 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
656 System-on-Chip devices.
659 bool "Nuvoton W90X900 CPU"
661 select ARCH_REQUIRE_GPIOLIB
664 select GENERIC_CLOCKEVENTS
666 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
667 At present, the w90x900 has been renamed nuc900, regarding
668 the ARM series product line, you can login the following
669 link address to know more.
671 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
672 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
678 select GENERIC_CLOCKEVENTS
682 select MIGHT_HAVE_CACHE_L2X0
683 select ARCH_HAS_CPUFREQ
686 This enables support for NVIDIA Tegra based systems (Tegra APX,
687 Tegra 6xx and Tegra 2 series).
689 config ARCH_PICOXCELL
690 bool "Picochip picoXcell"
691 select ARCH_REQUIRE_GPIOLIB
692 select ARM_PATCH_PHYS_VIRT
696 select DW_APB_TIMER_OF
697 select GENERIC_CLOCKEVENTS
704 This enables support for systems based on the Picochip picoXcell
705 family of Femtocell devices. The picoxcell support requires device tree
709 bool "Philips Nexperia PNX4008 Mobile"
712 select ARCH_USES_GETTIMEOFFSET
714 This enables support for Philips PNX4008 mobile platform.
717 bool "PXA2xx/PXA3xx-based"
720 select ARCH_HAS_CPUFREQ
723 select ARCH_REQUIRE_GPIOLIB
724 select GENERIC_CLOCKEVENTS
729 select MULTI_IRQ_HANDLER
730 select ARM_CPU_SUSPEND if PM
733 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
738 select GENERIC_CLOCKEVENTS
739 select ARCH_REQUIRE_GPIOLIB
742 Support for Qualcomm MSM/QSD based systems. This runs on the
743 apps processor of the MSM/QSD and depends on a shared memory
744 interface to the modem processor which runs the baseband
745 stack and controls some vital subsystems
746 (clock and power control, etc).
749 bool "Renesas SH-Mobile / R-Mobile"
752 select HAVE_MACH_CLKDEV
754 select GENERIC_CLOCKEVENTS
755 select MIGHT_HAVE_CACHE_L2X0
758 select MULTI_IRQ_HANDLER
759 select PM_GENERIC_DOMAINS if PM
760 select NEED_MACH_MEMORY_H
762 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
768 select ARCH_MAY_HAVE_PC_FDC
769 select HAVE_PATA_PLATFORM
772 select ARCH_SPARSEMEM_ENABLE
773 select ARCH_USES_GETTIMEOFFSET
775 select NEED_MACH_IO_H
776 select NEED_MACH_MEMORY_H
778 On the Acorn Risc-PC, Linux can support the internal IDE disk and
779 CD-ROM interface, serial and parallel port, and the floppy drive.
786 select ARCH_SPARSEMEM_ENABLE
788 select ARCH_HAS_CPUFREQ
790 select GENERIC_CLOCKEVENTS
792 select ARCH_REQUIRE_GPIOLIB
794 select NEED_MACH_MEMORY_H
797 Support for StrongARM 11x0 based boards.
800 bool "Samsung S3C24XX SoCs"
802 select ARCH_HAS_CPUFREQ
805 select ARCH_USES_GETTIMEOFFSET
806 select HAVE_S3C2410_I2C if I2C
807 select HAVE_S3C_RTC if RTC_CLASS
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select NEED_MACH_IO_H
811 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
812 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
813 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
814 Samsung SMDK2410 development board (and derivatives).
817 bool "Samsung S3C64XX"
825 select ARCH_USES_GETTIMEOFFSET
826 select ARCH_HAS_CPUFREQ
827 select ARCH_REQUIRE_GPIOLIB
828 select SAMSUNG_CLKSRC
829 select SAMSUNG_IRQ_VIC_TIMER
830 select S3C_GPIO_TRACK
832 select USB_ARCH_HAS_OHCI
833 select SAMSUNG_GPIOLIB_4BIT
834 select HAVE_S3C2410_I2C if I2C
835 select HAVE_S3C2410_WATCHDOG if WATCHDOG
837 Samsung S3C64XX series based systems
840 bool "Samsung S5P6440 S5P6450"
846 select HAVE_S3C2410_WATCHDOG if WATCHDOG
847 select GENERIC_CLOCKEVENTS
848 select HAVE_S3C2410_I2C if I2C
849 select HAVE_S3C_RTC if RTC_CLASS
851 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
855 bool "Samsung S5PC100"
860 select ARCH_USES_GETTIMEOFFSET
861 select HAVE_S3C2410_I2C if I2C
862 select HAVE_S3C_RTC if RTC_CLASS
863 select HAVE_S3C2410_WATCHDOG if WATCHDOG
865 Samsung S5PC100 series based systems
868 bool "Samsung S5PV210/S5PC110"
870 select ARCH_SPARSEMEM_ENABLE
871 select ARCH_HAS_HOLES_MEMORYMODEL
876 select ARCH_HAS_CPUFREQ
877 select GENERIC_CLOCKEVENTS
878 select HAVE_S3C2410_I2C if I2C
879 select HAVE_S3C_RTC if RTC_CLASS
880 select HAVE_S3C2410_WATCHDOG if WATCHDOG
881 select NEED_MACH_MEMORY_H
883 Samsung S5PV210/S5PC110 series based systems
886 bool "SAMSUNG EXYNOS"
888 select ARCH_SPARSEMEM_ENABLE
889 select ARCH_HAS_HOLES_MEMORYMODEL
893 select ARCH_HAS_CPUFREQ
894 select GENERIC_CLOCKEVENTS
895 select HAVE_S3C_RTC if RTC_CLASS
896 select HAVE_S3C2410_I2C if I2C
897 select HAVE_S3C2410_WATCHDOG if WATCHDOG
898 select NEED_MACH_MEMORY_H
900 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
909 select ARCH_USES_GETTIMEOFFSET
910 select NEED_MACH_MEMORY_H
912 Support for the StrongARM based Digital DNARD machine, also known
913 as "Shark" (<http://www.shark-linux.de/shark.html>).
916 bool "ST-Ericsson U300 Series"
922 select ARM_PATCH_PHYS_VIRT
924 select GENERIC_CLOCKEVENTS
928 select ARCH_REQUIRE_GPIOLIB
930 Support for ST-Ericsson U300 series mobile platforms.
933 bool "ST-Ericsson U8500 Series"
937 select GENERIC_CLOCKEVENTS
939 select ARCH_REQUIRE_GPIOLIB
940 select ARCH_HAS_CPUFREQ
942 select MIGHT_HAVE_CACHE_L2X0
944 Support for ST-Ericsson's Ux500 architecture
947 bool "STMicroelectronics Nomadik"
952 select GENERIC_CLOCKEVENTS
954 select MIGHT_HAVE_CACHE_L2X0
955 select ARCH_REQUIRE_GPIOLIB
957 Support for the Nomadik platform by ST-Ericsson
961 select GENERIC_CLOCKEVENTS
962 select ARCH_REQUIRE_GPIOLIB
966 select GENERIC_ALLOCATOR
967 select GENERIC_IRQ_CHIP
968 select ARCH_HAS_HOLES_MEMORYMODEL
970 Support for TI's DaVinci platform.
976 select ARCH_REQUIRE_GPIOLIB
977 select ARCH_HAS_CPUFREQ
979 select GENERIC_CLOCKEVENTS
980 select ARCH_HAS_HOLES_MEMORYMODEL
982 Support for TI's OMAP platform (OMAP1/2/3/4).
987 select ARCH_REQUIRE_GPIOLIB
991 select GENERIC_CLOCKEVENTS
994 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
997 bool "VIA/WonderMedia 85xx"
1000 select ARCH_HAS_CPUFREQ
1001 select GENERIC_CLOCKEVENTS
1002 select ARCH_REQUIRE_GPIOLIB
1004 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1007 bool "Xilinx Zynq ARM Cortex A9 Platform"
1009 select GENERIC_CLOCKEVENTS
1010 select CLKDEV_LOOKUP
1014 select MIGHT_HAVE_CACHE_L2X0
1017 Support for Xilinx Zynq ARM Cortex A9 Platform
1021 # This is sorted alphabetically by mach-* pathname. However, plat-*
1022 # Kconfigs may be included either alphabetically (according to the
1023 # plat- suffix) or along side the corresponding mach-* source.
1025 source "arch/arm/mach-mvebu/Kconfig"
1027 source "arch/arm/mach-at91/Kconfig"
1029 source "arch/arm/mach-bcmring/Kconfig"
1031 source "arch/arm/mach-clps711x/Kconfig"
1033 source "arch/arm/mach-cns3xxx/Kconfig"
1035 source "arch/arm/mach-davinci/Kconfig"
1037 source "arch/arm/mach-dove/Kconfig"
1039 source "arch/arm/mach-ep93xx/Kconfig"
1041 source "arch/arm/mach-footbridge/Kconfig"
1043 source "arch/arm/mach-gemini/Kconfig"
1045 source "arch/arm/mach-h720x/Kconfig"
1047 source "arch/arm/mach-integrator/Kconfig"
1049 source "arch/arm/mach-iop32x/Kconfig"
1051 source "arch/arm/mach-iop33x/Kconfig"
1053 source "arch/arm/mach-iop13xx/Kconfig"
1055 source "arch/arm/mach-ixp4xx/Kconfig"
1057 source "arch/arm/mach-kirkwood/Kconfig"
1059 source "arch/arm/mach-ks8695/Kconfig"
1061 source "arch/arm/mach-msm/Kconfig"
1063 source "arch/arm/mach-mv78xx0/Kconfig"
1065 source "arch/arm/plat-mxc/Kconfig"
1067 source "arch/arm/mach-mxs/Kconfig"
1069 source "arch/arm/mach-netx/Kconfig"
1071 source "arch/arm/mach-nomadik/Kconfig"
1072 source "arch/arm/plat-nomadik/Kconfig"
1074 source "arch/arm/plat-omap/Kconfig"
1076 source "arch/arm/mach-omap1/Kconfig"
1078 source "arch/arm/mach-omap2/Kconfig"
1080 source "arch/arm/mach-orion5x/Kconfig"
1082 source "arch/arm/mach-pxa/Kconfig"
1083 source "arch/arm/plat-pxa/Kconfig"
1085 source "arch/arm/mach-mmp/Kconfig"
1087 source "arch/arm/mach-realview/Kconfig"
1089 source "arch/arm/mach-sa1100/Kconfig"
1091 source "arch/arm/plat-samsung/Kconfig"
1092 source "arch/arm/plat-s3c24xx/Kconfig"
1094 source "arch/arm/plat-spear/Kconfig"
1096 source "arch/arm/mach-s3c24xx/Kconfig"
1098 source "arch/arm/mach-s3c2412/Kconfig"
1099 source "arch/arm/mach-s3c2440/Kconfig"
1103 source "arch/arm/mach-s3c64xx/Kconfig"
1106 source "arch/arm/mach-s5p64x0/Kconfig"
1108 source "arch/arm/mach-s5pc100/Kconfig"
1110 source "arch/arm/mach-s5pv210/Kconfig"
1112 source "arch/arm/mach-exynos/Kconfig"
1114 source "arch/arm/mach-shmobile/Kconfig"
1116 source "arch/arm/mach-tegra/Kconfig"
1118 source "arch/arm/mach-u300/Kconfig"
1120 source "arch/arm/mach-ux500/Kconfig"
1122 source "arch/arm/mach-versatile/Kconfig"
1124 source "arch/arm/mach-vexpress/Kconfig"
1125 source "arch/arm/plat-versatile/Kconfig"
1127 source "arch/arm/mach-vt8500/Kconfig"
1129 source "arch/arm/mach-w90x900/Kconfig"
1131 # Definitions to make life easier
1137 select GENERIC_CLOCKEVENTS
1142 select GENERIC_IRQ_CHIP
1149 config PLAT_VERSATILE
1152 config ARM_TIMER_SP804
1155 select HAVE_SCHED_CLOCK
1157 source arch/arm/mm/Kconfig
1161 default 16 if ARCH_EP93XX
1165 bool "Enable iWMMXt support"
1166 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1167 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1169 Enable support for iWMMXt context switching at run time if
1170 running on a CPU that supports it.
1174 depends on CPU_XSCALE
1178 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1179 (!ARCH_OMAP3 || OMAP3_EMU)
1183 config MULTI_IRQ_HANDLER
1186 Allow each machine to specify it's own IRQ handler at run time.
1189 source "arch/arm/Kconfig-nommu"
1192 config ARM_ERRATA_326103
1193 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1196 Executing a SWP instruction to read-only memory does not set bit 11
1197 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1198 treat the access as a read, preventing a COW from occurring and
1199 causing the faulting task to livelock.
1201 config ARM_ERRATA_411920
1202 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1203 depends on CPU_V6 || CPU_V6K
1205 Invalidation of the Instruction Cache operation can
1206 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1207 It does not affect the MPCore. This option enables the ARM Ltd.
1208 recommended workaround.
1210 config ARM_ERRATA_430973
1211 bool "ARM errata: Stale prediction on replaced interworking branch"
1214 This option enables the workaround for the 430973 Cortex-A8
1215 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1216 interworking branch is replaced with another code sequence at the
1217 same virtual address, whether due to self-modifying code or virtual
1218 to physical address re-mapping, Cortex-A8 does not recover from the
1219 stale interworking branch prediction. This results in Cortex-A8
1220 executing the new code sequence in the incorrect ARM or Thumb state.
1221 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1222 and also flushes the branch target cache at every context switch.
1223 Note that setting specific bits in the ACTLR register may not be
1224 available in non-secure mode.
1226 config ARM_ERRATA_458693
1227 bool "ARM errata: Processor deadlock when a false hazard is created"
1230 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1231 erratum. For very specific sequences of memory operations, it is
1232 possible for a hazard condition intended for a cache line to instead
1233 be incorrectly associated with a different cache line. This false
1234 hazard might then cause a processor deadlock. The workaround enables
1235 the L1 caching of the NEON accesses and disables the PLD instruction
1236 in the ACTLR register. Note that setting specific bits in the ACTLR
1237 register may not be available in non-secure mode.
1239 config ARM_ERRATA_460075
1240 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1243 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1244 erratum. Any asynchronous access to the L2 cache may encounter a
1245 situation in which recent store transactions to the L2 cache are lost
1246 and overwritten with stale memory contents from external memory. The
1247 workaround disables the write-allocate mode for the L2 cache via the
1248 ACTLR register. Note that setting specific bits in the ACTLR register
1249 may not be available in non-secure mode.
1251 config ARM_ERRATA_742230
1252 bool "ARM errata: DMB operation may be faulty"
1253 depends on CPU_V7 && SMP
1255 This option enables the workaround for the 742230 Cortex-A9
1256 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1257 between two write operations may not ensure the correct visibility
1258 ordering of the two writes. This workaround sets a specific bit in
1259 the diagnostic register of the Cortex-A9 which causes the DMB
1260 instruction to behave as a DSB, ensuring the correct behaviour of
1263 config ARM_ERRATA_742231
1264 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1265 depends on CPU_V7 && SMP
1267 This option enables the workaround for the 742231 Cortex-A9
1268 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1269 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1270 accessing some data located in the same cache line, may get corrupted
1271 data due to bad handling of the address hazard when the line gets
1272 replaced from one of the CPUs at the same time as another CPU is
1273 accessing it. This workaround sets specific bits in the diagnostic
1274 register of the Cortex-A9 which reduces the linefill issuing
1275 capabilities of the processor.
1277 config PL310_ERRATA_588369
1278 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1279 depends on CACHE_L2X0
1281 The PL310 L2 cache controller implements three types of Clean &
1282 Invalidate maintenance operations: by Physical Address
1283 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1284 They are architecturally defined to behave as the execution of a
1285 clean operation followed immediately by an invalidate operation,
1286 both performing to the same memory location. This functionality
1287 is not correctly implemented in PL310 as clean lines are not
1288 invalidated as a result of these operations.
1290 config ARM_ERRATA_720789
1291 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1294 This option enables the workaround for the 720789 Cortex-A9 (prior to
1295 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1296 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1297 As a consequence of this erratum, some TLB entries which should be
1298 invalidated are not, resulting in an incoherency in the system page
1299 tables. The workaround changes the TLB flushing routines to invalidate
1300 entries regardless of the ASID.
1302 config PL310_ERRATA_727915
1303 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1304 depends on CACHE_L2X0
1306 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1307 operation (offset 0x7FC). This operation runs in background so that
1308 PL310 can handle normal accesses while it is in progress. Under very
1309 rare circumstances, due to this erratum, write data can be lost when
1310 PL310 treats a cacheable write transaction during a Clean &
1311 Invalidate by Way operation.
1313 config ARM_ERRATA_743622
1314 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1317 This option enables the workaround for the 743622 Cortex-A9
1318 (r2p*) erratum. Under very rare conditions, a faulty
1319 optimisation in the Cortex-A9 Store Buffer may lead to data
1320 corruption. This workaround sets a specific bit in the diagnostic
1321 register of the Cortex-A9 which disables the Store Buffer
1322 optimisation, preventing the defect from occurring. This has no
1323 visible impact on the overall performance or power consumption of the
1326 config ARM_ERRATA_751472
1327 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1330 This option enables the workaround for the 751472 Cortex-A9 (prior
1331 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1332 completion of a following broadcasted operation if the second
1333 operation is received by a CPU before the ICIALLUIS has completed,
1334 potentially leading to corrupted entries in the cache or TLB.
1336 config PL310_ERRATA_753970
1337 bool "PL310 errata: cache sync operation may be faulty"
1338 depends on CACHE_PL310
1340 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1342 Under some condition the effect of cache sync operation on
1343 the store buffer still remains when the operation completes.
1344 This means that the store buffer is always asked to drain and
1345 this prevents it from merging any further writes. The workaround
1346 is to replace the normal offset of cache sync operation (0x730)
1347 by another offset targeting an unmapped PL310 register 0x740.
1348 This has the same effect as the cache sync operation: store buffer
1349 drain and waiting for all buffers empty.
1351 config ARM_ERRATA_754322
1352 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1355 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1356 r3p*) erratum. A speculative memory access may cause a page table walk
1357 which starts prior to an ASID switch but completes afterwards. This
1358 can populate the micro-TLB with a stale entry which may be hit with
1359 the new ASID. This workaround places two dsb instructions in the mm
1360 switching code so that no page table walks can cross the ASID switch.
1362 config ARM_ERRATA_754327
1363 bool "ARM errata: no automatic Store Buffer drain"
1364 depends on CPU_V7 && SMP
1366 This option enables the workaround for the 754327 Cortex-A9 (prior to
1367 r2p0) erratum. The Store Buffer does not have any automatic draining
1368 mechanism and therefore a livelock may occur if an external agent
1369 continuously polls a memory location waiting to observe an update.
1370 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1371 written polling loops from denying visibility of updates to memory.
1373 config ARM_ERRATA_364296
1374 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1375 depends on CPU_V6 && !SMP
1377 This options enables the workaround for the 364296 ARM1136
1378 r0p2 erratum (possible cache data corruption with
1379 hit-under-miss enabled). It sets the undocumented bit 31 in
1380 the auxiliary control register and the FI bit in the control
1381 register, thus disabling hit-under-miss without putting the
1382 processor into full low interrupt latency mode. ARM11MPCore
1385 config ARM_ERRATA_764369
1386 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1387 depends on CPU_V7 && SMP
1389 This option enables the workaround for erratum 764369
1390 affecting Cortex-A9 MPCore with two or more processors (all
1391 current revisions). Under certain timing circumstances, a data
1392 cache line maintenance operation by MVA targeting an Inner
1393 Shareable memory region may fail to proceed up to either the
1394 Point of Coherency or to the Point of Unification of the
1395 system. This workaround adds a DSB instruction before the
1396 relevant cache maintenance functions and sets a specific bit
1397 in the diagnostic control register of the SCU.
1399 config PL310_ERRATA_769419
1400 bool "PL310 errata: no automatic Store Buffer drain"
1401 depends on CACHE_L2X0
1403 On revisions of the PL310 prior to r3p2, the Store Buffer does
1404 not automatically drain. This can cause normal, non-cacheable
1405 writes to be retained when the memory system is idle, leading
1406 to suboptimal I/O performance for drivers using coherent DMA.
1407 This option adds a write barrier to the cpu_idle loop so that,
1408 on systems with an outer cache, the store buffer is drained
1413 source "arch/arm/common/Kconfig"
1423 Find out whether you have ISA slots on your motherboard. ISA is the
1424 name of a bus system, i.e. the way the CPU talks to the other stuff
1425 inside your box. Other bus systems are PCI, EISA, MicroChannel
1426 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1427 newer boards don't support it. If you have ISA, say Y, otherwise N.
1429 # Select ISA DMA controller support
1434 # Select ISA DMA interface
1439 bool "PCI support" if MIGHT_HAVE_PCI
1441 Find out whether you have a PCI motherboard. PCI is the name of a
1442 bus system, i.e. the way the CPU talks to the other stuff inside
1443 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1444 VESA. If you have PCI, say Y, otherwise N.
1450 config PCI_NANOENGINE
1451 bool "BSE nanoEngine PCI support"
1452 depends on SA1100_NANOENGINE
1454 Enable PCI on the BSE nanoEngine board.
1459 # Select the host bridge type
1460 config PCI_HOST_VIA82C505
1462 depends on PCI && ARCH_SHARK
1465 config PCI_HOST_ITE8152
1467 depends on PCI && MACH_ARMCORE
1471 source "drivers/pci/Kconfig"
1473 source "drivers/pcmcia/Kconfig"
1477 menu "Kernel Features"
1482 This option should be selected by machines which have an SMP-
1485 The only effect of this option is to make the SMP-related
1486 options available to the user for configuration.
1489 bool "Symmetric Multi-Processing"
1490 depends on CPU_V6K || CPU_V7
1491 depends on GENERIC_CLOCKEVENTS
1494 select USE_GENERIC_SMP_HELPERS
1495 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1497 This enables support for systems with more than one CPU. If you have
1498 a system with only one CPU, like most personal computers, say N. If
1499 you have a system with more than one CPU, say Y.
1501 If you say N here, the kernel will run on single and multiprocessor
1502 machines, but will use only one CPU of a multiprocessor machine. If
1503 you say Y here, the kernel will run on many, but not all, single
1504 processor machines. On a single processor machine, the kernel will
1505 run faster if you say N here.
1507 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1508 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1509 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1511 If you don't know what to do here, say N.
1514 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1515 depends on EXPERIMENTAL
1516 depends on SMP && !XIP_KERNEL
1519 SMP kernels contain instructions which fail on non-SMP processors.
1520 Enabling this option allows the kernel to modify itself to make
1521 these instructions safe. Disabling it allows about 1K of space
1524 If you don't know what to do here, say Y.
1526 config ARM_CPU_TOPOLOGY
1527 bool "Support cpu topology definition"
1528 depends on SMP && CPU_V7
1531 Support ARM cpu topology definition. The MPIDR register defines
1532 affinity between processors which is then used to describe the cpu
1533 topology of an ARM System.
1536 bool "Multi-core scheduler support"
1537 depends on ARM_CPU_TOPOLOGY
1539 Multi-core scheduler support improves the CPU scheduler's decision
1540 making when dealing with multi-core CPU chips at a cost of slightly
1541 increased overhead in some places. If unsure say N here.
1544 bool "SMT scheduler support"
1545 depends on ARM_CPU_TOPOLOGY
1547 Improves the CPU scheduler's decision making when dealing with
1548 MultiThreading at a cost of slightly increased overhead in some
1549 places. If unsure say N here.
1554 This option enables support for the ARM system coherency unit
1556 config ARM_ARCH_TIMER
1557 bool "Architected timer support"
1560 This option enables support for the ARM architected timer
1566 This options enables support for the ARM timer and watchdog unit
1569 prompt "Memory split"
1572 Select the desired split between kernel and user memory.
1574 If you are not absolutely sure what you are doing, leave this
1578 bool "3G/1G user/kernel split"
1580 bool "2G/2G user/kernel split"
1582 bool "1G/3G user/kernel split"
1587 default 0x40000000 if VMSPLIT_1G
1588 default 0x80000000 if VMSPLIT_2G
1592 int "Maximum number of CPUs (2-32)"
1598 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1599 depends on SMP && HOTPLUG && EXPERIMENTAL
1601 Say Y here to experiment with turning CPUs off and on. CPUs
1602 can be controlled through /sys/devices/system/cpu.
1605 bool "Use local timer interrupts"
1608 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1610 Enable support for local timers on SMP platforms, rather then the
1611 legacy IPI broadcast method. Local timers allows the system
1612 accounting to be spread across the timer interval, preventing a
1613 "thundering herd" at every timer tick.
1617 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1618 default 355 if ARCH_U8500
1619 default 264 if MACH_H4700
1620 default 512 if SOC_OMAP5
1623 Maximum number of GPIOs in the system.
1625 If unsure, leave the default value.
1627 source kernel/Kconfig.preempt
1631 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1632 ARCH_S5PV210 || ARCH_EXYNOS4
1633 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1634 default AT91_TIMER_HZ if ARCH_AT91
1635 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1638 config THUMB2_KERNEL
1639 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1640 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1642 select ARM_ASM_UNIFIED
1645 By enabling this option, the kernel will be compiled in
1646 Thumb-2 mode. A compiler/assembler that understand the unified
1647 ARM-Thumb syntax is needed.
1651 config THUMB2_AVOID_R_ARM_THM_JUMP11
1652 bool "Work around buggy Thumb-2 short branch relocations in gas"
1653 depends on THUMB2_KERNEL && MODULES
1656 Various binutils versions can resolve Thumb-2 branches to
1657 locally-defined, preemptible global symbols as short-range "b.n"
1658 branch instructions.
1660 This is a problem, because there's no guarantee the final
1661 destination of the symbol, or any candidate locations for a
1662 trampoline, are within range of the branch. For this reason, the
1663 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1664 relocation in modules at all, and it makes little sense to add
1667 The symptom is that the kernel fails with an "unsupported
1668 relocation" error when loading some modules.
1670 Until fixed tools are available, passing
1671 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1672 code which hits this problem, at the cost of a bit of extra runtime
1673 stack usage in some cases.
1675 The problem is described in more detail at:
1676 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1678 Only Thumb-2 kernels are affected.
1680 Unless you are sure your tools don't have this problem, say Y.
1682 config ARM_ASM_UNIFIED
1686 bool "Use the ARM EABI to compile the kernel"
1688 This option allows for the kernel to be compiled using the latest
1689 ARM ABI (aka EABI). This is only useful if you are using a user
1690 space environment that is also compiled with EABI.
1692 Since there are major incompatibilities between the legacy ABI and
1693 EABI, especially with regard to structure member alignment, this
1694 option also changes the kernel syscall calling convention to
1695 disambiguate both ABIs and allow for backward compatibility support
1696 (selected with CONFIG_OABI_COMPAT).
1698 To use this you need GCC version 4.0.0 or later.
1701 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1702 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1705 This option preserves the old syscall interface along with the
1706 new (ARM EABI) one. It also provides a compatibility layer to
1707 intercept syscalls that have structure arguments which layout
1708 in memory differs between the legacy ABI and the new ARM EABI
1709 (only for non "thumb" binaries). This option adds a tiny
1710 overhead to all syscalls and produces a slightly larger kernel.
1711 If you know you'll be using only pure EABI user space then you
1712 can say N here. If this option is not selected and you attempt
1713 to execute a legacy ABI binary then the result will be
1714 UNPREDICTABLE (in fact it can be predicted that it won't work
1715 at all). If in doubt say Y.
1717 config ARCH_HAS_HOLES_MEMORYMODEL
1720 config ARCH_SPARSEMEM_ENABLE
1723 config ARCH_SPARSEMEM_DEFAULT
1724 def_bool ARCH_SPARSEMEM_ENABLE
1726 config ARCH_SELECT_MEMORY_MODEL
1727 def_bool ARCH_SPARSEMEM_ENABLE
1729 config HAVE_ARCH_PFN_VALID
1730 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1733 bool "High Memory Support"
1736 The address space of ARM processors is only 4 Gigabytes large
1737 and it has to accommodate user address space, kernel address
1738 space as well as some memory mapped IO. That means that, if you
1739 have a large amount of physical memory and/or IO, not all of the
1740 memory can be "permanently mapped" by the kernel. The physical
1741 memory that is not permanently mapped is called "high memory".
1743 Depending on the selected kernel/user memory split, minimum
1744 vmalloc space and actual amount of RAM, you may not need this
1745 option which should result in a slightly faster kernel.
1750 bool "Allocate 2nd-level pagetables from highmem"
1753 config HW_PERF_EVENTS
1754 bool "Enable hardware performance counter support for perf events"
1755 depends on PERF_EVENTS && CPU_HAS_PMU
1758 Enable hardware performance counter support for perf events. If
1759 disabled, perf events will use software events only.
1763 config FORCE_MAX_ZONEORDER
1764 int "Maximum zone order" if ARCH_SHMOBILE
1765 range 11 64 if ARCH_SHMOBILE
1766 default "9" if SA1111
1769 The kernel memory allocator divides physically contiguous memory
1770 blocks into "zones", where each zone is a power of two number of
1771 pages. This option selects the largest power of two that the kernel
1772 keeps in the memory allocator. If you need to allocate very large
1773 blocks of physically contiguous memory, then you may need to
1774 increase this value.
1776 This config option is actually maximum order plus one. For example,
1777 a value of 11 means that the largest free memory block is 2^10 pages.
1780 bool "Timer and CPU usage LEDs"
1781 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1782 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1783 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1784 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1785 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1786 ARCH_AT91 || ARCH_DAVINCI || \
1787 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1789 If you say Y here, the LEDs on your machine will be used
1790 to provide useful information about your current system status.
1792 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1793 be able to select which LEDs are active using the options below. If
1794 you are compiling a kernel for the EBSA-110 or the LART however, the
1795 red LED will simply flash regularly to indicate that the system is
1796 still functional. It is safe to say Y here if you have a CATS
1797 system, but the driver will do nothing.
1800 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1801 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1802 || MACH_OMAP_PERSEUS2
1804 depends on !GENERIC_CLOCKEVENTS
1805 default y if ARCH_EBSA110
1807 If you say Y here, one of the system LEDs (the green one on the
1808 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1809 will flash regularly to indicate that the system is still
1810 operational. This is mainly useful to kernel hackers who are
1811 debugging unstable kernels.
1813 The LART uses the same LED for both Timer LED and CPU usage LED
1814 functions. You may choose to use both, but the Timer LED function
1815 will overrule the CPU usage LED.
1818 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1820 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1821 || MACH_OMAP_PERSEUS2
1824 If you say Y here, the red LED will be used to give a good real
1825 time indication of CPU usage, by lighting whenever the idle task
1826 is not currently executing.
1828 The LART uses the same LED for both Timer LED and CPU usage LED
1829 functions. You may choose to use both, but the Timer LED function
1830 will overrule the CPU usage LED.
1832 config ALIGNMENT_TRAP
1834 depends on CPU_CP15_MMU
1835 default y if !ARCH_EBSA110
1836 select HAVE_PROC_CPU if PROC_FS
1838 ARM processors cannot fetch/store information which is not
1839 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1840 address divisible by 4. On 32-bit ARM processors, these non-aligned
1841 fetch/store instructions will be emulated in software if you say
1842 here, which has a severe performance impact. This is necessary for
1843 correct operation of some network protocols. With an IP-only
1844 configuration it is safe to say N, otherwise say Y.
1846 config UACCESS_WITH_MEMCPY
1847 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1848 depends on MMU && EXPERIMENTAL
1849 default y if CPU_FEROCEON
1851 Implement faster copy_to_user and clear_user methods for CPU
1852 cores where a 8-word STM instruction give significantly higher
1853 memory write throughput than a sequence of individual 32bit stores.
1855 A possible side effect is a slight increase in scheduling latency
1856 between threads sharing the same address space if they invoke
1857 such copy operations with large buffers.
1859 However, if the CPU data cache is using a write-allocate mode,
1860 this option is unlikely to provide any performance gain.
1864 prompt "Enable seccomp to safely compute untrusted bytecode"
1866 This kernel feature is useful for number crunching applications
1867 that may need to compute untrusted bytecode during their
1868 execution. By using pipes or other transports made available to
1869 the process as file descriptors supporting the read/write
1870 syscalls, it's possible to isolate those applications in
1871 their own address space using seccomp. Once seccomp is
1872 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1873 and the task is only allowed to execute a few safe syscalls
1874 defined by each seccomp mode.
1876 config CC_STACKPROTECTOR
1877 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1878 depends on EXPERIMENTAL
1880 This option turns on the -fstack-protector GCC feature. This
1881 feature puts, at the beginning of functions, a canary value on
1882 the stack just before the return address, and validates
1883 the value just before actually returning. Stack based buffer
1884 overflows (that need to overwrite this return address) now also
1885 overwrite the canary, which gets detected and the attack is then
1886 neutralized via a kernel panic.
1887 This feature requires gcc version 4.2 or above.
1889 config DEPRECATED_PARAM_STRUCT
1890 bool "Provide old way to pass kernel parameters"
1892 This was deprecated in 2001 and announced to live on for 5 years.
1893 Some old boot loaders still use this way.
1900 bool "Flattened Device Tree support"
1902 select OF_EARLY_FLATTREE
1905 Include support for flattened device tree machine descriptions.
1907 # Compressed boot loader in ROM. Yes, we really want to ask about
1908 # TEXT and BSS so we preserve their values in the config files.
1909 config ZBOOT_ROM_TEXT
1910 hex "Compressed ROM boot loader base address"
1913 The physical address at which the ROM-able zImage is to be
1914 placed in the target. Platforms which normally make use of
1915 ROM-able zImage formats normally set this to a suitable
1916 value in their defconfig file.
1918 If ZBOOT_ROM is not enabled, this has no effect.
1920 config ZBOOT_ROM_BSS
1921 hex "Compressed ROM boot loader BSS address"
1924 The base address of an area of read/write memory in the target
1925 for the ROM-able zImage which must be available while the
1926 decompressor is running. It must be large enough to hold the
1927 entire decompressed kernel plus an additional 128 KiB.
1928 Platforms which normally make use of ROM-able zImage formats
1929 normally set this to a suitable value in their defconfig file.
1931 If ZBOOT_ROM is not enabled, this has no effect.
1934 bool "Compressed boot loader in ROM/flash"
1935 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1937 Say Y here if you intend to execute your compressed kernel image
1938 (zImage) directly from ROM or flash. If unsure, say N.
1941 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1942 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1943 default ZBOOT_ROM_NONE
1945 Include experimental SD/MMC loading code in the ROM-able zImage.
1946 With this enabled it is possible to write the ROM-able zImage
1947 kernel image to an MMC or SD card and boot the kernel straight
1948 from the reset vector. At reset the processor Mask ROM will load
1949 the first part of the ROM-able zImage which in turn loads the
1950 rest the kernel image to RAM.
1952 config ZBOOT_ROM_NONE
1953 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1955 Do not load image from SD or MMC
1957 config ZBOOT_ROM_MMCIF
1958 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1960 Load image from MMCIF hardware block.
1962 config ZBOOT_ROM_SH_MOBILE_SDHI
1963 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1965 Load image from SDHI hardware block
1969 config ARM_APPENDED_DTB
1970 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1971 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1973 With this option, the boot code will look for a device tree binary
1974 (DTB) appended to zImage
1975 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1977 This is meant as a backward compatibility convenience for those
1978 systems with a bootloader that can't be upgraded to accommodate
1979 the documented boot protocol using a device tree.
1981 Beware that there is very little in terms of protection against
1982 this option being confused by leftover garbage in memory that might
1983 look like a DTB header after a reboot if no actual DTB is appended
1984 to zImage. Do not leave this option active in a production kernel
1985 if you don't intend to always append a DTB. Proper passing of the
1986 location into r2 of a bootloader provided DTB is always preferable
1989 config ARM_ATAG_DTB_COMPAT
1990 bool "Supplement the appended DTB with traditional ATAG information"
1991 depends on ARM_APPENDED_DTB
1993 Some old bootloaders can't be updated to a DTB capable one, yet
1994 they provide ATAGs with memory configuration, the ramdisk address,
1995 the kernel cmdline string, etc. Such information is dynamically
1996 provided by the bootloader and can't always be stored in a static
1997 DTB. To allow a device tree enabled kernel to be used with such
1998 bootloaders, this option allows zImage to extract the information
1999 from the ATAG list and store it at run time into the appended DTB.
2002 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2003 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2005 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2006 bool "Use bootloader kernel arguments if available"
2008 Uses the command-line options passed by the boot loader instead of
2009 the device tree bootargs property. If the boot loader doesn't provide
2010 any, the device tree bootargs property will be used.
2012 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2013 bool "Extend with bootloader kernel arguments"
2015 The command-line arguments provided by the boot loader will be
2016 appended to the the device tree bootargs property.
2021 string "Default kernel command string"
2024 On some architectures (EBSA110 and CATS), there is currently no way
2025 for the boot loader to pass arguments to the kernel. For these
2026 architectures, you should supply some command-line options at build
2027 time by entering them here. As a minimum, you should specify the
2028 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2031 prompt "Kernel command line type" if CMDLINE != ""
2032 default CMDLINE_FROM_BOOTLOADER
2034 config CMDLINE_FROM_BOOTLOADER
2035 bool "Use bootloader kernel arguments if available"
2037 Uses the command-line options passed by the boot loader. If
2038 the boot loader doesn't provide any, the default kernel command
2039 string provided in CMDLINE will be used.
2041 config CMDLINE_EXTEND
2042 bool "Extend bootloader kernel arguments"
2044 The command-line arguments provided by the boot loader will be
2045 appended to the default kernel command string.
2047 config CMDLINE_FORCE
2048 bool "Always use the default kernel command string"
2050 Always use the default kernel command string, even if the boot
2051 loader passes other arguments to the kernel.
2052 This is useful if you cannot or don't want to change the
2053 command-line options your boot loader passes to the kernel.
2057 bool "Kernel Execute-In-Place from ROM"
2058 depends on !ZBOOT_ROM && !ARM_LPAE
2060 Execute-In-Place allows the kernel to run from non-volatile storage
2061 directly addressable by the CPU, such as NOR flash. This saves RAM
2062 space since the text section of the kernel is not loaded from flash
2063 to RAM. Read-write sections, such as the data section and stack,
2064 are still copied to RAM. The XIP kernel is not compressed since
2065 it has to run directly from flash, so it will take more space to
2066 store it. The flash address used to link the kernel object files,
2067 and for storing it, is configuration dependent. Therefore, if you
2068 say Y here, you must know the proper physical address where to
2069 store the kernel image depending on your own flash memory usage.
2071 Also note that the make target becomes "make xipImage" rather than
2072 "make zImage" or "make Image". The final kernel binary to put in
2073 ROM memory will be arch/arm/boot/xipImage.
2077 config XIP_PHYS_ADDR
2078 hex "XIP Kernel Physical Location"
2079 depends on XIP_KERNEL
2080 default "0x00080000"
2082 This is the physical address in your flash memory the kernel will
2083 be linked for and stored to. This address is dependent on your
2087 bool "Kexec system call (EXPERIMENTAL)"
2088 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2090 kexec is a system call that implements the ability to shutdown your
2091 current kernel, and to start another kernel. It is like a reboot
2092 but it is independent of the system firmware. And like a reboot
2093 you can start any kernel with it, not just Linux.
2095 It is an ongoing process to be certain the hardware in a machine
2096 is properly shutdown, so do not be surprised if this code does not
2097 initially work for you. It may help to enable device hotplugging
2101 bool "Export atags in procfs"
2105 Should the atags used to boot the kernel be exported in an "atags"
2106 file in procfs. Useful with kexec.
2109 bool "Build kdump crash kernel (EXPERIMENTAL)"
2110 depends on EXPERIMENTAL
2112 Generate crash dump after being started by kexec. This should
2113 be normally only set in special crash dump kernels which are
2114 loaded in the main kernel with kexec-tools into a specially
2115 reserved region and then later executed after a crash by
2116 kdump/kexec. The crash dump kernel must be compiled to a
2117 memory address not used by the main kernel
2119 For more details see Documentation/kdump/kdump.txt
2121 config AUTO_ZRELADDR
2122 bool "Auto calculation of the decompressed kernel image address"
2123 depends on !ZBOOT_ROM && !ARCH_U300
2125 ZRELADDR is the physical address where the decompressed kernel
2126 image will be placed. If AUTO_ZRELADDR is selected, the address
2127 will be determined at run-time by masking the current IP with
2128 0xf8000000. This assumes the zImage being placed in the first 128MB
2129 from start of memory.
2133 menu "CPU Power Management"
2137 source "drivers/cpufreq/Kconfig"
2140 tristate "CPUfreq driver for i.MX CPUs"
2141 depends on ARCH_MXC && CPU_FREQ
2143 This enables the CPUfreq driver for i.MX CPUs.
2145 config CPU_FREQ_SA1100
2148 config CPU_FREQ_SA1110
2151 config CPU_FREQ_INTEGRATOR
2152 tristate "CPUfreq driver for ARM Integrator CPUs"
2153 depends on ARCH_INTEGRATOR && CPU_FREQ
2156 This enables the CPUfreq driver for ARM Integrator CPUs.
2158 For details, take a look at <file:Documentation/cpu-freq>.
2164 depends on CPU_FREQ && ARCH_PXA && PXA25x
2166 select CPU_FREQ_TABLE
2167 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2172 Internal configuration node for common cpufreq on Samsung SoC
2174 config CPU_FREQ_S3C24XX
2175 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2176 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2179 This enables the CPUfreq driver for the Samsung S3C24XX family
2182 For details, take a look at <file:Documentation/cpu-freq>.
2186 config CPU_FREQ_S3C24XX_PLL
2187 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2188 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2190 Compile in support for changing the PLL frequency from the
2191 S3C24XX series CPUfreq driver. The PLL takes time to settle
2192 after a frequency change, so by default it is not enabled.
2194 This also means that the PLL tables for the selected CPU(s) will
2195 be built which may increase the size of the kernel image.
2197 config CPU_FREQ_S3C24XX_DEBUG
2198 bool "Debug CPUfreq Samsung driver core"
2199 depends on CPU_FREQ_S3C24XX
2201 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2203 config CPU_FREQ_S3C24XX_IODEBUG
2204 bool "Debug CPUfreq Samsung driver IO timing"
2205 depends on CPU_FREQ_S3C24XX
2207 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2209 config CPU_FREQ_S3C24XX_DEBUGFS
2210 bool "Export debugfs for CPUFreq"
2211 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2213 Export status information via debugfs.
2217 source "drivers/cpuidle/Kconfig"
2221 menu "Floating point emulation"
2223 comment "At least one emulation must be selected"
2226 bool "NWFPE math emulation"
2227 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2229 Say Y to include the NWFPE floating point emulator in the kernel.
2230 This is necessary to run most binaries. Linux does not currently
2231 support floating point hardware so you need to say Y here even if
2232 your machine has an FPA or floating point co-processor podule.
2234 You may say N here if you are going to load the Acorn FPEmulator
2235 early in the bootup.
2238 bool "Support extended precision"
2239 depends on FPE_NWFPE
2241 Say Y to include 80-bit support in the kernel floating-point
2242 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2243 Note that gcc does not generate 80-bit operations by default,
2244 so in most cases this option only enlarges the size of the
2245 floating point emulator without any good reason.
2247 You almost surely want to say N here.
2250 bool "FastFPE math emulation (EXPERIMENTAL)"
2251 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2253 Say Y here to include the FAST floating point emulator in the kernel.
2254 This is an experimental much faster emulator which now also has full
2255 precision for the mantissa. It does not support any exceptions.
2256 It is very simple, and approximately 3-6 times faster than NWFPE.
2258 It should be sufficient for most programs. It may be not suitable
2259 for scientific calculations, but you have to check this for yourself.
2260 If you do not feel you need a faster FP emulation you should better
2264 bool "VFP-format floating point maths"
2265 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2267 Say Y to include VFP support code in the kernel. This is needed
2268 if your hardware includes a VFP unit.
2270 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2271 release notes and additional status information.
2273 Say N if your target does not have VFP hardware.
2281 bool "Advanced SIMD (NEON) Extension support"
2282 depends on VFPv3 && CPU_V7
2284 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2289 menu "Userspace binary formats"
2291 source "fs/Kconfig.binfmt"
2294 tristate "RISC OS personality"
2297 Say Y here to include the kernel code necessary if you want to run
2298 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2299 experimental; if this sounds frightening, say N and sleep in peace.
2300 You can also say M here to compile this support as a module (which
2301 will be called arthur).
2305 menu "Power management options"
2307 source "kernel/power/Kconfig"
2309 config ARCH_SUSPEND_POSSIBLE
2310 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2311 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2312 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2315 config ARM_CPU_SUSPEND
2320 source "net/Kconfig"
2322 source "drivers/Kconfig"
2326 source "arch/arm/Kconfig.debug"
2328 source "security/Kconfig"
2330 source "crypto/Kconfig"
2332 source "lib/Kconfig"