5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
72 select GENERIC_ALLOCATOR
83 The Extended Industry Standard Architecture (EISA) bus was
84 developed as an open alternative to the IBM MicroChannel bus.
86 The EISA bus provided some of the features of the IBM MicroChannel
87 bus while maintaining backward compatibility with cards made for
88 the older ISA bus. The EISA bus saw limited use between 1988 and
89 1995 when it was made obsolete by the PCI bus.
91 Say Y here if you are building a kernel for an EISA-based machine.
101 MicroChannel Architecture is found in some IBM PS/2 machines and
102 laptops. It is a bus system similar to PCI or ISA. See
103 <file:Documentation/mca.txt> (and especially the web page given
104 there) before attempting to build an MCA bus kernel.
106 config STACKTRACE_SUPPORT
110 config HAVE_LATENCYTOP_SUPPORT
115 config LOCKDEP_SUPPORT
119 config TRACE_IRQFLAGS_SUPPORT
123 config HARDIRQS_SW_RESEND
127 config GENERIC_IRQ_PROBE
131 config GENERIC_LOCKBREAK
134 depends on SMP && PREEMPT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config ARCH_HAS_CPU_IDLE_WAIT
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config GENERIC_ISA_DMA
187 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
188 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 The base address of exception vectors.
193 config ARM_PATCH_PHYS_VIRT
194 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
195 depends on EXPERIMENTAL
196 depends on !XIP_KERNEL && MMU
197 depends on !ARCH_REALVIEW || !SPARSEMEM
199 Patch phys-to-virt translation functions at runtime according to
200 the position of the kernel in system memory.
202 This can only be used with non-XIP with MMU kernels where
203 the base of physical memory is at a 16MB boundary.
205 config ARM_PATCH_PHYS_VIRT_16BIT
207 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
209 source "init/Kconfig"
211 source "kernel/Kconfig.freezer"
216 bool "MMU-based Paged Memory Management Support"
219 Select if you want MMU-based virtualised addressing space
220 support by paged memory management. If unsure, say 'Y'.
223 # The "ARM system type" choice list is ordered alphabetically by option
224 # text. Please add new entries in the option alphabetic order.
227 prompt "ARM system type"
228 default ARCH_VERSATILE
230 config ARCH_INTEGRATOR
231 bool "ARM Ltd. Integrator family"
233 select ARCH_HAS_CPUFREQ
236 select GENERIC_CLOCKEVENTS
237 select PLAT_VERSATILE
238 select PLAT_VERSATILE_FPGA_IRQ
240 Support for ARM's Integrator platform.
243 bool "ARM Ltd. RealView family"
247 select GENERIC_CLOCKEVENTS
248 select ARCH_WANT_OPTIONAL_GPIOLIB
249 select PLAT_VERSATILE
250 select PLAT_VERSATILE_CLCD
251 select ARM_TIMER_SP804
252 select GPIO_PL061 if GPIOLIB
254 This enables support for ARM Ltd RealView boards.
256 config ARCH_VERSATILE
257 bool "ARM Ltd. Versatile family"
262 select GENERIC_CLOCKEVENTS
263 select ARCH_WANT_OPTIONAL_GPIOLIB
264 select PLAT_VERSATILE
265 select PLAT_VERSATILE_CLCD
266 select PLAT_VERSATILE_FPGA_IRQ
267 select ARM_TIMER_SP804
269 This enables support for ARM Ltd Versatile board.
272 bool "ARM Ltd. Versatile Express family"
273 select ARCH_WANT_OPTIONAL_GPIOLIB
275 select ARM_TIMER_SP804
277 select GENERIC_CLOCKEVENTS
279 select HAVE_PATA_PLATFORM
281 select PLAT_VERSATILE
282 select PLAT_VERSATILE_CLCD
284 This enables support for the ARM Ltd Versatile Express boards.
288 select ARCH_REQUIRE_GPIOLIB
291 This enables support for systems based on the Atmel AT91RM9200,
292 AT91SAM9 and AT91CAP9 processors.
295 bool "Broadcom BCMRING"
300 select GENERIC_CLOCKEVENTS
301 select ARCH_WANT_OPTIONAL_GPIOLIB
303 Support for Broadcom's BCMRing platform.
306 bool "Cirrus Logic CLPS711x/EP721x-based"
308 select ARCH_USES_GETTIMEOFFSET
310 Support for Cirrus Logic 711x/721x based boards.
313 bool "Cavium Networks CNS3XXX family"
315 select GENERIC_CLOCKEVENTS
317 select MIGHT_HAVE_PCI
318 select PCI_DOMAINS if PCI
320 Support for Cavium Networks CNS3XXX platform.
323 bool "Cortina Systems Gemini"
325 select ARCH_REQUIRE_GPIOLIB
326 select ARCH_USES_GETTIMEOFFSET
328 Support for the Cortina Systems Gemini family SoCs
335 select ARCH_USES_GETTIMEOFFSET
337 This is an evaluation board for the StrongARM processor available
338 from Digital. It has limited hardware on-board, including an
339 Ethernet interface, two PCMCIA sockets, two serial ports and a
348 select ARCH_REQUIRE_GPIOLIB
349 select ARCH_HAS_HOLES_MEMORYMODEL
350 select ARCH_USES_GETTIMEOFFSET
352 This enables support for the Cirrus EP93xx series of CPUs.
354 config ARCH_FOOTBRIDGE
358 select GENERIC_CLOCKEVENTS
360 Support for systems based on the DC21285 companion chip
361 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
364 bool "Freescale MXC/iMX-based"
365 select GENERIC_CLOCKEVENTS
366 select ARCH_REQUIRE_GPIOLIB
369 Support for Freescale MXC/iMX-based family of processors
372 bool "Freescale MXS-based"
373 select GENERIC_CLOCKEVENTS
374 select ARCH_REQUIRE_GPIOLIB
377 Support for Freescale MXS-based family of processors
380 bool "Freescale STMP3xxx"
383 select ARCH_REQUIRE_GPIOLIB
384 select GENERIC_CLOCKEVENTS
385 select USB_ARCH_HAS_EHCI
387 Support for systems based on the Freescale 3xxx CPUs.
390 bool "Hilscher NetX based"
393 select GENERIC_CLOCKEVENTS
395 This enables support for systems based on the Hilscher NetX Soc
398 bool "Hynix HMS720x-based"
401 select ARCH_USES_GETTIMEOFFSET
403 This enables support for systems based on the Hynix HMS720x
411 select ARCH_SUPPORTS_MSI
414 Support for Intel's IOP13XX (XScale) family of processors.
422 select ARCH_REQUIRE_GPIOLIB
424 Support for Intel's 80219 and IOP32X (XScale) family of
433 select ARCH_REQUIRE_GPIOLIB
435 Support for Intel's IOP33X (XScale) family of processors.
442 select ARCH_USES_GETTIMEOFFSET
444 Support for Intel's IXP23xx (XScale) family of processors.
447 bool "IXP2400/2800-based"
451 select ARCH_USES_GETTIMEOFFSET
453 Support for Intel's IXP2400/2800 (XScale) family of processors.
460 select GENERIC_CLOCKEVENTS
461 select HAVE_SCHED_CLOCK
462 select MIGHT_HAVE_PCI
463 select DMABOUNCE if PCI
465 Support for Intel's IXP4XX (XScale) family of processors.
471 select ARCH_REQUIRE_GPIOLIB
472 select GENERIC_CLOCKEVENTS
475 Support for the Marvell Dove SoC 88AP510
478 bool "Marvell Kirkwood"
481 select ARCH_REQUIRE_GPIOLIB
482 select GENERIC_CLOCKEVENTS
485 Support for the following Marvell Kirkwood series SoCs:
486 88F6180, 88F6192 and 88F6281.
489 bool "Marvell Loki (88RC8480)"
491 select GENERIC_CLOCKEVENTS
494 Support for the Marvell Loki (88RC8480) SoC.
499 select ARCH_REQUIRE_GPIOLIB
502 select USB_ARCH_HAS_OHCI
505 select GENERIC_CLOCKEVENTS
507 Support for the NXP LPC32XX family of processors
510 bool "Marvell MV78xx0"
513 select ARCH_REQUIRE_GPIOLIB
514 select GENERIC_CLOCKEVENTS
517 Support for the following Marvell MV78xx0 series SoCs:
525 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
529 Support for the following Marvell Orion 5x series SoCs:
530 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
531 Orion-2 (5281), Orion-1-90 (6183).
534 bool "Marvell PXA168/910/MMP2"
536 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
539 select HAVE_SCHED_CLOCK
544 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
547 bool "Micrel/Kendin KS8695"
549 select ARCH_REQUIRE_GPIOLIB
550 select ARCH_USES_GETTIMEOFFSET
552 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
553 System-on-Chip devices.
556 bool "NetSilicon NS9xxx"
559 select GENERIC_CLOCKEVENTS
562 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
565 <http://www.digi.com/products/microprocessors/index.jsp>
568 bool "Nuvoton W90X900 CPU"
570 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
574 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
575 At present, the w90x900 has been renamed nuc900, regarding
576 the ARM series product line, you can login the following
577 link address to know more.
579 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
580 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
583 bool "Nuvoton NUC93X CPU"
587 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
588 low-power and high performance MPEG-4/JPEG multimedia controller chip.
594 select GENERIC_CLOCKEVENTS
597 select HAVE_SCHED_CLOCK
598 select ARCH_HAS_BARRIERS if CACHE_L2X0
599 select ARCH_HAS_CPUFREQ
601 This enables support for NVIDIA Tegra based systems (Tegra APX,
602 Tegra 6xx and Tegra 2 series).
605 bool "Philips Nexperia PNX4008 Mobile"
608 select ARCH_USES_GETTIMEOFFSET
610 This enables support for Philips PNX4008 mobile platform.
613 bool "PXA2xx/PXA3xx-based"
616 select ARCH_HAS_CPUFREQ
618 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
620 select HAVE_SCHED_CLOCK
625 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
630 select GENERIC_CLOCKEVENTS
631 select ARCH_REQUIRE_GPIOLIB
633 Support for Qualcomm MSM/QSD based systems. This runs on the
634 apps processor of the MSM/QSD and depends on a shared memory
635 interface to the modem processor which runs the baseband
636 stack and controls some vital subsystems
637 (clock and power control, etc).
640 bool "Renesas SH-Mobile / R-Mobile"
643 select GENERIC_CLOCKEVENTS
646 select MULTI_IRQ_HANDLER
648 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
655 select ARCH_MAY_HAVE_PC_FDC
656 select HAVE_PATA_PLATFORM
659 select ARCH_SPARSEMEM_ENABLE
660 select ARCH_USES_GETTIMEOFFSET
662 On the Acorn Risc-PC, Linux can support the internal IDE disk and
663 CD-ROM interface, serial and parallel port, and the floppy drive.
669 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_HAS_CPUFREQ
673 select GENERIC_CLOCKEVENTS
675 select HAVE_SCHED_CLOCK
677 select ARCH_REQUIRE_GPIOLIB
679 Support for StrongARM 11x0 based boards.
682 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
684 select ARCH_HAS_CPUFREQ
686 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_S3C2410_I2C if I2C
689 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
690 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
691 the Samsung SMDK2410 development board (and derivatives).
693 Note, the S3C2416 and the S3C2450 are so close that they even share
694 the same SoC ID code. This means that there is no seperate machine
695 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
698 bool "Samsung S3C64XX"
704 select ARCH_USES_GETTIMEOFFSET
705 select ARCH_HAS_CPUFREQ
706 select ARCH_REQUIRE_GPIOLIB
707 select SAMSUNG_CLKSRC
708 select SAMSUNG_IRQ_VIC_TIMER
709 select SAMSUNG_IRQ_UART
710 select S3C_GPIO_TRACK
711 select S3C_GPIO_PULL_UPDOWN
712 select S3C_GPIO_CFG_S3C24XX
713 select S3C_GPIO_CFG_S3C64XX
715 select USB_ARCH_HAS_OHCI
716 select SAMSUNG_GPIOLIB_4BIT
717 select HAVE_S3C2410_I2C if I2C
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
720 Samsung S3C64XX series based systems
723 bool "Samsung S5P6440 S5P6450"
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
728 select ARCH_USES_GETTIMEOFFSET
729 select HAVE_S3C2410_I2C if I2C
730 select HAVE_S3C_RTC if RTC_CLASS
732 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
736 bool "Samsung S5P6442"
740 select ARCH_USES_GETTIMEOFFSET
741 select HAVE_S3C2410_WATCHDOG if WATCHDOG
743 Samsung S5P6442 CPU based systems
746 bool "Samsung S5PC100"
750 select ARM_L1_CACHE_SHIFT_6
751 select ARCH_USES_GETTIMEOFFSET
752 select HAVE_S3C2410_I2C if I2C
753 select HAVE_S3C_RTC if RTC_CLASS
754 select HAVE_S3C2410_WATCHDOG if WATCHDOG
756 Samsung S5PC100 series based systems
759 bool "Samsung S5PV210/S5PC110"
761 select ARCH_SPARSEMEM_ENABLE
764 select ARM_L1_CACHE_SHIFT_6
765 select ARCH_HAS_CPUFREQ
766 select ARCH_USES_GETTIMEOFFSET
767 select HAVE_S3C2410_I2C if I2C
768 select HAVE_S3C_RTC if RTC_CLASS
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 Samsung S5PV210/S5PC110 series based systems
774 bool "Samsung S5PV310/S5PC210"
776 select ARCH_SPARSEMEM_ENABLE
779 select ARCH_HAS_CPUFREQ
780 select GENERIC_CLOCKEVENTS
781 select HAVE_S3C_RTC if RTC_CLASS
782 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 Samsung S5PV310 series based systems
794 select ARCH_USES_GETTIMEOFFSET
796 Support for the StrongARM based Digital DNARD machine, also known
797 as "Shark" (<http://www.shark-linux.de/shark.html>).
800 bool "Telechips TCC ARM926-based systems"
804 select GENERIC_CLOCKEVENTS
806 Support for Telechips TCC ARM926-based systems.
809 bool "ST-Ericsson U300 Series"
812 select HAVE_SCHED_CLOCK
816 select GENERIC_CLOCKEVENTS
820 Support for ST-Ericsson U300 series mobile platforms.
823 bool "ST-Ericsson U8500 Series"
826 select GENERIC_CLOCKEVENTS
828 select ARCH_REQUIRE_GPIOLIB
829 select ARCH_HAS_CPUFREQ
831 Support for ST-Ericsson's Ux500 architecture
834 bool "STMicroelectronics Nomadik"
839 select GENERIC_CLOCKEVENTS
840 select ARCH_REQUIRE_GPIOLIB
842 Support for the Nomadik platform by ST-Ericsson
846 select GENERIC_CLOCKEVENTS
847 select ARCH_REQUIRE_GPIOLIB
851 select GENERIC_ALLOCATOR
852 select ARCH_HAS_HOLES_MEMORYMODEL
854 Support for TI's DaVinci platform.
859 select ARCH_REQUIRE_GPIOLIB
860 select ARCH_HAS_CPUFREQ
861 select GENERIC_CLOCKEVENTS
862 select HAVE_SCHED_CLOCK
863 select ARCH_HAS_HOLES_MEMORYMODEL
865 Support for TI's OMAP platform (OMAP1/2/3/4).
870 select ARCH_REQUIRE_GPIOLIB
872 select GENERIC_CLOCKEVENTS
875 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
878 bool "VIA/WonderMedia 85xx"
881 select ARCH_HAS_CPUFREQ
882 select GENERIC_CLOCKEVENTS
883 select ARCH_REQUIRE_GPIOLIB
886 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
890 # This is sorted alphabetically by mach-* pathname. However, plat-*
891 # Kconfigs may be included either alphabetically (according to the
892 # plat- suffix) or along side the corresponding mach-* source.
894 source "arch/arm/mach-at91/Kconfig"
896 source "arch/arm/mach-bcmring/Kconfig"
898 source "arch/arm/mach-clps711x/Kconfig"
900 source "arch/arm/mach-cns3xxx/Kconfig"
902 source "arch/arm/mach-davinci/Kconfig"
904 source "arch/arm/mach-dove/Kconfig"
906 source "arch/arm/mach-ep93xx/Kconfig"
908 source "arch/arm/mach-footbridge/Kconfig"
910 source "arch/arm/mach-gemini/Kconfig"
912 source "arch/arm/mach-h720x/Kconfig"
914 source "arch/arm/mach-integrator/Kconfig"
916 source "arch/arm/mach-iop32x/Kconfig"
918 source "arch/arm/mach-iop33x/Kconfig"
920 source "arch/arm/mach-iop13xx/Kconfig"
922 source "arch/arm/mach-ixp4xx/Kconfig"
924 source "arch/arm/mach-ixp2000/Kconfig"
926 source "arch/arm/mach-ixp23xx/Kconfig"
928 source "arch/arm/mach-kirkwood/Kconfig"
930 source "arch/arm/mach-ks8695/Kconfig"
932 source "arch/arm/mach-loki/Kconfig"
934 source "arch/arm/mach-lpc32xx/Kconfig"
936 source "arch/arm/mach-msm/Kconfig"
938 source "arch/arm/mach-mv78xx0/Kconfig"
940 source "arch/arm/plat-mxc/Kconfig"
942 source "arch/arm/mach-mxs/Kconfig"
944 source "arch/arm/mach-netx/Kconfig"
946 source "arch/arm/mach-nomadik/Kconfig"
947 source "arch/arm/plat-nomadik/Kconfig"
949 source "arch/arm/mach-ns9xxx/Kconfig"
951 source "arch/arm/mach-nuc93x/Kconfig"
953 source "arch/arm/plat-omap/Kconfig"
955 source "arch/arm/mach-omap1/Kconfig"
957 source "arch/arm/mach-omap2/Kconfig"
959 source "arch/arm/mach-orion5x/Kconfig"
961 source "arch/arm/mach-pxa/Kconfig"
962 source "arch/arm/plat-pxa/Kconfig"
964 source "arch/arm/mach-mmp/Kconfig"
966 source "arch/arm/mach-realview/Kconfig"
968 source "arch/arm/mach-sa1100/Kconfig"
970 source "arch/arm/plat-samsung/Kconfig"
971 source "arch/arm/plat-s3c24xx/Kconfig"
972 source "arch/arm/plat-s5p/Kconfig"
974 source "arch/arm/plat-spear/Kconfig"
976 source "arch/arm/plat-tcc/Kconfig"
979 source "arch/arm/mach-s3c2400/Kconfig"
980 source "arch/arm/mach-s3c2410/Kconfig"
981 source "arch/arm/mach-s3c2412/Kconfig"
982 source "arch/arm/mach-s3c2416/Kconfig"
983 source "arch/arm/mach-s3c2440/Kconfig"
984 source "arch/arm/mach-s3c2443/Kconfig"
988 source "arch/arm/mach-s3c64xx/Kconfig"
991 source "arch/arm/mach-s5p64x0/Kconfig"
993 source "arch/arm/mach-s5p6442/Kconfig"
995 source "arch/arm/mach-s5pc100/Kconfig"
997 source "arch/arm/mach-s5pv210/Kconfig"
999 source "arch/arm/mach-s5pv310/Kconfig"
1001 source "arch/arm/mach-shmobile/Kconfig"
1003 source "arch/arm/plat-stmp3xxx/Kconfig"
1005 source "arch/arm/mach-tegra/Kconfig"
1007 source "arch/arm/mach-u300/Kconfig"
1009 source "arch/arm/mach-ux500/Kconfig"
1011 source "arch/arm/mach-versatile/Kconfig"
1013 source "arch/arm/mach-vexpress/Kconfig"
1014 source "arch/arm/plat-versatile/Kconfig"
1016 source "arch/arm/mach-vt8500/Kconfig"
1018 source "arch/arm/mach-w90x900/Kconfig"
1020 # Definitions to make life easier
1026 select GENERIC_CLOCKEVENTS
1027 select HAVE_SCHED_CLOCK
1031 select HAVE_SCHED_CLOCK
1036 config PLAT_VERSATILE
1039 config ARM_TIMER_SP804
1042 source arch/arm/mm/Kconfig
1045 bool "Enable iWMMXt support"
1046 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1047 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1049 Enable support for iWMMXt context switching at run time if
1050 running on a CPU that supports it.
1052 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1055 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1059 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1060 (!ARCH_OMAP3 || OMAP3_EMU)
1064 config MULTI_IRQ_HANDLER
1067 Allow each machine to specify it's own IRQ handler at run time.
1070 source "arch/arm/Kconfig-nommu"
1073 config ARM_ERRATA_411920
1074 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1075 depends on CPU_V6 || CPU_V6K
1077 Invalidation of the Instruction Cache operation can
1078 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1079 It does not affect the MPCore. This option enables the ARM Ltd.
1080 recommended workaround.
1082 config ARM_ERRATA_430973
1083 bool "ARM errata: Stale prediction on replaced interworking branch"
1086 This option enables the workaround for the 430973 Cortex-A8
1087 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1088 interworking branch is replaced with another code sequence at the
1089 same virtual address, whether due to self-modifying code or virtual
1090 to physical address re-mapping, Cortex-A8 does not recover from the
1091 stale interworking branch prediction. This results in Cortex-A8
1092 executing the new code sequence in the incorrect ARM or Thumb state.
1093 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1094 and also flushes the branch target cache at every context switch.
1095 Note that setting specific bits in the ACTLR register may not be
1096 available in non-secure mode.
1098 config ARM_ERRATA_458693
1099 bool "ARM errata: Processor deadlock when a false hazard is created"
1102 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1103 erratum. For very specific sequences of memory operations, it is
1104 possible for a hazard condition intended for a cache line to instead
1105 be incorrectly associated with a different cache line. This false
1106 hazard might then cause a processor deadlock. The workaround enables
1107 the L1 caching of the NEON accesses and disables the PLD instruction
1108 in the ACTLR register. Note that setting specific bits in the ACTLR
1109 register may not be available in non-secure mode.
1111 config ARM_ERRATA_460075
1112 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1115 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1116 erratum. Any asynchronous access to the L2 cache may encounter a
1117 situation in which recent store transactions to the L2 cache are lost
1118 and overwritten with stale memory contents from external memory. The
1119 workaround disables the write-allocate mode for the L2 cache via the
1120 ACTLR register. Note that setting specific bits in the ACTLR register
1121 may not be available in non-secure mode.
1123 config ARM_ERRATA_742230
1124 bool "ARM errata: DMB operation may be faulty"
1125 depends on CPU_V7 && SMP
1127 This option enables the workaround for the 742230 Cortex-A9
1128 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1129 between two write operations may not ensure the correct visibility
1130 ordering of the two writes. This workaround sets a specific bit in
1131 the diagnostic register of the Cortex-A9 which causes the DMB
1132 instruction to behave as a DSB, ensuring the correct behaviour of
1135 config ARM_ERRATA_742231
1136 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1137 depends on CPU_V7 && SMP
1139 This option enables the workaround for the 742231 Cortex-A9
1140 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1141 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1142 accessing some data located in the same cache line, may get corrupted
1143 data due to bad handling of the address hazard when the line gets
1144 replaced from one of the CPUs at the same time as another CPU is
1145 accessing it. This workaround sets specific bits in the diagnostic
1146 register of the Cortex-A9 which reduces the linefill issuing
1147 capabilities of the processor.
1149 config PL310_ERRATA_588369
1150 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1151 depends on CACHE_L2X0
1153 The PL310 L2 cache controller implements three types of Clean &
1154 Invalidate maintenance operations: by Physical Address
1155 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1156 They are architecturally defined to behave as the execution of a
1157 clean operation followed immediately by an invalidate operation,
1158 both performing to the same memory location. This functionality
1159 is not correctly implemented in PL310 as clean lines are not
1160 invalidated as a result of these operations.
1162 config ARM_ERRATA_720789
1163 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1164 depends on CPU_V7 && SMP
1166 This option enables the workaround for the 720789 Cortex-A9 (prior to
1167 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1168 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1169 As a consequence of this erratum, some TLB entries which should be
1170 invalidated are not, resulting in an incoherency in the system page
1171 tables. The workaround changes the TLB flushing routines to invalidate
1172 entries regardless of the ASID.
1174 config PL310_ERRATA_727915
1175 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1176 depends on CACHE_L2X0
1178 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1179 operation (offset 0x7FC). This operation runs in background so that
1180 PL310 can handle normal accesses while it is in progress. Under very
1181 rare circumstances, due to this erratum, write data can be lost when
1182 PL310 treats a cacheable write transaction during a Clean &
1183 Invalidate by Way operation.
1185 config ARM_ERRATA_743622
1186 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1189 This option enables the workaround for the 743622 Cortex-A9
1190 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1191 optimisation in the Cortex-A9 Store Buffer may lead to data
1192 corruption. This workaround sets a specific bit in the diagnostic
1193 register of the Cortex-A9 which disables the Store Buffer
1194 optimisation, preventing the defect from occurring. This has no
1195 visible impact on the overall performance or power consumption of the
1198 config ARM_ERRATA_751472
1199 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1200 depends on CPU_V7 && SMP
1202 This option enables the workaround for the 751472 Cortex-A9 (prior
1203 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1204 completion of a following broadcasted operation if the second
1205 operation is received by a CPU before the ICIALLUIS has completed,
1206 potentially leading to corrupted entries in the cache or TLB.
1208 config ARM_ERRATA_753970
1209 bool "ARM errata: cache sync operation may be faulty"
1210 depends on CACHE_PL310
1212 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1214 Under some condition the effect of cache sync operation on
1215 the store buffer still remains when the operation completes.
1216 This means that the store buffer is always asked to drain and
1217 this prevents it from merging any further writes. The workaround
1218 is to replace the normal offset of cache sync operation (0x730)
1219 by another offset targeting an unmapped PL310 register 0x740.
1220 This has the same effect as the cache sync operation: store buffer
1221 drain and waiting for all buffers empty.
1223 config ARM_ERRATA_754322
1224 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1227 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1228 r3p*) erratum. A speculative memory access may cause a page table walk
1229 which starts prior to an ASID switch but completes afterwards. This
1230 can populate the micro-TLB with a stale entry which may be hit with
1231 the new ASID. This workaround places two dsb instructions in the mm
1232 switching code so that no page table walks can cross the ASID switch.
1234 config ARM_ERRATA_754327
1235 bool "ARM errata: no automatic Store Buffer drain"
1236 depends on CPU_V7 && SMP
1238 This option enables the workaround for the 754327 Cortex-A9 (prior to
1239 r2p0) erratum. The Store Buffer does not have any automatic draining
1240 mechanism and therefore a livelock may occur if an external agent
1241 continuously polls a memory location waiting to observe an update.
1242 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1243 written polling loops from denying visibility of updates to memory.
1247 source "arch/arm/common/Kconfig"
1257 Find out whether you have ISA slots on your motherboard. ISA is the
1258 name of a bus system, i.e. the way the CPU talks to the other stuff
1259 inside your box. Other bus systems are PCI, EISA, MicroChannel
1260 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1261 newer boards don't support it. If you have ISA, say Y, otherwise N.
1263 # Select ISA DMA controller support
1268 # Select ISA DMA interface
1273 bool "PCI support" if MIGHT_HAVE_PCI
1275 Find out whether you have a PCI motherboard. PCI is the name of a
1276 bus system, i.e. the way the CPU talks to the other stuff inside
1277 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1278 VESA. If you have PCI, say Y, otherwise N.
1284 config PCI_NANOENGINE
1285 bool "BSE nanoEngine PCI support"
1286 depends on SA1100_NANOENGINE
1288 Enable PCI on the BSE nanoEngine board.
1293 # Select the host bridge type
1294 config PCI_HOST_VIA82C505
1296 depends on PCI && ARCH_SHARK
1299 config PCI_HOST_ITE8152
1301 depends on PCI && MACH_ARMCORE
1305 source "drivers/pci/Kconfig"
1307 source "drivers/pcmcia/Kconfig"
1311 menu "Kernel Features"
1313 source "kernel/time/Kconfig"
1316 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1317 depends on EXPERIMENTAL
1318 depends on CPU_V6K || CPU_V7
1319 depends on GENERIC_CLOCKEVENTS
1320 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1321 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1322 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1323 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1324 select USE_GENERIC_SMP_HELPERS
1325 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1327 This enables support for systems with more than one CPU. If you have
1328 a system with only one CPU, like most personal computers, say N. If
1329 you have a system with more than one CPU, say Y.
1331 If you say N here, the kernel will run on single and multiprocessor
1332 machines, but will use only one CPU of a multiprocessor machine. If
1333 you say Y here, the kernel will run on many, but not all, single
1334 processor machines. On a single processor machine, the kernel will
1335 run faster if you say N here.
1337 See also <file:Documentation/i386/IO-APIC.txt>,
1338 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1339 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1341 If you don't know what to do here, say N.
1344 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1345 depends on EXPERIMENTAL
1346 depends on SMP && !XIP_KERNEL
1349 SMP kernels contain instructions which fail on non-SMP processors.
1350 Enabling this option allows the kernel to modify itself to make
1351 these instructions safe. Disabling it allows about 1K of space
1354 If you don't know what to do here, say Y.
1360 This option enables support for the ARM system coherency unit
1367 This options enables support for the ARM timer and watchdog unit
1370 prompt "Memory split"
1373 Select the desired split between kernel and user memory.
1375 If you are not absolutely sure what you are doing, leave this
1379 bool "3G/1G user/kernel split"
1381 bool "2G/2G user/kernel split"
1383 bool "1G/3G user/kernel split"
1388 default 0x40000000 if VMSPLIT_1G
1389 default 0x80000000 if VMSPLIT_2G
1393 int "Maximum number of CPUs (2-32)"
1399 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1400 depends on SMP && HOTPLUG && EXPERIMENTAL
1401 depends on !ARCH_MSM
1403 Say Y here to experiment with turning CPUs off and on. CPUs
1404 can be controlled through /sys/devices/system/cpu.
1407 bool "Use local timer interrupts"
1410 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1412 Enable support for local timers on SMP platforms, rather then the
1413 legacy IPI broadcast method. Local timers allows the system
1414 accounting to be spread across the timer interval, preventing a
1415 "thundering herd" at every timer tick.
1417 source kernel/Kconfig.preempt
1421 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1422 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1423 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1424 default AT91_TIMER_HZ if ARCH_AT91
1425 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1428 config THUMB2_KERNEL
1429 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1430 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1432 select ARM_ASM_UNIFIED
1434 By enabling this option, the kernel will be compiled in
1435 Thumb-2 mode. A compiler/assembler that understand the unified
1436 ARM-Thumb syntax is needed.
1440 config THUMB2_AVOID_R_ARM_THM_JUMP11
1441 bool "Work around buggy Thumb-2 short branch relocations in gas"
1442 depends on THUMB2_KERNEL && MODULES
1445 Various binutils versions can resolve Thumb-2 branches to
1446 locally-defined, preemptible global symbols as short-range "b.n"
1447 branch instructions.
1449 This is a problem, because there's no guarantee the final
1450 destination of the symbol, or any candidate locations for a
1451 trampoline, are within range of the branch. For this reason, the
1452 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1453 relocation in modules at all, and it makes little sense to add
1456 The symptom is that the kernel fails with an "unsupported
1457 relocation" error when loading some modules.
1459 Until fixed tools are available, passing
1460 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1461 code which hits this problem, at the cost of a bit of extra runtime
1462 stack usage in some cases.
1464 The problem is described in more detail at:
1465 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1467 Only Thumb-2 kernels are affected.
1469 Unless you are sure your tools don't have this problem, say Y.
1471 config ARM_ASM_UNIFIED
1475 bool "Use the ARM EABI to compile the kernel"
1477 This option allows for the kernel to be compiled using the latest
1478 ARM ABI (aka EABI). This is only useful if you are using a user
1479 space environment that is also compiled with EABI.
1481 Since there are major incompatibilities between the legacy ABI and
1482 EABI, especially with regard to structure member alignment, this
1483 option also changes the kernel syscall calling convention to
1484 disambiguate both ABIs and allow for backward compatibility support
1485 (selected with CONFIG_OABI_COMPAT).
1487 To use this you need GCC version 4.0.0 or later.
1490 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1491 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1494 This option preserves the old syscall interface along with the
1495 new (ARM EABI) one. It also provides a compatibility layer to
1496 intercept syscalls that have structure arguments which layout
1497 in memory differs between the legacy ABI and the new ARM EABI
1498 (only for non "thumb" binaries). This option adds a tiny
1499 overhead to all syscalls and produces a slightly larger kernel.
1500 If you know you'll be using only pure EABI user space then you
1501 can say N here. If this option is not selected and you attempt
1502 to execute a legacy ABI binary then the result will be
1503 UNPREDICTABLE (in fact it can be predicted that it won't work
1504 at all). If in doubt say Y.
1506 config ARCH_HAS_HOLES_MEMORYMODEL
1509 config ARCH_SPARSEMEM_ENABLE
1512 config ARCH_SPARSEMEM_DEFAULT
1513 def_bool ARCH_SPARSEMEM_ENABLE
1515 config ARCH_SELECT_MEMORY_MODEL
1516 def_bool ARCH_SPARSEMEM_ENABLE
1519 bool "High Memory Support (EXPERIMENTAL)"
1520 depends on MMU && EXPERIMENTAL
1522 The address space of ARM processors is only 4 Gigabytes large
1523 and it has to accommodate user address space, kernel address
1524 space as well as some memory mapped IO. That means that, if you
1525 have a large amount of physical memory and/or IO, not all of the
1526 memory can be "permanently mapped" by the kernel. The physical
1527 memory that is not permanently mapped is called "high memory".
1529 Depending on the selected kernel/user memory split, minimum
1530 vmalloc space and actual amount of RAM, you may not need this
1531 option which should result in a slightly faster kernel.
1536 bool "Allocate 2nd-level pagetables from highmem"
1538 depends on !OUTER_CACHE
1540 config HW_PERF_EVENTS
1541 bool "Enable hardware performance counter support for perf events"
1542 depends on PERF_EVENTS && CPU_HAS_PMU
1545 Enable hardware performance counter support for perf events. If
1546 disabled, perf events will use software events only.
1550 config FORCE_MAX_ZONEORDER
1551 int "Maximum zone order" if ARCH_SHMOBILE
1552 range 11 64 if ARCH_SHMOBILE
1553 default "9" if SA1111
1556 The kernel memory allocator divides physically contiguous memory
1557 blocks into "zones", where each zone is a power of two number of
1558 pages. This option selects the largest power of two that the kernel
1559 keeps in the memory allocator. If you need to allocate very large
1560 blocks of physically contiguous memory, then you may need to
1561 increase this value.
1563 This config option is actually maximum order plus one. For example,
1564 a value of 11 means that the largest free memory block is 2^10 pages.
1567 bool "Timer and CPU usage LEDs"
1568 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1569 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1570 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1571 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1572 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1573 ARCH_AT91 || ARCH_DAVINCI || \
1574 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1576 If you say Y here, the LEDs on your machine will be used
1577 to provide useful information about your current system status.
1579 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1580 be able to select which LEDs are active using the options below. If
1581 you are compiling a kernel for the EBSA-110 or the LART however, the
1582 red LED will simply flash regularly to indicate that the system is
1583 still functional. It is safe to say Y here if you have a CATS
1584 system, but the driver will do nothing.
1587 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1588 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1589 || MACH_OMAP_PERSEUS2
1591 depends on !GENERIC_CLOCKEVENTS
1592 default y if ARCH_EBSA110
1594 If you say Y here, one of the system LEDs (the green one on the
1595 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1596 will flash regularly to indicate that the system is still
1597 operational. This is mainly useful to kernel hackers who are
1598 debugging unstable kernels.
1600 The LART uses the same LED for both Timer LED and CPU usage LED
1601 functions. You may choose to use both, but the Timer LED function
1602 will overrule the CPU usage LED.
1605 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1607 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1608 || MACH_OMAP_PERSEUS2
1611 If you say Y here, the red LED will be used to give a good real
1612 time indication of CPU usage, by lighting whenever the idle task
1613 is not currently executing.
1615 The LART uses the same LED for both Timer LED and CPU usage LED
1616 functions. You may choose to use both, but the Timer LED function
1617 will overrule the CPU usage LED.
1619 config ALIGNMENT_TRAP
1621 depends on CPU_CP15_MMU
1622 default y if !ARCH_EBSA110
1623 select HAVE_PROC_CPU if PROC_FS
1625 ARM processors cannot fetch/store information which is not
1626 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1627 address divisible by 4. On 32-bit ARM processors, these non-aligned
1628 fetch/store instructions will be emulated in software if you say
1629 here, which has a severe performance impact. This is necessary for
1630 correct operation of some network protocols. With an IP-only
1631 configuration it is safe to say N, otherwise say Y.
1633 config UACCESS_WITH_MEMCPY
1634 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1635 depends on MMU && EXPERIMENTAL
1636 default y if CPU_FEROCEON
1638 Implement faster copy_to_user and clear_user methods for CPU
1639 cores where a 8-word STM instruction give significantly higher
1640 memory write throughput than a sequence of individual 32bit stores.
1642 A possible side effect is a slight increase in scheduling latency
1643 between threads sharing the same address space if they invoke
1644 such copy operations with large buffers.
1646 However, if the CPU data cache is using a write-allocate mode,
1647 this option is unlikely to provide any performance gain.
1651 prompt "Enable seccomp to safely compute untrusted bytecode"
1653 This kernel feature is useful for number crunching applications
1654 that may need to compute untrusted bytecode during their
1655 execution. By using pipes or other transports made available to
1656 the process as file descriptors supporting the read/write
1657 syscalls, it's possible to isolate those applications in
1658 their own address space using seccomp. Once seccomp is
1659 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1660 and the task is only allowed to execute a few safe syscalls
1661 defined by each seccomp mode.
1663 config CC_STACKPROTECTOR
1664 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1665 depends on EXPERIMENTAL
1667 This option turns on the -fstack-protector GCC feature. This
1668 feature puts, at the beginning of functions, a canary value on
1669 the stack just before the return address, and validates
1670 the value just before actually returning. Stack based buffer
1671 overflows (that need to overwrite this return address) now also
1672 overwrite the canary, which gets detected and the attack is then
1673 neutralized via a kernel panic.
1674 This feature requires gcc version 4.2 or above.
1676 config DEPRECATED_PARAM_STRUCT
1677 bool "Provide old way to pass kernel parameters"
1679 This was deprecated in 2001 and announced to live on for 5 years.
1680 Some old boot loaders still use this way.
1686 # Compressed boot loader in ROM. Yes, we really want to ask about
1687 # TEXT and BSS so we preserve their values in the config files.
1688 config ZBOOT_ROM_TEXT
1689 hex "Compressed ROM boot loader base address"
1692 The physical address at which the ROM-able zImage is to be
1693 placed in the target. Platforms which normally make use of
1694 ROM-able zImage formats normally set this to a suitable
1695 value in their defconfig file.
1697 If ZBOOT_ROM is not enabled, this has no effect.
1699 config ZBOOT_ROM_BSS
1700 hex "Compressed ROM boot loader BSS address"
1703 The base address of an area of read/write memory in the target
1704 for the ROM-able zImage which must be available while the
1705 decompressor is running. It must be large enough to hold the
1706 entire decompressed kernel plus an additional 128 KiB.
1707 Platforms which normally make use of ROM-able zImage formats
1708 normally set this to a suitable value in their defconfig file.
1710 If ZBOOT_ROM is not enabled, this has no effect.
1713 bool "Compressed boot loader in ROM/flash"
1714 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1716 Say Y here if you intend to execute your compressed kernel image
1717 (zImage) directly from ROM or flash. If unsure, say N.
1719 config ZBOOT_ROM_MMCIF
1720 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1721 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1723 Say Y here to include experimental MMCIF loading code in the
1724 ROM-able zImage. With this enabled it is possible to write the
1725 the ROM-able zImage kernel image to an MMC card and boot the
1726 kernel straight from the reset vector. At reset the processor
1727 Mask ROM will load the first part of the the ROM-able zImage
1728 which in turn loads the rest the kernel image to RAM using the
1729 MMCIF hardware block.
1732 string "Default kernel command string"
1735 On some architectures (EBSA110 and CATS), there is currently no way
1736 for the boot loader to pass arguments to the kernel. For these
1737 architectures, you should supply some command-line options at build
1738 time by entering them here. As a minimum, you should specify the
1739 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1741 config CMDLINE_FORCE
1742 bool "Always use the default kernel command string"
1743 depends on CMDLINE != ""
1745 Always use the default kernel command string, even if the boot
1746 loader passes other arguments to the kernel.
1747 This is useful if you cannot or don't want to change the
1748 command-line options your boot loader passes to the kernel.
1753 bool "Kernel Execute-In-Place from ROM"
1754 depends on !ZBOOT_ROM
1756 Execute-In-Place allows the kernel to run from non-volatile storage
1757 directly addressable by the CPU, such as NOR flash. This saves RAM
1758 space since the text section of the kernel is not loaded from flash
1759 to RAM. Read-write sections, such as the data section and stack,
1760 are still copied to RAM. The XIP kernel is not compressed since
1761 it has to run directly from flash, so it will take more space to
1762 store it. The flash address used to link the kernel object files,
1763 and for storing it, is configuration dependent. Therefore, if you
1764 say Y here, you must know the proper physical address where to
1765 store the kernel image depending on your own flash memory usage.
1767 Also note that the make target becomes "make xipImage" rather than
1768 "make zImage" or "make Image". The final kernel binary to put in
1769 ROM memory will be arch/arm/boot/xipImage.
1773 config XIP_PHYS_ADDR
1774 hex "XIP Kernel Physical Location"
1775 depends on XIP_KERNEL
1776 default "0x00080000"
1778 This is the physical address in your flash memory the kernel will
1779 be linked for and stored to. This address is dependent on your
1783 bool "Kexec system call (EXPERIMENTAL)"
1784 depends on EXPERIMENTAL
1786 kexec is a system call that implements the ability to shutdown your
1787 current kernel, and to start another kernel. It is like a reboot
1788 but it is independent of the system firmware. And like a reboot
1789 you can start any kernel with it, not just Linux.
1791 It is an ongoing process to be certain the hardware in a machine
1792 is properly shutdown, so do not be surprised if this code does not
1793 initially work for you. It may help to enable device hotplugging
1797 bool "Export atags in procfs"
1801 Should the atags used to boot the kernel be exported in an "atags"
1802 file in procfs. Useful with kexec.
1805 bool "Build kdump crash kernel (EXPERIMENTAL)"
1806 depends on EXPERIMENTAL
1808 Generate crash dump after being started by kexec. This should
1809 be normally only set in special crash dump kernels which are
1810 loaded in the main kernel with kexec-tools into a specially
1811 reserved region and then later executed after a crash by
1812 kdump/kexec. The crash dump kernel must be compiled to a
1813 memory address not used by the main kernel
1815 For more details see Documentation/kdump/kdump.txt
1817 config AUTO_ZRELADDR
1818 bool "Auto calculation of the decompressed kernel image address"
1819 depends on !ZBOOT_ROM && !ARCH_U300
1821 ZRELADDR is the physical address where the decompressed kernel
1822 image will be placed. If AUTO_ZRELADDR is selected, the address
1823 will be determined at run-time by masking the current IP with
1824 0xf8000000. This assumes the zImage being placed in the first 128MB
1825 from start of memory.
1829 menu "CPU Power Management"
1833 source "drivers/cpufreq/Kconfig"
1836 tristate "CPUfreq driver for i.MX CPUs"
1837 depends on ARCH_MXC && CPU_FREQ
1839 This enables the CPUfreq driver for i.MX CPUs.
1841 config CPU_FREQ_SA1100
1844 config CPU_FREQ_SA1110
1847 config CPU_FREQ_INTEGRATOR
1848 tristate "CPUfreq driver for ARM Integrator CPUs"
1849 depends on ARCH_INTEGRATOR && CPU_FREQ
1852 This enables the CPUfreq driver for ARM Integrator CPUs.
1854 For details, take a look at <file:Documentation/cpu-freq>.
1860 depends on CPU_FREQ && ARCH_PXA && PXA25x
1862 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1864 config CPU_FREQ_S3C64XX
1865 bool "CPUfreq support for Samsung S3C64XX CPUs"
1866 depends on CPU_FREQ && CPU_S3C6410
1871 Internal configuration node for common cpufreq on Samsung SoC
1873 config CPU_FREQ_S3C24XX
1874 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1875 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1878 This enables the CPUfreq driver for the Samsung S3C24XX family
1881 For details, take a look at <file:Documentation/cpu-freq>.
1885 config CPU_FREQ_S3C24XX_PLL
1886 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1887 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1889 Compile in support for changing the PLL frequency from the
1890 S3C24XX series CPUfreq driver. The PLL takes time to settle
1891 after a frequency change, so by default it is not enabled.
1893 This also means that the PLL tables for the selected CPU(s) will
1894 be built which may increase the size of the kernel image.
1896 config CPU_FREQ_S3C24XX_DEBUG
1897 bool "Debug CPUfreq Samsung driver core"
1898 depends on CPU_FREQ_S3C24XX
1900 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1902 config CPU_FREQ_S3C24XX_IODEBUG
1903 bool "Debug CPUfreq Samsung driver IO timing"
1904 depends on CPU_FREQ_S3C24XX
1906 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1908 config CPU_FREQ_S3C24XX_DEBUGFS
1909 bool "Export debugfs for CPUFreq"
1910 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1912 Export status information via debugfs.
1916 source "drivers/cpuidle/Kconfig"
1920 menu "Floating point emulation"
1922 comment "At least one emulation must be selected"
1925 bool "NWFPE math emulation"
1926 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1928 Say Y to include the NWFPE floating point emulator in the kernel.
1929 This is necessary to run most binaries. Linux does not currently
1930 support floating point hardware so you need to say Y here even if
1931 your machine has an FPA or floating point co-processor podule.
1933 You may say N here if you are going to load the Acorn FPEmulator
1934 early in the bootup.
1937 bool "Support extended precision"
1938 depends on FPE_NWFPE
1940 Say Y to include 80-bit support in the kernel floating-point
1941 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1942 Note that gcc does not generate 80-bit operations by default,
1943 so in most cases this option only enlarges the size of the
1944 floating point emulator without any good reason.
1946 You almost surely want to say N here.
1949 bool "FastFPE math emulation (EXPERIMENTAL)"
1950 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1952 Say Y here to include the FAST floating point emulator in the kernel.
1953 This is an experimental much faster emulator which now also has full
1954 precision for the mantissa. It does not support any exceptions.
1955 It is very simple, and approximately 3-6 times faster than NWFPE.
1957 It should be sufficient for most programs. It may be not suitable
1958 for scientific calculations, but you have to check this for yourself.
1959 If you do not feel you need a faster FP emulation you should better
1963 bool "VFP-format floating point maths"
1964 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1966 Say Y to include VFP support code in the kernel. This is needed
1967 if your hardware includes a VFP unit.
1969 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1970 release notes and additional status information.
1972 Say N if your target does not have VFP hardware.
1980 bool "Advanced SIMD (NEON) Extension support"
1981 depends on VFPv3 && CPU_V7
1983 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1988 menu "Userspace binary formats"
1990 source "fs/Kconfig.binfmt"
1993 tristate "RISC OS personality"
1996 Say Y here to include the kernel code necessary if you want to run
1997 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1998 experimental; if this sounds frightening, say N and sleep in peace.
1999 You can also say M here to compile this support as a module (which
2000 will be called arthur).
2004 menu "Power management options"
2006 source "kernel/power/Kconfig"
2008 config ARCH_SUSPEND_POSSIBLE
2013 source "net/Kconfig"
2015 source "drivers/Kconfig"
2019 source "arch/arm/Kconfig.debug"
2021 source "security/Kconfig"
2023 source "crypto/Kconfig"
2025 source "lib/Kconfig"