arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select GENERIC_ALLOCATOR
  20         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  21         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  22         select GENERIC_IDLE_POLL_SETUP
  23         select GENERIC_IRQ_PROBE
  24         select GENERIC_IRQ_SHOW
  25         select GENERIC_PCI_IOMAP
  26         select GENERIC_SCHED_CLOCK
  27         select GENERIC_SMP_IDLE_THREAD
  28         select GENERIC_STRNCPY_FROM_USER
  29         select GENERIC_STRNLEN_USER
  30         select HANDLE_DOMAIN_IRQ
  31         select HARDIRQS_SW_RESEND
  32         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  33         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  34         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  35         select HAVE_ARCH_KGDB
  36         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_TRACEHOOK
  38         select HAVE_BPF_JIT
  39         select HAVE_CC_STACKPROTECTOR
  40         select HAVE_CONTEXT_TRACKING
  41         select HAVE_C_RECORDMCOUNT
  42         select HAVE_DEBUG_KMEMLEAK
  43         select HAVE_DMA_API_DEBUG
  44         select HAVE_DMA_ATTRS
  45         select HAVE_DMA_CONTIGUOUS if MMU
  46         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  47         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  48         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  49         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  50         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  51         select HAVE_GENERIC_DMA_COHERENT
  52         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  53         select HAVE_IDE if PCI || ISA || PCMCIA
  54         select HAVE_IRQ_TIME_ACCOUNTING
  55         select HAVE_KERNEL_GZIP
  56         select HAVE_KERNEL_LZ4
  57         select HAVE_KERNEL_LZMA
  58         select HAVE_KERNEL_LZO
  59         select HAVE_KERNEL_XZ
  60         select HAVE_KPROBES if !XIP_KERNEL
  61         select HAVE_KRETPROBES if (HAVE_KPROBES)
  62         select HAVE_MEMBLOCK
  63         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  64         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  65         select HAVE_OPTPROBES if !THUMB2_KERNEL
  66         select HAVE_PERF_EVENTS
  67         select HAVE_PERF_REGS
  68         select HAVE_PERF_USER_STACK_DUMP
  69         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  70         select HAVE_REGS_AND_STACK_ACCESS_API
  71         select HAVE_SYSCALL_TRACEPOINTS
  72         select HAVE_UID16
  73         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  74         select IRQ_FORCED_THREADING
  75         select MODULES_USE_ELF_REL
  76         select NO_BOOTMEM
  77         select OLD_SIGACTION
  78         select OLD_SIGSUSPEND3
  79         select PERF_USE_VMALLOC
  80         select RTC_LIB
  81         select SYS_SUPPORTS_APM_EMULATION
  82         # Above selects are sorted alphabetically; please add new ones
  83         # according to that.  Thanks.
  84         help
  85           The ARM series is a line of low-power-consumption RISC chip designs
  86           licensed by ARM Ltd and targeted at embedded applications and
  87           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  88           manufactured, but legacy ARM-based PC hardware remains popular in
  89           Europe.  There is an ARM Linux project with a web page at
  90           <http://www.arm.linux.org.uk/>.
  91
  92 config ARM_HAS_SG_CHAIN
  93         select ARCH_HAS_SG_CHAIN
  94         bool
  95
  96 config NEED_SG_DMA_LENGTH
  97         bool
  98
  99 config ARM_DMA_USE_IOMMU
 100         bool
 101         select ARM_HAS_SG_CHAIN
 102         select NEED_SG_DMA_LENGTH
 103
 104 if ARM_DMA_USE_IOMMU
 105
 106 config ARM_DMA_IOMMU_ALIGNMENT
 107         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 108         range 4 9
 109         default 8
 110         help
 111           DMA mapping framework by default aligns all buffers to the smallest
 112           PAGE_SIZE order which is greater than or equal to the requested buffer
 113           size. This works well for buffers up to a few hundreds kilobytes, but
 114           for larger buffers it just a waste of address space. Drivers which has
 115           relatively small addressing window (like 64Mib) might run out of
 116           virtual space with just a few allocations.
 117
 118           With this parameter you can specify the maximum PAGE_SIZE order for
 119           DMA IOMMU buffers. Larger buffers will be aligned only to this
 120           specified order. The order is expressed as a power of two multiplied
 121           by the PAGE_SIZE.
 122
 123 endif
 124
 125 config MIGHT_HAVE_PCI
 126         bool
 127
 128 config SYS_SUPPORTS_APM_EMULATION
 129         bool
 130
 131 config HAVE_TCM
 132         bool
 133         select GENERIC_ALLOCATOR
 134
 135 config HAVE_PROC_CPU
 136         bool
 137
 138 config NO_IOPORT_MAP
 139         bool
 140
 141 config EISA
 142         bool
 143         ---help---
 144           The Extended Industry Standard Architecture (EISA) bus was
 145           developed as an open alternative to the IBM MicroChannel bus.
 146
 147           The EISA bus provided some of the features of the IBM MicroChannel
 148           bus while maintaining backward compatibility with cards made for
 149           the older ISA bus.  The EISA bus saw limited use between 1988 and
 150           1995 when it was made obsolete by the PCI bus.
 151
 152           Say Y here if you are building a kernel for an EISA-based machine.
 153
 154           Otherwise, say N.
 155
 156 config SBUS
 157         bool
 158
 159 config STACKTRACE_SUPPORT
 160         bool
 161         default y
 162
 163 config HAVE_LATENCYTOP_SUPPORT
 164         bool
 165         depends on !SMP
 166         default y
 167
 168 config LOCKDEP_SUPPORT
 169         bool
 170         default y
 171
 172 config TRACE_IRQFLAGS_SUPPORT
 173         bool
 174         default y
 175
 176 config RWSEM_XCHGADD_ALGORITHM
 177         bool
 178         default y
 179
 180 config ARCH_HAS_ILOG2_U32
 181         bool
 182
 183 config ARCH_HAS_ILOG2_U64
 184         bool
 185
 186 config ARCH_HAS_BANDGAP
 187         bool
 188
 189 config GENERIC_HWEIGHT
 190         bool
 191         default y
 192
 193 config GENERIC_CALIBRATE_DELAY
 194         bool
 195         default y
 196
 197 config ARCH_MAY_HAVE_PC_FDC
 198         bool
 199
 200 config ZONE_DMA
 201         bool
 202
 203 config NEED_DMA_MAP_STATE
 204        def_bool y
 205
 206 config ARCH_SUPPORTS_UPROBES
 207         def_bool y
 208
 209 config ARCH_HAS_DMA_SET_COHERENT_MASK
 210         bool
 211
 212 config GENERIC_ISA_DMA
 213         bool
 214
 215 config FIQ
 216         bool
 217
 218 config NEED_RET_TO_USER
 219         bool
 220
 221 config ARCH_MTD_XIP
 222         bool
 223
 224 config VECTORS_BASE
 225         hex
 226         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 227         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 228         default 0x00000000
 229         help
 230           The base address of exception vectors.  This must be two pages
 231           in size.
 232
 233 config ARM_PATCH_PHYS_VIRT
 234         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 235         default y
 236         depends on !XIP_KERNEL && MMU
 237         depends on !ARCH_REALVIEW || !SPARSEMEM
 238         help
 239           Patch phys-to-virt and virt-to-phys translation functions at
 240           boot and module load time according to the position of the
 241           kernel in system memory.
 242
 243           This can only be used with non-XIP MMU kernels where the base
 244           of physical memory is at a 16MB boundary.
 245
 246           Only disable this option if you know that you do not require
 247           this feature (eg, building a kernel for a single machine) and
 248           you need to shrink the kernel to the minimal size.
 249
 250 config NEED_MACH_IO_H
 251         bool
 252         help
 253           Select this when mach/io.h is required to provide special
 254           definitions for this platform.  The need for mach/io.h should
 255           be avoided when possible.
 256
 257 config NEED_MACH_MEMORY_H
 258         bool
 259         help
 260           Select this when mach/memory.h is required to provide special
 261           definitions for this platform.  The need for mach/memory.h should
 262           be avoided when possible.
 263
 264 config PHYS_OFFSET
 265         hex "Physical address of main memory" if MMU
 266         depends on !ARM_PATCH_PHYS_VIRT
 267         default DRAM_BASE if !MMU
 268         default 0x00000000 if ARCH_EBSA110 || \
 269                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 270                         ARCH_FOOTBRIDGE || \
 271                         ARCH_INTEGRATOR || \
 272                         ARCH_IOP13XX || \
 273                         ARCH_KS8695 || \
 274                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 275         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 276         default 0x20000000 if ARCH_S5PV210
 277         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 278         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 279         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 280         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 281         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 282         help
 283           Please provide the physical address corresponding to the
 284           location of main memory in your system.
 285
 286 config GENERIC_BUG
 287         def_bool y
 288         depends on BUG
 289
 290 config PGTABLE_LEVELS
 291         int
 292         default 3 if ARM_LPAE
 293         default 2
 294
 295 source "init/Kconfig"
 296
 297 source "kernel/Kconfig.freezer"
 298
 299 menu "System Type"
 300
 301 config MMU
 302         bool "MMU-based Paged Memory Management Support"
 303         default y
 304         help
 305           Select if you want MMU-based virtualised addressing space
 306           support by paged memory management. If unsure, say 'Y'.
 307
 308 #
 309 # The "ARM system type" choice list is ordered alphabetically by option
 310 # text.  Please add new entries in the option alphabetic order.
 311 #
 312 choice
 313         prompt "ARM system type"
 314         default ARCH_VERSATILE if !MMU
 315         default ARCH_MULTIPLATFORM if MMU
 316
 317 config ARCH_MULTIPLATFORM
 318         bool "Allow multiple platforms to be selected"
 319         depends on MMU
 320         select ARCH_WANT_OPTIONAL_GPIOLIB
 321         select ARM_HAS_SG_CHAIN
 322         select ARM_PATCH_PHYS_VIRT
 323         select AUTO_ZRELADDR
 324         select CLKSRC_OF
 325         select COMMON_CLK
 326         select GENERIC_CLOCKEVENTS
 327         select MIGHT_HAVE_PCI
 328         select MULTI_IRQ_HANDLER
 329         select SPARSE_IRQ
 330         select USE_OF
 331
 332 config ARCH_REALVIEW
 333         bool "ARM Ltd. RealView family"
 334         select ARCH_WANT_OPTIONAL_GPIOLIB
 335         select ARM_AMBA
 336         select ARM_TIMER_SP804
 337         select COMMON_CLK
 338         select COMMON_CLK_VERSATILE
 339         select GENERIC_CLOCKEVENTS
 340         select GPIO_PL061 if GPIOLIB
 341         select ICST
 342         select NEED_MACH_MEMORY_H
 343         select PLAT_VERSATILE
 344         select PLAT_VERSATILE_SCHED_CLOCK
 345         help
 346           This enables support for ARM Ltd RealView boards.
 347
 348 config ARCH_VERSATILE
 349         bool "ARM Ltd. Versatile family"
 350         select ARCH_WANT_OPTIONAL_GPIOLIB
 351         select ARM_AMBA
 352         select ARM_TIMER_SP804
 353         select ARM_VIC
 354         select CLKDEV_LOOKUP
 355         select GENERIC_CLOCKEVENTS
 356         select HAVE_MACH_CLKDEV
 357         select ICST
 358         select PLAT_VERSATILE
 359         select PLAT_VERSATILE_CLOCK
 360         select PLAT_VERSATILE_SCHED_CLOCK
 361         select VERSATILE_FPGA_IRQ
 362         help
 363           This enables support for ARM Ltd Versatile board.
 364
 365 config ARCH_AT91
 366         bool "Atmel AT91"
 367         select ARCH_REQUIRE_GPIOLIB
 368         select CLKDEV_LOOKUP
 369         select IRQ_DOMAIN
 370         select NEED_MACH_IO_H if PCCARD
 371         select PINCTRL
 372         select PINCTRL_AT91
 373         select USE_OF
 374         help
 375           This enables support for systems based on Atmel
 376           AT91RM9200, AT91SAM9 and SAMA5 processors.
 377
 378 config ARCH_CLPS711X
 379         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 380         select ARCH_REQUIRE_GPIOLIB
 381         select AUTO_ZRELADDR
 382         select CLKSRC_MMIO
 383         select COMMON_CLK
 384         select CPU_ARM720T
 385         select GENERIC_CLOCKEVENTS
 386         select MFD_SYSCON
 387         select SOC_BUS
 388         help
 389           Support for Cirrus Logic 711x/721x/731x based boards.
 390
 391 config ARCH_GEMINI
 392         bool "Cortina Systems Gemini"
 393         select ARCH_REQUIRE_GPIOLIB
 394         select CLKSRC_MMIO
 395         select CPU_FA526
 396         select GENERIC_CLOCKEVENTS
 397         help
 398           Support for the Cortina Systems Gemini family SoCs
 399
 400 config ARCH_EBSA110
 401         bool "EBSA-110"
 402         select ARCH_USES_GETTIMEOFFSET
 403         select CPU_SA110
 404         select ISA
 405         select NEED_MACH_IO_H
 406         select NEED_MACH_MEMORY_H
 407         select NO_IOPORT_MAP
 408         help
 409           This is an evaluation board for the StrongARM processor available
 410           from Digital. It has limited hardware on-board, including an
 411           Ethernet interface, two PCMCIA sockets, two serial ports and a
 412           parallel port.
 413
 414 config ARCH_EFM32
 415         bool "Energy Micro efm32"
 416         depends on !MMU
 417         select ARCH_REQUIRE_GPIOLIB
 418         select ARM_NVIC
 419         select AUTO_ZRELADDR
 420         select CLKSRC_OF
 421         select COMMON_CLK
 422         select CPU_V7M
 423         select GENERIC_CLOCKEVENTS
 424         select NO_DMA
 425         select NO_IOPORT_MAP
 426         select SPARSE_IRQ
 427         select USE_OF
 428         help
 429           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 430           processors.
 431
 432 config ARCH_EP93XX
 433         bool "EP93xx-based"
 434         select ARCH_HAS_HOLES_MEMORYMODEL
 435         select ARCH_REQUIRE_GPIOLIB
 436         select ARCH_USES_GETTIMEOFFSET
 437         select ARM_AMBA
 438         select ARM_VIC
 439         select CLKDEV_LOOKUP
 440         select CPU_ARM920T
 441         help
 442           This enables support for the Cirrus EP93xx series of CPUs.
 443
 444 config ARCH_FOOTBRIDGE
 445         bool "FootBridge"
 446         select CPU_SA110
 447         select FOOTBRIDGE
 448         select GENERIC_CLOCKEVENTS
 449         select HAVE_IDE
 450         select NEED_MACH_IO_H if !MMU
 451         select NEED_MACH_MEMORY_H
 452         help
 453           Support for systems based on the DC21285 companion chip
 454           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 455
 456 config ARCH_NETX
 457         bool "Hilscher NetX based"
 458         select ARM_VIC
 459         select CLKSRC_MMIO
 460         select CPU_ARM926T
 461         select GENERIC_CLOCKEVENTS
 462         help
 463           This enables support for systems based on the Hilscher NetX Soc
 464
 465 config ARCH_IOP13XX
 466         bool "IOP13xx-based"
 467         depends on MMU
 468         select CPU_XSC3
 469         select NEED_MACH_MEMORY_H
 470         select NEED_RET_TO_USER
 471         select PCI
 472         select PLAT_IOP
 473         select VMSPLIT_1G
 474         select SPARSE_IRQ
 475         help
 476           Support for Intel's IOP13XX (XScale) family of processors.
 477
 478 config ARCH_IOP32X
 479         bool "IOP32x-based"
 480         depends on MMU
 481         select ARCH_REQUIRE_GPIOLIB
 482         select CPU_XSCALE
 483         select GPIO_IOP
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         help
 488           Support for Intel's 80219 and IOP32X (XScale) family of
 489           processors.
 490
 491 config ARCH_IOP33X
 492         bool "IOP33x-based"
 493         depends on MMU
 494         select ARCH_REQUIRE_GPIOLIB
 495         select CPU_XSCALE
 496         select GPIO_IOP
 497         select NEED_RET_TO_USER
 498         select PCI
 499         select PLAT_IOP
 500         help
 501           Support for Intel's IOP33X (XScale) family of processors.
 502
 503 config ARCH_IXP4XX
 504         bool "IXP4xx-based"
 505         depends on MMU
 506         select ARCH_HAS_DMA_SET_COHERENT_MASK
 507         select ARCH_REQUIRE_GPIOLIB
 508         select ARCH_SUPPORTS_BIG_ENDIAN
 509         select CLKSRC_MMIO
 510         select CPU_XSCALE
 511         select DMABOUNCE if PCI
 512         select GENERIC_CLOCKEVENTS
 513         select MIGHT_HAVE_PCI
 514         select NEED_MACH_IO_H
 515         select USB_EHCI_BIG_ENDIAN_DESC
 516         select USB_EHCI_BIG_ENDIAN_MMIO
 517         help
 518           Support for Intel's IXP4XX (XScale) family of processors.
 519
 520 config ARCH_DOVE
 521         bool "Marvell Dove"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_PJ4
 524         select GENERIC_CLOCKEVENTS
 525         select MIGHT_HAVE_PCI
 526         select MVEBU_MBUS
 527         select PINCTRL
 528         select PINCTRL_DOVE
 529         select PLAT_ORION_LEGACY
 530         help
 531           Support for the Marvell Dove SoC 88AP510
 532
 533 config ARCH_MV78XX0
 534         bool "Marvell MV78xx0"
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select MVEBU_MBUS
 539         select PCI
 540         select PLAT_ORION_LEGACY
 541         help
 542           Support for the following Marvell MV78xx0 series SoCs:
 543           MV781x0, MV782x0.
 544
 545 config ARCH_ORION5X
 546         bool "Marvell Orion"
 547         depends on MMU
 548         select ARCH_REQUIRE_GPIOLIB
 549         select CPU_FEROCEON
 550         select GENERIC_CLOCKEVENTS
 551         select MVEBU_MBUS
 552         select PCI
 553         select PLAT_ORION_LEGACY
 554         help
 555           Support for the following Marvell Orion 5x series SoCs:
 556           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 557           Orion-2 (5281), Orion-1-90 (6183).
 558
 559 config ARCH_MMP
 560         bool "Marvell PXA168/910/MMP2"
 561         depends on MMU
 562         select ARCH_REQUIRE_GPIOLIB
 563         select CLKDEV_LOOKUP
 564         select GENERIC_ALLOCATOR
 565         select GENERIC_CLOCKEVENTS
 566         select GPIO_PXA
 567         select IRQ_DOMAIN
 568         select MULTI_IRQ_HANDLER
 569         select PINCTRL
 570         select PLAT_PXA
 571         select SPARSE_IRQ
 572         help
 573           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 574
 575 config ARCH_KS8695
 576         bool "Micrel/Kendin KS8695"
 577         select ARCH_REQUIRE_GPIOLIB
 578         select CLKSRC_MMIO
 579         select CPU_ARM922T
 580         select GENERIC_CLOCKEVENTS
 581         select NEED_MACH_MEMORY_H
 582         help
 583           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 584           System-on-Chip devices.
 585
 586 config ARCH_W90X900
 587         bool "Nuvoton W90X900 CPU"
 588         select ARCH_REQUIRE_GPIOLIB
 589         select CLKDEV_LOOKUP
 590         select CLKSRC_MMIO
 591         select CPU_ARM926T
 592         select GENERIC_CLOCKEVENTS
 593         help
 594           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 595           At present, the w90x900 has been renamed nuc900, regarding
 596           the ARM series product line, you can login the following
 597           link address to know more.
 598
 599           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 600                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 601
 602 config ARCH_LPC32XX
 603         bool "NXP LPC32XX"
 604         select ARCH_REQUIRE_GPIOLIB
 605         select ARM_AMBA
 606         select CLKDEV_LOOKUP
 607         select CLKSRC_MMIO
 608         select CPU_ARM926T
 609         select GENERIC_CLOCKEVENTS
 610         select HAVE_IDE
 611         select USE_OF
 612         help
 613           Support for the NXP LPC32XX family of processors
 614
 615 config ARCH_PXA
 616         bool "PXA2xx/PXA3xx-based"
 617         depends on MMU
 618         select ARCH_MTD_XIP
 619         select ARCH_REQUIRE_GPIOLIB
 620         select ARM_CPU_SUSPEND if PM
 621         select AUTO_ZRELADDR
 622         select CLKDEV_LOOKUP
 623         select CLKSRC_MMIO
 624         select CLKSRC_OF
 625         select GENERIC_CLOCKEVENTS
 626         select GPIO_PXA
 627         select HAVE_IDE
 628         select IRQ_DOMAIN
 629         select MULTI_IRQ_HANDLER
 630         select PLAT_PXA
 631         select SPARSE_IRQ
 632         help
 633           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 634
 635 config ARCH_MSM
 636         bool "Qualcomm MSM (non-multiplatform)"
 637         select ARCH_REQUIRE_GPIOLIB
 638         select COMMON_CLK
 639         select GENERIC_CLOCKEVENTS
 640         help
 641           Support for Qualcomm MSM/QSD based systems.  This runs on the
 642           apps processor of the MSM/QSD and depends on a shared memory
 643           interface to the modem processor which runs the baseband
 644           stack and controls some vital subsystems
 645           (clock and power control, etc).
 646
 647 config ARCH_SHMOBILE_LEGACY
 648         bool "Renesas ARM SoCs (non-multiplatform)"
 649         select ARCH_SHMOBILE
 650         select ARM_PATCH_PHYS_VIRT if MMU
 651         select CLKDEV_LOOKUP
 652         select CPU_V7
 653         select GENERIC_CLOCKEVENTS
 654         select HAVE_ARM_SCU if SMP
 655         select HAVE_ARM_TWD if SMP
 656         select HAVE_MACH_CLKDEV
 657         select HAVE_SMP
 658         select MIGHT_HAVE_CACHE_L2X0
 659         select MULTI_IRQ_HANDLER
 660         select NO_IOPORT_MAP
 661         select PINCTRL
 662         select PM_GENERIC_DOMAINS if PM
 663         select SH_CLK_CPG
 664         select SPARSE_IRQ
 665         help
 666           Support for Renesas ARM SoC platforms using a non-multiplatform
 667           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 668           and RZ families.
 669
 670 config ARCH_RPC
 671         bool "RiscPC"
 672         select ARCH_ACORN
 673         select ARCH_MAY_HAVE_PC_FDC
 674         select ARCH_SPARSEMEM_ENABLE
 675         select ARCH_USES_GETTIMEOFFSET
 676         select CPU_SA110
 677         select FIQ
 678         select HAVE_IDE
 679         select HAVE_PATA_PLATFORM
 680         select ISA_DMA_API
 681         select NEED_MACH_IO_H
 682         select NEED_MACH_MEMORY_H
 683         select NO_IOPORT_MAP
 684         select VIRT_TO_BUS
 685         help
 686           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 687           CD-ROM interface, serial and parallel port, and the floppy drive.
 688
 689 config ARCH_SA1100
 690         bool "SA1100-based"
 691         select ARCH_MTD_XIP
 692         select ARCH_REQUIRE_GPIOLIB
 693         select ARCH_SPARSEMEM_ENABLE
 694         select CLKDEV_LOOKUP
 695         select CLKSRC_MMIO
 696         select CPU_FREQ
 697         select CPU_SA1100
 698         select GENERIC_CLOCKEVENTS
 699         select HAVE_IDE
 700         select IRQ_DOMAIN
 701         select ISA
 702         select MULTI_IRQ_HANDLER
 703         select NEED_MACH_MEMORY_H
 704         select SPARSE_IRQ
 705         help
 706           Support for StrongARM 11x0 based boards.
 707
 708 config ARCH_S3C24XX
 709         bool "Samsung S3C24XX SoCs"
 710         select ARCH_REQUIRE_GPIOLIB
 711         select ATAGS
 712         select CLKDEV_LOOKUP
 713         select CLKSRC_SAMSUNG_PWM
 714         select GENERIC_CLOCKEVENTS
 715         select GPIO_SAMSUNG
 716         select HAVE_S3C2410_I2C if I2C
 717         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 718         select HAVE_S3C_RTC if RTC_CLASS
 719         select MULTI_IRQ_HANDLER
 720         select NEED_MACH_IO_H
 721         select SAMSUNG_ATAGS
 722         help
 723           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 724           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 725           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 726           Samsung SMDK2410 development board (and derivatives).
 727
 728 config ARCH_S3C64XX
 729         bool "Samsung S3C64XX"
 730         select ARCH_REQUIRE_GPIOLIB
 731         select ARM_AMBA
 732         select ARM_VIC
 733         select ATAGS
 734         select CLKDEV_LOOKUP
 735         select CLKSRC_SAMSUNG_PWM
 736         select COMMON_CLK_SAMSUNG
 737         select CPU_V6K
 738         select GENERIC_CLOCKEVENTS
 739         select GPIO_SAMSUNG
 740         select HAVE_S3C2410_I2C if I2C
 741         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 742         select HAVE_TCM
 743         select NO_IOPORT_MAP
 744         select PLAT_SAMSUNG
 745         select PM_GENERIC_DOMAINS if PM
 746         select S3C_DEV_NAND
 747         select S3C_GPIO_TRACK
 748         select SAMSUNG_ATAGS
 749         select SAMSUNG_WAKEMASK
 750         select SAMSUNG_WDT_RESET
 751         help
 752           Samsung S3C64XX series based systems
 753
 754 config ARCH_DAVINCI
 755         bool "TI DaVinci"
 756         select ARCH_HAS_HOLES_MEMORYMODEL
 757         select ARCH_REQUIRE_GPIOLIB
 758         select CLKDEV_LOOKUP
 759         select GENERIC_ALLOCATOR
 760         select GENERIC_CLOCKEVENTS
 761         select GENERIC_IRQ_CHIP
 762         select HAVE_IDE
 763         select TI_PRIV_EDMA
 764         select USE_OF
 765         select ZONE_DMA
 766         help
 767           Support for TI's DaVinci platform.
 768
 769 config ARCH_OMAP1
 770         bool "TI OMAP1"
 771         depends on MMU
 772         select ARCH_HAS_HOLES_MEMORYMODEL
 773         select ARCH_OMAP
 774         select ARCH_REQUIRE_GPIOLIB
 775         select CLKDEV_LOOKUP
 776         select CLKSRC_MMIO
 777         select GENERIC_CLOCKEVENTS
 778         select GENERIC_IRQ_CHIP
 779         select HAVE_IDE
 780         select IRQ_DOMAIN
 781         select NEED_MACH_IO_H if PCCARD
 782         select NEED_MACH_MEMORY_H
 783         help
 784           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 785
 786 endchoice
 787
 788 menu "Multiple platform selection"
 789         depends on ARCH_MULTIPLATFORM
 790
 791 comment "CPU Core family selection"
 792
 793 config ARCH_MULTI_V4
 794         bool "ARMv4 based platforms (FA526)"
 795         depends on !ARCH_MULTI_V6_V7
 796         select ARCH_MULTI_V4_V5
 797         select CPU_FA526
 798
 799 config ARCH_MULTI_V4T
 800         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 801         depends on !ARCH_MULTI_V6_V7
 802         select ARCH_MULTI_V4_V5
 803         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 804                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 805                 CPU_ARM925T || CPU_ARM940T)
 806
 807 config ARCH_MULTI_V5
 808         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 809         depends on !ARCH_MULTI_V6_V7
 810         select ARCH_MULTI_V4_V5
 811         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 812                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 813                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 814
 815 config ARCH_MULTI_V4_V5
 816         bool
 817
 818 config ARCH_MULTI_V6
 819         bool "ARMv6 based platforms (ARM11)"
 820         select ARCH_MULTI_V6_V7
 821         select CPU_V6K
 822
 823 config ARCH_MULTI_V7
 824         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 825         default y
 826         select ARCH_MULTI_V6_V7
 827         select CPU_V7
 828         select HAVE_SMP
 829
 830 config ARCH_MULTI_V6_V7
 831         bool
 832         select MIGHT_HAVE_CACHE_L2X0
 833
 834 config ARCH_MULTI_CPU_AUTO
 835         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 836         select ARCH_MULTI_V5
 837
 838 endmenu
 839
 840 config ARCH_VIRT
 841         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 842         select ARM_AMBA
 843         select ARM_GIC
 844         select ARM_PSCI
 845         select HAVE_ARM_ARCH_TIMER
 846
 847 #
 848 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 849 # Kconfigs may be included either alphabetically (according to the
 850 # plat- suffix) or along side the corresponding mach-* source.
 851 #
 852 source "arch/arm/mach-mvebu/Kconfig"
 853
 854 source "arch/arm/mach-asm9260/Kconfig"
 855
 856 source "arch/arm/mach-at91/Kconfig"
 857
 858 source "arch/arm/mach-axxia/Kconfig"
 859
 860 source "arch/arm/mach-bcm/Kconfig"
 861
 862 source "arch/arm/mach-berlin/Kconfig"
 863
 864 source "arch/arm/mach-clps711x/Kconfig"
 865
 866 source "arch/arm/mach-cns3xxx/Kconfig"
 867
 868 source "arch/arm/mach-davinci/Kconfig"
 869
 870 source "arch/arm/mach-digicolor/Kconfig"
 871
 872 source "arch/arm/mach-dove/Kconfig"
 873
 874 source "arch/arm/mach-ep93xx/Kconfig"
 875
 876 source "arch/arm/mach-footbridge/Kconfig"
 877
 878 source "arch/arm/mach-gemini/Kconfig"
 879
 880 source "arch/arm/mach-highbank/Kconfig"
 881
 882 source "arch/arm/mach-hisi/Kconfig"
 883
 884 source "arch/arm/mach-integrator/Kconfig"
 885
 886 source "arch/arm/mach-iop32x/Kconfig"
 887
 888 source "arch/arm/mach-iop33x/Kconfig"
 889
 890 source "arch/arm/mach-iop13xx/Kconfig"
 891
 892 source "arch/arm/mach-ixp4xx/Kconfig"
 893
 894 source "arch/arm/mach-keystone/Kconfig"
 895
 896 source "arch/arm/mach-ks8695/Kconfig"
 897
 898 source "arch/arm/mach-meson/Kconfig"
 899
 900 source "arch/arm/mach-msm/Kconfig"
 901
 902 source "arch/arm/mach-moxart/Kconfig"
 903
 904 source "arch/arm/mach-mv78xx0/Kconfig"
 905
 906 source "arch/arm/mach-imx/Kconfig"
 907
 908 source "arch/arm/mach-mediatek/Kconfig"
 909
 910 source "arch/arm/mach-mxs/Kconfig"
 911
 912 source "arch/arm/mach-netx/Kconfig"
 913
 914 source "arch/arm/mach-nomadik/Kconfig"
 915
 916 source "arch/arm/mach-nspire/Kconfig"
 917
 918 source "arch/arm/plat-omap/Kconfig"
 919
 920 source "arch/arm/mach-omap1/Kconfig"
 921
 922 source "arch/arm/mach-omap2/Kconfig"
 923
 924 source "arch/arm/mach-orion5x/Kconfig"
 925
 926 source "arch/arm/mach-picoxcell/Kconfig"
 927
 928 source "arch/arm/mach-pxa/Kconfig"
 929 source "arch/arm/plat-pxa/Kconfig"
 930
 931 source "arch/arm/mach-mmp/Kconfig"
 932
 933 source "arch/arm/mach-qcom/Kconfig"
 934
 935 source "arch/arm/mach-realview/Kconfig"
 936
 937 source "arch/arm/mach-rockchip/Kconfig"
 938
 939 source "arch/arm/mach-sa1100/Kconfig"
 940
 941 source "arch/arm/mach-socfpga/Kconfig"
 942
 943 source "arch/arm/mach-spear/Kconfig"
 944
 945 source "arch/arm/mach-sti/Kconfig"
 946
 947 source "arch/arm/mach-s3c24xx/Kconfig"
 948
 949 source "arch/arm/mach-s3c64xx/Kconfig"
 950
 951 source "arch/arm/mach-s5pv210/Kconfig"
 952
 953 source "arch/arm/mach-exynos/Kconfig"
 954 source "arch/arm/plat-samsung/Kconfig"
 955
 956 source "arch/arm/mach-shmobile/Kconfig"
 957
 958 source "arch/arm/mach-sunxi/Kconfig"
 959
 960 source "arch/arm/mach-prima2/Kconfig"
 961
 962 source "arch/arm/mach-tegra/Kconfig"
 963
 964 source "arch/arm/mach-u300/Kconfig"
 965
 966 source "arch/arm/mach-ux500/Kconfig"
 967
 968 source "arch/arm/mach-versatile/Kconfig"
 969
 970 source "arch/arm/mach-vexpress/Kconfig"
 971 source "arch/arm/plat-versatile/Kconfig"
 972
 973 source "arch/arm/mach-vt8500/Kconfig"
 974
 975 source "arch/arm/mach-w90x900/Kconfig"
 976
 977 source "arch/arm/mach-zynq/Kconfig"
 978
 979 # Definitions to make life easier
 980 config ARCH_ACORN
 981         bool
 982
 983 config PLAT_IOP
 984         bool
 985         select GENERIC_CLOCKEVENTS
 986
 987 config PLAT_ORION
 988         bool
 989         select CLKSRC_MMIO
 990         select COMMON_CLK
 991         select GENERIC_IRQ_CHIP
 992         select IRQ_DOMAIN
 993
 994 config PLAT_ORION_LEGACY
 995         bool
 996         select PLAT_ORION
 997
 998 config PLAT_PXA
 999         bool
1000
1001 config PLAT_VERSATILE
1002         bool
1003
1004 config ARM_TIMER_SP804
1005         bool
1006         select CLKSRC_MMIO
1007         select CLKSRC_OF if OF
1008
1009 source "arch/arm/firmware/Kconfig"
1010
1011 source arch/arm/mm/Kconfig
1012
1013 config IWMMXT
1014         bool "Enable iWMMXt support"
1015         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1016         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1017         help
1018           Enable support for iWMMXt context switching at run time if
1019           running on a CPU that supports it.
1020
1021 config MULTI_IRQ_HANDLER
1022         bool
1023         help
1024           Allow each machine to specify it's own IRQ handler at run time.
1025
1026 if !MMU
1027 source "arch/arm/Kconfig-nommu"
1028 endif
1029
1030 config PJ4B_ERRATA_4742
1031         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1032         depends on CPU_PJ4B && MACH_ARMADA_370
1033         default y
1034         help
1035           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1036           Event (WFE) IDLE states, a specific timing sensitivity exists between
1037           the retiring WFI/WFE instructions and the newly issued subsequent
1038           instructions.  This sensitivity can result in a CPU hang scenario.
1039           Workaround:
1040           The software must insert either a Data Synchronization Barrier (DSB)
1041           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1042           instruction
1043
1044 config ARM_ERRATA_326103
1045         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1046         depends on CPU_V6
1047         help
1048           Executing a SWP instruction to read-only memory does not set bit 11
1049           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1050           treat the access as a read, preventing a COW from occurring and
1051           causing the faulting task to livelock.
1052
1053 config ARM_ERRATA_411920
1054         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1055         depends on CPU_V6 || CPU_V6K
1056         help
1057           Invalidation of the Instruction Cache operation can
1058           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1059           It does not affect the MPCore. This option enables the ARM Ltd.
1060           recommended workaround.
1061
1062 config ARM_ERRATA_430973
1063         bool "ARM errata: Stale prediction on replaced interworking branch"
1064         depends on CPU_V7
1065         help
1066           This option enables the workaround for the 430973 Cortex-A8
1067           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1068           interworking branch is replaced with another code sequence at the
1069           same virtual address, whether due to self-modifying code or virtual
1070           to physical address re-mapping, Cortex-A8 does not recover from the
1071           stale interworking branch prediction. This results in Cortex-A8
1072           executing the new code sequence in the incorrect ARM or Thumb state.
1073           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1074           and also flushes the branch target cache at every context switch.
1075           Note that setting specific bits in the ACTLR register may not be
1076           available in non-secure mode.
1077
1078 config ARM_ERRATA_458693
1079         bool "ARM errata: Processor deadlock when a false hazard is created"
1080         depends on CPU_V7
1081         depends on !ARCH_MULTIPLATFORM
1082         help
1083           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1084           erratum. For very specific sequences of memory operations, it is
1085           possible for a hazard condition intended for a cache line to instead
1086           be incorrectly associated with a different cache line. This false
1087           hazard might then cause a processor deadlock. The workaround enables
1088           the L1 caching of the NEON accesses and disables the PLD instruction
1089           in the ACTLR register. Note that setting specific bits in the ACTLR
1090           register may not be available in non-secure mode.
1091
1092 config ARM_ERRATA_460075
1093         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1094         depends on CPU_V7
1095         depends on !ARCH_MULTIPLATFORM
1096         help
1097           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1098           erratum. Any asynchronous access to the L2 cache may encounter a
1099           situation in which recent store transactions to the L2 cache are lost
1100           and overwritten with stale memory contents from external memory. The
1101           workaround disables the write-allocate mode for the L2 cache via the
1102           ACTLR register. Note that setting specific bits in the ACTLR register
1103           may not be available in non-secure mode.
1104
1105 config ARM_ERRATA_742230
1106         bool "ARM errata: DMB operation may be faulty"
1107         depends on CPU_V7 && SMP
1108         depends on !ARCH_MULTIPLATFORM
1109         help
1110           This option enables the workaround for the 742230 Cortex-A9
1111           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1112           between two write operations may not ensure the correct visibility
1113           ordering of the two writes. This workaround sets a specific bit in
1114           the diagnostic register of the Cortex-A9 which causes the DMB
1115           instruction to behave as a DSB, ensuring the correct behaviour of
1116           the two writes.
1117
1118 config ARM_ERRATA_742231
1119         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1120         depends on CPU_V7 && SMP
1121         depends on !ARCH_MULTIPLATFORM
1122         help
1123           This option enables the workaround for the 742231 Cortex-A9
1124           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1125           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1126           accessing some data located in the same cache line, may get corrupted
1127           data due to bad handling of the address hazard when the line gets
1128           replaced from one of the CPUs at the same time as another CPU is
1129           accessing it. This workaround sets specific bits in the diagnostic
1130           register of the Cortex-A9 which reduces the linefill issuing
1131           capabilities of the processor.
1132
1133 config ARM_ERRATA_643719
1134         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1135         depends on CPU_V7 && SMP
1136         help
1137           This option enables the workaround for the 643719 Cortex-A9 (prior to
1138           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1139           register returns zero when it should return one. The workaround
1140           corrects this value, ensuring cache maintenance operations which use
1141           it behave as intended and avoiding data corruption.
1142
1143 config ARM_ERRATA_720789
1144         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1145         depends on CPU_V7
1146         help
1147           This option enables the workaround for the 720789 Cortex-A9 (prior to
1148           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1149           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1150           As a consequence of this erratum, some TLB entries which should be
1151           invalidated are not, resulting in an incoherency in the system page
1152           tables. The workaround changes the TLB flushing routines to invalidate
1153           entries regardless of the ASID.
1154
1155 config ARM_ERRATA_743622
1156         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1157         depends on CPU_V7
1158         depends on !ARCH_MULTIPLATFORM
1159         help
1160           This option enables the workaround for the 743622 Cortex-A9
1161           (r2p*) erratum. Under very rare conditions, a faulty
1162           optimisation in the Cortex-A9 Store Buffer may lead to data
1163           corruption. This workaround sets a specific bit in the diagnostic
1164           register of the Cortex-A9 which disables the Store Buffer
1165           optimisation, preventing the defect from occurring. This has no
1166           visible impact on the overall performance or power consumption of the
1167           processor.
1168
1169 config ARM_ERRATA_751472
1170         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1171         depends on CPU_V7
1172         depends on !ARCH_MULTIPLATFORM
1173         help
1174           This option enables the workaround for the 751472 Cortex-A9 (prior
1175           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1176           completion of a following broadcasted operation if the second
1177           operation is received by a CPU before the ICIALLUIS has completed,
1178           potentially leading to corrupted entries in the cache or TLB.
1179
1180 config ARM_ERRATA_754322
1181         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1182         depends on CPU_V7
1183         help
1184           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1185           r3p*) erratum. A speculative memory access may cause a page table walk
1186           which starts prior to an ASID switch but completes afterwards. This
1187           can populate the micro-TLB with a stale entry which may be hit with
1188           the new ASID. This workaround places two dsb instructions in the mm
1189           switching code so that no page table walks can cross the ASID switch.
1190
1191 config ARM_ERRATA_754327
1192         bool "ARM errata: no automatic Store Buffer drain"
1193         depends on CPU_V7 && SMP
1194         help
1195           This option enables the workaround for the 754327 Cortex-A9 (prior to
1196           r2p0) erratum. The Store Buffer does not have any automatic draining
1197           mechanism and therefore a livelock may occur if an external agent
1198           continuously polls a memory location waiting to observe an update.
1199           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1200           written polling loops from denying visibility of updates to memory.
1201
1202 config ARM_ERRATA_364296
1203         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1204         depends on CPU_V6
1205         help
1206           This options enables the workaround for the 364296 ARM1136
1207           r0p2 erratum (possible cache data corruption with
1208           hit-under-miss enabled). It sets the undocumented bit 31 in
1209           the auxiliary control register and the FI bit in the control
1210           register, thus disabling hit-under-miss without putting the
1211           processor into full low interrupt latency mode. ARM11MPCore
1212           is not affected.
1213
1214 config ARM_ERRATA_764369
1215         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1216         depends on CPU_V7 && SMP
1217         help
1218           This option enables the workaround for erratum 764369
1219           affecting Cortex-A9 MPCore with two or more processors (all
1220           current revisions). Under certain timing circumstances, a data
1221           cache line maintenance operation by MVA targeting an Inner
1222           Shareable memory region may fail to proceed up to either the
1223           Point of Coherency or to the Point of Unification of the
1224           system. This workaround adds a DSB instruction before the
1225           relevant cache maintenance functions and sets a specific bit
1226           in the diagnostic control register of the SCU.
1227
1228 config ARM_ERRATA_775420
1229        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1230        depends on CPU_V7
1231        help
1232          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1233          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1234          operation aborts with MMU exception, it might cause the processor
1235          to deadlock. This workaround puts DSB before executing ISB if
1236          an abort may occur on cache maintenance.
1237
1238 config ARM_ERRATA_798181
1239         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1240         depends on CPU_V7 && SMP
1241         help
1242           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1243           adequately shooting down all use of the old entries. This
1244           option enables the Linux kernel workaround for this erratum
1245           which sends an IPI to the CPUs that are running the same ASID
1246           as the one being invalidated.
1247
1248 config ARM_ERRATA_773022
1249         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1250         depends on CPU_V7
1251         help
1252           This option enables the workaround for the 773022 Cortex-A15
1253           (up to r0p4) erratum. In certain rare sequences of code, the
1254           loop buffer may deliver incorrect instructions. This
1255           workaround disables the loop buffer to avoid the erratum.
1256
1257 endmenu
1258
1259 source "arch/arm/common/Kconfig"
1260
1261 menu "Bus support"
1262
1263 config ISA
1264         bool
1265         help
1266           Find out whether you have ISA slots on your motherboard.  ISA is the
1267           name of a bus system, i.e. the way the CPU talks to the other stuff
1268           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1269           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1270           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1271
1272 # Select ISA DMA controller support
1273 config ISA_DMA
1274         bool
1275         select ISA_DMA_API
1276
1277 # Select ISA DMA interface
1278 config ISA_DMA_API
1279         bool
1280
1281 config PCI
1282         bool "PCI support" if MIGHT_HAVE_PCI
1283         help
1284           Find out whether you have a PCI motherboard. PCI is the name of a
1285           bus system, i.e. the way the CPU talks to the other stuff inside
1286           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1287           VESA. If you have PCI, say Y, otherwise N.
1288
1289 config PCI_DOMAINS
1290         bool
1291         depends on PCI
1292
1293 config PCI_DOMAINS_GENERIC
1294         def_bool PCI_DOMAINS
1295
1296 config PCI_NANOENGINE
1297         bool "BSE nanoEngine PCI support"
1298         depends on SA1100_NANOENGINE
1299         help
1300           Enable PCI on the BSE nanoEngine board.
1301
1302 config PCI_SYSCALL
1303         def_bool PCI
1304
1305 config PCI_HOST_ITE8152
1306         bool
1307         depends on PCI && MACH_ARMCORE
1308         default y
1309         select DMABOUNCE
1310
1311 source "drivers/pci/Kconfig"
1312 source "drivers/pci/pcie/Kconfig"
1313
1314 source "drivers/pcmcia/Kconfig"
1315
1316 endmenu
1317
1318 menu "Kernel Features"
1319
1320 config HAVE_SMP
1321         bool
1322         help
1323           This option should be selected by machines which have an SMP-
1324           capable CPU.
1325
1326           The only effect of this option is to make the SMP-related
1327           options available to the user for configuration.
1328
1329 config SMP
1330         bool "Symmetric Multi-Processing"
1331         depends on CPU_V6K || CPU_V7
1332         depends on GENERIC_CLOCKEVENTS
1333         depends on HAVE_SMP
1334         depends on MMU || ARM_MPU
1335         help
1336           This enables support for systems with more than one CPU. If you have
1337           a system with only one CPU, say N. If you have a system with more
1338           than one CPU, say Y.
1339
1340           If you say N here, the kernel will run on uni- and multiprocessor
1341           machines, but will use only one CPU of a multiprocessor machine. If
1342           you say Y here, the kernel will run on many, but not all,
1343           uniprocessor machines. On a uniprocessor machine, the kernel
1344           will run faster if you say N here.
1345
1346           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1347           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1348           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1349
1350           If you don't know what to do here, say N.
1351
1352 config SMP_ON_UP
1353         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1354         depends on SMP && !XIP_KERNEL && MMU
1355         default y
1356         help
1357           SMP kernels contain instructions which fail on non-SMP processors.
1358           Enabling this option allows the kernel to modify itself to make
1359           these instructions safe.  Disabling it allows about 1K of space
1360           savings.
1361
1362           If you don't know what to do here, say Y.
1363
1364 config ARM_CPU_TOPOLOGY
1365         bool "Support cpu topology definition"
1366         depends on SMP && CPU_V7
1367         default y
1368         help
1369           Support ARM cpu topology definition. The MPIDR register defines
1370           affinity between processors which is then used to describe the cpu
1371           topology of an ARM System.
1372
1373 config SCHED_MC
1374         bool "Multi-core scheduler support"
1375         depends on ARM_CPU_TOPOLOGY
1376         help
1377           Multi-core scheduler support improves the CPU scheduler's decision
1378           making when dealing with multi-core CPU chips at a cost of slightly
1379           increased overhead in some places. If unsure say N here.
1380
1381 config SCHED_SMT
1382         bool "SMT scheduler support"
1383         depends on ARM_CPU_TOPOLOGY
1384         help
1385           Improves the CPU scheduler's decision making when dealing with
1386           MultiThreading at a cost of slightly increased overhead in some
1387           places. If unsure say N here.
1388
1389 config HAVE_ARM_SCU
1390         bool
1391         help
1392           This option enables support for the ARM system coherency unit
1393
1394 config HAVE_ARM_ARCH_TIMER
1395         bool "Architected timer support"
1396         depends on CPU_V7
1397         select ARM_ARCH_TIMER
1398         select GENERIC_CLOCKEVENTS
1399         help
1400           This option enables support for the ARM architected timer
1401
1402 config HAVE_ARM_TWD
1403         bool
1404         depends on SMP
1405         select CLKSRC_OF if OF
1406         help
1407           This options enables support for the ARM timer and watchdog unit
1408
1409 config MCPM
1410         bool "Multi-Cluster Power Management"
1411         depends on CPU_V7 && SMP
1412         help
1413           This option provides the common power management infrastructure
1414           for (multi-)cluster based systems, such as big.LITTLE based
1415           systems.
1416
1417 config MCPM_QUAD_CLUSTER
1418         bool
1419         depends on MCPM
1420         help
1421           To avoid wasting resources unnecessarily, MCPM only supports up
1422           to 2 clusters by default.
1423           Platforms with 3 or 4 clusters that use MCPM must select this
1424           option to allow the additional clusters to be managed.
1425
1426 config BIG_LITTLE
1427         bool "big.LITTLE support (Experimental)"
1428         depends on CPU_V7 && SMP
1429         select MCPM
1430         help
1431           This option enables support selections for the big.LITTLE
1432           system architecture.
1433
1434 config BL_SWITCHER
1435         bool "big.LITTLE switcher support"
1436         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1437         select ARM_CPU_SUSPEND
1438         select CPU_PM
1439         help
1440           The big.LITTLE "switcher" provides the core functionality to
1441           transparently handle transition between a cluster of A15's
1442           and a cluster of A7's in a big.LITTLE system.
1443
1444 config BL_SWITCHER_DUMMY_IF
1445         tristate "Simple big.LITTLE switcher user interface"
1446         depends on BL_SWITCHER && DEBUG_KERNEL
1447         help
1448           This is a simple and dummy char dev interface to control
1449           the big.LITTLE switcher core code.  It is meant for
1450           debugging purposes only.
1451
1452 choice
1453         prompt "Memory split"
1454         depends on MMU
1455         default VMSPLIT_3G
1456         help
1457           Select the desired split between kernel and user memory.
1458
1459           If you are not absolutely sure what you are doing, leave this
1460           option alone!
1461
1462         config VMSPLIT_3G
1463                 bool "3G/1G user/kernel split"
1464         config VMSPLIT_2G
1465                 bool "2G/2G user/kernel split"
1466         config VMSPLIT_1G
1467                 bool "1G/3G user/kernel split"
1468 endchoice
1469
1470 config PAGE_OFFSET
1471         hex
1472         default PHYS_OFFSET if !MMU
1473         default 0x40000000 if VMSPLIT_1G
1474         default 0x80000000 if VMSPLIT_2G
1475         default 0xC0000000
1476
1477 config NR_CPUS
1478         int "Maximum number of CPUs (2-32)"
1479         range 2 32
1480         depends on SMP
1481         default "4"
1482
1483 config HOTPLUG_CPU
1484         bool "Support for hot-pluggable CPUs"
1485         depends on SMP
1486         help
1487           Say Y here to experiment with turning CPUs off and on.  CPUs
1488           can be controlled through /sys/devices/system/cpu.
1489
1490 config ARM_PSCI
1491         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1492         depends on CPU_V7
1493         help
1494           Say Y here if you want Linux to communicate with system firmware
1495           implementing the PSCI specification for CPU-centric power
1496           management operations described in ARM document number ARM DEN
1497           0022A ("Power State Coordination Interface System Software on
1498           ARM processors").
1499
1500 # The GPIO number here must be sorted by descending number. In case of
1501 # a multiplatform kernel, we just want the highest value required by the
1502 # selected platforms.
1503 config ARCH_NR_GPIO
1504         int
1505         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1506         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1507                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1508         default 416 if ARCH_SUNXI
1509         default 392 if ARCH_U8500
1510         default 352 if ARCH_VT8500
1511         default 288 if ARCH_ROCKCHIP
1512         default 264 if MACH_H4700
1513         default 0
1514         help
1515           Maximum number of GPIOs in the system.
1516
1517           If unsure, leave the default value.
1518
1519 source kernel/Kconfig.preempt
1520
1521 config HZ_FIXED
1522         int
1523         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1524                 ARCH_S5PV210 || ARCH_EXYNOS4
1525         default AT91_TIMER_HZ if ARCH_AT91
1526         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1527         default 0
1528
1529 choice
1530         depends on HZ_FIXED = 0
1531         prompt "Timer frequency"
1532
1533 config HZ_100
1534         bool "100 Hz"
1535
1536 config HZ_200
1537         bool "200 Hz"
1538
1539 config HZ_250
1540         bool "250 Hz"
1541
1542 config HZ_300
1543         bool "300 Hz"
1544
1545 config HZ_500
1546         bool "500 Hz"
1547
1548 config HZ_1000
1549         bool "1000 Hz"
1550
1551 endchoice
1552
1553 config HZ
1554         int
1555         default HZ_FIXED if HZ_FIXED != 0
1556         default 100 if HZ_100
1557         default 200 if HZ_200
1558         default 250 if HZ_250
1559         default 300 if HZ_300
1560         default 500 if HZ_500
1561         default 1000
1562
1563 config SCHED_HRTICK
1564         def_bool HIGH_RES_TIMERS
1565
1566 config THUMB2_KERNEL
1567         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1568         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1569         default y if CPU_THUMBONLY
1570         select AEABI
1571         select ARM_ASM_UNIFIED
1572         select ARM_UNWIND
1573         help
1574           By enabling this option, the kernel will be compiled in
1575           Thumb-2 mode. A compiler/assembler that understand the unified
1576           ARM-Thumb syntax is needed.
1577
1578           If unsure, say N.
1579
1580 config THUMB2_AVOID_R_ARM_THM_JUMP11
1581         bool "Work around buggy Thumb-2 short branch relocations in gas"
1582         depends on THUMB2_KERNEL && MODULES
1583         default y
1584         help
1585           Various binutils versions can resolve Thumb-2 branches to
1586           locally-defined, preemptible global symbols as short-range "b.n"
1587           branch instructions.
1588
1589           This is a problem, because there's no guarantee the final
1590           destination of the symbol, or any candidate locations for a
1591           trampoline, are within range of the branch.  For this reason, the
1592           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1593           relocation in modules at all, and it makes little sense to add
1594           support.
1595
1596           The symptom is that the kernel fails with an "unsupported
1597           relocation" error when loading some modules.
1598
1599           Until fixed tools are available, passing
1600           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1601           code which hits this problem, at the cost of a bit of extra runtime
1602           stack usage in some cases.
1603
1604           The problem is described in more detail at:
1605               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1606
1607           Only Thumb-2 kernels are affected.
1608
1609           Unless you are sure your tools don't have this problem, say Y.
1610
1611 config ARM_ASM_UNIFIED
1612         bool
1613
1614 config AEABI
1615         bool "Use the ARM EABI to compile the kernel"
1616         help
1617           This option allows for the kernel to be compiled using the latest
1618           ARM ABI (aka EABI).  This is only useful if you are using a user
1619           space environment that is also compiled with EABI.
1620
1621           Since there are major incompatibilities between the legacy ABI and
1622           EABI, especially with regard to structure member alignment, this
1623           option also changes the kernel syscall calling convention to
1624           disambiguate both ABIs and allow for backward compatibility support
1625           (selected with CONFIG_OABI_COMPAT).
1626
1627           To use this you need GCC version 4.0.0 or later.
1628
1629 config OABI_COMPAT
1630         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1631         depends on AEABI && !THUMB2_KERNEL
1632         help
1633           This option preserves the old syscall interface along with the
1634           new (ARM EABI) one. It also provides a compatibility layer to
1635           intercept syscalls that have structure arguments which layout
1636           in memory differs between the legacy ABI and the new ARM EABI
1637           (only for non "thumb" binaries). This option adds a tiny
1638           overhead to all syscalls and produces a slightly larger kernel.
1639
1640           The seccomp filter system will not be available when this is
1641           selected, since there is no way yet to sensibly distinguish
1642           between calling conventions during filtering.
1643
1644           If you know you'll be using only pure EABI user space then you
1645           can say N here. If this option is not selected and you attempt
1646           to execute a legacy ABI binary then the result will be
1647           UNPREDICTABLE (in fact it can be predicted that it won't work
1648           at all). If in doubt say N.
1649
1650 config ARCH_HAS_HOLES_MEMORYMODEL
1651         bool
1652
1653 config ARCH_SPARSEMEM_ENABLE
1654         bool
1655
1656 config ARCH_SPARSEMEM_DEFAULT
1657         def_bool ARCH_SPARSEMEM_ENABLE
1658
1659 config ARCH_SELECT_MEMORY_MODEL
1660         def_bool ARCH_SPARSEMEM_ENABLE
1661
1662 config HAVE_ARCH_PFN_VALID
1663         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1664
1665 config HAVE_GENERIC_RCU_GUP
1666         def_bool y
1667         depends on ARM_LPAE
1668
1669 config HIGHMEM
1670         bool "High Memory Support"
1671         depends on MMU
1672         help
1673           The address space of ARM processors is only 4 Gigabytes large
1674           and it has to accommodate user address space, kernel address
1675           space as well as some memory mapped IO. That means that, if you
1676           have a large amount of physical memory and/or IO, not all of the
1677           memory can be "permanently mapped" by the kernel. The physical
1678           memory that is not permanently mapped is called "high memory".
1679
1680           Depending on the selected kernel/user memory split, minimum
1681           vmalloc space and actual amount of RAM, you may not need this
1682           option which should result in a slightly faster kernel.
1683
1684           If unsure, say n.
1685
1686 config HIGHPTE
1687         bool "Allocate 2nd-level pagetables from highmem"
1688         depends on HIGHMEM
1689
1690 config HW_PERF_EVENTS
1691         bool "Enable hardware performance counter support for perf events"
1692         depends on PERF_EVENTS
1693         default y
1694         help
1695           Enable hardware performance counter support for perf events. If
1696           disabled, perf events will use software events only.
1697
1698 config SYS_SUPPORTS_HUGETLBFS
1699        def_bool y
1700        depends on ARM_LPAE
1701
1702 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1703        def_bool y
1704        depends on ARM_LPAE
1705
1706 config ARCH_WANT_GENERAL_HUGETLB
1707         def_bool y
1708
1709 source "mm/Kconfig"
1710
1711 config FORCE_MAX_ZONEORDER
1712         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1713         range 11 64 if ARCH_SHMOBILE_LEGACY
1714         default "12" if SOC_AM33XX
1715         default "9" if SA1111 || ARCH_EFM32
1716         default "11"
1717         help
1718           The kernel memory allocator divides physically contiguous memory
1719           blocks into "zones", where each zone is a power of two number of
1720           pages.  This option selects the largest power of two that the kernel
1721           keeps in the memory allocator.  If you need to allocate very large
1722           blocks of physically contiguous memory, then you may need to
1723           increase this value.
1724
1725           This config option is actually maximum order plus one. For example,
1726           a value of 11 means that the largest free memory block is 2^10 pages.
1727
1728 config ALIGNMENT_TRAP
1729         bool
1730         depends on CPU_CP15_MMU
1731         default y if !ARCH_EBSA110
1732         select HAVE_PROC_CPU if PROC_FS
1733         help
1734           ARM processors cannot fetch/store information which is not
1735           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1736           address divisible by 4. On 32-bit ARM processors, these non-aligned
1737           fetch/store instructions will be emulated in software if you say
1738           here, which has a severe performance impact. This is necessary for
1739           correct operation of some network protocols. With an IP-only
1740           configuration it is safe to say N, otherwise say Y.
1741
1742 config UACCESS_WITH_MEMCPY
1743         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1744         depends on MMU
1745         default y if CPU_FEROCEON
1746         help
1747           Implement faster copy_to_user and clear_user methods for CPU
1748           cores where a 8-word STM instruction give significantly higher
1749           memory write throughput than a sequence of individual 32bit stores.
1750
1751           A possible side effect is a slight increase in scheduling latency
1752           between threads sharing the same address space if they invoke
1753           such copy operations with large buffers.
1754
1755           However, if the CPU data cache is using a write-allocate mode,
1756           this option is unlikely to provide any performance gain.
1757
1758 config SECCOMP
1759         bool
1760         prompt "Enable seccomp to safely compute untrusted bytecode"
1761         ---help---
1762           This kernel feature is useful for number crunching applications
1763           that may need to compute untrusted bytecode during their
1764           execution. By using pipes or other transports made available to
1765           the process as file descriptors supporting the read/write
1766           syscalls, it's possible to isolate those applications in
1767           their own address space using seccomp. Once seccomp is
1768           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1769           and the task is only allowed to execute a few safe syscalls
1770           defined by each seccomp mode.
1771
1772 config SWIOTLB
1773         def_bool y
1774
1775 config IOMMU_HELPER
1776         def_bool SWIOTLB
1777
1778 config XEN_DOM0
1779         def_bool y
1780         depends on XEN
1781
1782 config XEN
1783         bool "Xen guest support on ARM"
1784         depends on ARM && AEABI && OF
1785         depends on CPU_V7 && !CPU_V6
1786         depends on !GENERIC_ATOMIC64
1787         depends on MMU
1788         select ARCH_DMA_ADDR_T_64BIT
1789         select ARM_PSCI
1790         select SWIOTLB_XEN
1791         help
1792           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1793
1794 endmenu
1795
1796 menu "Boot options"
1797
1798 config USE_OF
1799         bool "Flattened Device Tree support"
1800         select IRQ_DOMAIN
1801         select OF
1802         select OF_EARLY_FLATTREE
1803         select OF_RESERVED_MEM
1804         help
1805           Include support for flattened device tree machine descriptions.
1806
1807 config ATAGS
1808         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1809         default y
1810         help
1811           This is the traditional way of passing data to the kernel at boot
1812           time. If you are solely relying on the flattened device tree (or
1813           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1814           to remove ATAGS support from your kernel binary.  If unsure,
1815           leave this to y.
1816
1817 config DEPRECATED_PARAM_STRUCT
1818         bool "Provide old way to pass kernel parameters"
1819         depends on ATAGS
1820         help
1821           This was deprecated in 2001 and announced to live on for 5 years.
1822           Some old boot loaders still use this way.
1823
1824 # Compressed boot loader in ROM.  Yes, we really want to ask about
1825 # TEXT and BSS so we preserve their values in the config files.
1826 config ZBOOT_ROM_TEXT
1827         hex "Compressed ROM boot loader base address"
1828         default "0"
1829         help
1830           The physical address at which the ROM-able zImage is to be
1831           placed in the target.  Platforms which normally make use of
1832           ROM-able zImage formats normally set this to a suitable
1833           value in their defconfig file.
1834
1835           If ZBOOT_ROM is not enabled, this has no effect.
1836
1837 config ZBOOT_ROM_BSS
1838         hex "Compressed ROM boot loader BSS address"
1839         default "0"
1840         help
1841           The base address of an area of read/write memory in the target
1842           for the ROM-able zImage which must be available while the
1843           decompressor is running. It must be large enough to hold the
1844           entire decompressed kernel plus an additional 128 KiB.
1845           Platforms which normally make use of ROM-able zImage formats
1846           normally set this to a suitable value in their defconfig file.
1847
1848           If ZBOOT_ROM is not enabled, this has no effect.
1849
1850 config ZBOOT_ROM
1851         bool "Compressed boot loader in ROM/flash"
1852         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1853         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1854         help
1855           Say Y here if you intend to execute your compressed kernel image
1856           (zImage) directly from ROM or flash.  If unsure, say N.
1857
1858 choice
1859         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1860         depends on ZBOOT_ROM && ARCH_SH7372
1861         default ZBOOT_ROM_NONE
1862         help
1863           Include experimental SD/MMC loading code in the ROM-able zImage.
1864           With this enabled it is possible to write the ROM-able zImage
1865           kernel image to an MMC or SD card and boot the kernel straight
1866           from the reset vector. At reset the processor Mask ROM will load
1867           the first part of the ROM-able zImage which in turn loads the
1868           rest the kernel image to RAM.
1869
1870 config ZBOOT_ROM_NONE
1871         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1872         help
1873           Do not load image from SD or MMC
1874
1875 config ZBOOT_ROM_MMCIF
1876         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1877         help
1878           Load image from MMCIF hardware block.
1879
1880 config ZBOOT_ROM_SH_MOBILE_SDHI
1881         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1882         help
1883           Load image from SDHI hardware block
1884
1885 endchoice
1886
1887 config ARM_APPENDED_DTB
1888         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1889         depends on OF
1890         help
1891           With this option, the boot code will look for a device tree binary
1892           (DTB) appended to zImage
1893           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1894
1895           This is meant as a backward compatibility convenience for those
1896           systems with a bootloader that can't be upgraded to accommodate
1897           the documented boot protocol using a device tree.
1898
1899           Beware that there is very little in terms of protection against
1900           this option being confused by leftover garbage in memory that might
1901           look like a DTB header after a reboot if no actual DTB is appended
1902           to zImage.  Do not leave this option active in a production kernel
1903           if you don't intend to always append a DTB.  Proper passing of the
1904           location into r2 of a bootloader provided DTB is always preferable
1905           to this option.
1906
1907 config ARM_ATAG_DTB_COMPAT
1908         bool "Supplement the appended DTB with traditional ATAG information"
1909         depends on ARM_APPENDED_DTB
1910         help
1911           Some old bootloaders can't be updated to a DTB capable one, yet
1912           they provide ATAGs with memory configuration, the ramdisk address,
1913           the kernel cmdline string, etc.  Such information is dynamically
1914           provided by the bootloader and can't always be stored in a static
1915           DTB.  To allow a device tree enabled kernel to be used with such
1916           bootloaders, this option allows zImage to extract the information
1917           from the ATAG list and store it at run time into the appended DTB.
1918
1919 choice
1920         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1921         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1922
1923 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1924         bool "Use bootloader kernel arguments if available"
1925         help
1926           Uses the command-line options passed by the boot loader instead of
1927           the device tree bootargs property. If the boot loader doesn't provide
1928           any, the device tree bootargs property will be used.
1929
1930 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1931         bool "Extend with bootloader kernel arguments"
1932         help
1933           The command-line arguments provided by the boot loader will be
1934           appended to the the device tree bootargs property.
1935
1936 endchoice
1937
1938 config CMDLINE
1939         string "Default kernel command string"
1940         default ""
1941         help
1942           On some architectures (EBSA110 and CATS), there is currently no way
1943           for the boot loader to pass arguments to the kernel. For these
1944           architectures, you should supply some command-line options at build
1945           time by entering them here. As a minimum, you should specify the
1946           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1947
1948 choice
1949         prompt "Kernel command line type" if CMDLINE != ""
1950         default CMDLINE_FROM_BOOTLOADER
1951         depends on ATAGS
1952
1953 config CMDLINE_FROM_BOOTLOADER
1954         bool "Use bootloader kernel arguments if available"
1955         help
1956           Uses the command-line options passed by the boot loader. If
1957           the boot loader doesn't provide any, the default kernel command
1958           string provided in CMDLINE will be used.
1959
1960 config CMDLINE_EXTEND
1961         bool "Extend bootloader kernel arguments"
1962         help
1963           The command-line arguments provided by the boot loader will be
1964           appended to the default kernel command string.
1965
1966 config CMDLINE_FORCE
1967         bool "Always use the default kernel command string"
1968         help
1969           Always use the default kernel command string, even if the boot
1970           loader passes other arguments to the kernel.
1971           This is useful if you cannot or don't want to change the
1972           command-line options your boot loader passes to the kernel.
1973 endchoice
1974
1975 config XIP_KERNEL
1976         bool "Kernel Execute-In-Place from ROM"
1977         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1978         help
1979           Execute-In-Place allows the kernel to run from non-volatile storage
1980           directly addressable by the CPU, such as NOR flash. This saves RAM
1981           space since the text section of the kernel is not loaded from flash
1982           to RAM.  Read-write sections, such as the data section and stack,
1983           are still copied to RAM.  The XIP kernel is not compressed since
1984           it has to run directly from flash, so it will take more space to
1985           store it.  The flash address used to link the kernel object files,
1986           and for storing it, is configuration dependent. Therefore, if you
1987           say Y here, you must know the proper physical address where to
1988           store the kernel image depending on your own flash memory usage.
1989
1990           Also note that the make target becomes "make xipImage" rather than
1991           "make zImage" or "make Image".  The final kernel binary to put in
1992           ROM memory will be arch/arm/boot/xipImage.
1993
1994           If unsure, say N.
1995
1996 config XIP_PHYS_ADDR
1997         hex "XIP Kernel Physical Location"
1998         depends on XIP_KERNEL
1999         default "0x00080000"
2000         help
2001           This is the physical address in your flash memory the kernel will
2002           be linked for and stored to.  This address is dependent on your
2003           own flash usage.
2004
2005 config KEXEC
2006         bool "Kexec system call (EXPERIMENTAL)"
2007         depends on (!SMP || PM_SLEEP_SMP)
2008         help
2009           kexec is a system call that implements the ability to shutdown your
2010           current kernel, and to start another kernel.  It is like a reboot
2011           but it is independent of the system firmware.   And like a reboot
2012           you can start any kernel with it, not just Linux.
2013
2014           It is an ongoing process to be certain the hardware in a machine
2015           is properly shutdown, so do not be surprised if this code does not
2016           initially work for you.
2017
2018 config ATAGS_PROC
2019         bool "Export atags in procfs"
2020         depends on ATAGS && KEXEC
2021         default y
2022         help
2023           Should the atags used to boot the kernel be exported in an "atags"
2024           file in procfs. Useful with kexec.
2025
2026 config CRASH_DUMP
2027         bool "Build kdump crash kernel (EXPERIMENTAL)"
2028         help
2029           Generate crash dump after being started by kexec. This should
2030           be normally only set in special crash dump kernels which are
2031           loaded in the main kernel with kexec-tools into a specially
2032           reserved region and then later executed after a crash by
2033           kdump/kexec. The crash dump kernel must be compiled to a
2034           memory address not used by the main kernel
2035
2036           For more details see Documentation/kdump/kdump.txt
2037
2038 config AUTO_ZRELADDR
2039         bool "Auto calculation of the decompressed kernel image address"
2040         help
2041           ZRELADDR is the physical address where the decompressed kernel
2042           image will be placed. If AUTO_ZRELADDR is selected, the address
2043           will be determined at run-time by masking the current IP with
2044           0xf8000000. This assumes the zImage being placed in the first 128MB
2045           from start of memory.
2046
2047 endmenu
2048
2049 menu "CPU Power Management"
2050
2051 source "drivers/cpufreq/Kconfig"
2052
2053 source "drivers/cpuidle/Kconfig"
2054
2055 endmenu
2056
2057 menu "Floating point emulation"
2058
2059 comment "At least one emulation must be selected"
2060
2061 config FPE_NWFPE
2062         bool "NWFPE math emulation"
2063         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2064         ---help---
2065           Say Y to include the NWFPE floating point emulator in the kernel.
2066           This is necessary to run most binaries. Linux does not currently
2067           support floating point hardware so you need to say Y here even if
2068           your machine has an FPA or floating point co-processor podule.
2069
2070           You may say N here if you are going to load the Acorn FPEmulator
2071           early in the bootup.
2072
2073 config FPE_NWFPE_XP
2074         bool "Support extended precision"
2075         depends on FPE_NWFPE
2076         help
2077           Say Y to include 80-bit support in the kernel floating-point
2078           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2079           Note that gcc does not generate 80-bit operations by default,
2080           so in most cases this option only enlarges the size of the
2081           floating point emulator without any good reason.
2082
2083           You almost surely want to say N here.
2084
2085 config FPE_FASTFPE
2086         bool "FastFPE math emulation (EXPERIMENTAL)"
2087         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2088         ---help---
2089           Say Y here to include the FAST floating point emulator in the kernel.
2090           This is an experimental much faster emulator which now also has full
2091           precision for the mantissa.  It does not support any exceptions.
2092           It is very simple, and approximately 3-6 times faster than NWFPE.
2093
2094           It should be sufficient for most programs.  It may be not suitable
2095           for scientific calculations, but you have to check this for yourself.
2096           If you do not feel you need a faster FP emulation you should better
2097           choose NWFPE.
2098
2099 config VFP
2100         bool "VFP-format floating point maths"
2101         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2102         help
2103           Say Y to include VFP support code in the kernel. This is needed
2104           if your hardware includes a VFP unit.
2105
2106           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2107           release notes and additional status information.
2108
2109           Say N if your target does not have VFP hardware.
2110
2111 config VFPv3
2112         bool
2113         depends on VFP
2114         default y if CPU_V7
2115
2116 config NEON
2117         bool "Advanced SIMD (NEON) Extension support"
2118         depends on VFPv3 && CPU_V7
2119         help
2120           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2121           Extension.
2122
2123 config KERNEL_MODE_NEON
2124         bool "Support for NEON in kernel mode"
2125         depends on NEON && AEABI
2126         help
2127           Say Y to include support for NEON in kernel mode.
2128
2129 endmenu
2130
2131 menu "Userspace binary formats"
2132
2133 source "fs/Kconfig.binfmt"
2134
2135 config ARTHUR
2136         tristate "RISC OS personality"
2137         depends on !AEABI
2138         help
2139           Say Y here to include the kernel code necessary if you want to run
2140           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2141           experimental; if this sounds frightening, say N and sleep in peace.
2142           You can also say M here to compile this support as a module (which
2143           will be called arthur).
2144
2145 endmenu
2146
2147 menu "Power management options"
2148
2149 source "kernel/power/Kconfig"
2150
2151 config ARCH_SUSPEND_POSSIBLE
2152         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2153                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2154         def_bool y
2155
2156 config ARM_CPU_SUSPEND
2157         def_bool PM_SLEEP
2158
2159 config ARCH_HIBERNATION_POSSIBLE
2160         bool
2161         depends on MMU
2162         default y if ARCH_SUSPEND_POSSIBLE
2163
2164 endmenu
2165
2166 source "net/Kconfig"
2167
2168 source "drivers/Kconfig"
2169
2170 source "fs/Kconfig"
2171
2172 source "arch/arm/Kconfig.debug"
2173
2174 source "security/Kconfig"
2175
2176 source "crypto/Kconfig"
2177
2178 source "lib/Kconfig"
2179
2180 source "arch/arm/kvm/Kconfig"