4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_GPIO_H
208 Select this when mach/gpio.h is required to provide special
209 definitions for this platform. The need for mach/gpio.h should
210 be avoided when possible.
212 config NEED_MACH_IO_H
215 Select this when mach/io.h is required to provide special
216 definitions for this platform. The need for mach/io.h should
217 be avoided when possible.
219 config NEED_MACH_MEMORY_H
222 Select this when mach/memory.h is required to provide special
223 definitions for this platform. The need for mach/memory.h should
224 be avoided when possible.
227 hex "Physical address of main memory" if MMU
228 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
229 default DRAM_BASE if !MMU
231 Please provide the physical address corresponding to the
232 location of main memory in your system.
238 source "init/Kconfig"
240 source "kernel/Kconfig.freezer"
245 bool "MMU-based Paged Memory Management Support"
248 Select if you want MMU-based virtualised addressing space
249 support by paged memory management. If unsure, say 'Y'.
252 # The "ARM system type" choice list is ordered alphabetically by option
253 # text. Please add new entries in the option alphabetic order.
256 prompt "ARM system type"
257 default ARCH_MULTIPLATFORM
259 config ARCH_MULTIPLATFORM
260 bool "Allow multiple platforms to be selected"
261 select ARM_PATCH_PHYS_VIRT
264 select MULTI_IRQ_HANDLER
269 config ARCH_INTEGRATOR
270 bool "ARM Ltd. Integrator family"
272 select ARCH_HAS_CPUFREQ
274 select COMMON_CLK_VERSATILE
277 select GENERIC_CLOCKEVENTS
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_FPGA_IRQ
280 select NEED_MACH_MEMORY_H
282 select MULTI_IRQ_HANDLER
284 Support for ARM's Integrator platform.
287 bool "ARM Ltd. RealView family"
290 select COMMON_CLK_VERSATILE
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select ARM_TIMER_SP804
297 select GPIO_PL061 if GPIOLIB
298 select NEED_MACH_MEMORY_H
300 This enables support for ARM Ltd RealView boards.
302 config ARCH_VERSATILE
303 bool "ARM Ltd. Versatile family"
307 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLOCK
313 select PLAT_VERSATILE_CLCD
314 select PLAT_VERSATILE_FPGA_IRQ
315 select ARM_TIMER_SP804
317 This enables support for ARM Ltd Versatile board.
321 select ARCH_REQUIRE_GPIOLIB
325 select NEED_MACH_GPIO_H
326 select NEED_MACH_IO_H if PCCARD
328 This enables support for systems based on Atmel
329 AT91RM9200 and AT91SAM9* processors.
332 bool "Broadcom BCM2835 family"
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 select ARM_ERRATA_411920
336 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select MULTI_IRQ_HANDLER
345 This enables support for the Broadcom BCM2835 SoC. This SoC is
346 use in the Raspberry Pi, and Roku 2 devices.
349 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
351 select ARCH_USES_GETTIMEOFFSET
354 select NEED_MACH_MEMORY_H
356 Support for Cirrus Logic 711x/721x/731x based boards.
359 bool "Cavium Networks CNS3XXX family"
361 select GENERIC_CLOCKEVENTS
363 select MIGHT_HAVE_CACHE_L2X0
364 select MIGHT_HAVE_PCI
365 select PCI_DOMAINS if PCI
367 Support for Cavium Networks CNS3XXX platform.
370 bool "Cortina Systems Gemini"
372 select ARCH_REQUIRE_GPIOLIB
373 select ARCH_USES_GETTIMEOFFSET
375 Support for the Cortina Systems Gemini family SoCs
380 select ARCH_REQUIRE_GPIOLIB
381 select GENERIC_CLOCKEVENTS
383 select GENERIC_IRQ_CHIP
384 select MIGHT_HAVE_CACHE_L2X0
389 Support for CSR SiRFprimaII/Marco/Polo platforms
396 select ARCH_USES_GETTIMEOFFSET
397 select NEED_MACH_IO_H
398 select NEED_MACH_MEMORY_H
400 This is an evaluation board for the StrongARM processor available
401 from Digital. It has limited hardware on-board, including an
402 Ethernet interface, two PCMCIA sockets, two serial ports and a
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_HAS_HOLES_MEMORYMODEL
413 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_MEMORY_H
416 This enables support for the Cirrus EP93xx series of CPUs.
418 config ARCH_FOOTBRIDGE
422 select GENERIC_CLOCKEVENTS
424 select NEED_MACH_IO_H if !MMU
425 select NEED_MACH_MEMORY_H
427 Support for systems based on the DC21285 companion chip
428 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
431 bool "Freescale MXC/iMX-based"
432 select GENERIC_CLOCKEVENTS
433 select ARCH_REQUIRE_GPIOLIB
436 select GENERIC_IRQ_CHIP
437 select MULTI_IRQ_HANDLER
441 Support for Freescale MXC/iMX-based family of processors
444 bool "Freescale MXS-based"
445 select GENERIC_CLOCKEVENTS
446 select ARCH_REQUIRE_GPIOLIB
450 select HAVE_CLK_PREPARE
451 select MULTI_IRQ_HANDLER
456 Support for Freescale MXS-based family of processors
459 bool "Hilscher NetX based"
463 select GENERIC_CLOCKEVENTS
465 This enables support for systems based on the Hilscher NetX Soc
468 bool "Hynix HMS720x-based"
471 select ARCH_USES_GETTIMEOFFSET
473 This enables support for systems based on the Hynix HMS720x
481 select ARCH_SUPPORTS_MSI
483 select NEED_MACH_MEMORY_H
484 select NEED_RET_TO_USER
486 Support for Intel's IOP13XX (XScale) family of processors.
492 select NEED_MACH_GPIO_H
493 select NEED_MACH_IO_H
494 select NEED_RET_TO_USER
497 select ARCH_REQUIRE_GPIOLIB
499 Support for Intel's 80219 and IOP32X (XScale) family of
506 select NEED_MACH_GPIO_H
507 select NEED_MACH_IO_H
508 select NEED_RET_TO_USER
511 select ARCH_REQUIRE_GPIOLIB
513 Support for Intel's IOP33X (XScale) family of processors.
518 select ARCH_HAS_DMA_SET_COHERENT_MASK
521 select ARCH_REQUIRE_GPIOLIB
522 select GENERIC_CLOCKEVENTS
523 select MIGHT_HAVE_PCI
524 select NEED_MACH_IO_H
525 select DMABOUNCE if PCI
527 Support for Intel's IXP4XX (XScale) family of processors.
533 select ARCH_REQUIRE_GPIOLIB
534 select GENERIC_CLOCKEVENTS
537 Support for the Marvell Dove SoC 88AP510
540 bool "Marvell Kirkwood"
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
547 Support for the following Marvell Kirkwood series SoCs:
548 88F6180, 88F6192 and 88F6281.
554 select ARCH_REQUIRE_GPIOLIB
557 select USB_ARCH_HAS_OHCI
559 select GENERIC_CLOCKEVENTS
563 Support for the NXP LPC32XX family of processors
566 bool "Marvell MV78xx0"
569 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
573 Support for the following Marvell MV78xx0 series SoCs:
581 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
585 Support for the following Marvell Orion 5x series SoCs:
586 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
587 Orion-2 (5281), Orion-1-90 (6183).
590 bool "Marvell PXA168/910/MMP2"
592 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
599 select GENERIC_ALLOCATOR
600 select NEED_MACH_GPIO_H
602 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
605 bool "Micrel/Kendin KS8695"
607 select ARCH_REQUIRE_GPIOLIB
608 select NEED_MACH_MEMORY_H
610 select GENERIC_CLOCKEVENTS
612 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
613 System-on-Chip devices.
616 bool "Nuvoton W90X900 CPU"
618 select ARCH_REQUIRE_GPIOLIB
621 select GENERIC_CLOCKEVENTS
623 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
624 At present, the w90x900 has been renamed nuc900, regarding
625 the ARM series product line, you can login the following
626 link address to know more.
628 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
629 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
635 select GENERIC_CLOCKEVENTS
639 select MIGHT_HAVE_CACHE_L2X0
640 select ARCH_HAS_CPUFREQ
644 This enables support for NVIDIA Tegra based systems (Tegra APX,
645 Tegra 6xx and Tegra 2 series).
648 bool "PXA2xx/PXA3xx-based"
651 select ARCH_HAS_CPUFREQ
654 select ARCH_REQUIRE_GPIOLIB
655 select GENERIC_CLOCKEVENTS
660 select MULTI_IRQ_HANDLER
661 select ARM_CPU_SUSPEND if PM
663 select NEED_MACH_GPIO_H
665 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
670 select GENERIC_CLOCKEVENTS
671 select ARCH_REQUIRE_GPIOLIB
674 Support for Qualcomm MSM/QSD based systems. This runs on the
675 apps processor of the MSM/QSD and depends on a shared memory
676 interface to the modem processor which runs the baseband
677 stack and controls some vital subsystems
678 (clock and power control, etc).
681 bool "Renesas SH-Mobile / R-Mobile"
684 select HAVE_MACH_CLKDEV
686 select GENERIC_CLOCKEVENTS
687 select MIGHT_HAVE_CACHE_L2X0
690 select MULTI_IRQ_HANDLER
691 select PM_GENERIC_DOMAINS if PM
692 select NEED_MACH_MEMORY_H
694 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
700 select ARCH_MAY_HAVE_PC_FDC
701 select HAVE_PATA_PLATFORM
704 select ARCH_SPARSEMEM_ENABLE
705 select ARCH_USES_GETTIMEOFFSET
707 select NEED_MACH_IO_H
708 select NEED_MACH_MEMORY_H
710 On the Acorn Risc-PC, Linux can support the internal IDE disk and
711 CD-ROM interface, serial and parallel port, and the floppy drive.
718 select ARCH_SPARSEMEM_ENABLE
720 select ARCH_HAS_CPUFREQ
722 select GENERIC_CLOCKEVENTS
724 select ARCH_REQUIRE_GPIOLIB
726 select NEED_MACH_GPIO_H
727 select NEED_MACH_MEMORY_H
730 Support for StrongARM 11x0 based boards.
733 bool "Samsung S3C24XX SoCs"
735 select ARCH_HAS_CPUFREQ
738 select ARCH_USES_GETTIMEOFFSET
739 select HAVE_S3C2410_I2C if I2C
740 select HAVE_S3C_RTC if RTC_CLASS
741 select HAVE_S3C2410_WATCHDOG if WATCHDOG
742 select NEED_MACH_GPIO_H
743 select NEED_MACH_IO_H
745 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
746 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
747 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
748 Samsung SMDK2410 development board (and derivatives).
751 bool "Samsung S3C64XX"
759 select ARCH_USES_GETTIMEOFFSET
760 select ARCH_HAS_CPUFREQ
761 select ARCH_REQUIRE_GPIOLIB
762 select SAMSUNG_CLKSRC
763 select SAMSUNG_IRQ_VIC_TIMER
764 select S3C_GPIO_TRACK
766 select USB_ARCH_HAS_OHCI
767 select SAMSUNG_GPIOLIB_4BIT
768 select HAVE_S3C2410_I2C if I2C
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 select NEED_MACH_GPIO_H
772 Samsung S3C64XX series based systems
775 bool "Samsung S5P6440 S5P6450"
781 select HAVE_S3C2410_WATCHDOG if WATCHDOG
782 select GENERIC_CLOCKEVENTS
783 select HAVE_S3C2410_I2C if I2C
784 select HAVE_S3C_RTC if RTC_CLASS
785 select NEED_MACH_GPIO_H
787 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
791 bool "Samsung S5PC100"
796 select ARCH_USES_GETTIMEOFFSET
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C_RTC if RTC_CLASS
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select NEED_MACH_GPIO_H
802 Samsung S5PC100 series based systems
805 bool "Samsung S5PV210/S5PC110"
807 select ARCH_SPARSEMEM_ENABLE
808 select ARCH_HAS_HOLES_MEMORYMODEL
813 select ARCH_HAS_CPUFREQ
814 select GENERIC_CLOCKEVENTS
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C_RTC if RTC_CLASS
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 select NEED_MACH_GPIO_H
819 select NEED_MACH_MEMORY_H
821 Samsung S5PV210/S5PC110 series based systems
824 bool "SAMSUNG EXYNOS"
826 select ARCH_SPARSEMEM_ENABLE
827 select ARCH_HAS_HOLES_MEMORYMODEL
831 select ARCH_HAS_CPUFREQ
832 select GENERIC_CLOCKEVENTS
833 select HAVE_S3C_RTC if RTC_CLASS
834 select HAVE_S3C2410_I2C if I2C
835 select HAVE_S3C2410_WATCHDOG if WATCHDOG
836 select NEED_MACH_GPIO_H
837 select NEED_MACH_MEMORY_H
839 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
848 select ARCH_USES_GETTIMEOFFSET
849 select NEED_MACH_MEMORY_H
851 Support for the StrongARM based Digital DNARD machine, also known
852 as "Shark" (<http://www.shark-linux.de/shark.html>).
855 bool "ST-Ericsson U300 Series"
861 select ARM_PATCH_PHYS_VIRT
863 select GENERIC_CLOCKEVENTS
867 select ARCH_REQUIRE_GPIOLIB
870 Support for ST-Ericsson U300 series mobile platforms.
873 bool "ST-Ericsson U8500 Series"
877 select GENERIC_CLOCKEVENTS
879 select ARCH_REQUIRE_GPIOLIB
880 select ARCH_HAS_CPUFREQ
882 select MIGHT_HAVE_CACHE_L2X0
884 Support for ST-Ericsson's Ux500 architecture
887 bool "STMicroelectronics Nomadik"
892 select GENERIC_CLOCKEVENTS
894 select PINCTRL_STN8815
895 select MIGHT_HAVE_CACHE_L2X0
896 select ARCH_REQUIRE_GPIOLIB
898 Support for the Nomadik platform by ST-Ericsson
902 select GENERIC_CLOCKEVENTS
903 select ARCH_REQUIRE_GPIOLIB
907 select GENERIC_ALLOCATOR
908 select GENERIC_IRQ_CHIP
909 select ARCH_HAS_HOLES_MEMORYMODEL
910 select NEED_MACH_GPIO_H
912 Support for TI's DaVinci platform.
918 select ARCH_REQUIRE_GPIOLIB
919 select ARCH_HAS_CPUFREQ
921 select GENERIC_CLOCKEVENTS
922 select ARCH_HAS_HOLES_MEMORYMODEL
923 select NEED_MACH_GPIO_H
925 Support for TI's OMAP platform (OMAP1/2/3/4).
930 select ARCH_REQUIRE_GPIOLIB
934 select GENERIC_CLOCKEVENTS
937 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
940 bool "VIA/WonderMedia 85xx"
943 select ARCH_HAS_CPUFREQ
944 select GENERIC_CLOCKEVENTS
945 select ARCH_REQUIRE_GPIOLIB
951 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
954 bool "Xilinx Zynq ARM Cortex A9 Platform"
956 select GENERIC_CLOCKEVENTS
961 select MIGHT_HAVE_CACHE_L2X0
964 Support for Xilinx Zynq ARM Cortex A9 Platform
967 menu "Multiple platform selection"
968 depends on ARCH_MULTIPLATFORM
970 comment "CPU Core family selection"
973 bool "ARMv4 based platforms (FA526, StrongARM)"
974 select ARCH_MULTI_V4_V5
975 depends on !ARCH_MULTI_V6_V7
977 config ARCH_MULTI_V4T
978 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
979 select ARCH_MULTI_V4_V5
980 depends on !ARCH_MULTI_V6_V7
983 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
984 select ARCH_MULTI_V4_V5
985 depends on !ARCH_MULTI_V6_V7
987 config ARCH_MULTI_V4_V5
991 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
993 select ARCH_MULTI_V6_V7
996 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1000 select ARCH_MULTI_V6_V7
1002 config ARCH_MULTI_V6_V7
1005 config ARCH_MULTI_CPU_AUTO
1006 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1007 select ARCH_MULTI_V5
1012 # This is sorted alphabetically by mach-* pathname. However, plat-*
1013 # Kconfigs may be included either alphabetically (according to the
1014 # plat- suffix) or along side the corresponding mach-* source.
1016 source "arch/arm/mach-mvebu/Kconfig"
1018 source "arch/arm/mach-at91/Kconfig"
1020 source "arch/arm/mach-clps711x/Kconfig"
1022 source "arch/arm/mach-cns3xxx/Kconfig"
1024 source "arch/arm/mach-davinci/Kconfig"
1026 source "arch/arm/mach-dove/Kconfig"
1028 source "arch/arm/mach-ep93xx/Kconfig"
1030 source "arch/arm/mach-footbridge/Kconfig"
1032 source "arch/arm/mach-gemini/Kconfig"
1034 source "arch/arm/mach-h720x/Kconfig"
1036 source "arch/arm/mach-highbank/Kconfig"
1038 source "arch/arm/mach-integrator/Kconfig"
1040 source "arch/arm/mach-iop32x/Kconfig"
1042 source "arch/arm/mach-iop33x/Kconfig"
1044 source "arch/arm/mach-iop13xx/Kconfig"
1046 source "arch/arm/mach-ixp4xx/Kconfig"
1048 source "arch/arm/mach-kirkwood/Kconfig"
1050 source "arch/arm/mach-ks8695/Kconfig"
1052 source "arch/arm/mach-msm/Kconfig"
1054 source "arch/arm/mach-mv78xx0/Kconfig"
1056 source "arch/arm/plat-mxc/Kconfig"
1058 source "arch/arm/mach-mxs/Kconfig"
1060 source "arch/arm/mach-netx/Kconfig"
1062 source "arch/arm/mach-nomadik/Kconfig"
1063 source "arch/arm/plat-nomadik/Kconfig"
1065 source "arch/arm/plat-omap/Kconfig"
1067 source "arch/arm/mach-omap1/Kconfig"
1069 source "arch/arm/mach-omap2/Kconfig"
1071 source "arch/arm/mach-orion5x/Kconfig"
1073 source "arch/arm/mach-picoxcell/Kconfig"
1075 source "arch/arm/mach-pxa/Kconfig"
1076 source "arch/arm/plat-pxa/Kconfig"
1078 source "arch/arm/mach-mmp/Kconfig"
1080 source "arch/arm/mach-realview/Kconfig"
1082 source "arch/arm/mach-sa1100/Kconfig"
1084 source "arch/arm/plat-samsung/Kconfig"
1085 source "arch/arm/plat-s3c24xx/Kconfig"
1087 source "arch/arm/mach-socfpga/Kconfig"
1089 source "arch/arm/plat-spear/Kconfig"
1091 source "arch/arm/mach-s3c24xx/Kconfig"
1093 source "arch/arm/mach-s3c2412/Kconfig"
1094 source "arch/arm/mach-s3c2440/Kconfig"
1098 source "arch/arm/mach-s3c64xx/Kconfig"
1101 source "arch/arm/mach-s5p64x0/Kconfig"
1103 source "arch/arm/mach-s5pc100/Kconfig"
1105 source "arch/arm/mach-s5pv210/Kconfig"
1107 source "arch/arm/mach-exynos/Kconfig"
1109 source "arch/arm/mach-shmobile/Kconfig"
1111 source "arch/arm/mach-prima2/Kconfig"
1113 source "arch/arm/mach-tegra/Kconfig"
1115 source "arch/arm/mach-u300/Kconfig"
1117 source "arch/arm/mach-ux500/Kconfig"
1119 source "arch/arm/mach-versatile/Kconfig"
1121 source "arch/arm/mach-vexpress/Kconfig"
1122 source "arch/arm/plat-versatile/Kconfig"
1124 source "arch/arm/mach-w90x900/Kconfig"
1126 # Definitions to make life easier
1132 select GENERIC_CLOCKEVENTS
1137 select GENERIC_IRQ_CHIP
1144 config PLAT_VERSATILE
1147 config ARM_TIMER_SP804
1150 select HAVE_SCHED_CLOCK
1152 source arch/arm/mm/Kconfig
1156 default 16 if ARCH_EP93XX
1160 bool "Enable iWMMXt support"
1161 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1162 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1164 Enable support for iWMMXt context switching at run time if
1165 running on a CPU that supports it.
1169 depends on CPU_XSCALE
1172 config MULTI_IRQ_HANDLER
1175 Allow each machine to specify it's own IRQ handler at run time.
1178 source "arch/arm/Kconfig-nommu"
1181 config ARM_ERRATA_326103
1182 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1185 Executing a SWP instruction to read-only memory does not set bit 11
1186 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1187 treat the access as a read, preventing a COW from occurring and
1188 causing the faulting task to livelock.
1190 config ARM_ERRATA_411920
1191 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1192 depends on CPU_V6 || CPU_V6K
1194 Invalidation of the Instruction Cache operation can
1195 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1196 It does not affect the MPCore. This option enables the ARM Ltd.
1197 recommended workaround.
1199 config ARM_ERRATA_430973
1200 bool "ARM errata: Stale prediction on replaced interworking branch"
1203 This option enables the workaround for the 430973 Cortex-A8
1204 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1205 interworking branch is replaced with another code sequence at the
1206 same virtual address, whether due to self-modifying code or virtual
1207 to physical address re-mapping, Cortex-A8 does not recover from the
1208 stale interworking branch prediction. This results in Cortex-A8
1209 executing the new code sequence in the incorrect ARM or Thumb state.
1210 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1211 and also flushes the branch target cache at every context switch.
1212 Note that setting specific bits in the ACTLR register may not be
1213 available in non-secure mode.
1215 config ARM_ERRATA_458693
1216 bool "ARM errata: Processor deadlock when a false hazard is created"
1219 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1220 erratum. For very specific sequences of memory operations, it is
1221 possible for a hazard condition intended for a cache line to instead
1222 be incorrectly associated with a different cache line. This false
1223 hazard might then cause a processor deadlock. The workaround enables
1224 the L1 caching of the NEON accesses and disables the PLD instruction
1225 in the ACTLR register. Note that setting specific bits in the ACTLR
1226 register may not be available in non-secure mode.
1228 config ARM_ERRATA_460075
1229 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1232 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1233 erratum. Any asynchronous access to the L2 cache may encounter a
1234 situation in which recent store transactions to the L2 cache are lost
1235 and overwritten with stale memory contents from external memory. The
1236 workaround disables the write-allocate mode for the L2 cache via the
1237 ACTLR register. Note that setting specific bits in the ACTLR register
1238 may not be available in non-secure mode.
1240 config ARM_ERRATA_742230
1241 bool "ARM errata: DMB operation may be faulty"
1242 depends on CPU_V7 && SMP
1244 This option enables the workaround for the 742230 Cortex-A9
1245 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1246 between two write operations may not ensure the correct visibility
1247 ordering of the two writes. This workaround sets a specific bit in
1248 the diagnostic register of the Cortex-A9 which causes the DMB
1249 instruction to behave as a DSB, ensuring the correct behaviour of
1252 config ARM_ERRATA_742231
1253 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1254 depends on CPU_V7 && SMP
1256 This option enables the workaround for the 742231 Cortex-A9
1257 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1258 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1259 accessing some data located in the same cache line, may get corrupted
1260 data due to bad handling of the address hazard when the line gets
1261 replaced from one of the CPUs at the same time as another CPU is
1262 accessing it. This workaround sets specific bits in the diagnostic
1263 register of the Cortex-A9 which reduces the linefill issuing
1264 capabilities of the processor.
1266 config PL310_ERRATA_588369
1267 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1268 depends on CACHE_L2X0
1270 The PL310 L2 cache controller implements three types of Clean &
1271 Invalidate maintenance operations: by Physical Address
1272 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1273 They are architecturally defined to behave as the execution of a
1274 clean operation followed immediately by an invalidate operation,
1275 both performing to the same memory location. This functionality
1276 is not correctly implemented in PL310 as clean lines are not
1277 invalidated as a result of these operations.
1279 config ARM_ERRATA_720789
1280 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1283 This option enables the workaround for the 720789 Cortex-A9 (prior to
1284 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1285 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1286 As a consequence of this erratum, some TLB entries which should be
1287 invalidated are not, resulting in an incoherency in the system page
1288 tables. The workaround changes the TLB flushing routines to invalidate
1289 entries regardless of the ASID.
1291 config PL310_ERRATA_727915
1292 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1293 depends on CACHE_L2X0
1295 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1296 operation (offset 0x7FC). This operation runs in background so that
1297 PL310 can handle normal accesses while it is in progress. Under very
1298 rare circumstances, due to this erratum, write data can be lost when
1299 PL310 treats a cacheable write transaction during a Clean &
1300 Invalidate by Way operation.
1302 config ARM_ERRATA_743622
1303 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1306 This option enables the workaround for the 743622 Cortex-A9
1307 (r2p*) erratum. Under very rare conditions, a faulty
1308 optimisation in the Cortex-A9 Store Buffer may lead to data
1309 corruption. This workaround sets a specific bit in the diagnostic
1310 register of the Cortex-A9 which disables the Store Buffer
1311 optimisation, preventing the defect from occurring. This has no
1312 visible impact on the overall performance or power consumption of the
1315 config ARM_ERRATA_751472
1316 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1319 This option enables the workaround for the 751472 Cortex-A9 (prior
1320 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1321 completion of a following broadcasted operation if the second
1322 operation is received by a CPU before the ICIALLUIS has completed,
1323 potentially leading to corrupted entries in the cache or TLB.
1325 config PL310_ERRATA_753970
1326 bool "PL310 errata: cache sync operation may be faulty"
1327 depends on CACHE_PL310
1329 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1331 Under some condition the effect of cache sync operation on
1332 the store buffer still remains when the operation completes.
1333 This means that the store buffer is always asked to drain and
1334 this prevents it from merging any further writes. The workaround
1335 is to replace the normal offset of cache sync operation (0x730)
1336 by another offset targeting an unmapped PL310 register 0x740.
1337 This has the same effect as the cache sync operation: store buffer
1338 drain and waiting for all buffers empty.
1340 config ARM_ERRATA_754322
1341 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1344 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1345 r3p*) erratum. A speculative memory access may cause a page table walk
1346 which starts prior to an ASID switch but completes afterwards. This
1347 can populate the micro-TLB with a stale entry which may be hit with
1348 the new ASID. This workaround places two dsb instructions in the mm
1349 switching code so that no page table walks can cross the ASID switch.
1351 config ARM_ERRATA_754327
1352 bool "ARM errata: no automatic Store Buffer drain"
1353 depends on CPU_V7 && SMP
1355 This option enables the workaround for the 754327 Cortex-A9 (prior to
1356 r2p0) erratum. The Store Buffer does not have any automatic draining
1357 mechanism and therefore a livelock may occur if an external agent
1358 continuously polls a memory location waiting to observe an update.
1359 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1360 written polling loops from denying visibility of updates to memory.
1362 config ARM_ERRATA_364296
1363 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1364 depends on CPU_V6 && !SMP
1366 This options enables the workaround for the 364296 ARM1136
1367 r0p2 erratum (possible cache data corruption with
1368 hit-under-miss enabled). It sets the undocumented bit 31 in
1369 the auxiliary control register and the FI bit in the control
1370 register, thus disabling hit-under-miss without putting the
1371 processor into full low interrupt latency mode. ARM11MPCore
1374 config ARM_ERRATA_764369
1375 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1376 depends on CPU_V7 && SMP
1378 This option enables the workaround for erratum 764369
1379 affecting Cortex-A9 MPCore with two or more processors (all
1380 current revisions). Under certain timing circumstances, a data
1381 cache line maintenance operation by MVA targeting an Inner
1382 Shareable memory region may fail to proceed up to either the
1383 Point of Coherency or to the Point of Unification of the
1384 system. This workaround adds a DSB instruction before the
1385 relevant cache maintenance functions and sets a specific bit
1386 in the diagnostic control register of the SCU.
1388 config PL310_ERRATA_769419
1389 bool "PL310 errata: no automatic Store Buffer drain"
1390 depends on CACHE_L2X0
1392 On revisions of the PL310 prior to r3p2, the Store Buffer does
1393 not automatically drain. This can cause normal, non-cacheable
1394 writes to be retained when the memory system is idle, leading
1395 to suboptimal I/O performance for drivers using coherent DMA.
1396 This option adds a write barrier to the cpu_idle loop so that,
1397 on systems with an outer cache, the store buffer is drained
1402 source "arch/arm/common/Kconfig"
1412 Find out whether you have ISA slots on your motherboard. ISA is the
1413 name of a bus system, i.e. the way the CPU talks to the other stuff
1414 inside your box. Other bus systems are PCI, EISA, MicroChannel
1415 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1416 newer boards don't support it. If you have ISA, say Y, otherwise N.
1418 # Select ISA DMA controller support
1423 # Select ISA DMA interface
1428 bool "PCI support" if MIGHT_HAVE_PCI
1430 Find out whether you have a PCI motherboard. PCI is the name of a
1431 bus system, i.e. the way the CPU talks to the other stuff inside
1432 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1433 VESA. If you have PCI, say Y, otherwise N.
1439 config PCI_NANOENGINE
1440 bool "BSE nanoEngine PCI support"
1441 depends on SA1100_NANOENGINE
1443 Enable PCI on the BSE nanoEngine board.
1448 # Select the host bridge type
1449 config PCI_HOST_VIA82C505
1451 depends on PCI && ARCH_SHARK
1454 config PCI_HOST_ITE8152
1456 depends on PCI && MACH_ARMCORE
1460 source "drivers/pci/Kconfig"
1462 source "drivers/pcmcia/Kconfig"
1466 menu "Kernel Features"
1471 This option should be selected by machines which have an SMP-
1474 The only effect of this option is to make the SMP-related
1475 options available to the user for configuration.
1478 bool "Symmetric Multi-Processing"
1479 depends on CPU_V6K || CPU_V7
1480 depends on GENERIC_CLOCKEVENTS
1483 select USE_GENERIC_SMP_HELPERS
1484 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1486 This enables support for systems with more than one CPU. If you have
1487 a system with only one CPU, like most personal computers, say N. If
1488 you have a system with more than one CPU, say Y.
1490 If you say N here, the kernel will run on single and multiprocessor
1491 machines, but will use only one CPU of a multiprocessor machine. If
1492 you say Y here, the kernel will run on many, but not all, single
1493 processor machines. On a single processor machine, the kernel will
1494 run faster if you say N here.
1496 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1497 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1498 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1500 If you don't know what to do here, say N.
1503 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1504 depends on EXPERIMENTAL
1505 depends on SMP && !XIP_KERNEL
1508 SMP kernels contain instructions which fail on non-SMP processors.
1509 Enabling this option allows the kernel to modify itself to make
1510 these instructions safe. Disabling it allows about 1K of space
1513 If you don't know what to do here, say Y.
1515 config ARM_CPU_TOPOLOGY
1516 bool "Support cpu topology definition"
1517 depends on SMP && CPU_V7
1520 Support ARM cpu topology definition. The MPIDR register defines
1521 affinity between processors which is then used to describe the cpu
1522 topology of an ARM System.
1525 bool "Multi-core scheduler support"
1526 depends on ARM_CPU_TOPOLOGY
1528 Multi-core scheduler support improves the CPU scheduler's decision
1529 making when dealing with multi-core CPU chips at a cost of slightly
1530 increased overhead in some places. If unsure say N here.
1533 bool "SMT scheduler support"
1534 depends on ARM_CPU_TOPOLOGY
1536 Improves the CPU scheduler's decision making when dealing with
1537 MultiThreading at a cost of slightly increased overhead in some
1538 places. If unsure say N here.
1543 This option enables support for the ARM system coherency unit
1545 config ARM_ARCH_TIMER
1546 bool "Architected timer support"
1549 This option enables support for the ARM architected timer
1555 This options enables support for the ARM timer and watchdog unit
1558 prompt "Memory split"
1561 Select the desired split between kernel and user memory.
1563 If you are not absolutely sure what you are doing, leave this
1567 bool "3G/1G user/kernel split"
1569 bool "2G/2G user/kernel split"
1571 bool "1G/3G user/kernel split"
1576 default 0x40000000 if VMSPLIT_1G
1577 default 0x80000000 if VMSPLIT_2G
1581 int "Maximum number of CPUs (2-32)"
1587 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1588 depends on SMP && HOTPLUG && EXPERIMENTAL
1590 Say Y here to experiment with turning CPUs off and on. CPUs
1591 can be controlled through /sys/devices/system/cpu.
1594 bool "Use local timer interrupts"
1597 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1599 Enable support for local timers on SMP platforms, rather then the
1600 legacy IPI broadcast method. Local timers allows the system
1601 accounting to be spread across the timer interval, preventing a
1602 "thundering herd" at every timer tick.
1606 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1607 default 355 if ARCH_U8500
1608 default 264 if MACH_H4700
1609 default 512 if SOC_OMAP5
1610 default 288 if ARCH_VT8500
1613 Maximum number of GPIOs in the system.
1615 If unsure, leave the default value.
1617 source kernel/Kconfig.preempt
1621 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1622 ARCH_S5PV210 || ARCH_EXYNOS4
1623 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1624 default AT91_TIMER_HZ if ARCH_AT91
1625 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1628 config THUMB2_KERNEL
1629 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1630 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1632 select ARM_ASM_UNIFIED
1635 By enabling this option, the kernel will be compiled in
1636 Thumb-2 mode. A compiler/assembler that understand the unified
1637 ARM-Thumb syntax is needed.
1641 config THUMB2_AVOID_R_ARM_THM_JUMP11
1642 bool "Work around buggy Thumb-2 short branch relocations in gas"
1643 depends on THUMB2_KERNEL && MODULES
1646 Various binutils versions can resolve Thumb-2 branches to
1647 locally-defined, preemptible global symbols as short-range "b.n"
1648 branch instructions.
1650 This is a problem, because there's no guarantee the final
1651 destination of the symbol, or any candidate locations for a
1652 trampoline, are within range of the branch. For this reason, the
1653 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1654 relocation in modules at all, and it makes little sense to add
1657 The symptom is that the kernel fails with an "unsupported
1658 relocation" error when loading some modules.
1660 Until fixed tools are available, passing
1661 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1662 code which hits this problem, at the cost of a bit of extra runtime
1663 stack usage in some cases.
1665 The problem is described in more detail at:
1666 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1668 Only Thumb-2 kernels are affected.
1670 Unless you are sure your tools don't have this problem, say Y.
1672 config ARM_ASM_UNIFIED
1676 bool "Use the ARM EABI to compile the kernel"
1678 This option allows for the kernel to be compiled using the latest
1679 ARM ABI (aka EABI). This is only useful if you are using a user
1680 space environment that is also compiled with EABI.
1682 Since there are major incompatibilities between the legacy ABI and
1683 EABI, especially with regard to structure member alignment, this
1684 option also changes the kernel syscall calling convention to
1685 disambiguate both ABIs and allow for backward compatibility support
1686 (selected with CONFIG_OABI_COMPAT).
1688 To use this you need GCC version 4.0.0 or later.
1691 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1692 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1695 This option preserves the old syscall interface along with the
1696 new (ARM EABI) one. It also provides a compatibility layer to
1697 intercept syscalls that have structure arguments which layout
1698 in memory differs between the legacy ABI and the new ARM EABI
1699 (only for non "thumb" binaries). This option adds a tiny
1700 overhead to all syscalls and produces a slightly larger kernel.
1701 If you know you'll be using only pure EABI user space then you
1702 can say N here. If this option is not selected and you attempt
1703 to execute a legacy ABI binary then the result will be
1704 UNPREDICTABLE (in fact it can be predicted that it won't work
1705 at all). If in doubt say Y.
1707 config ARCH_HAS_HOLES_MEMORYMODEL
1710 config ARCH_SPARSEMEM_ENABLE
1713 config ARCH_SPARSEMEM_DEFAULT
1714 def_bool ARCH_SPARSEMEM_ENABLE
1716 config ARCH_SELECT_MEMORY_MODEL
1717 def_bool ARCH_SPARSEMEM_ENABLE
1719 config HAVE_ARCH_PFN_VALID
1720 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1723 bool "High Memory Support"
1726 The address space of ARM processors is only 4 Gigabytes large
1727 and it has to accommodate user address space, kernel address
1728 space as well as some memory mapped IO. That means that, if you
1729 have a large amount of physical memory and/or IO, not all of the
1730 memory can be "permanently mapped" by the kernel. The physical
1731 memory that is not permanently mapped is called "high memory".
1733 Depending on the selected kernel/user memory split, minimum
1734 vmalloc space and actual amount of RAM, you may not need this
1735 option which should result in a slightly faster kernel.
1740 bool "Allocate 2nd-level pagetables from highmem"
1743 config HW_PERF_EVENTS
1744 bool "Enable hardware performance counter support for perf events"
1745 depends on PERF_EVENTS
1748 Enable hardware performance counter support for perf events. If
1749 disabled, perf events will use software events only.
1753 config FORCE_MAX_ZONEORDER
1754 int "Maximum zone order" if ARCH_SHMOBILE
1755 range 11 64 if ARCH_SHMOBILE
1756 default "9" if SA1111
1759 The kernel memory allocator divides physically contiguous memory
1760 blocks into "zones", where each zone is a power of two number of
1761 pages. This option selects the largest power of two that the kernel
1762 keeps in the memory allocator. If you need to allocate very large
1763 blocks of physically contiguous memory, then you may need to
1764 increase this value.
1766 This config option is actually maximum order plus one. For example,
1767 a value of 11 means that the largest free memory block is 2^10 pages.
1769 config ALIGNMENT_TRAP
1771 depends on CPU_CP15_MMU
1772 default y if !ARCH_EBSA110
1773 select HAVE_PROC_CPU if PROC_FS
1775 ARM processors cannot fetch/store information which is not
1776 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1777 address divisible by 4. On 32-bit ARM processors, these non-aligned
1778 fetch/store instructions will be emulated in software if you say
1779 here, which has a severe performance impact. This is necessary for
1780 correct operation of some network protocols. With an IP-only
1781 configuration it is safe to say N, otherwise say Y.
1783 config UACCESS_WITH_MEMCPY
1784 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1785 depends on MMU && EXPERIMENTAL
1786 default y if CPU_FEROCEON
1788 Implement faster copy_to_user and clear_user methods for CPU
1789 cores where a 8-word STM instruction give significantly higher
1790 memory write throughput than a sequence of individual 32bit stores.
1792 A possible side effect is a slight increase in scheduling latency
1793 between threads sharing the same address space if they invoke
1794 such copy operations with large buffers.
1796 However, if the CPU data cache is using a write-allocate mode,
1797 this option is unlikely to provide any performance gain.
1801 prompt "Enable seccomp to safely compute untrusted bytecode"
1803 This kernel feature is useful for number crunching applications
1804 that may need to compute untrusted bytecode during their
1805 execution. By using pipes or other transports made available to
1806 the process as file descriptors supporting the read/write
1807 syscalls, it's possible to isolate those applications in
1808 their own address space using seccomp. Once seccomp is
1809 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1810 and the task is only allowed to execute a few safe syscalls
1811 defined by each seccomp mode.
1813 config CC_STACKPROTECTOR
1814 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1815 depends on EXPERIMENTAL
1817 This option turns on the -fstack-protector GCC feature. This
1818 feature puts, at the beginning of functions, a canary value on
1819 the stack just before the return address, and validates
1820 the value just before actually returning. Stack based buffer
1821 overflows (that need to overwrite this return address) now also
1822 overwrite the canary, which gets detected and the attack is then
1823 neutralized via a kernel panic.
1824 This feature requires gcc version 4.2 or above.
1826 config DEPRECATED_PARAM_STRUCT
1827 bool "Provide old way to pass kernel parameters"
1829 This was deprecated in 2001 and announced to live on for 5 years.
1830 Some old boot loaders still use this way.
1837 bool "Flattened Device Tree support"
1839 select OF_EARLY_FLATTREE
1842 Include support for flattened device tree machine descriptions.
1844 # Compressed boot loader in ROM. Yes, we really want to ask about
1845 # TEXT and BSS so we preserve their values in the config files.
1846 config ZBOOT_ROM_TEXT
1847 hex "Compressed ROM boot loader base address"
1850 The physical address at which the ROM-able zImage is to be
1851 placed in the target. Platforms which normally make use of
1852 ROM-able zImage formats normally set this to a suitable
1853 value in their defconfig file.
1855 If ZBOOT_ROM is not enabled, this has no effect.
1857 config ZBOOT_ROM_BSS
1858 hex "Compressed ROM boot loader BSS address"
1861 The base address of an area of read/write memory in the target
1862 for the ROM-able zImage which must be available while the
1863 decompressor is running. It must be large enough to hold the
1864 entire decompressed kernel plus an additional 128 KiB.
1865 Platforms which normally make use of ROM-able zImage formats
1866 normally set this to a suitable value in their defconfig file.
1868 If ZBOOT_ROM is not enabled, this has no effect.
1871 bool "Compressed boot loader in ROM/flash"
1872 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1874 Say Y here if you intend to execute your compressed kernel image
1875 (zImage) directly from ROM or flash. If unsure, say N.
1878 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1879 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1880 default ZBOOT_ROM_NONE
1882 Include experimental SD/MMC loading code in the ROM-able zImage.
1883 With this enabled it is possible to write the ROM-able zImage
1884 kernel image to an MMC or SD card and boot the kernel straight
1885 from the reset vector. At reset the processor Mask ROM will load
1886 the first part of the ROM-able zImage which in turn loads the
1887 rest the kernel image to RAM.
1889 config ZBOOT_ROM_NONE
1890 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1892 Do not load image from SD or MMC
1894 config ZBOOT_ROM_MMCIF
1895 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1897 Load image from MMCIF hardware block.
1899 config ZBOOT_ROM_SH_MOBILE_SDHI
1900 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1902 Load image from SDHI hardware block
1906 config ARM_APPENDED_DTB
1907 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1908 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1910 With this option, the boot code will look for a device tree binary
1911 (DTB) appended to zImage
1912 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1914 This is meant as a backward compatibility convenience for those
1915 systems with a bootloader that can't be upgraded to accommodate
1916 the documented boot protocol using a device tree.
1918 Beware that there is very little in terms of protection against
1919 this option being confused by leftover garbage in memory that might
1920 look like a DTB header after a reboot if no actual DTB is appended
1921 to zImage. Do not leave this option active in a production kernel
1922 if you don't intend to always append a DTB. Proper passing of the
1923 location into r2 of a bootloader provided DTB is always preferable
1926 config ARM_ATAG_DTB_COMPAT
1927 bool "Supplement the appended DTB with traditional ATAG information"
1928 depends on ARM_APPENDED_DTB
1930 Some old bootloaders can't be updated to a DTB capable one, yet
1931 they provide ATAGs with memory configuration, the ramdisk address,
1932 the kernel cmdline string, etc. Such information is dynamically
1933 provided by the bootloader and can't always be stored in a static
1934 DTB. To allow a device tree enabled kernel to be used with such
1935 bootloaders, this option allows zImage to extract the information
1936 from the ATAG list and store it at run time into the appended DTB.
1939 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1940 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1942 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1943 bool "Use bootloader kernel arguments if available"
1945 Uses the command-line options passed by the boot loader instead of
1946 the device tree bootargs property. If the boot loader doesn't provide
1947 any, the device tree bootargs property will be used.
1949 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1950 bool "Extend with bootloader kernel arguments"
1952 The command-line arguments provided by the boot loader will be
1953 appended to the the device tree bootargs property.
1958 string "Default kernel command string"
1961 On some architectures (EBSA110 and CATS), there is currently no way
1962 for the boot loader to pass arguments to the kernel. For these
1963 architectures, you should supply some command-line options at build
1964 time by entering them here. As a minimum, you should specify the
1965 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1968 prompt "Kernel command line type" if CMDLINE != ""
1969 default CMDLINE_FROM_BOOTLOADER
1971 config CMDLINE_FROM_BOOTLOADER
1972 bool "Use bootloader kernel arguments if available"
1974 Uses the command-line options passed by the boot loader. If
1975 the boot loader doesn't provide any, the default kernel command
1976 string provided in CMDLINE will be used.
1978 config CMDLINE_EXTEND
1979 bool "Extend bootloader kernel arguments"
1981 The command-line arguments provided by the boot loader will be
1982 appended to the default kernel command string.
1984 config CMDLINE_FORCE
1985 bool "Always use the default kernel command string"
1987 Always use the default kernel command string, even if the boot
1988 loader passes other arguments to the kernel.
1989 This is useful if you cannot or don't want to change the
1990 command-line options your boot loader passes to the kernel.
1994 bool "Kernel Execute-In-Place from ROM"
1995 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
1997 Execute-In-Place allows the kernel to run from non-volatile storage
1998 directly addressable by the CPU, such as NOR flash. This saves RAM
1999 space since the text section of the kernel is not loaded from flash
2000 to RAM. Read-write sections, such as the data section and stack,
2001 are still copied to RAM. The XIP kernel is not compressed since
2002 it has to run directly from flash, so it will take more space to
2003 store it. The flash address used to link the kernel object files,
2004 and for storing it, is configuration dependent. Therefore, if you
2005 say Y here, you must know the proper physical address where to
2006 store the kernel image depending on your own flash memory usage.
2008 Also note that the make target becomes "make xipImage" rather than
2009 "make zImage" or "make Image". The final kernel binary to put in
2010 ROM memory will be arch/arm/boot/xipImage.
2014 config XIP_PHYS_ADDR
2015 hex "XIP Kernel Physical Location"
2016 depends on XIP_KERNEL
2017 default "0x00080000"
2019 This is the physical address in your flash memory the kernel will
2020 be linked for and stored to. This address is dependent on your
2024 bool "Kexec system call (EXPERIMENTAL)"
2025 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2027 kexec is a system call that implements the ability to shutdown your
2028 current kernel, and to start another kernel. It is like a reboot
2029 but it is independent of the system firmware. And like a reboot
2030 you can start any kernel with it, not just Linux.
2032 It is an ongoing process to be certain the hardware in a machine
2033 is properly shutdown, so do not be surprised if this code does not
2034 initially work for you. It may help to enable device hotplugging
2038 bool "Export atags in procfs"
2042 Should the atags used to boot the kernel be exported in an "atags"
2043 file in procfs. Useful with kexec.
2046 bool "Build kdump crash kernel (EXPERIMENTAL)"
2047 depends on EXPERIMENTAL
2049 Generate crash dump after being started by kexec. This should
2050 be normally only set in special crash dump kernels which are
2051 loaded in the main kernel with kexec-tools into a specially
2052 reserved region and then later executed after a crash by
2053 kdump/kexec. The crash dump kernel must be compiled to a
2054 memory address not used by the main kernel
2056 For more details see Documentation/kdump/kdump.txt
2058 config AUTO_ZRELADDR
2059 bool "Auto calculation of the decompressed kernel image address"
2060 depends on !ZBOOT_ROM && !ARCH_U300
2062 ZRELADDR is the physical address where the decompressed kernel
2063 image will be placed. If AUTO_ZRELADDR is selected, the address
2064 will be determined at run-time by masking the current IP with
2065 0xf8000000. This assumes the zImage being placed in the first 128MB
2066 from start of memory.
2070 menu "CPU Power Management"
2074 source "drivers/cpufreq/Kconfig"
2077 tristate "CPUfreq driver for i.MX CPUs"
2078 depends on ARCH_MXC && CPU_FREQ
2079 select CPU_FREQ_TABLE
2081 This enables the CPUfreq driver for i.MX CPUs.
2083 config CPU_FREQ_SA1100
2086 config CPU_FREQ_SA1110
2089 config CPU_FREQ_INTEGRATOR
2090 tristate "CPUfreq driver for ARM Integrator CPUs"
2091 depends on ARCH_INTEGRATOR && CPU_FREQ
2094 This enables the CPUfreq driver for ARM Integrator CPUs.
2096 For details, take a look at <file:Documentation/cpu-freq>.
2102 depends on CPU_FREQ && ARCH_PXA && PXA25x
2104 select CPU_FREQ_TABLE
2105 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2110 Internal configuration node for common cpufreq on Samsung SoC
2112 config CPU_FREQ_S3C24XX
2113 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2114 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2117 This enables the CPUfreq driver for the Samsung S3C24XX family
2120 For details, take a look at <file:Documentation/cpu-freq>.
2124 config CPU_FREQ_S3C24XX_PLL
2125 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2126 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2128 Compile in support for changing the PLL frequency from the
2129 S3C24XX series CPUfreq driver. The PLL takes time to settle
2130 after a frequency change, so by default it is not enabled.
2132 This also means that the PLL tables for the selected CPU(s) will
2133 be built which may increase the size of the kernel image.
2135 config CPU_FREQ_S3C24XX_DEBUG
2136 bool "Debug CPUfreq Samsung driver core"
2137 depends on CPU_FREQ_S3C24XX
2139 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2141 config CPU_FREQ_S3C24XX_IODEBUG
2142 bool "Debug CPUfreq Samsung driver IO timing"
2143 depends on CPU_FREQ_S3C24XX
2145 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2147 config CPU_FREQ_S3C24XX_DEBUGFS
2148 bool "Export debugfs for CPUFreq"
2149 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2151 Export status information via debugfs.
2155 source "drivers/cpuidle/Kconfig"
2159 menu "Floating point emulation"
2161 comment "At least one emulation must be selected"
2164 bool "NWFPE math emulation"
2165 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2167 Say Y to include the NWFPE floating point emulator in the kernel.
2168 This is necessary to run most binaries. Linux does not currently
2169 support floating point hardware so you need to say Y here even if
2170 your machine has an FPA or floating point co-processor podule.
2172 You may say N here if you are going to load the Acorn FPEmulator
2173 early in the bootup.
2176 bool "Support extended precision"
2177 depends on FPE_NWFPE
2179 Say Y to include 80-bit support in the kernel floating-point
2180 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2181 Note that gcc does not generate 80-bit operations by default,
2182 so in most cases this option only enlarges the size of the
2183 floating point emulator without any good reason.
2185 You almost surely want to say N here.
2188 bool "FastFPE math emulation (EXPERIMENTAL)"
2189 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2191 Say Y here to include the FAST floating point emulator in the kernel.
2192 This is an experimental much faster emulator which now also has full
2193 precision for the mantissa. It does not support any exceptions.
2194 It is very simple, and approximately 3-6 times faster than NWFPE.
2196 It should be sufficient for most programs. It may be not suitable
2197 for scientific calculations, but you have to check this for yourself.
2198 If you do not feel you need a faster FP emulation you should better
2202 bool "VFP-format floating point maths"
2203 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2205 Say Y to include VFP support code in the kernel. This is needed
2206 if your hardware includes a VFP unit.
2208 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2209 release notes and additional status information.
2211 Say N if your target does not have VFP hardware.
2219 bool "Advanced SIMD (NEON) Extension support"
2220 depends on VFPv3 && CPU_V7
2222 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2227 menu "Userspace binary formats"
2229 source "fs/Kconfig.binfmt"
2232 tristate "RISC OS personality"
2235 Say Y here to include the kernel code necessary if you want to run
2236 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2237 experimental; if this sounds frightening, say N and sleep in peace.
2238 You can also say M here to compile this support as a module (which
2239 will be called arthur).
2243 menu "Power management options"
2245 source "kernel/power/Kconfig"
2247 config ARCH_SUSPEND_POSSIBLE
2248 depends on !ARCH_S5PC100
2249 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2250 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2253 config ARM_CPU_SUSPEND
2258 source "net/Kconfig"
2260 source "drivers/Kconfig"
2264 source "arch/arm/Kconfig.debug"
2266 source "security/Kconfig"
2268 source "crypto/Kconfig"
2270 source "lib/Kconfig"