8 select SYS_SUPPORTS_APM_EMULATION
9 select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
10 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_KPROBES if (!XIP_KERNEL)
13 select HAVE_KRETPROBES if (HAVE_KPROBES)
14 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
15 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
16 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
17 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
18 select HAVE_GENERIC_DMA_COHERENT
19 select HAVE_KERNEL_GZIP
20 select HAVE_KERNEL_LZO
21 select HAVE_KERNEL_LZMA
23 select HAVE_PERF_EVENTS
24 select PERF_USE_VMALLOC
25 select HAVE_REGS_AND_STACK_ACCESS_API
26 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
28 The ARM series is a line of low-power-consumption RISC chip designs
29 licensed by ARM Ltd and targeted at embedded applications and
30 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
31 manufactured, but legacy ARM-based PC hardware remains popular in
32 Europe. There is an ARM Linux project with a web page at
33 <http://www.arm.linux.org.uk/>.
38 config SYS_SUPPORTS_APM_EMULATION
44 config ARCH_USES_GETTIMEOFFSET
48 config GENERIC_CLOCKEVENTS
51 config GENERIC_CLOCKEVENTS_BROADCAST
53 depends on GENERIC_CLOCKEVENTS
58 select GENERIC_ALLOCATOR
69 The Extended Industry Standard Architecture (EISA) bus was
70 developed as an open alternative to the IBM MicroChannel bus.
72 The EISA bus provided some of the features of the IBM MicroChannel
73 bus while maintaining backward compatibility with cards made for
74 the older ISA bus. The EISA bus saw limited use between 1988 and
75 1995 when it was made obsolete by the PCI bus.
77 Say Y here if you are building a kernel for an EISA-based machine.
87 MicroChannel Architecture is found in some IBM PS/2 machines and
88 laptops. It is a bus system similar to PCI or ISA. See
89 <file:Documentation/mca.txt> (and especially the web page given
90 there) before attempting to build an MCA bus kernel.
92 config GENERIC_HARDIRQS
96 config STACKTRACE_SUPPORT
100 config HAVE_LATENCYTOP_SUPPORT
105 config LOCKDEP_SUPPORT
109 config TRACE_IRQFLAGS_SUPPORT
113 config HARDIRQS_SW_RESEND
117 config GENERIC_IRQ_PROBE
121 config GENERIC_LOCKBREAK
124 depends on SMP && PREEMPT
126 config RWSEM_GENERIC_SPINLOCK
130 config RWSEM_XCHGADD_ALGORITHM
133 config ARCH_HAS_ILOG2_U32
136 config ARCH_HAS_ILOG2_U64
139 config ARCH_HAS_CPUFREQ
142 Internal node to signify that the ARCH has CPUFREQ support
143 and that the relevant menu configurations are displayed for
146 config ARCH_HAS_CPU_IDLE_WAIT
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config GENERIC_ISA_DMA
175 config GENERIC_HARDIRQS_NO__DO_IRQ
178 config ARM_L1_CACHE_SHIFT_6
181 Setting ARM L1 cache line size to 64 Bytes.
185 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
186 default DRAM_BASE if REMAP_VECTORS_TO_RAM
189 The base address of exception vectors.
191 source "init/Kconfig"
193 source "kernel/Kconfig.freezer"
198 bool "MMU-based Paged Memory Management Support"
201 Select if you want MMU-based virtualised addressing space
202 support by paged memory management. If unsure, say 'Y'.
205 # The "ARM system type" choice list is ordered alphabetically by option
206 # text. Please add new entries in the option alphabetic order.
209 prompt "ARM system type"
210 default ARCH_VERSATILE
213 bool "Agilent AAEC-2000 based"
217 select ARCH_USES_GETTIMEOFFSET
219 This enables support for systems based on the Agilent AAEC-2000
221 config ARCH_INTEGRATOR
222 bool "ARM Ltd. Integrator family"
224 select ARCH_HAS_CPUFREQ
227 select GENERIC_CLOCKEVENTS
228 select PLAT_VERSATILE
230 Support for ARM's Integrator platform.
233 bool "ARM Ltd. RealView family"
237 select GENERIC_CLOCKEVENTS
238 select ARCH_WANT_OPTIONAL_GPIOLIB
239 select PLAT_VERSATILE
240 select ARM_TIMER_SP804
241 select GPIO_PL061 if GPIOLIB
243 This enables support for ARM Ltd RealView boards.
245 config ARCH_VERSATILE
246 bool "ARM Ltd. Versatile family"
251 select GENERIC_CLOCKEVENTS
252 select ARCH_WANT_OPTIONAL_GPIOLIB
253 select PLAT_VERSATILE
254 select ARM_TIMER_SP804
256 This enables support for ARM Ltd Versatile board.
259 bool "ARM Ltd. Versatile Express family"
260 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select ARM_TIMER_SP804
264 select GENERIC_CLOCKEVENTS
267 select PLAT_VERSATILE
269 This enables support for the ARM Ltd Versatile Express boards.
273 select ARCH_REQUIRE_GPIOLIB
276 This enables support for systems based on the Atmel AT91RM9200,
277 AT91SAM9 and AT91CAP9 processors.
280 bool "Broadcom BCMRING"
285 select GENERIC_CLOCKEVENTS
286 select ARCH_WANT_OPTIONAL_GPIOLIB
288 Support for Broadcom's BCMRing platform.
291 bool "Cirrus Logic CLPS711x/EP721x-based"
293 select ARCH_USES_GETTIMEOFFSET
295 Support for Cirrus Logic 711x/721x based boards.
298 bool "Cavium Networks CNS3XXX family"
300 select GENERIC_CLOCKEVENTS
302 select PCI_DOMAINS if PCI
304 Support for Cavium Networks CNS3XXX platform.
307 bool "Cortina Systems Gemini"
309 select ARCH_REQUIRE_GPIOLIB
310 select ARCH_USES_GETTIMEOFFSET
312 Support for the Cortina Systems Gemini family SoCs
319 select ARCH_USES_GETTIMEOFFSET
321 This is an evaluation board for the StrongARM processor available
322 from Digital. It has limited hardware on-board, including an
323 Ethernet interface, two PCMCIA sockets, two serial ports and a
332 select ARCH_REQUIRE_GPIOLIB
333 select ARCH_HAS_HOLES_MEMORYMODEL
334 select ARCH_USES_GETTIMEOFFSET
336 This enables support for the Cirrus EP93xx series of CPUs.
338 config ARCH_FOOTBRIDGE
342 select ARCH_USES_GETTIMEOFFSET
344 Support for systems based on the DC21285 companion chip
345 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
348 bool "Freescale MXC/iMX-based"
349 select GENERIC_CLOCKEVENTS
350 select ARCH_REQUIRE_GPIOLIB
353 Support for Freescale MXC/iMX-based family of processors
356 bool "Freescale STMP3xxx"
359 select ARCH_REQUIRE_GPIOLIB
360 select GENERIC_CLOCKEVENTS
361 select USB_ARCH_HAS_EHCI
363 Support for systems based on the Freescale 3xxx CPUs.
366 bool "Hilscher NetX based"
369 select GENERIC_CLOCKEVENTS
371 This enables support for systems based on the Hilscher NetX Soc
374 bool "Hynix HMS720x-based"
377 select ARCH_USES_GETTIMEOFFSET
379 This enables support for systems based on the Hynix HMS720x
387 select ARCH_SUPPORTS_MSI
390 Support for Intel's IOP13XX (XScale) family of processors.
398 select ARCH_REQUIRE_GPIOLIB
400 Support for Intel's 80219 and IOP32X (XScale) family of
409 select ARCH_REQUIRE_GPIOLIB
411 Support for Intel's IOP33X (XScale) family of processors.
418 select ARCH_USES_GETTIMEOFFSET
420 Support for Intel's IXP23xx (XScale) family of processors.
423 bool "IXP2400/2800-based"
427 select ARCH_USES_GETTIMEOFFSET
429 Support for Intel's IXP2400/2800 (XScale) family of processors.
436 select GENERIC_CLOCKEVENTS
437 select DMABOUNCE if PCI
439 Support for Intel's IXP4XX (XScale) family of processors.
444 select ARCH_REQUIRE_GPIOLIB
445 select GENERIC_CLOCKEVENTS
448 Support for the Marvell Dove SoC 88AP510
451 bool "Marvell Kirkwood"
454 select ARCH_REQUIRE_GPIOLIB
455 select GENERIC_CLOCKEVENTS
458 Support for the following Marvell Kirkwood series SoCs:
459 88F6180, 88F6192 and 88F6281.
462 bool "Marvell Loki (88RC8480)"
464 select GENERIC_CLOCKEVENTS
467 Support for the Marvell Loki (88RC8480) SoC.
472 select ARCH_REQUIRE_GPIOLIB
475 select USB_ARCH_HAS_OHCI
478 select GENERIC_CLOCKEVENTS
480 Support for the NXP LPC32XX family of processors
483 bool "Marvell MV78xx0"
486 select ARCH_REQUIRE_GPIOLIB
487 select GENERIC_CLOCKEVENTS
490 Support for the following Marvell MV78xx0 series SoCs:
498 select ARCH_REQUIRE_GPIOLIB
499 select GENERIC_CLOCKEVENTS
502 Support for the following Marvell Orion 5x series SoCs:
503 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
504 Orion-2 (5281), Orion-1-90 (6183).
507 bool "Marvell PXA168/910/MMP2"
509 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
516 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
519 bool "Micrel/Kendin KS8695"
521 select ARCH_REQUIRE_GPIOLIB
522 select ARCH_USES_GETTIMEOFFSET
524 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
525 System-on-Chip devices.
528 bool "NetSilicon NS9xxx"
531 select GENERIC_CLOCKEVENTS
534 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
537 <http://www.digi.com/products/microprocessors/index.jsp>
540 bool "Nuvoton W90X900 CPU"
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
546 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
547 At present, the w90x900 has been renamed nuc900, regarding
548 the ARM series product line, you can login the following
549 link address to know more.
551 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
552 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
555 bool "Nuvoton NUC93X CPU"
559 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
560 low-power and high performance MPEG-4/JPEG multimedia controller chip.
565 select GENERIC_CLOCKEVENTS
569 select ARCH_HAS_BARRIERS if CACHE_L2X0
570 select ARCH_HAS_CPUFREQ
572 This enables support for NVIDIA Tegra based systems (Tegra APX,
573 Tegra 6xx and Tegra 2 series).
576 bool "Philips Nexperia PNX4008 Mobile"
579 select ARCH_USES_GETTIMEOFFSET
581 This enables support for Philips PNX4008 mobile platform.
584 bool "PXA2xx/PXA3xx-based"
587 select ARCH_HAS_CPUFREQ
589 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
595 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
600 select GENERIC_CLOCKEVENTS
601 select ARCH_REQUIRE_GPIOLIB
603 Support for Qualcomm MSM/QSD based systems. This runs on the
604 apps processor of the MSM/QSD and depends on a shared memory
605 interface to the modem processor which runs the baseband
606 stack and controls some vital subsystems
607 (clock and power control, etc).
610 bool "Renesas SH-Mobile"
612 Support for Renesas's SH-Mobile ARM platforms
619 select ARCH_MAY_HAVE_PC_FDC
620 select HAVE_PATA_PLATFORM
623 select ARCH_SPARSEMEM_ENABLE
624 select ARCH_USES_GETTIMEOFFSET
626 On the Acorn Risc-PC, Linux can support the internal IDE disk and
627 CD-ROM interface, serial and parallel port, and the floppy drive.
633 select ARCH_SPARSEMEM_ENABLE
635 select ARCH_HAS_CPUFREQ
637 select GENERIC_CLOCKEVENTS
640 select ARCH_REQUIRE_GPIOLIB
642 Support for StrongARM 11x0 based boards.
645 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
647 select ARCH_HAS_CPUFREQ
649 select ARCH_USES_GETTIMEOFFSET
650 select HAVE_S3C2410_I2C if I2C
652 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
653 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
654 the Samsung SMDK2410 development board (and derivatives).
656 Note, the S3C2416 and the S3C2450 are so close that they even share
657 the same SoC ID code. This means that there is no seperate machine
658 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
661 bool "Samsung S3C64XX"
667 select ARCH_USES_GETTIMEOFFSET
668 select ARCH_HAS_CPUFREQ
669 select ARCH_REQUIRE_GPIOLIB
670 select SAMSUNG_CLKSRC
671 select SAMSUNG_IRQ_VIC_TIMER
672 select SAMSUNG_IRQ_UART
673 select S3C_GPIO_TRACK
674 select S3C_GPIO_PULL_UPDOWN
675 select S3C_GPIO_CFG_S3C24XX
676 select S3C_GPIO_CFG_S3C64XX
678 select USB_ARCH_HAS_OHCI
679 select SAMSUNG_GPIOLIB_4BIT
680 select HAVE_S3C2410_I2C if I2C
681 select HAVE_S3C2410_WATCHDOG if WATCHDOG
683 Samsung S3C64XX series based systems
686 bool "Samsung S5P6440 S5P6450"
690 select HAVE_S3C2410_WATCHDOG if WATCHDOG
691 select ARCH_USES_GETTIMEOFFSET
692 select HAVE_S3C2410_I2C if I2C
693 select HAVE_S3C_RTC if RTC_CLASS
695 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
699 bool "Samsung S5P6442"
703 select ARCH_USES_GETTIMEOFFSET
704 select HAVE_S3C2410_WATCHDOG if WATCHDOG
706 Samsung S5P6442 CPU based systems
709 bool "Samsung S5PC100"
713 select ARM_L1_CACHE_SHIFT_6
714 select ARCH_USES_GETTIMEOFFSET
715 select HAVE_S3C2410_I2C if I2C
716 select HAVE_S3C_RTC if RTC_CLASS
717 select HAVE_S3C2410_WATCHDOG if WATCHDOG
719 Samsung S5PC100 series based systems
722 bool "Samsung S5PV210/S5PC110"
724 select ARCH_SPARSEMEM_ENABLE
727 select ARM_L1_CACHE_SHIFT_6
728 select ARCH_HAS_CPUFREQ
729 select ARCH_USES_GETTIMEOFFSET
730 select HAVE_S3C2410_I2C if I2C
731 select HAVE_S3C_RTC if RTC_CLASS
732 select HAVE_S3C2410_WATCHDOG if WATCHDOG
734 Samsung S5PV210/S5PC110 series based systems
737 bool "Samsung S5PV310/S5PC210"
739 select ARCH_SPARSEMEM_ENABLE
742 select GENERIC_CLOCKEVENTS
743 select HAVE_S3C_RTC if RTC_CLASS
744 select HAVE_S3C2410_I2C if I2C
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 Samsung S5PV310 series based systems
756 select ARCH_USES_GETTIMEOFFSET
758 Support for the StrongARM based Digital DNARD machine, also known
759 as "Shark" (<http://www.shark-linux.de/shark.html>).
762 bool "Telechips TCC ARM926-based systems"
766 select GENERIC_CLOCKEVENTS
768 Support for Telechips TCC ARM926-based systems.
773 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
774 select ARCH_USES_GETTIMEOFFSET
776 Say Y here for systems based on one of the Sharp LH7A40X
777 System on a Chip processors. These CPUs include an ARM922T
778 core with a wide array of integrated devices for
779 hand-held and low-power applications.
782 bool "ST-Ericsson U300 Series"
788 select GENERIC_CLOCKEVENTS
792 Support for ST-Ericsson U300 series mobile platforms.
795 bool "ST-Ericsson U8500 Series"
798 select GENERIC_CLOCKEVENTS
800 select ARCH_REQUIRE_GPIOLIB
802 Support for ST-Ericsson's Ux500 architecture
805 bool "STMicroelectronics Nomadik"
810 select GENERIC_CLOCKEVENTS
811 select ARCH_REQUIRE_GPIOLIB
813 Support for the Nomadik platform by ST-Ericsson
817 select GENERIC_CLOCKEVENTS
818 select ARCH_REQUIRE_GPIOLIB
822 select GENERIC_ALLOCATOR
823 select ARCH_HAS_HOLES_MEMORYMODEL
825 Support for TI's DaVinci platform.
830 select ARCH_REQUIRE_GPIOLIB
831 select ARCH_HAS_CPUFREQ
832 select GENERIC_CLOCKEVENTS
833 select ARCH_HAS_HOLES_MEMORYMODEL
835 Support for TI's OMAP platform (OMAP1/2/3/4).
840 select ARCH_REQUIRE_GPIOLIB
842 select GENERIC_CLOCKEVENTS
845 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
850 # This is sorted alphabetically by mach-* pathname. However, plat-*
851 # Kconfigs may be included either alphabetically (according to the
852 # plat- suffix) or along side the corresponding mach-* source.
854 source "arch/arm/mach-aaec2000/Kconfig"
856 source "arch/arm/mach-at91/Kconfig"
858 source "arch/arm/mach-bcmring/Kconfig"
860 source "arch/arm/mach-clps711x/Kconfig"
862 source "arch/arm/mach-cns3xxx/Kconfig"
864 source "arch/arm/mach-davinci/Kconfig"
866 source "arch/arm/mach-dove/Kconfig"
868 source "arch/arm/mach-ep93xx/Kconfig"
870 source "arch/arm/mach-footbridge/Kconfig"
872 source "arch/arm/mach-gemini/Kconfig"
874 source "arch/arm/mach-h720x/Kconfig"
876 source "arch/arm/mach-integrator/Kconfig"
878 source "arch/arm/mach-iop32x/Kconfig"
880 source "arch/arm/mach-iop33x/Kconfig"
882 source "arch/arm/mach-iop13xx/Kconfig"
884 source "arch/arm/mach-ixp4xx/Kconfig"
886 source "arch/arm/mach-ixp2000/Kconfig"
888 source "arch/arm/mach-ixp23xx/Kconfig"
890 source "arch/arm/mach-kirkwood/Kconfig"
892 source "arch/arm/mach-ks8695/Kconfig"
894 source "arch/arm/mach-lh7a40x/Kconfig"
896 source "arch/arm/mach-loki/Kconfig"
898 source "arch/arm/mach-lpc32xx/Kconfig"
900 source "arch/arm/mach-msm/Kconfig"
902 source "arch/arm/mach-mv78xx0/Kconfig"
904 source "arch/arm/plat-mxc/Kconfig"
906 source "arch/arm/mach-netx/Kconfig"
908 source "arch/arm/mach-nomadik/Kconfig"
909 source "arch/arm/plat-nomadik/Kconfig"
911 source "arch/arm/mach-ns9xxx/Kconfig"
913 source "arch/arm/mach-nuc93x/Kconfig"
915 source "arch/arm/plat-omap/Kconfig"
917 source "arch/arm/mach-omap1/Kconfig"
919 source "arch/arm/mach-omap2/Kconfig"
921 source "arch/arm/mach-orion5x/Kconfig"
923 source "arch/arm/mach-pxa/Kconfig"
924 source "arch/arm/plat-pxa/Kconfig"
926 source "arch/arm/mach-mmp/Kconfig"
928 source "arch/arm/mach-realview/Kconfig"
930 source "arch/arm/mach-sa1100/Kconfig"
932 source "arch/arm/plat-samsung/Kconfig"
933 source "arch/arm/plat-s3c24xx/Kconfig"
934 source "arch/arm/plat-s5p/Kconfig"
936 source "arch/arm/plat-spear/Kconfig"
938 source "arch/arm/plat-tcc/Kconfig"
941 source "arch/arm/mach-s3c2400/Kconfig"
942 source "arch/arm/mach-s3c2410/Kconfig"
943 source "arch/arm/mach-s3c2412/Kconfig"
944 source "arch/arm/mach-s3c2416/Kconfig"
945 source "arch/arm/mach-s3c2440/Kconfig"
946 source "arch/arm/mach-s3c2443/Kconfig"
950 source "arch/arm/mach-s3c64xx/Kconfig"
953 source "arch/arm/mach-s5p64x0/Kconfig"
955 source "arch/arm/mach-s5p6442/Kconfig"
957 source "arch/arm/mach-s5pc100/Kconfig"
959 source "arch/arm/mach-s5pv210/Kconfig"
961 source "arch/arm/mach-s5pv310/Kconfig"
963 source "arch/arm/mach-shmobile/Kconfig"
965 source "arch/arm/plat-stmp3xxx/Kconfig"
967 source "arch/arm/mach-tegra/Kconfig"
969 source "arch/arm/mach-u300/Kconfig"
971 source "arch/arm/mach-ux500/Kconfig"
973 source "arch/arm/mach-versatile/Kconfig"
975 source "arch/arm/mach-vexpress/Kconfig"
977 source "arch/arm/mach-w90x900/Kconfig"
979 # Definitions to make life easier
985 select GENERIC_CLOCKEVENTS
993 config PLAT_VERSATILE
996 config ARM_TIMER_SP804
999 source arch/arm/mm/Kconfig
1002 bool "Enable iWMMXt support"
1003 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
1004 default y if PXA27x || PXA3xx || ARCH_MMP
1006 Enable support for iWMMXt context switching at run time if
1007 running on a CPU that supports it.
1009 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1012 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1016 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1017 (!ARCH_OMAP3 || OMAP3_EMU)
1022 source "arch/arm/Kconfig-nommu"
1025 config ARM_ERRATA_411920
1026 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1029 Invalidation of the Instruction Cache operation can
1030 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1031 It does not affect the MPCore. This option enables the ARM Ltd.
1032 recommended workaround.
1034 config ARM_ERRATA_430973
1035 bool "ARM errata: Stale prediction on replaced interworking branch"
1038 This option enables the workaround for the 430973 Cortex-A8
1039 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1040 interworking branch is replaced with another code sequence at the
1041 same virtual address, whether due to self-modifying code or virtual
1042 to physical address re-mapping, Cortex-A8 does not recover from the
1043 stale interworking branch prediction. This results in Cortex-A8
1044 executing the new code sequence in the incorrect ARM or Thumb state.
1045 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1046 and also flushes the branch target cache at every context switch.
1047 Note that setting specific bits in the ACTLR register may not be
1048 available in non-secure mode.
1050 config ARM_ERRATA_458693
1051 bool "ARM errata: Processor deadlock when a false hazard is created"
1054 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1055 erratum. For very specific sequences of memory operations, it is
1056 possible for a hazard condition intended for a cache line to instead
1057 be incorrectly associated with a different cache line. This false
1058 hazard might then cause a processor deadlock. The workaround enables
1059 the L1 caching of the NEON accesses and disables the PLD instruction
1060 in the ACTLR register. Note that setting specific bits in the ACTLR
1061 register may not be available in non-secure mode.
1063 config ARM_ERRATA_460075
1064 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1067 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1068 erratum. Any asynchronous access to the L2 cache may encounter a
1069 situation in which recent store transactions to the L2 cache are lost
1070 and overwritten with stale memory contents from external memory. The
1071 workaround disables the write-allocate mode for the L2 cache via the
1072 ACTLR register. Note that setting specific bits in the ACTLR register
1073 may not be available in non-secure mode.
1075 config ARM_ERRATA_742230
1076 bool "ARM errata: DMB operation may be faulty"
1077 depends on CPU_V7 && SMP
1079 This option enables the workaround for the 742230 Cortex-A9
1080 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1081 between two write operations may not ensure the correct visibility
1082 ordering of the two writes. This workaround sets a specific bit in
1083 the diagnostic register of the Cortex-A9 which causes the DMB
1084 instruction to behave as a DSB, ensuring the correct behaviour of
1087 config ARM_ERRATA_742231
1088 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1089 depends on CPU_V7 && SMP
1091 This option enables the workaround for the 742231 Cortex-A9
1092 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1093 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1094 accessing some data located in the same cache line, may get corrupted
1095 data due to bad handling of the address hazard when the line gets
1096 replaced from one of the CPUs at the same time as another CPU is
1097 accessing it. This workaround sets specific bits in the diagnostic
1098 register of the Cortex-A9 which reduces the linefill issuing
1099 capabilities of the processor.
1101 config PL310_ERRATA_588369
1102 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1103 depends on CACHE_L2X0 && ARCH_OMAP4
1105 The PL310 L2 cache controller implements three types of Clean &
1106 Invalidate maintenance operations: by Physical Address
1107 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1108 They are architecturally defined to behave as the execution of a
1109 clean operation followed immediately by an invalidate operation,
1110 both performing to the same memory location. This functionality
1111 is not correctly implemented in PL310 as clean lines are not
1112 invalidated as a result of these operations. Note that this errata
1113 uses Texas Instrument's secure monitor api.
1115 config ARM_ERRATA_720789
1116 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1117 depends on CPU_V7 && SMP
1119 This option enables the workaround for the 720789 Cortex-A9 (prior to
1120 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1121 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1122 As a consequence of this erratum, some TLB entries which should be
1123 invalidated are not, resulting in an incoherency in the system page
1124 tables. The workaround changes the TLB flushing routines to invalidate
1125 entries regardless of the ASID.
1127 config ARM_ERRATA_743622
1128 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1131 This option enables the workaround for the 743622 Cortex-A9
1132 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1133 optimisation in the Cortex-A9 Store Buffer may lead to data
1134 corruption. This workaround sets a specific bit in the diagnostic
1135 register of the Cortex-A9 which disables the Store Buffer
1136 optimisation, preventing the defect from occurring. This has no
1137 visible impact on the overall performance or power consumption of the
1142 source "arch/arm/common/Kconfig"
1152 Find out whether you have ISA slots on your motherboard. ISA is the
1153 name of a bus system, i.e. the way the CPU talks to the other stuff
1154 inside your box. Other bus systems are PCI, EISA, MicroChannel
1155 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1156 newer boards don't support it. If you have ISA, say Y, otherwise N.
1158 # Select ISA DMA controller support
1163 # Select ISA DMA interface
1168 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
1170 Find out whether you have a PCI motherboard. PCI is the name of a
1171 bus system, i.e. the way the CPU talks to the other stuff inside
1172 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1173 VESA. If you have PCI, say Y, otherwise N.
1182 # Select the host bridge type
1183 config PCI_HOST_VIA82C505
1185 depends on PCI && ARCH_SHARK
1188 config PCI_HOST_ITE8152
1190 depends on PCI && MACH_ARMCORE
1194 source "drivers/pci/Kconfig"
1196 source "drivers/pcmcia/Kconfig"
1200 menu "Kernel Features"
1202 source "kernel/time/Kconfig"
1205 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1206 depends on EXPERIMENTAL
1207 depends on GENERIC_CLOCKEVENTS
1208 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1209 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1210 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1212 select USE_GENERIC_SMP_HELPERS
1213 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1215 This enables support for systems with more than one CPU. If you have
1216 a system with only one CPU, like most personal computers, say N. If
1217 you have a system with more than one CPU, say Y.
1219 If you say N here, the kernel will run on single and multiprocessor
1220 machines, but will use only one CPU of a multiprocessor machine. If
1221 you say Y here, the kernel will run on many, but not all, single
1222 processor machines. On a single processor machine, the kernel will
1223 run faster if you say N here.
1225 See also <file:Documentation/i386/IO-APIC.txt>,
1226 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1227 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1229 If you don't know what to do here, say N.
1232 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1233 depends on EXPERIMENTAL
1234 depends on SMP && !XIP && !THUMB2_KERNEL
1237 SMP kernels contain instructions which fail on non-SMP processors.
1238 Enabling this option allows the kernel to modify itself to make
1239 these instructions safe. Disabling it allows about 1K of space
1242 If you don't know what to do here, say Y.
1248 This option enables support for the ARM system coherency unit
1254 This options enables support for the ARM timer and watchdog unit
1257 prompt "Memory split"
1260 Select the desired split between kernel and user memory.
1262 If you are not absolutely sure what you are doing, leave this
1266 bool "3G/1G user/kernel split"
1268 bool "2G/2G user/kernel split"
1270 bool "1G/3G user/kernel split"
1275 default 0x40000000 if VMSPLIT_1G
1276 default 0x80000000 if VMSPLIT_2G
1280 int "Maximum number of CPUs (2-32)"
1286 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1287 depends on SMP && HOTPLUG && EXPERIMENTAL
1288 depends on !ARCH_MSM
1290 Say Y here to experiment with turning CPUs off and on. CPUs
1291 can be controlled through /sys/devices/system/cpu.
1294 bool "Use local timer interrupts"
1297 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1299 Enable support for local timers on SMP platforms, rather then the
1300 legacy IPI broadcast method. Local timers allows the system
1301 accounting to be spread across the timer interval, preventing a
1302 "thundering herd" at every timer tick.
1304 source kernel/Kconfig.preempt
1308 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1309 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1310 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1311 default AT91_TIMER_HZ if ARCH_AT91
1312 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1315 config THUMB2_KERNEL
1316 bool "Compile the kernel in Thumb-2 mode"
1317 depends on CPU_V7 && EXPERIMENTAL
1319 select ARM_ASM_UNIFIED
1321 By enabling this option, the kernel will be compiled in
1322 Thumb-2 mode. A compiler/assembler that understand the unified
1323 ARM-Thumb syntax is needed.
1327 config ARM_ASM_UNIFIED
1331 bool "Use the ARM EABI to compile the kernel"
1333 This option allows for the kernel to be compiled using the latest
1334 ARM ABI (aka EABI). This is only useful if you are using a user
1335 space environment that is also compiled with EABI.
1337 Since there are major incompatibilities between the legacy ABI and
1338 EABI, especially with regard to structure member alignment, this
1339 option also changes the kernel syscall calling convention to
1340 disambiguate both ABIs and allow for backward compatibility support
1341 (selected with CONFIG_OABI_COMPAT).
1343 To use this you need GCC version 4.0.0 or later.
1346 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1347 depends on AEABI && EXPERIMENTAL
1350 This option preserves the old syscall interface along with the
1351 new (ARM EABI) one. It also provides a compatibility layer to
1352 intercept syscalls that have structure arguments which layout
1353 in memory differs between the legacy ABI and the new ARM EABI
1354 (only for non "thumb" binaries). This option adds a tiny
1355 overhead to all syscalls and produces a slightly larger kernel.
1356 If you know you'll be using only pure EABI user space then you
1357 can say N here. If this option is not selected and you attempt
1358 to execute a legacy ABI binary then the result will be
1359 UNPREDICTABLE (in fact it can be predicted that it won't work
1360 at all). If in doubt say Y.
1362 config ARCH_HAS_HOLES_MEMORYMODEL
1365 config ARCH_SPARSEMEM_ENABLE
1368 config ARCH_SPARSEMEM_DEFAULT
1369 def_bool ARCH_SPARSEMEM_ENABLE
1371 config ARCH_SELECT_MEMORY_MODEL
1372 def_bool ARCH_SPARSEMEM_ENABLE
1375 bool "High Memory Support (EXPERIMENTAL)"
1376 depends on MMU && EXPERIMENTAL
1378 The address space of ARM processors is only 4 Gigabytes large
1379 and it has to accommodate user address space, kernel address
1380 space as well as some memory mapped IO. That means that, if you
1381 have a large amount of physical memory and/or IO, not all of the
1382 memory can be "permanently mapped" by the kernel. The physical
1383 memory that is not permanently mapped is called "high memory".
1385 Depending on the selected kernel/user memory split, minimum
1386 vmalloc space and actual amount of RAM, you may not need this
1387 option which should result in a slightly faster kernel.
1392 bool "Allocate 2nd-level pagetables from highmem"
1394 depends on !OUTER_CACHE
1396 config HW_PERF_EVENTS
1397 bool "Enable hardware performance counter support for perf events"
1398 depends on PERF_EVENTS && CPU_HAS_PMU
1401 Enable hardware performance counter support for perf events. If
1402 disabled, perf events will use software events only.
1407 This enables support for sparse irqs. This is useful in general
1408 as most CPUs have a fairly sparse array of IRQ vectors, which
1409 the irq_desc then maps directly on to. Systems with a high
1410 number of off-chip IRQs will want to treat this as
1411 experimental until they have been independently verified.
1415 config FORCE_MAX_ZONEORDER
1416 int "Maximum zone order" if ARCH_SHMOBILE
1417 range 11 64 if ARCH_SHMOBILE
1418 default "9" if SA1111
1421 The kernel memory allocator divides physically contiguous memory
1422 blocks into "zones", where each zone is a power of two number of
1423 pages. This option selects the largest power of two that the kernel
1424 keeps in the memory allocator. If you need to allocate very large
1425 blocks of physically contiguous memory, then you may need to
1426 increase this value.
1428 This config option is actually maximum order plus one. For example,
1429 a value of 11 means that the largest free memory block is 2^10 pages.
1432 bool "Timer and CPU usage LEDs"
1433 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1434 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1435 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1436 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1437 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1438 ARCH_AT91 || ARCH_DAVINCI || \
1439 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1441 If you say Y here, the LEDs on your machine will be used
1442 to provide useful information about your current system status.
1444 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1445 be able to select which LEDs are active using the options below. If
1446 you are compiling a kernel for the EBSA-110 or the LART however, the
1447 red LED will simply flash regularly to indicate that the system is
1448 still functional. It is safe to say Y here if you have a CATS
1449 system, but the driver will do nothing.
1452 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1453 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1454 || MACH_OMAP_PERSEUS2
1456 depends on !GENERIC_CLOCKEVENTS
1457 default y if ARCH_EBSA110
1459 If you say Y here, one of the system LEDs (the green one on the
1460 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1461 will flash regularly to indicate that the system is still
1462 operational. This is mainly useful to kernel hackers who are
1463 debugging unstable kernels.
1465 The LART uses the same LED for both Timer LED and CPU usage LED
1466 functions. You may choose to use both, but the Timer LED function
1467 will overrule the CPU usage LED.
1470 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1472 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1473 || MACH_OMAP_PERSEUS2
1476 If you say Y here, the red LED will be used to give a good real
1477 time indication of CPU usage, by lighting whenever the idle task
1478 is not currently executing.
1480 The LART uses the same LED for both Timer LED and CPU usage LED
1481 functions. You may choose to use both, but the Timer LED function
1482 will overrule the CPU usage LED.
1484 config ALIGNMENT_TRAP
1486 depends on CPU_CP15_MMU
1487 default y if !ARCH_EBSA110
1488 select HAVE_PROC_CPU if PROC_FS
1490 ARM processors cannot fetch/store information which is not
1491 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1492 address divisible by 4. On 32-bit ARM processors, these non-aligned
1493 fetch/store instructions will be emulated in software if you say
1494 here, which has a severe performance impact. This is necessary for
1495 correct operation of some network protocols. With an IP-only
1496 configuration it is safe to say N, otherwise say Y.
1498 config UACCESS_WITH_MEMCPY
1499 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1500 depends on MMU && EXPERIMENTAL
1501 default y if CPU_FEROCEON
1503 Implement faster copy_to_user and clear_user methods for CPU
1504 cores where a 8-word STM instruction give significantly higher
1505 memory write throughput than a sequence of individual 32bit stores.
1507 A possible side effect is a slight increase in scheduling latency
1508 between threads sharing the same address space if they invoke
1509 such copy operations with large buffers.
1511 However, if the CPU data cache is using a write-allocate mode,
1512 this option is unlikely to provide any performance gain.
1516 prompt "Enable seccomp to safely compute untrusted bytecode"
1518 This kernel feature is useful for number crunching applications
1519 that may need to compute untrusted bytecode during their
1520 execution. By using pipes or other transports made available to
1521 the process as file descriptors supporting the read/write
1522 syscalls, it's possible to isolate those applications in
1523 their own address space using seccomp. Once seccomp is
1524 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1525 and the task is only allowed to execute a few safe syscalls
1526 defined by each seccomp mode.
1528 config CC_STACKPROTECTOR
1529 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1531 This option turns on the -fstack-protector GCC feature. This
1532 feature puts, at the beginning of functions, a canary value on
1533 the stack just before the return address, and validates
1534 the value just before actually returning. Stack based buffer
1535 overflows (that need to overwrite this return address) now also
1536 overwrite the canary, which gets detected and the attack is then
1537 neutralized via a kernel panic.
1538 This feature requires gcc version 4.2 or above.
1540 config DEPRECATED_PARAM_STRUCT
1541 bool "Provide old way to pass kernel parameters"
1543 This was deprecated in 2001 and announced to live on for 5 years.
1544 Some old boot loaders still use this way.
1550 # Compressed boot loader in ROM. Yes, we really want to ask about
1551 # TEXT and BSS so we preserve their values in the config files.
1552 config ZBOOT_ROM_TEXT
1553 hex "Compressed ROM boot loader base address"
1556 The physical address at which the ROM-able zImage is to be
1557 placed in the target. Platforms which normally make use of
1558 ROM-able zImage formats normally set this to a suitable
1559 value in their defconfig file.
1561 If ZBOOT_ROM is not enabled, this has no effect.
1563 config ZBOOT_ROM_BSS
1564 hex "Compressed ROM boot loader BSS address"
1567 The base address of an area of read/write memory in the target
1568 for the ROM-able zImage which must be available while the
1569 decompressor is running. It must be large enough to hold the
1570 entire decompressed kernel plus an additional 128 KiB.
1571 Platforms which normally make use of ROM-able zImage formats
1572 normally set this to a suitable value in their defconfig file.
1574 If ZBOOT_ROM is not enabled, this has no effect.
1577 bool "Compressed boot loader in ROM/flash"
1578 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1580 Say Y here if you intend to execute your compressed kernel image
1581 (zImage) directly from ROM or flash. If unsure, say N.
1584 string "Default kernel command string"
1587 On some architectures (EBSA110 and CATS), there is currently no way
1588 for the boot loader to pass arguments to the kernel. For these
1589 architectures, you should supply some command-line options at build
1590 time by entering them here. As a minimum, you should specify the
1591 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1593 config CMDLINE_FORCE
1594 bool "Always use the default kernel command string"
1595 depends on CMDLINE != ""
1597 Always use the default kernel command string, even if the boot
1598 loader passes other arguments to the kernel.
1599 This is useful if you cannot or don't want to change the
1600 command-line options your boot loader passes to the kernel.
1605 bool "Kernel Execute-In-Place from ROM"
1606 depends on !ZBOOT_ROM
1608 Execute-In-Place allows the kernel to run from non-volatile storage
1609 directly addressable by the CPU, such as NOR flash. This saves RAM
1610 space since the text section of the kernel is not loaded from flash
1611 to RAM. Read-write sections, such as the data section and stack,
1612 are still copied to RAM. The XIP kernel is not compressed since
1613 it has to run directly from flash, so it will take more space to
1614 store it. The flash address used to link the kernel object files,
1615 and for storing it, is configuration dependent. Therefore, if you
1616 say Y here, you must know the proper physical address where to
1617 store the kernel image depending on your own flash memory usage.
1619 Also note that the make target becomes "make xipImage" rather than
1620 "make zImage" or "make Image". The final kernel binary to put in
1621 ROM memory will be arch/arm/boot/xipImage.
1625 config XIP_PHYS_ADDR
1626 hex "XIP Kernel Physical Location"
1627 depends on XIP_KERNEL
1628 default "0x00080000"
1630 This is the physical address in your flash memory the kernel will
1631 be linked for and stored to. This address is dependent on your
1635 bool "Kexec system call (EXPERIMENTAL)"
1636 depends on EXPERIMENTAL
1638 kexec is a system call that implements the ability to shutdown your
1639 current kernel, and to start another kernel. It is like a reboot
1640 but it is independent of the system firmware. And like a reboot
1641 you can start any kernel with it, not just Linux.
1643 It is an ongoing process to be certain the hardware in a machine
1644 is properly shutdown, so do not be surprised if this code does not
1645 initially work for you. It may help to enable device hotplugging
1649 bool "Export atags in procfs"
1653 Should the atags used to boot the kernel be exported in an "atags"
1654 file in procfs. Useful with kexec.
1656 config AUTO_ZRELADDR
1657 bool "Auto calculation of the decompressed kernel image address"
1658 depends on !ZBOOT_ROM && !ARCH_U300
1660 ZRELADDR is the physical address where the decompressed kernel
1661 image will be placed. If AUTO_ZRELADDR is selected, the address
1662 will be determined at run-time by masking the current IP with
1663 0xf8000000. This assumes the zImage being placed in the first 128MB
1664 from start of memory.
1668 menu "CPU Power Management"
1672 source "drivers/cpufreq/Kconfig"
1675 tristate "CPUfreq driver for i.MX CPUs"
1676 depends on ARCH_MXC && CPU_FREQ
1678 This enables the CPUfreq driver for i.MX CPUs.
1680 config CPU_FREQ_SA1100
1683 config CPU_FREQ_SA1110
1686 config CPU_FREQ_INTEGRATOR
1687 tristate "CPUfreq driver for ARM Integrator CPUs"
1688 depends on ARCH_INTEGRATOR && CPU_FREQ
1691 This enables the CPUfreq driver for ARM Integrator CPUs.
1693 For details, take a look at <file:Documentation/cpu-freq>.
1699 depends on CPU_FREQ && ARCH_PXA && PXA25x
1701 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1703 config CPU_FREQ_S3C64XX
1704 bool "CPUfreq support for Samsung S3C64XX CPUs"
1705 depends on CPU_FREQ && CPU_S3C6410
1710 Internal configuration node for common cpufreq on Samsung SoC
1712 config CPU_FREQ_S3C24XX
1713 bool "CPUfreq driver for Samsung S3C24XX series CPUs"
1714 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1717 This enables the CPUfreq driver for the Samsung S3C24XX family
1720 For details, take a look at <file:Documentation/cpu-freq>.
1724 config CPU_FREQ_S3C24XX_PLL
1725 bool "Support CPUfreq changing of PLL frequency"
1726 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1728 Compile in support for changing the PLL frequency from the
1729 S3C24XX series CPUfreq driver. The PLL takes time to settle
1730 after a frequency change, so by default it is not enabled.
1732 This also means that the PLL tables for the selected CPU(s) will
1733 be built which may increase the size of the kernel image.
1735 config CPU_FREQ_S3C24XX_DEBUG
1736 bool "Debug CPUfreq Samsung driver core"
1737 depends on CPU_FREQ_S3C24XX
1739 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1741 config CPU_FREQ_S3C24XX_IODEBUG
1742 bool "Debug CPUfreq Samsung driver IO timing"
1743 depends on CPU_FREQ_S3C24XX
1745 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1747 config CPU_FREQ_S3C24XX_DEBUGFS
1748 bool "Export debugfs for CPUFreq"
1749 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1751 Export status information via debugfs.
1755 source "drivers/cpuidle/Kconfig"
1759 menu "Floating point emulation"
1761 comment "At least one emulation must be selected"
1764 bool "NWFPE math emulation"
1765 depends on !AEABI || OABI_COMPAT
1767 Say Y to include the NWFPE floating point emulator in the kernel.
1768 This is necessary to run most binaries. Linux does not currently
1769 support floating point hardware so you need to say Y here even if
1770 your machine has an FPA or floating point co-processor podule.
1772 You may say N here if you are going to load the Acorn FPEmulator
1773 early in the bootup.
1776 bool "Support extended precision"
1777 depends on FPE_NWFPE
1779 Say Y to include 80-bit support in the kernel floating-point
1780 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1781 Note that gcc does not generate 80-bit operations by default,
1782 so in most cases this option only enlarges the size of the
1783 floating point emulator without any good reason.
1785 You almost surely want to say N here.
1788 bool "FastFPE math emulation (EXPERIMENTAL)"
1789 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1791 Say Y here to include the FAST floating point emulator in the kernel.
1792 This is an experimental much faster emulator which now also has full
1793 precision for the mantissa. It does not support any exceptions.
1794 It is very simple, and approximately 3-6 times faster than NWFPE.
1796 It should be sufficient for most programs. It may be not suitable
1797 for scientific calculations, but you have to check this for yourself.
1798 If you do not feel you need a faster FP emulation you should better
1802 bool "VFP-format floating point maths"
1803 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1805 Say Y to include VFP support code in the kernel. This is needed
1806 if your hardware includes a VFP unit.
1808 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1809 release notes and additional status information.
1811 Say N if your target does not have VFP hardware.
1819 bool "Advanced SIMD (NEON) Extension support"
1820 depends on VFPv3 && CPU_V7
1822 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1827 menu "Userspace binary formats"
1829 source "fs/Kconfig.binfmt"
1832 tristate "RISC OS personality"
1835 Say Y here to include the kernel code necessary if you want to run
1836 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1837 experimental; if this sounds frightening, say N and sleep in peace.
1838 You can also say M here to compile this support as a module (which
1839 will be called arthur).
1843 menu "Power management options"
1845 source "kernel/power/Kconfig"
1847 config ARCH_SUSPEND_POSSIBLE
1852 source "net/Kconfig"
1854 source "drivers/Kconfig"
1858 source "arch/arm/Kconfig.debug"
1860 source "security/Kconfig"
1862 source "crypto/Kconfig"
1864 source "lib/Kconfig"