arch/arm/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0
   2 config ARM
   3         bool
   4         default y
   5         select ARCH_CLOCKSOURCE_DATA
   6         select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
   7         select ARCH_HAS_DEBUG_VIRTUAL if MMU
   8         select ARCH_HAS_DEVMEM_IS_ALLOWED
   9         select ARCH_HAS_ELF_RANDOMIZE
  10         select ARCH_HAS_FORTIFY_SOURCE
  11         select ARCH_HAS_SET_MEMORY
  12         select ARCH_HAS_PHYS_TO_DMA
  13         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  14         select ARCH_HAS_STRICT_MODULE_RWX if MMU
  15         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  16         select ARCH_HAVE_CUSTOM_GPIO_H
  17         select ARCH_HAS_GCOV_PROFILE_ALL
  18         select ARCH_MIGHT_HAVE_PC_PARPORT
  19         select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  20         select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  21         select ARCH_SUPPORTS_ATOMIC_RMW
  22         select ARCH_USE_BUILTIN_BSWAP
  23         select ARCH_USE_CMPXCHG_LOCKREF
  24         select ARCH_WANT_IPC_PARSE_VERSION
  25         select BUILDTIME_EXTABLE_SORT if MMU
  26         select CLONE_BACKWARDS
  27         select CPU_PM if (SUSPEND || CPU_IDLE)
  28         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  29         select DMA_DIRECT_OPS if !MMU
  30         select EDAC_SUPPORT
  31         select EDAC_ATOMIC_SCRUB
  32         select GENERIC_ALLOCATOR
  33         select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  34         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  35         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  36         select GENERIC_CPU_AUTOPROBE
  37         select GENERIC_EARLY_IOREMAP
  38         select GENERIC_IDLE_POLL_SETUP
  39         select GENERIC_IRQ_PROBE
  40         select GENERIC_IRQ_SHOW
  41         select GENERIC_IRQ_SHOW_LEVEL
  42         select GENERIC_PCI_IOMAP
  43         select GENERIC_SCHED_CLOCK
  44         select GENERIC_SMP_IDLE_THREAD
  45         select GENERIC_STRNCPY_FROM_USER
  46         select GENERIC_STRNLEN_USER
  47         select HANDLE_DOMAIN_IRQ
  48         select HARDIRQS_SW_RESEND
  49         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  50         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  51         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  52         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  53         select HAVE_ARCH_MMAP_RND_BITS if MMU
  54         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  55         select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  56         select HAVE_ARCH_TRACEHOOK
  57         select HAVE_ARM_SMCCC if CPU_V7
  58         select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  59         select HAVE_CC_STACKPROTECTOR
  60         select HAVE_CONTEXT_TRACKING
  61         select HAVE_C_RECORDMCOUNT
  62         select HAVE_DEBUG_KMEMLEAK
  63         select HAVE_DMA_CONTIGUOUS if MMU
  64         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  65         select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  66         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  67         select HAVE_EXIT_THREAD
  68         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  69         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  70         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  71         select HAVE_GCC_PLUGINS
  72         select HAVE_GENERIC_DMA_COHERENT
  73         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  74         select HAVE_IDE if PCI || ISA || PCMCIA
  75         select HAVE_IRQ_TIME_ACCOUNTING
  76         select HAVE_KERNEL_GZIP
  77         select HAVE_KERNEL_LZ4
  78         select HAVE_KERNEL_LZMA
  79         select HAVE_KERNEL_LZO
  80         select HAVE_KERNEL_XZ
  81         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  82         select HAVE_KRETPROBES if (HAVE_KPROBES)
  83         select HAVE_MEMBLOCK
  84         select HAVE_MOD_ARCH_SPECIFIC
  85         select HAVE_NMI
  86         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  87         select HAVE_OPTPROBES if !THUMB2_KERNEL
  88         select HAVE_PERF_EVENTS
  89         select HAVE_PERF_REGS
  90         select HAVE_PERF_USER_STACK_DUMP
  91         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  92         select HAVE_REGS_AND_STACK_ACCESS_API
  93         select HAVE_SYSCALL_TRACEPOINTS
  94         select HAVE_UID16
  95         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  96         select IRQ_FORCED_THREADING
  97         select MODULES_USE_ELF_REL
  98         select NEED_DMA_MAP_STATE
  99         select NO_BOOTMEM
 100         select OF_EARLY_FLATTREE if OF
 101         select OF_RESERVED_MEM if OF
 102         select OLD_SIGACTION
 103         select OLD_SIGSUSPEND3
 104         select PERF_USE_VMALLOC
 105         select REFCOUNT_FULL
 106         select RTC_LIB
 107         select SYS_SUPPORTS_APM_EMULATION
 108         # Above selects are sorted alphabetically; please add new ones
 109         # according to that.  Thanks.
 110         help
 111           The ARM series is a line of low-power-consumption RISC chip designs
 112           licensed by ARM Ltd and targeted at embedded applications and
 113           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 114           manufactured, but legacy ARM-based PC hardware remains popular in
 115           Europe.  There is an ARM Linux project with a web page at
 116           <http://www.arm.linux.org.uk/>.
 117
 118 config ARM_HAS_SG_CHAIN
 119         select ARCH_HAS_SG_CHAIN
 120         bool
 121
 122 config ARM_DMA_USE_IOMMU
 123         bool
 124         select ARM_HAS_SG_CHAIN
 125         select NEED_SG_DMA_LENGTH
 126
 127 if ARM_DMA_USE_IOMMU
 128
 129 config ARM_DMA_IOMMU_ALIGNMENT
 130         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 131         range 4 9
 132         default 8
 133         help
 134           DMA mapping framework by default aligns all buffers to the smallest
 135           PAGE_SIZE order which is greater than or equal to the requested buffer
 136           size. This works well for buffers up to a few hundreds kilobytes, but
 137           for larger buffers it just a waste of address space. Drivers which has
 138           relatively small addressing window (like 64Mib) might run out of
 139           virtual space with just a few allocations.
 140
 141           With this parameter you can specify the maximum PAGE_SIZE order for
 142           DMA IOMMU buffers. Larger buffers will be aligned only to this
 143           specified order. The order is expressed as a power of two multiplied
 144           by the PAGE_SIZE.
 145
 146 endif
 147
 148 config MIGHT_HAVE_PCI
 149         bool
 150
 151 config SYS_SUPPORTS_APM_EMULATION
 152         bool
 153
 154 config HAVE_TCM
 155         bool
 156         select GENERIC_ALLOCATOR
 157
 158 config HAVE_PROC_CPU
 159         bool
 160
 161 config NO_IOPORT_MAP
 162         bool
 163
 164 config EISA
 165         bool
 166         ---help---
 167           The Extended Industry Standard Architecture (EISA) bus was
 168           developed as an open alternative to the IBM MicroChannel bus.
 169
 170           The EISA bus provided some of the features of the IBM MicroChannel
 171           bus while maintaining backward compatibility with cards made for
 172           the older ISA bus.  The EISA bus saw limited use between 1988 and
 173           1995 when it was made obsolete by the PCI bus.
 174
 175           Say Y here if you are building a kernel for an EISA-based machine.
 176
 177           Otherwise, say N.
 178
 179 config SBUS
 180         bool
 181
 182 config STACKTRACE_SUPPORT
 183         bool
 184         default y
 185
 186 config LOCKDEP_SUPPORT
 187         bool
 188         default y
 189
 190 config TRACE_IRQFLAGS_SUPPORT
 191         bool
 192         default !CPU_V7M
 193
 194 config RWSEM_XCHGADD_ALGORITHM
 195         bool
 196         default y
 197
 198 config ARCH_HAS_ILOG2_U32
 199         bool
 200
 201 config ARCH_HAS_ILOG2_U64
 202         bool
 203
 204 config ARCH_HAS_BANDGAP
 205         bool
 206
 207 config FIX_EARLYCON_MEM
 208         def_bool y if MMU
 209
 210 config GENERIC_HWEIGHT
 211         bool
 212         default y
 213
 214 config GENERIC_CALIBRATE_DELAY
 215         bool
 216         default y
 217
 218 config ARCH_MAY_HAVE_PC_FDC
 219         bool
 220
 221 config ZONE_DMA
 222         bool
 223
 224 config ARCH_SUPPORTS_UPROBES
 225         def_bool y
 226
 227 config ARCH_HAS_DMA_SET_COHERENT_MASK
 228         bool
 229
 230 config GENERIC_ISA_DMA
 231         bool
 232
 233 config FIQ
 234         bool
 235
 236 config NEED_RET_TO_USER
 237         bool
 238
 239 config ARCH_MTD_XIP
 240         bool
 241
 242 config ARM_PATCH_PHYS_VIRT
 243         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 244         default y
 245         depends on !XIP_KERNEL && MMU
 246         help
 247           Patch phys-to-virt and virt-to-phys translation functions at
 248           boot and module load time according to the position of the
 249           kernel in system memory.
 250
 251           This can only be used with non-XIP MMU kernels where the base
 252           of physical memory is at a 16MB boundary.
 253
 254           Only disable this option if you know that you do not require
 255           this feature (eg, building a kernel for a single machine) and
 256           you need to shrink the kernel to the minimal size.
 257
 258 config NEED_MACH_IO_H
 259         bool
 260         help
 261           Select this when mach/io.h is required to provide special
 262           definitions for this platform.  The need for mach/io.h should
 263           be avoided when possible.
 264
 265 config NEED_MACH_MEMORY_H
 266         bool
 267         help
 268           Select this when mach/memory.h is required to provide special
 269           definitions for this platform.  The need for mach/memory.h should
 270           be avoided when possible.
 271
 272 config PHYS_OFFSET
 273         hex "Physical address of main memory" if MMU
 274         depends on !ARM_PATCH_PHYS_VIRT
 275         default DRAM_BASE if !MMU
 276         default 0x00000000 if ARCH_EBSA110 || \
 277                         ARCH_FOOTBRIDGE || \
 278                         ARCH_INTEGRATOR || \
 279                         ARCH_IOP13XX || \
 280                         ARCH_KS8695 || \
 281                         ARCH_REALVIEW
 282         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 283         default 0x20000000 if ARCH_S5PV210
 284         default 0xc0000000 if ARCH_SA1100
 285         help
 286           Please provide the physical address corresponding to the
 287           location of main memory in your system.
 288
 289 config GENERIC_BUG
 290         def_bool y
 291         depends on BUG
 292
 293 config PGTABLE_LEVELS
 294         int
 295         default 3 if ARM_LPAE
 296         default 2
 297
 298 source "init/Kconfig"
 299
 300 source "kernel/Kconfig.freezer"
 301
 302 menu "System Type"
 303
 304 config MMU
 305         bool "MMU-based Paged Memory Management Support"
 306         default y
 307         help
 308           Select if you want MMU-based virtualised addressing space
 309           support by paged memory management. If unsure, say 'Y'.
 310
 311 config ARCH_MMAP_RND_BITS_MIN
 312         default 8
 313
 314 config ARCH_MMAP_RND_BITS_MAX
 315         default 14 if PAGE_OFFSET=0x40000000
 316         default 15 if PAGE_OFFSET=0x80000000
 317         default 16
 318
 319 #
 320 # The "ARM system type" choice list is ordered alphabetically by option
 321 # text.  Please add new entries in the option alphabetic order.
 322 #
 323 choice
 324         prompt "ARM system type"
 325         default ARM_SINGLE_ARMV7M if !MMU
 326         default ARCH_MULTIPLATFORM if MMU
 327
 328 config ARCH_MULTIPLATFORM
 329         bool "Allow multiple platforms to be selected"
 330         depends on MMU
 331         select ARM_HAS_SG_CHAIN
 332         select ARM_PATCH_PHYS_VIRT
 333         select AUTO_ZRELADDR
 334         select TIMER_OF
 335         select COMMON_CLK
 336         select GENERIC_CLOCKEVENTS
 337         select MIGHT_HAVE_PCI
 338         select MULTI_IRQ_HANDLER
 339         select PCI_DOMAINS if PCI
 340         select SPARSE_IRQ
 341         select USE_OF
 342
 343 config ARM_SINGLE_ARMV7M
 344         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 345         depends on !MMU
 346         select ARM_NVIC
 347         select AUTO_ZRELADDR
 348         select TIMER_OF
 349         select COMMON_CLK
 350         select CPU_V7M
 351         select GENERIC_CLOCKEVENTS
 352         select NO_IOPORT_MAP
 353         select SPARSE_IRQ
 354         select USE_OF
 355
 356 config ARCH_EBSA110
 357         bool "EBSA-110"
 358         select ARCH_USES_GETTIMEOFFSET
 359         select CPU_SA110
 360         select ISA
 361         select NEED_MACH_IO_H
 362         select NEED_MACH_MEMORY_H
 363         select NO_IOPORT_MAP
 364         help
 365           This is an evaluation board for the StrongARM processor available
 366           from Digital. It has limited hardware on-board, including an
 367           Ethernet interface, two PCMCIA sockets, two serial ports and a
 368           parallel port.
 369
 370 config ARCH_EP93XX
 371         bool "EP93xx-based"
 372         select ARCH_SPARSEMEM_ENABLE
 373         select ARM_AMBA
 374         imply ARM_PATCH_PHYS_VIRT
 375         select ARM_VIC
 376         select AUTO_ZRELADDR
 377         select CLKDEV_LOOKUP
 378         select CLKSRC_MMIO
 379         select CPU_ARM920T
 380         select GENERIC_CLOCKEVENTS
 381         select GPIOLIB
 382         help
 383           This enables support for the Cirrus EP93xx series of CPUs.
 384
 385 config ARCH_FOOTBRIDGE
 386         bool "FootBridge"
 387         select CPU_SA110
 388         select FOOTBRIDGE
 389         select GENERIC_CLOCKEVENTS
 390         select HAVE_IDE
 391         select NEED_MACH_IO_H if !MMU
 392         select NEED_MACH_MEMORY_H
 393         help
 394           Support for systems based on the DC21285 companion chip
 395           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 396
 397 config ARCH_NETX
 398         bool "Hilscher NetX based"
 399         select ARM_VIC
 400         select CLKSRC_MMIO
 401         select CPU_ARM926T
 402         select GENERIC_CLOCKEVENTS
 403         help
 404           This enables support for systems based on the Hilscher NetX Soc
 405
 406 config ARCH_IOP13XX
 407         bool "IOP13xx-based"
 408         depends on MMU
 409         select CPU_XSC3
 410         select NEED_MACH_MEMORY_H
 411         select NEED_RET_TO_USER
 412         select PCI
 413         select PLAT_IOP
 414         select VMSPLIT_1G
 415         select SPARSE_IRQ
 416         help
 417           Support for Intel's IOP13XX (XScale) family of processors.
 418
 419 config ARCH_IOP32X
 420         bool "IOP32x-based"
 421         depends on MMU
 422         select CPU_XSCALE
 423         select GPIO_IOP
 424         select GPIOLIB
 425         select NEED_RET_TO_USER
 426         select PCI
 427         select PLAT_IOP
 428         help
 429           Support for Intel's 80219 and IOP32X (XScale) family of
 430           processors.
 431
 432 config ARCH_IOP33X
 433         bool "IOP33x-based"
 434         depends on MMU
 435         select CPU_XSCALE
 436         select GPIO_IOP
 437         select GPIOLIB
 438         select NEED_RET_TO_USER
 439         select PCI
 440         select PLAT_IOP
 441         help
 442           Support for Intel's IOP33X (XScale) family of processors.
 443
 444 config ARCH_IXP4XX
 445         bool "IXP4xx-based"
 446         depends on MMU
 447         select ARCH_HAS_DMA_SET_COHERENT_MASK
 448         select ARCH_SUPPORTS_BIG_ENDIAN
 449         select CLKSRC_MMIO
 450         select CPU_XSCALE
 451         select DMABOUNCE if PCI
 452         select GENERIC_CLOCKEVENTS
 453         select GPIOLIB
 454         select MIGHT_HAVE_PCI
 455         select NEED_MACH_IO_H
 456         select USB_EHCI_BIG_ENDIAN_DESC
 457         select USB_EHCI_BIG_ENDIAN_MMIO
 458         help
 459           Support for Intel's IXP4XX (XScale) family of processors.
 460
 461 config ARCH_DOVE
 462         bool "Marvell Dove"
 463         select CPU_PJ4
 464         select GENERIC_CLOCKEVENTS
 465         select GPIOLIB
 466         select MIGHT_HAVE_PCI
 467         select MULTI_IRQ_HANDLER
 468         select MVEBU_MBUS
 469         select PINCTRL
 470         select PINCTRL_DOVE
 471         select PLAT_ORION_LEGACY
 472         select SPARSE_IRQ
 473         select PM_GENERIC_DOMAINS if PM
 474         help
 475           Support for the Marvell Dove SoC 88AP510
 476
 477 config ARCH_KS8695
 478         bool "Micrel/Kendin KS8695"
 479         select CLKSRC_MMIO
 480         select CPU_ARM922T
 481         select GENERIC_CLOCKEVENTS
 482         select GPIOLIB
 483         select NEED_MACH_MEMORY_H
 484         help
 485           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 486           System-on-Chip devices.
 487
 488 config ARCH_W90X900
 489         bool "Nuvoton W90X900 CPU"
 490         select CLKDEV_LOOKUP
 491         select CLKSRC_MMIO
 492         select CPU_ARM926T
 493         select GENERIC_CLOCKEVENTS
 494         select GPIOLIB
 495         help
 496           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 497           At present, the w90x900 has been renamed nuc900, regarding
 498           the ARM series product line, you can login the following
 499           link address to know more.
 500
 501           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 502                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 503
 504 config ARCH_LPC32XX
 505         bool "NXP LPC32XX"
 506         select ARM_AMBA
 507         select CLKDEV_LOOKUP
 508         select CLKSRC_LPC32XX
 509         select COMMON_CLK
 510         select CPU_ARM926T
 511         select GENERIC_CLOCKEVENTS
 512         select GPIOLIB
 513         select MULTI_IRQ_HANDLER
 514         select SPARSE_IRQ
 515         select USE_OF
 516         help
 517           Support for the NXP LPC32XX family of processors
 518
 519 config ARCH_PXA
 520         bool "PXA2xx/PXA3xx-based"
 521         depends on MMU
 522         select ARCH_MTD_XIP
 523         select ARM_CPU_SUSPEND if PM
 524         select AUTO_ZRELADDR
 525         select COMMON_CLK
 526         select CLKDEV_LOOKUP
 527         select CLKSRC_PXA
 528         select CLKSRC_MMIO
 529         select TIMER_OF
 530         select CPU_XSCALE if !CPU_XSC3
 531         select GENERIC_CLOCKEVENTS
 532         select GPIO_PXA
 533         select GPIOLIB
 534         select HAVE_IDE
 535         select IRQ_DOMAIN
 536         select MULTI_IRQ_HANDLER
 537         select PLAT_PXA
 538         select SPARSE_IRQ
 539         help
 540           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 541
 542 config ARCH_RPC
 543         bool "RiscPC"
 544         depends on MMU
 545         select ARCH_ACORN
 546         select ARCH_MAY_HAVE_PC_FDC
 547         select ARCH_SPARSEMEM_ENABLE
 548         select ARCH_USES_GETTIMEOFFSET
 549         select CPU_SA110
 550         select FIQ
 551         select HAVE_IDE
 552         select HAVE_PATA_PLATFORM
 553         select ISA_DMA_API
 554         select NEED_MACH_IO_H
 555         select NEED_MACH_MEMORY_H
 556         select NO_IOPORT_MAP
 557         help
 558           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 559           CD-ROM interface, serial and parallel port, and the floppy drive.
 560
 561 config ARCH_SA1100
 562         bool "SA1100-based"
 563         select ARCH_MTD_XIP
 564         select ARCH_SPARSEMEM_ENABLE
 565         select CLKDEV_LOOKUP
 566         select CLKSRC_MMIO
 567         select CLKSRC_PXA
 568         select TIMER_OF if OF
 569         select CPU_FREQ
 570         select CPU_SA1100
 571         select GENERIC_CLOCKEVENTS
 572         select GPIOLIB
 573         select HAVE_IDE
 574         select IRQ_DOMAIN
 575         select ISA
 576         select MULTI_IRQ_HANDLER
 577         select NEED_MACH_MEMORY_H
 578         select SPARSE_IRQ
 579         help
 580           Support for StrongARM 11x0 based boards.
 581
 582 config ARCH_S3C24XX
 583         bool "Samsung S3C24XX SoCs"
 584         select ATAGS
 585         select CLKDEV_LOOKUP
 586         select CLKSRC_SAMSUNG_PWM
 587         select GENERIC_CLOCKEVENTS
 588         select GPIO_SAMSUNG
 589         select GPIOLIB
 590         select HAVE_S3C2410_I2C if I2C
 591         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 592         select HAVE_S3C_RTC if RTC_CLASS
 593         select MULTI_IRQ_HANDLER
 594         select NEED_MACH_IO_H
 595         select SAMSUNG_ATAGS
 596         select USE_OF
 597         help
 598           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 599           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 600           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 601           Samsung SMDK2410 development board (and derivatives).
 602
 603 config ARCH_DAVINCI
 604         bool "TI DaVinci"
 605         select ARCH_HAS_HOLES_MEMORYMODEL
 606         select CLKDEV_LOOKUP
 607         select CPU_ARM926T
 608         select GENERIC_ALLOCATOR
 609         select GENERIC_CLOCKEVENTS
 610         select GENERIC_IRQ_CHIP
 611         select GPIOLIB
 612         select HAVE_IDE
 613         select USE_OF
 614         select ZONE_DMA
 615         help
 616           Support for TI's DaVinci platform.
 617
 618 config ARCH_OMAP1
 619         bool "TI OMAP1"
 620         depends on MMU
 621         select ARCH_HAS_HOLES_MEMORYMODEL
 622         select ARCH_OMAP
 623         select CLKDEV_LOOKUP
 624         select CLKSRC_MMIO
 625         select GENERIC_CLOCKEVENTS
 626         select GENERIC_IRQ_CHIP
 627         select GPIOLIB
 628         select HAVE_IDE
 629         select IRQ_DOMAIN
 630         select MULTI_IRQ_HANDLER
 631         select NEED_MACH_IO_H if PCCARD
 632         select NEED_MACH_MEMORY_H
 633         select SPARSE_IRQ
 634         help
 635           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 636
 637 endchoice
 638
 639 menu "Multiple platform selection"
 640         depends on ARCH_MULTIPLATFORM
 641
 642 comment "CPU Core family selection"
 643
 644 config ARCH_MULTI_V4
 645         bool "ARMv4 based platforms (FA526)"
 646         depends on !ARCH_MULTI_V6_V7
 647         select ARCH_MULTI_V4_V5
 648         select CPU_FA526
 649
 650 config ARCH_MULTI_V4T
 651         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 652         depends on !ARCH_MULTI_V6_V7
 653         select ARCH_MULTI_V4_V5
 654         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 655                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 656                 CPU_ARM925T || CPU_ARM940T)
 657
 658 config ARCH_MULTI_V5
 659         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 660         depends on !ARCH_MULTI_V6_V7
 661         select ARCH_MULTI_V4_V5
 662         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 663                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 664                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 665
 666 config ARCH_MULTI_V4_V5
 667         bool
 668
 669 config ARCH_MULTI_V6
 670         bool "ARMv6 based platforms (ARM11)"
 671         select ARCH_MULTI_V6_V7
 672         select CPU_V6K
 673
 674 config ARCH_MULTI_V7
 675         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 676         default y
 677         select ARCH_MULTI_V6_V7
 678         select CPU_V7
 679         select HAVE_SMP
 680
 681 config ARCH_MULTI_V6_V7
 682         bool
 683         select MIGHT_HAVE_CACHE_L2X0
 684
 685 config ARCH_MULTI_CPU_AUTO
 686         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 687         select ARCH_MULTI_V5
 688
 689 endmenu
 690
 691 config ARCH_VIRT
 692         bool "Dummy Virtual Machine"
 693         depends on ARCH_MULTI_V7
 694         select ARM_AMBA
 695         select ARM_GIC
 696         select ARM_GIC_V2M if PCI
 697         select ARM_GIC_V3
 698         select ARM_GIC_V3_ITS if PCI
 699         select ARM_PSCI
 700         select HAVE_ARM_ARCH_TIMER
 701
 702 #
 703 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 704 # Kconfigs may be included either alphabetically (according to the
 705 # plat- suffix) or along side the corresponding mach-* source.
 706 #
 707 source "arch/arm/mach-actions/Kconfig"
 708
 709 source "arch/arm/mach-alpine/Kconfig"
 710
 711 source "arch/arm/mach-artpec/Kconfig"
 712
 713 source "arch/arm/mach-asm9260/Kconfig"
 714
 715 source "arch/arm/mach-aspeed/Kconfig"
 716
 717 source "arch/arm/mach-at91/Kconfig"
 718
 719 source "arch/arm/mach-axxia/Kconfig"
 720
 721 source "arch/arm/mach-bcm/Kconfig"
 722
 723 source "arch/arm/mach-berlin/Kconfig"
 724
 725 source "arch/arm/mach-clps711x/Kconfig"
 726
 727 source "arch/arm/mach-cns3xxx/Kconfig"
 728
 729 source "arch/arm/mach-davinci/Kconfig"
 730
 731 source "arch/arm/mach-digicolor/Kconfig"
 732
 733 source "arch/arm/mach-dove/Kconfig"
 734
 735 source "arch/arm/mach-ep93xx/Kconfig"
 736
 737 source "arch/arm/mach-exynos/Kconfig"
 738 source "arch/arm/plat-samsung/Kconfig"
 739
 740 source "arch/arm/mach-footbridge/Kconfig"
 741
 742 source "arch/arm/mach-gemini/Kconfig"
 743
 744 source "arch/arm/mach-highbank/Kconfig"
 745
 746 source "arch/arm/mach-hisi/Kconfig"
 747
 748 source "arch/arm/mach-imx/Kconfig"
 749
 750 source "arch/arm/mach-integrator/Kconfig"
 751
 752 source "arch/arm/mach-iop13xx/Kconfig"
 753
 754 source "arch/arm/mach-iop32x/Kconfig"
 755
 756 source "arch/arm/mach-iop33x/Kconfig"
 757
 758 source "arch/arm/mach-ixp4xx/Kconfig"
 759
 760 source "arch/arm/mach-keystone/Kconfig"
 761
 762 source "arch/arm/mach-ks8695/Kconfig"
 763
 764 source "arch/arm/mach-mediatek/Kconfig"
 765
 766 source "arch/arm/mach-meson/Kconfig"
 767
 768 source "arch/arm/mach-mmp/Kconfig"
 769
 770 source "arch/arm/mach-moxart/Kconfig"
 771
 772 source "arch/arm/mach-mv78xx0/Kconfig"
 773
 774 source "arch/arm/mach-mvebu/Kconfig"
 775
 776 source "arch/arm/mach-mxs/Kconfig"
 777
 778 source "arch/arm/mach-netx/Kconfig"
 779
 780 source "arch/arm/mach-nomadik/Kconfig"
 781
 782 source "arch/arm/mach-npcm/Kconfig"
 783
 784 source "arch/arm/mach-nspire/Kconfig"
 785
 786 source "arch/arm/plat-omap/Kconfig"
 787
 788 source "arch/arm/mach-omap1/Kconfig"
 789
 790 source "arch/arm/mach-omap2/Kconfig"
 791
 792 source "arch/arm/mach-orion5x/Kconfig"
 793
 794 source "arch/arm/mach-oxnas/Kconfig"
 795
 796 source "arch/arm/mach-picoxcell/Kconfig"
 797
 798 source "arch/arm/mach-prima2/Kconfig"
 799
 800 source "arch/arm/mach-pxa/Kconfig"
 801 source "arch/arm/plat-pxa/Kconfig"
 802
 803 source "arch/arm/mach-qcom/Kconfig"
 804
 805 source "arch/arm/mach-realview/Kconfig"
 806
 807 source "arch/arm/mach-rockchip/Kconfig"
 808
 809 source "arch/arm/mach-s3c24xx/Kconfig"
 810
 811 source "arch/arm/mach-s3c64xx/Kconfig"
 812
 813 source "arch/arm/mach-s5pv210/Kconfig"
 814
 815 source "arch/arm/mach-sa1100/Kconfig"
 816
 817 source "arch/arm/mach-shmobile/Kconfig"
 818
 819 source "arch/arm/mach-socfpga/Kconfig"
 820
 821 source "arch/arm/mach-spear/Kconfig"
 822
 823 source "arch/arm/mach-sti/Kconfig"
 824
 825 source "arch/arm/mach-stm32/Kconfig"
 826
 827 source "arch/arm/mach-sunxi/Kconfig"
 828
 829 source "arch/arm/mach-tango/Kconfig"
 830
 831 source "arch/arm/mach-tegra/Kconfig"
 832
 833 source "arch/arm/mach-u300/Kconfig"
 834
 835 source "arch/arm/mach-uniphier/Kconfig"
 836
 837 source "arch/arm/mach-ux500/Kconfig"
 838
 839 source "arch/arm/mach-versatile/Kconfig"
 840
 841 source "arch/arm/mach-vexpress/Kconfig"
 842 source "arch/arm/plat-versatile/Kconfig"
 843
 844 source "arch/arm/mach-vt8500/Kconfig"
 845
 846 source "arch/arm/mach-w90x900/Kconfig"
 847
 848 source "arch/arm/mach-zx/Kconfig"
 849
 850 source "arch/arm/mach-zynq/Kconfig"
 851
 852 # ARMv7-M architecture
 853 config ARCH_EFM32
 854         bool "Energy Micro efm32"
 855         depends on ARM_SINGLE_ARMV7M
 856         select GPIOLIB
 857         help
 858           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 859           processors.
 860
 861 config ARCH_LPC18XX
 862         bool "NXP LPC18xx/LPC43xx"
 863         depends on ARM_SINGLE_ARMV7M
 864         select ARCH_HAS_RESET_CONTROLLER
 865         select ARM_AMBA
 866         select CLKSRC_LPC32XX
 867         select PINCTRL
 868         help
 869           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 870           high performance microcontrollers.
 871
 872 config ARCH_MPS2
 873         bool "ARM MPS2 platform"
 874         depends on ARM_SINGLE_ARMV7M
 875         select ARM_AMBA
 876         select CLKSRC_MPS2
 877         help
 878           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 879           with a range of available cores like Cortex-M3/M4/M7.
 880
 881           Please, note that depends which Application Note is used memory map
 882           for the platform may vary, so adjustment of RAM base might be needed.
 883
 884 # Definitions to make life easier
 885 config ARCH_ACORN
 886         bool
 887
 888 config PLAT_IOP
 889         bool
 890         select GENERIC_CLOCKEVENTS
 891
 892 config PLAT_ORION
 893         bool
 894         select CLKSRC_MMIO
 895         select COMMON_CLK
 896         select GENERIC_IRQ_CHIP
 897         select IRQ_DOMAIN
 898
 899 config PLAT_ORION_LEGACY
 900         bool
 901         select PLAT_ORION
 902
 903 config PLAT_PXA
 904         bool
 905
 906 config PLAT_VERSATILE
 907         bool
 908
 909 source "arch/arm/firmware/Kconfig"
 910
 911 source arch/arm/mm/Kconfig
 912
 913 config IWMMXT
 914         bool "Enable iWMMXt support"
 915         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 916         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 917         help
 918           Enable support for iWMMXt context switching at run time if
 919           running on a CPU that supports it.
 920
 921 config MULTI_IRQ_HANDLER
 922         bool
 923         help
 924           Allow each machine to specify it's own IRQ handler at run time.
 925
 926 if !MMU
 927 source "arch/arm/Kconfig-nommu"
 928 endif
 929
 930 config PJ4B_ERRATA_4742
 931         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 932         depends on CPU_PJ4B && MACH_ARMADA_370
 933         default y
 934         help
 935           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 936           Event (WFE) IDLE states, a specific timing sensitivity exists between
 937           the retiring WFI/WFE instructions and the newly issued subsequent
 938           instructions.  This sensitivity can result in a CPU hang scenario.
 939           Workaround:
 940           The software must insert either a Data Synchronization Barrier (DSB)
 941           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 942           instruction
 943
 944 config ARM_ERRATA_326103
 945         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 946         depends on CPU_V6
 947         help
 948           Executing a SWP instruction to read-only memory does not set bit 11
 949           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 950           treat the access as a read, preventing a COW from occurring and
 951           causing the faulting task to livelock.
 952
 953 config ARM_ERRATA_411920
 954         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 955         depends on CPU_V6 || CPU_V6K
 956         help
 957           Invalidation of the Instruction Cache operation can
 958           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 959           It does not affect the MPCore. This option enables the ARM Ltd.
 960           recommended workaround.
 961
 962 config ARM_ERRATA_430973
 963         bool "ARM errata: Stale prediction on replaced interworking branch"
 964         depends on CPU_V7
 965         help
 966           This option enables the workaround for the 430973 Cortex-A8
 967           r1p* erratum. If a code sequence containing an ARM/Thumb
 968           interworking branch is replaced with another code sequence at the
 969           same virtual address, whether due to self-modifying code or virtual
 970           to physical address re-mapping, Cortex-A8 does not recover from the
 971           stale interworking branch prediction. This results in Cortex-A8
 972           executing the new code sequence in the incorrect ARM or Thumb state.
 973           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 974           and also flushes the branch target cache at every context switch.
 975           Note that setting specific bits in the ACTLR register may not be
 976           available in non-secure mode.
 977
 978 config ARM_ERRATA_458693
 979         bool "ARM errata: Processor deadlock when a false hazard is created"
 980         depends on CPU_V7
 981         depends on !ARCH_MULTIPLATFORM
 982         help
 983           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 984           erratum. For very specific sequences of memory operations, it is
 985           possible for a hazard condition intended for a cache line to instead
 986           be incorrectly associated with a different cache line. This false
 987           hazard might then cause a processor deadlock. The workaround enables
 988           the L1 caching of the NEON accesses and disables the PLD instruction
 989           in the ACTLR register. Note that setting specific bits in the ACTLR
 990           register may not be available in non-secure mode.
 991
 992 config ARM_ERRATA_460075
 993         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
 994         depends on CPU_V7
 995         depends on !ARCH_MULTIPLATFORM
 996         help
 997           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
 998           erratum. Any asynchronous access to the L2 cache may encounter a
 999           situation in which recent store transactions to the L2 cache are lost
1000           and overwritten with stale memory contents from external memory. The
1001           workaround disables the write-allocate mode for the L2 cache via the
1002           ACTLR register. Note that setting specific bits in the ACTLR register
1003           may not be available in non-secure mode.
1004
1005 config ARM_ERRATA_742230
1006         bool "ARM errata: DMB operation may be faulty"
1007         depends on CPU_V7 && SMP
1008         depends on !ARCH_MULTIPLATFORM
1009         help
1010           This option enables the workaround for the 742230 Cortex-A9
1011           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1012           between two write operations may not ensure the correct visibility
1013           ordering of the two writes. This workaround sets a specific bit in
1014           the diagnostic register of the Cortex-A9 which causes the DMB
1015           instruction to behave as a DSB, ensuring the correct behaviour of
1016           the two writes.
1017
1018 config ARM_ERRATA_742231
1019         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1020         depends on CPU_V7 && SMP
1021         depends on !ARCH_MULTIPLATFORM
1022         help
1023           This option enables the workaround for the 742231 Cortex-A9
1024           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1025           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1026           accessing some data located in the same cache line, may get corrupted
1027           data due to bad handling of the address hazard when the line gets
1028           replaced from one of the CPUs at the same time as another CPU is
1029           accessing it. This workaround sets specific bits in the diagnostic
1030           register of the Cortex-A9 which reduces the linefill issuing
1031           capabilities of the processor.
1032
1033 config ARM_ERRATA_643719
1034         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1035         depends on CPU_V7 && SMP
1036         default y
1037         help
1038           This option enables the workaround for the 643719 Cortex-A9 (prior to
1039           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1040           register returns zero when it should return one. The workaround
1041           corrects this value, ensuring cache maintenance operations which use
1042           it behave as intended and avoiding data corruption.
1043
1044 config ARM_ERRATA_720789
1045         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1046         depends on CPU_V7
1047         help
1048           This option enables the workaround for the 720789 Cortex-A9 (prior to
1049           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1050           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1051           As a consequence of this erratum, some TLB entries which should be
1052           invalidated are not, resulting in an incoherency in the system page
1053           tables. The workaround changes the TLB flushing routines to invalidate
1054           entries regardless of the ASID.
1055
1056 config ARM_ERRATA_743622
1057         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1058         depends on CPU_V7
1059         depends on !ARCH_MULTIPLATFORM
1060         help
1061           This option enables the workaround for the 743622 Cortex-A9
1062           (r2p*) erratum. Under very rare conditions, a faulty
1063           optimisation in the Cortex-A9 Store Buffer may lead to data
1064           corruption. This workaround sets a specific bit in the diagnostic
1065           register of the Cortex-A9 which disables the Store Buffer
1066           optimisation, preventing the defect from occurring. This has no
1067           visible impact on the overall performance or power consumption of the
1068           processor.
1069
1070 config ARM_ERRATA_751472
1071         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1072         depends on CPU_V7
1073         depends on !ARCH_MULTIPLATFORM
1074         help
1075           This option enables the workaround for the 751472 Cortex-A9 (prior
1076           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1077           completion of a following broadcasted operation if the second
1078           operation is received by a CPU before the ICIALLUIS has completed,
1079           potentially leading to corrupted entries in the cache or TLB.
1080
1081 config ARM_ERRATA_754322
1082         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1083         depends on CPU_V7
1084         help
1085           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1086           r3p*) erratum. A speculative memory access may cause a page table walk
1087           which starts prior to an ASID switch but completes afterwards. This
1088           can populate the micro-TLB with a stale entry which may be hit with
1089           the new ASID. This workaround places two dsb instructions in the mm
1090           switching code so that no page table walks can cross the ASID switch.
1091
1092 config ARM_ERRATA_754327
1093         bool "ARM errata: no automatic Store Buffer drain"
1094         depends on CPU_V7 && SMP
1095         help
1096           This option enables the workaround for the 754327 Cortex-A9 (prior to
1097           r2p0) erratum. The Store Buffer does not have any automatic draining
1098           mechanism and therefore a livelock may occur if an external agent
1099           continuously polls a memory location waiting to observe an update.
1100           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1101           written polling loops from denying visibility of updates to memory.
1102
1103 config ARM_ERRATA_364296
1104         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1105         depends on CPU_V6
1106         help
1107           This options enables the workaround for the 364296 ARM1136
1108           r0p2 erratum (possible cache data corruption with
1109           hit-under-miss enabled). It sets the undocumented bit 31 in
1110           the auxiliary control register and the FI bit in the control
1111           register, thus disabling hit-under-miss without putting the
1112           processor into full low interrupt latency mode. ARM11MPCore
1113           is not affected.
1114
1115 config ARM_ERRATA_764369
1116         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1117         depends on CPU_V7 && SMP
1118         help
1119           This option enables the workaround for erratum 764369
1120           affecting Cortex-A9 MPCore with two or more processors (all
1121           current revisions). Under certain timing circumstances, a data
1122           cache line maintenance operation by MVA targeting an Inner
1123           Shareable memory region may fail to proceed up to either the
1124           Point of Coherency or to the Point of Unification of the
1125           system. This workaround adds a DSB instruction before the
1126           relevant cache maintenance functions and sets a specific bit
1127           in the diagnostic control register of the SCU.
1128
1129 config ARM_ERRATA_775420
1130        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1131        depends on CPU_V7
1132        help
1133          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1134          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1135          operation aborts with MMU exception, it might cause the processor
1136          to deadlock. This workaround puts DSB before executing ISB if
1137          an abort may occur on cache maintenance.
1138
1139 config ARM_ERRATA_798181
1140         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1141         depends on CPU_V7 && SMP
1142         help
1143           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1144           adequately shooting down all use of the old entries. This
1145           option enables the Linux kernel workaround for this erratum
1146           which sends an IPI to the CPUs that are running the same ASID
1147           as the one being invalidated.
1148
1149 config ARM_ERRATA_773022
1150         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1151         depends on CPU_V7
1152         help
1153           This option enables the workaround for the 773022 Cortex-A15
1154           (up to r0p4) erratum. In certain rare sequences of code, the
1155           loop buffer may deliver incorrect instructions. This
1156           workaround disables the loop buffer to avoid the erratum.
1157
1158 config ARM_ERRATA_818325_852422
1159         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1160         depends on CPU_V7
1161         help
1162           This option enables the workaround for:
1163           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1164             instruction might deadlock.  Fixed in r0p1.
1165           - Cortex-A12 852422: Execution of a sequence of instructions might
1166             lead to either a data corruption or a CPU deadlock.  Not fixed in
1167             any Cortex-A12 cores yet.
1168           This workaround for all both errata involves setting bit[12] of the
1169           Feature Register. This bit disables an optimisation applied to a
1170           sequence of 2 instructions that use opposing condition codes.
1171
1172 config ARM_ERRATA_821420
1173         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1174         depends on CPU_V7
1175         help
1176           This option enables the workaround for the 821420 Cortex-A12
1177           (all revs) erratum. In very rare timing conditions, a sequence
1178           of VMOV to Core registers instructions, for which the second
1179           one is in the shadow of a branch or abort, can lead to a
1180           deadlock when the VMOV instructions are issued out-of-order.
1181
1182 config ARM_ERRATA_825619
1183         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1184         depends on CPU_V7
1185         help
1186           This option enables the workaround for the 825619 Cortex-A12
1187           (all revs) erratum. Within rare timing constraints, executing a
1188           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1189           and Device/Strongly-Ordered loads and stores might cause deadlock
1190
1191 config ARM_ERRATA_852421
1192         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1193         depends on CPU_V7
1194         help
1195           This option enables the workaround for the 852421 Cortex-A17
1196           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1197           execution of a DMB ST instruction might fail to properly order
1198           stores from GroupA and stores from GroupB.
1199
1200 config ARM_ERRATA_852423
1201         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1202         depends on CPU_V7
1203         help
1204           This option enables the workaround for:
1205           - Cortex-A17 852423: Execution of a sequence of instructions might
1206             lead to either a data corruption or a CPU deadlock.  Not fixed in
1207             any Cortex-A17 cores yet.
1208           This is identical to Cortex-A12 erratum 852422.  It is a separate
1209           config option from the A12 erratum due to the way errata are checked
1210           for and handled.
1211
1212 endmenu
1213
1214 source "arch/arm/common/Kconfig"
1215
1216 menu "Bus support"
1217
1218 config ISA
1219         bool
1220         help
1221           Find out whether you have ISA slots on your motherboard.  ISA is the
1222           name of a bus system, i.e. the way the CPU talks to the other stuff
1223           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1224           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1225           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1226
1227 # Select ISA DMA controller support
1228 config ISA_DMA
1229         bool
1230         select ISA_DMA_API
1231
1232 # Select ISA DMA interface
1233 config ISA_DMA_API
1234         bool
1235
1236 config PCI
1237         bool "PCI support" if MIGHT_HAVE_PCI
1238         help
1239           Find out whether you have a PCI motherboard. PCI is the name of a
1240           bus system, i.e. the way the CPU talks to the other stuff inside
1241           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1242           VESA. If you have PCI, say Y, otherwise N.
1243
1244 config PCI_DOMAINS
1245         bool
1246         depends on PCI
1247
1248 config PCI_DOMAINS_GENERIC
1249         def_bool PCI_DOMAINS
1250
1251 config PCI_NANOENGINE
1252         bool "BSE nanoEngine PCI support"
1253         depends on SA1100_NANOENGINE
1254         help
1255           Enable PCI on the BSE nanoEngine board.
1256
1257 config PCI_SYSCALL
1258         def_bool PCI
1259
1260 config PCI_HOST_ITE8152
1261         bool
1262         depends on PCI && MACH_ARMCORE
1263         default y
1264         select DMABOUNCE
1265
1266 source "drivers/pci/Kconfig"
1267
1268 source "drivers/pcmcia/Kconfig"
1269
1270 endmenu
1271
1272 menu "Kernel Features"
1273
1274 config HAVE_SMP
1275         bool
1276         help
1277           This option should be selected by machines which have an SMP-
1278           capable CPU.
1279
1280           The only effect of this option is to make the SMP-related
1281           options available to the user for configuration.
1282
1283 config SMP
1284         bool "Symmetric Multi-Processing"
1285         depends on CPU_V6K || CPU_V7
1286         depends on GENERIC_CLOCKEVENTS
1287         depends on HAVE_SMP
1288         depends on MMU || ARM_MPU
1289         select IRQ_WORK
1290         help
1291           This enables support for systems with more than one CPU. If you have
1292           a system with only one CPU, say N. If you have a system with more
1293           than one CPU, say Y.
1294
1295           If you say N here, the kernel will run on uni- and multiprocessor
1296           machines, but will use only one CPU of a multiprocessor machine. If
1297           you say Y here, the kernel will run on many, but not all,
1298           uniprocessor machines. On a uniprocessor machine, the kernel
1299           will run faster if you say N here.
1300
1301           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1302           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1303           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1304
1305           If you don't know what to do here, say N.
1306
1307 config SMP_ON_UP
1308         bool "Allow booting SMP kernel on uniprocessor systems"
1309         depends on SMP && !XIP_KERNEL && MMU
1310         default y
1311         help
1312           SMP kernels contain instructions which fail on non-SMP processors.
1313           Enabling this option allows the kernel to modify itself to make
1314           these instructions safe.  Disabling it allows about 1K of space
1315           savings.
1316
1317           If you don't know what to do here, say Y.
1318
1319 config ARM_CPU_TOPOLOGY
1320         bool "Support cpu topology definition"
1321         depends on SMP && CPU_V7
1322         default y
1323         help
1324           Support ARM cpu topology definition. The MPIDR register defines
1325           affinity between processors which is then used to describe the cpu
1326           topology of an ARM System.
1327
1328 config SCHED_MC
1329         bool "Multi-core scheduler support"
1330         depends on ARM_CPU_TOPOLOGY
1331         help
1332           Multi-core scheduler support improves the CPU scheduler's decision
1333           making when dealing with multi-core CPU chips at a cost of slightly
1334           increased overhead in some places. If unsure say N here.
1335
1336 config SCHED_SMT
1337         bool "SMT scheduler support"
1338         depends on ARM_CPU_TOPOLOGY
1339         help
1340           Improves the CPU scheduler's decision making when dealing with
1341           MultiThreading at a cost of slightly increased overhead in some
1342           places. If unsure say N here.
1343
1344 config HAVE_ARM_SCU
1345         bool
1346         help
1347           This option enables support for the ARM system coherency unit
1348
1349 config HAVE_ARM_ARCH_TIMER
1350         bool "Architected timer support"
1351         depends on CPU_V7
1352         select ARM_ARCH_TIMER
1353         select GENERIC_CLOCKEVENTS
1354         help
1355           This option enables support for the ARM architected timer
1356
1357 config HAVE_ARM_TWD
1358         bool
1359         select TIMER_OF if OF
1360         help
1361           This options enables support for the ARM timer and watchdog unit
1362
1363 config MCPM
1364         bool "Multi-Cluster Power Management"
1365         depends on CPU_V7 && SMP
1366         help
1367           This option provides the common power management infrastructure
1368           for (multi-)cluster based systems, such as big.LITTLE based
1369           systems.
1370
1371 config MCPM_QUAD_CLUSTER
1372         bool
1373         depends on MCPM
1374         help
1375           To avoid wasting resources unnecessarily, MCPM only supports up
1376           to 2 clusters by default.
1377           Platforms with 3 or 4 clusters that use MCPM must select this
1378           option to allow the additional clusters to be managed.
1379
1380 config BIG_LITTLE
1381         bool "big.LITTLE support (Experimental)"
1382         depends on CPU_V7 && SMP
1383         select MCPM
1384         help
1385           This option enables support selections for the big.LITTLE
1386           system architecture.
1387
1388 config BL_SWITCHER
1389         bool "big.LITTLE switcher support"
1390         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1391         select CPU_PM
1392         help
1393           The big.LITTLE "switcher" provides the core functionality to
1394           transparently handle transition between a cluster of A15's
1395           and a cluster of A7's in a big.LITTLE system.
1396
1397 config BL_SWITCHER_DUMMY_IF
1398         tristate "Simple big.LITTLE switcher user interface"
1399         depends on BL_SWITCHER && DEBUG_KERNEL
1400         help
1401           This is a simple and dummy char dev interface to control
1402           the big.LITTLE switcher core code.  It is meant for
1403           debugging purposes only.
1404
1405 choice
1406         prompt "Memory split"
1407         depends on MMU
1408         default VMSPLIT_3G
1409         help
1410           Select the desired split between kernel and user memory.
1411
1412           If you are not absolutely sure what you are doing, leave this
1413           option alone!
1414
1415         config VMSPLIT_3G
1416                 bool "3G/1G user/kernel split"
1417         config VMSPLIT_3G_OPT
1418                 depends on !ARM_LPAE
1419                 bool "3G/1G user/kernel split (for full 1G low memory)"
1420         config VMSPLIT_2G
1421                 bool "2G/2G user/kernel split"
1422         config VMSPLIT_1G
1423                 bool "1G/3G user/kernel split"
1424 endchoice
1425
1426 config PAGE_OFFSET
1427         hex
1428         default PHYS_OFFSET if !MMU
1429         default 0x40000000 if VMSPLIT_1G
1430         default 0x80000000 if VMSPLIT_2G
1431         default 0xB0000000 if VMSPLIT_3G_OPT
1432         default 0xC0000000
1433
1434 config NR_CPUS
1435         int "Maximum number of CPUs (2-32)"
1436         range 2 32
1437         depends on SMP
1438         default "4"
1439
1440 config HOTPLUG_CPU
1441         bool "Support for hot-pluggable CPUs"
1442         depends on SMP
1443         help
1444           Say Y here to experiment with turning CPUs off and on.  CPUs
1445           can be controlled through /sys/devices/system/cpu.
1446
1447 config ARM_PSCI
1448         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1449         depends on HAVE_ARM_SMCCC
1450         select ARM_PSCI_FW
1451         help
1452           Say Y here if you want Linux to communicate with system firmware
1453           implementing the PSCI specification for CPU-centric power
1454           management operations described in ARM document number ARM DEN
1455           0022A ("Power State Coordination Interface System Software on
1456           ARM processors").
1457
1458 # The GPIO number here must be sorted by descending number. In case of
1459 # a multiplatform kernel, we just want the highest value required by the
1460 # selected platforms.
1461 config ARCH_NR_GPIO
1462         int
1463         default 2048 if ARCH_SOCFPGA
1464         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1465                 ARCH_ZYNQ
1466         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1467                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1468         default 416 if ARCH_SUNXI
1469         default 392 if ARCH_U8500
1470         default 352 if ARCH_VT8500
1471         default 288 if ARCH_ROCKCHIP
1472         default 264 if MACH_H4700
1473         default 0
1474         help
1475           Maximum number of GPIOs in the system.
1476
1477           If unsure, leave the default value.
1478
1479 source kernel/Kconfig.preempt
1480
1481 config HZ_FIXED
1482         int
1483         default 200 if ARCH_EBSA110
1484         default 128 if SOC_AT91RM9200
1485         default 0
1486
1487 choice
1488         depends on HZ_FIXED = 0
1489         prompt "Timer frequency"
1490
1491 config HZ_100
1492         bool "100 Hz"
1493
1494 config HZ_200
1495         bool "200 Hz"
1496
1497 config HZ_250
1498         bool "250 Hz"
1499
1500 config HZ_300
1501         bool "300 Hz"
1502
1503 config HZ_500
1504         bool "500 Hz"
1505
1506 config HZ_1000
1507         bool "1000 Hz"
1508
1509 endchoice
1510
1511 config HZ
1512         int
1513         default HZ_FIXED if HZ_FIXED != 0
1514         default 100 if HZ_100
1515         default 200 if HZ_200
1516         default 250 if HZ_250
1517         default 300 if HZ_300
1518         default 500 if HZ_500
1519         default 1000
1520
1521 config SCHED_HRTICK
1522         def_bool HIGH_RES_TIMERS
1523
1524 config THUMB2_KERNEL
1525         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1526         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1527         default y if CPU_THUMBONLY
1528         select ARM_UNWIND
1529         help
1530           By enabling this option, the kernel will be compiled in
1531           Thumb-2 mode.
1532
1533           If unsure, say N.
1534
1535 config THUMB2_AVOID_R_ARM_THM_JUMP11
1536         bool "Work around buggy Thumb-2 short branch relocations in gas"
1537         depends on THUMB2_KERNEL && MODULES
1538         default y
1539         help
1540           Various binutils versions can resolve Thumb-2 branches to
1541           locally-defined, preemptible global symbols as short-range "b.n"
1542           branch instructions.
1543
1544           This is a problem, because there's no guarantee the final
1545           destination of the symbol, or any candidate locations for a
1546           trampoline, are within range of the branch.  For this reason, the
1547           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1548           relocation in modules at all, and it makes little sense to add
1549           support.
1550
1551           The symptom is that the kernel fails with an "unsupported
1552           relocation" error when loading some modules.
1553
1554           Until fixed tools are available, passing
1555           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1556           code which hits this problem, at the cost of a bit of extra runtime
1557           stack usage in some cases.
1558
1559           The problem is described in more detail at:
1560               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1561
1562           Only Thumb-2 kernels are affected.
1563
1564           Unless you are sure your tools don't have this problem, say Y.
1565
1566 config ARM_PATCH_IDIV
1567         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1568         depends on CPU_32v7 && !XIP_KERNEL
1569         default y
1570         help
1571           The ARM compiler inserts calls to __aeabi_idiv() and
1572           __aeabi_uidiv() when it needs to perform division on signed
1573           and unsigned integers. Some v7 CPUs have support for the sdiv
1574           and udiv instructions that can be used to implement those
1575           functions.
1576
1577           Enabling this option allows the kernel to modify itself to
1578           replace the first two instructions of these library functions
1579           with the sdiv or udiv plus "bx lr" instructions when the CPU
1580           it is running on supports them. Typically this will be faster
1581           and less power intensive than running the original library
1582           code to do integer division.
1583
1584 config AEABI
1585         bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1586         default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1587         help
1588           This option allows for the kernel to be compiled using the latest
1589           ARM ABI (aka EABI).  This is only useful if you are using a user
1590           space environment that is also compiled with EABI.
1591
1592           Since there are major incompatibilities between the legacy ABI and
1593           EABI, especially with regard to structure member alignment, this
1594           option also changes the kernel syscall calling convention to
1595           disambiguate both ABIs and allow for backward compatibility support
1596           (selected with CONFIG_OABI_COMPAT).
1597
1598           To use this you need GCC version 4.0.0 or later.
1599
1600 config OABI_COMPAT
1601         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1602         depends on AEABI && !THUMB2_KERNEL
1603         help
1604           This option preserves the old syscall interface along with the
1605           new (ARM EABI) one. It also provides a compatibility layer to
1606           intercept syscalls that have structure arguments which layout
1607           in memory differs between the legacy ABI and the new ARM EABI
1608           (only for non "thumb" binaries). This option adds a tiny
1609           overhead to all syscalls and produces a slightly larger kernel.
1610
1611           The seccomp filter system will not be available when this is
1612           selected, since there is no way yet to sensibly distinguish
1613           between calling conventions during filtering.
1614
1615           If you know you'll be using only pure EABI user space then you
1616           can say N here. If this option is not selected and you attempt
1617           to execute a legacy ABI binary then the result will be
1618           UNPREDICTABLE (in fact it can be predicted that it won't work
1619           at all). If in doubt say N.
1620
1621 config ARCH_HAS_HOLES_MEMORYMODEL
1622         bool
1623
1624 config ARCH_SPARSEMEM_ENABLE
1625         bool
1626
1627 config ARCH_SPARSEMEM_DEFAULT
1628         def_bool ARCH_SPARSEMEM_ENABLE
1629
1630 config ARCH_SELECT_MEMORY_MODEL
1631         def_bool ARCH_SPARSEMEM_ENABLE
1632
1633 config HAVE_ARCH_PFN_VALID
1634         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1635
1636 config HAVE_GENERIC_GUP
1637         def_bool y
1638         depends on ARM_LPAE
1639
1640 config HIGHMEM
1641         bool "High Memory Support"
1642         depends on MMU
1643         help
1644           The address space of ARM processors is only 4 Gigabytes large
1645           and it has to accommodate user address space, kernel address
1646           space as well as some memory mapped IO. That means that, if you
1647           have a large amount of physical memory and/or IO, not all of the
1648           memory can be "permanently mapped" by the kernel. The physical
1649           memory that is not permanently mapped is called "high memory".
1650
1651           Depending on the selected kernel/user memory split, minimum
1652           vmalloc space and actual amount of RAM, you may not need this
1653           option which should result in a slightly faster kernel.
1654
1655           If unsure, say n.
1656
1657 config HIGHPTE
1658         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1659         depends on HIGHMEM
1660         default y
1661         help
1662           The VM uses one page of physical memory for each page table.
1663           For systems with a lot of processes, this can use a lot of
1664           precious low memory, eventually leading to low memory being
1665           consumed by page tables.  Setting this option will allow
1666           user-space 2nd level page tables to reside in high memory.
1667
1668 config CPU_SW_DOMAIN_PAN
1669         bool "Enable use of CPU domains to implement privileged no-access"
1670         depends on MMU && !ARM_LPAE
1671         default y
1672         help
1673           Increase kernel security by ensuring that normal kernel accesses
1674           are unable to access userspace addresses.  This can help prevent
1675           use-after-free bugs becoming an exploitable privilege escalation
1676           by ensuring that magic values (such as LIST_POISON) will always
1677           fault when dereferenced.
1678
1679           CPUs with low-vector mappings use a best-efforts implementation.
1680           Their lower 1MB needs to remain accessible for the vectors, but
1681           the remainder of userspace will become appropriately inaccessible.
1682
1683 config HW_PERF_EVENTS
1684         def_bool y
1685         depends on ARM_PMU
1686
1687 config SYS_SUPPORTS_HUGETLBFS
1688        def_bool y
1689        depends on ARM_LPAE
1690
1691 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1692        def_bool y
1693        depends on ARM_LPAE
1694
1695 config ARCH_WANT_GENERAL_HUGETLB
1696         def_bool y
1697
1698 config ARM_MODULE_PLTS
1699         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1700         depends on MODULES
1701         default y
1702         help
1703           Allocate PLTs when loading modules so that jumps and calls whose
1704           targets are too far away for their relative offsets to be encoded
1705           in the instructions themselves can be bounced via veneers in the
1706           module's PLT. This allows modules to be allocated in the generic
1707           vmalloc area after the dedicated module memory area has been
1708           exhausted. The modules will use slightly more memory, but after
1709           rounding up to page size, the actual memory footprint is usually
1710           the same.
1711
1712           Disabling this is usually safe for small single-platform
1713           configurations. If unsure, say y.
1714
1715 source "mm/Kconfig"
1716
1717 config FORCE_MAX_ZONEORDER
1718         int "Maximum zone order"
1719         default "12" if SOC_AM33XX
1720         default "9" if SA1111 || ARCH_EFM32
1721         default "11"
1722         help
1723           The kernel memory allocator divides physically contiguous memory
1724           blocks into "zones", where each zone is a power of two number of
1725           pages.  This option selects the largest power of two that the kernel
1726           keeps in the memory allocator.  If you need to allocate very large
1727           blocks of physically contiguous memory, then you may need to
1728           increase this value.
1729
1730           This config option is actually maximum order plus one. For example,
1731           a value of 11 means that the largest free memory block is 2^10 pages.
1732
1733 config ALIGNMENT_TRAP
1734         bool
1735         depends on CPU_CP15_MMU
1736         default y if !ARCH_EBSA110
1737         select HAVE_PROC_CPU if PROC_FS
1738         help
1739           ARM processors cannot fetch/store information which is not
1740           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1741           address divisible by 4. On 32-bit ARM processors, these non-aligned
1742           fetch/store instructions will be emulated in software if you say
1743           here, which has a severe performance impact. This is necessary for
1744           correct operation of some network protocols. With an IP-only
1745           configuration it is safe to say N, otherwise say Y.
1746
1747 config UACCESS_WITH_MEMCPY
1748         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1749         depends on MMU
1750         default y if CPU_FEROCEON
1751         help
1752           Implement faster copy_to_user and clear_user methods for CPU
1753           cores where a 8-word STM instruction give significantly higher
1754           memory write throughput than a sequence of individual 32bit stores.
1755
1756           A possible side effect is a slight increase in scheduling latency
1757           between threads sharing the same address space if they invoke
1758           such copy operations with large buffers.
1759
1760           However, if the CPU data cache is using a write-allocate mode,
1761           this option is unlikely to provide any performance gain.
1762
1763 config SECCOMP
1764         bool
1765         prompt "Enable seccomp to safely compute untrusted bytecode"
1766         ---help---
1767           This kernel feature is useful for number crunching applications
1768           that may need to compute untrusted bytecode during their
1769           execution. By using pipes or other transports made available to
1770           the process as file descriptors supporting the read/write
1771           syscalls, it's possible to isolate those applications in
1772           their own address space using seccomp. Once seccomp is
1773           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1774           and the task is only allowed to execute a few safe syscalls
1775           defined by each seccomp mode.
1776
1777 config PARAVIRT
1778         bool "Enable paravirtualization code"
1779         help
1780           This changes the kernel so it can modify itself when it is run
1781           under a hypervisor, potentially improving performance significantly
1782           over full virtualization.
1783
1784 config PARAVIRT_TIME_ACCOUNTING
1785         bool "Paravirtual steal time accounting"
1786         select PARAVIRT
1787         default n
1788         help
1789           Select this option to enable fine granularity task steal time
1790           accounting. Time spent executing other tasks in parallel with
1791           the current vCPU is discounted from the vCPU power. To account for
1792           that, there can be a small performance impact.
1793
1794           If in doubt, say N here.
1795
1796 config XEN_DOM0
1797         def_bool y
1798         depends on XEN
1799
1800 config XEN
1801         bool "Xen guest support on ARM"
1802         depends on ARM && AEABI && OF
1803         depends on CPU_V7 && !CPU_V6
1804         depends on !GENERIC_ATOMIC64
1805         depends on MMU
1806         select ARCH_DMA_ADDR_T_64BIT
1807         select ARM_PSCI
1808         select SWIOTLB
1809         select SWIOTLB_XEN
1810         select PARAVIRT
1811         help
1812           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1813
1814 endmenu
1815
1816 menu "Boot options"
1817
1818 config USE_OF
1819         bool "Flattened Device Tree support"
1820         select IRQ_DOMAIN
1821         select OF
1822         help
1823           Include support for flattened device tree machine descriptions.
1824
1825 config ATAGS
1826         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1827         default y
1828         help
1829           This is the traditional way of passing data to the kernel at boot
1830           time. If you are solely relying on the flattened device tree (or
1831           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1832           to remove ATAGS support from your kernel binary.  If unsure,
1833           leave this to y.
1834
1835 config DEPRECATED_PARAM_STRUCT
1836         bool "Provide old way to pass kernel parameters"
1837         depends on ATAGS
1838         help
1839           This was deprecated in 2001 and announced to live on for 5 years.
1840           Some old boot loaders still use this way.
1841
1842 # Compressed boot loader in ROM.  Yes, we really want to ask about
1843 # TEXT and BSS so we preserve their values in the config files.
1844 config ZBOOT_ROM_TEXT
1845         hex "Compressed ROM boot loader base address"
1846         default "0"
1847         help
1848           The physical address at which the ROM-able zImage is to be
1849           placed in the target.  Platforms which normally make use of
1850           ROM-able zImage formats normally set this to a suitable
1851           value in their defconfig file.
1852
1853           If ZBOOT_ROM is not enabled, this has no effect.
1854
1855 config ZBOOT_ROM_BSS
1856         hex "Compressed ROM boot loader BSS address"
1857         default "0"
1858         help
1859           The base address of an area of read/write memory in the target
1860           for the ROM-able zImage which must be available while the
1861           decompressor is running. It must be large enough to hold the
1862           entire decompressed kernel plus an additional 128 KiB.
1863           Platforms which normally make use of ROM-able zImage formats
1864           normally set this to a suitable value in their defconfig file.
1865
1866           If ZBOOT_ROM is not enabled, this has no effect.
1867
1868 config ZBOOT_ROM
1869         bool "Compressed boot loader in ROM/flash"
1870         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1871         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1872         help
1873           Say Y here if you intend to execute your compressed kernel image
1874           (zImage) directly from ROM or flash.  If unsure, say N.
1875
1876 config ARM_APPENDED_DTB
1877         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1878         depends on OF
1879         help
1880           With this option, the boot code will look for a device tree binary
1881           (DTB) appended to zImage
1882           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1883
1884           This is meant as a backward compatibility convenience for those
1885           systems with a bootloader that can't be upgraded to accommodate
1886           the documented boot protocol using a device tree.
1887
1888           Beware that there is very little in terms of protection against
1889           this option being confused by leftover garbage in memory that might
1890           look like a DTB header after a reboot if no actual DTB is appended
1891           to zImage.  Do not leave this option active in a production kernel
1892           if you don't intend to always append a DTB.  Proper passing of the
1893           location into r2 of a bootloader provided DTB is always preferable
1894           to this option.
1895
1896 config ARM_ATAG_DTB_COMPAT
1897         bool "Supplement the appended DTB with traditional ATAG information"
1898         depends on ARM_APPENDED_DTB
1899         help
1900           Some old bootloaders can't be updated to a DTB capable one, yet
1901           they provide ATAGs with memory configuration, the ramdisk address,
1902           the kernel cmdline string, etc.  Such information is dynamically
1903           provided by the bootloader and can't always be stored in a static
1904           DTB.  To allow a device tree enabled kernel to be used with such
1905           bootloaders, this option allows zImage to extract the information
1906           from the ATAG list and store it at run time into the appended DTB.
1907
1908 choice
1909         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1910         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1911
1912 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1913         bool "Use bootloader kernel arguments if available"
1914         help
1915           Uses the command-line options passed by the boot loader instead of
1916           the device tree bootargs property. If the boot loader doesn't provide
1917           any, the device tree bootargs property will be used.
1918
1919 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1920         bool "Extend with bootloader kernel arguments"
1921         help
1922           The command-line arguments provided by the boot loader will be
1923           appended to the the device tree bootargs property.
1924
1925 endchoice
1926
1927 config CMDLINE
1928         string "Default kernel command string"
1929         default ""
1930         help
1931           On some architectures (EBSA110 and CATS), there is currently no way
1932           for the boot loader to pass arguments to the kernel. For these
1933           architectures, you should supply some command-line options at build
1934           time by entering them here. As a minimum, you should specify the
1935           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1936
1937 choice
1938         prompt "Kernel command line type" if CMDLINE != ""
1939         default CMDLINE_FROM_BOOTLOADER
1940         depends on ATAGS
1941
1942 config CMDLINE_FROM_BOOTLOADER
1943         bool "Use bootloader kernel arguments if available"
1944         help
1945           Uses the command-line options passed by the boot loader. If
1946           the boot loader doesn't provide any, the default kernel command
1947           string provided in CMDLINE will be used.
1948
1949 config CMDLINE_EXTEND
1950         bool "Extend bootloader kernel arguments"
1951         help
1952           The command-line arguments provided by the boot loader will be
1953           appended to the default kernel command string.
1954
1955 config CMDLINE_FORCE
1956         bool "Always use the default kernel command string"
1957         help
1958           Always use the default kernel command string, even if the boot
1959           loader passes other arguments to the kernel.
1960           This is useful if you cannot or don't want to change the
1961           command-line options your boot loader passes to the kernel.
1962 endchoice
1963
1964 config XIP_KERNEL
1965         bool "Kernel Execute-In-Place from ROM"
1966         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1967         help
1968           Execute-In-Place allows the kernel to run from non-volatile storage
1969           directly addressable by the CPU, such as NOR flash. This saves RAM
1970           space since the text section of the kernel is not loaded from flash
1971           to RAM.  Read-write sections, such as the data section and stack,
1972           are still copied to RAM.  The XIP kernel is not compressed since
1973           it has to run directly from flash, so it will take more space to
1974           store it.  The flash address used to link the kernel object files,
1975           and for storing it, is configuration dependent. Therefore, if you
1976           say Y here, you must know the proper physical address where to
1977           store the kernel image depending on your own flash memory usage.
1978
1979           Also note that the make target becomes "make xipImage" rather than
1980           "make zImage" or "make Image".  The final kernel binary to put in
1981           ROM memory will be arch/arm/boot/xipImage.
1982
1983           If unsure, say N.
1984
1985 config XIP_PHYS_ADDR
1986         hex "XIP Kernel Physical Location"
1987         depends on XIP_KERNEL
1988         default "0x00080000"
1989         help
1990           This is the physical address in your flash memory the kernel will
1991           be linked for and stored to.  This address is dependent on your
1992           own flash usage.
1993
1994 config XIP_DEFLATED_DATA
1995         bool "Store kernel .data section compressed in ROM"
1996         depends on XIP_KERNEL
1997         select ZLIB_INFLATE
1998         help
1999           Before the kernel is actually executed, its .data section has to be
2000           copied to RAM from ROM. This option allows for storing that data
2001           in compressed form and decompressed to RAM rather than merely being
2002           copied, saving some precious ROM space. A possible drawback is a
2003           slightly longer boot delay.
2004
2005 config KEXEC
2006         bool "Kexec system call (EXPERIMENTAL)"
2007         depends on (!SMP || PM_SLEEP_SMP)
2008         depends on !CPU_V7M
2009         select KEXEC_CORE
2010         help
2011           kexec is a system call that implements the ability to shutdown your
2012           current kernel, and to start another kernel.  It is like a reboot
2013           but it is independent of the system firmware.   And like a reboot
2014           you can start any kernel with it, not just Linux.
2015
2016           It is an ongoing process to be certain the hardware in a machine
2017           is properly shutdown, so do not be surprised if this code does not
2018           initially work for you.
2019
2020 config ATAGS_PROC
2021         bool "Export atags in procfs"
2022         depends on ATAGS && KEXEC
2023         default y
2024         help
2025           Should the atags used to boot the kernel be exported in an "atags"
2026           file in procfs. Useful with kexec.
2027
2028 config CRASH_DUMP
2029         bool "Build kdump crash kernel (EXPERIMENTAL)"
2030         help
2031           Generate crash dump after being started by kexec. This should
2032           be normally only set in special crash dump kernels which are
2033           loaded in the main kernel with kexec-tools into a specially
2034           reserved region and then later executed after a crash by
2035           kdump/kexec. The crash dump kernel must be compiled to a
2036           memory address not used by the main kernel
2037
2038           For more details see Documentation/kdump/kdump.txt
2039
2040 config AUTO_ZRELADDR
2041         bool "Auto calculation of the decompressed kernel image address"
2042         help
2043           ZRELADDR is the physical address where the decompressed kernel
2044           image will be placed. If AUTO_ZRELADDR is selected, the address
2045           will be determined at run-time by masking the current IP with
2046           0xf8000000. This assumes the zImage being placed in the first 128MB
2047           from start of memory.
2048
2049 config EFI_STUB
2050         bool
2051
2052 config EFI
2053         bool "UEFI runtime support"
2054         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2055         select UCS2_STRING
2056         select EFI_PARAMS_FROM_FDT
2057         select EFI_STUB
2058         select EFI_ARMSTUB
2059         select EFI_RUNTIME_WRAPPERS
2060         ---help---
2061           This option provides support for runtime services provided
2062           by UEFI firmware (such as non-volatile variables, realtime
2063           clock, and platform reset). A UEFI stub is also provided to
2064           allow the kernel to be booted as an EFI application. This
2065           is only useful for kernels that may run on systems that have
2066           UEFI firmware.
2067
2068 config DMI
2069         bool "Enable support for SMBIOS (DMI) tables"
2070         depends on EFI
2071         default y
2072         help
2073           This enables SMBIOS/DMI feature for systems.
2074
2075           This option is only useful on systems that have UEFI firmware.
2076           However, even with this option, the resultant kernel should
2077           continue to boot on existing non-UEFI platforms.
2078
2079           NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2080           i.e., the the practice of identifying the platform via DMI to
2081           decide whether certain workarounds for buggy hardware and/or
2082           firmware need to be enabled. This would require the DMI subsystem
2083           to be enabled much earlier than we do on ARM, which is non-trivial.
2084
2085 endmenu
2086
2087 menu "CPU Power Management"
2088
2089 source "drivers/cpufreq/Kconfig"
2090
2091 source "drivers/cpuidle/Kconfig"
2092
2093 endmenu
2094
2095 menu "Floating point emulation"
2096
2097 comment "At least one emulation must be selected"
2098
2099 config FPE_NWFPE
2100         bool "NWFPE math emulation"
2101         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2102         ---help---
2103           Say Y to include the NWFPE floating point emulator in the kernel.
2104           This is necessary to run most binaries. Linux does not currently
2105           support floating point hardware so you need to say Y here even if
2106           your machine has an FPA or floating point co-processor podule.
2107
2108           You may say N here if you are going to load the Acorn FPEmulator
2109           early in the bootup.
2110
2111 config FPE_NWFPE_XP
2112         bool "Support extended precision"
2113         depends on FPE_NWFPE
2114         help
2115           Say Y to include 80-bit support in the kernel floating-point
2116           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2117           Note that gcc does not generate 80-bit operations by default,
2118           so in most cases this option only enlarges the size of the
2119           floating point emulator without any good reason.
2120
2121           You almost surely want to say N here.
2122
2123 config FPE_FASTFPE
2124         bool "FastFPE math emulation (EXPERIMENTAL)"
2125         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2126         ---help---
2127           Say Y here to include the FAST floating point emulator in the kernel.
2128           This is an experimental much faster emulator which now also has full
2129           precision for the mantissa.  It does not support any exceptions.
2130           It is very simple, and approximately 3-6 times faster than NWFPE.
2131
2132           It should be sufficient for most programs.  It may be not suitable
2133           for scientific calculations, but you have to check this for yourself.
2134           If you do not feel you need a faster FP emulation you should better
2135           choose NWFPE.
2136
2137 config VFP
2138         bool "VFP-format floating point maths"
2139         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2140         help
2141           Say Y to include VFP support code in the kernel. This is needed
2142           if your hardware includes a VFP unit.
2143
2144           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2145           release notes and additional status information.
2146
2147           Say N if your target does not have VFP hardware.
2148
2149 config VFPv3
2150         bool
2151         depends on VFP
2152         default y if CPU_V7
2153
2154 config NEON
2155         bool "Advanced SIMD (NEON) Extension support"
2156         depends on VFPv3 && CPU_V7
2157         help
2158           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2159           Extension.
2160
2161 config KERNEL_MODE_NEON
2162         bool "Support for NEON in kernel mode"
2163         depends on NEON && AEABI
2164         help
2165           Say Y to include support for NEON in kernel mode.
2166
2167 endmenu
2168
2169 menu "Userspace binary formats"
2170
2171 source "fs/Kconfig.binfmt"
2172
2173 endmenu
2174
2175 menu "Power management options"
2176
2177 source "kernel/power/Kconfig"
2178
2179 config ARCH_SUSPEND_POSSIBLE
2180         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2181                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2182         def_bool y
2183
2184 config ARM_CPU_SUSPEND
2185         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2186         depends on ARCH_SUSPEND_POSSIBLE
2187
2188 config ARCH_HIBERNATION_POSSIBLE
2189         bool
2190         depends on MMU
2191         default y if ARCH_SUSPEND_POSSIBLE
2192
2193 endmenu
2194
2195 source "net/Kconfig"
2196
2197 source "drivers/Kconfig"
2198
2199 source "drivers/firmware/Kconfig"
2200
2201 source "fs/Kconfig"
2202
2203 source "arch/arm/Kconfig.debug"
2204
2205 source "security/Kconfig"
2206
2207 source "crypto/Kconfig"
2208 if CRYPTO
2209 source "arch/arm/crypto/Kconfig"
2210 endif
2211
2212 source "lib/Kconfig"
2213
2214 source "arch/arm/kvm/Kconfig"