arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAVE_CUSTOM_GPIO_H
   5         select HAVE_AOUT
   6         select HAVE_DMA_API_DEBUG
   7         select HAVE_IDE if PCI || ISA || PCMCIA
   8         select HAVE_DMA_ATTRS
   9         select HAVE_DMA_CONTIGUOUS if MMU
  10         select HAVE_MEMBLOCK
  11         select RTC_LIB
  12         select SYS_SUPPORTS_APM_EMULATION
  13         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  15         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  16         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  17         select HAVE_ARCH_KGDB
  18         select HAVE_ARCH_TRACEHOOK
  19         select HAVE_SYSCALL_TRACEPOINTS
  20         select HAVE_KPROBES if !XIP_KERNEL
  21         select HAVE_KRETPROBES if (HAVE_KPROBES)
  22         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  23         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  24         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  25         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  26         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  27         select HAVE_GENERIC_DMA_COHERENT
  28         select HAVE_DEBUG_KMEMLEAK
  29         select HAVE_KERNEL_GZIP
  30         select HAVE_KERNEL_LZO
  31         select HAVE_KERNEL_LZMA
  32         select HAVE_KERNEL_XZ
  33         select HAVE_IRQ_WORK
  34         select HAVE_PERF_EVENTS
  35         select PERF_USE_VMALLOC
  36         select HAVE_REGS_AND_STACK_ACCESS_API
  37         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  38         select HAVE_C_RECORDMCOUNT
  39         select HAVE_GENERIC_HARDIRQS
  40         select HARDIRQS_SW_RESEND
  41         select GENERIC_IRQ_PROBE
  42         select GENERIC_IRQ_SHOW
  43         select HAVE_UID16
  44         select ARCH_WANT_IPC_PARSE_VERSION
  45         select HARDIRQS_SW_RESEND
  46         select CPU_PM if (SUSPEND || CPU_IDLE)
  47         select GENERIC_PCI_IOMAP
  48         select HAVE_BPF_JIT
  49         select GENERIC_SMP_IDLE_THREAD
  50         select KTIME_SCALAR
  51         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  52         select GENERIC_STRNCPY_FROM_USER
  53         select GENERIC_STRNLEN_USER
  54         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
  55         help
  56           The ARM series is a line of low-power-consumption RISC chip designs
  57           licensed by ARM Ltd and targeted at embedded applications and
  58           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  59           manufactured, but legacy ARM-based PC hardware remains popular in
  60           Europe.  There is an ARM Linux project with a web page at
  61           <http://www.arm.linux.org.uk/>.
  62
  63 config ARM_HAS_SG_CHAIN
  64         bool
  65
  66 config NEED_SG_DMA_LENGTH
  67         bool
  68
  69 config ARM_DMA_USE_IOMMU
  70         select NEED_SG_DMA_LENGTH
  71         select ARM_HAS_SG_CHAIN
  72         bool
  73
  74 config HAVE_PWM
  75         bool
  76
  77 config MIGHT_HAVE_PCI
  78         bool
  79
  80 config SYS_SUPPORTS_APM_EMULATION
  81         bool
  82
  83 config GENERIC_GPIO
  84         bool
  85
  86 config HAVE_TCM
  87         bool
  88         select GENERIC_ALLOCATOR
  89
  90 config HAVE_PROC_CPU
  91         bool
  92
  93 config NO_IOPORT
  94         bool
  95
  96 config EISA
  97         bool
  98         ---help---
  99           The Extended Industry Standard Architecture (EISA) bus was
 100           developed as an open alternative to the IBM MicroChannel bus.
 101
 102           The EISA bus provided some of the features of the IBM MicroChannel
 103           bus while maintaining backward compatibility with cards made for
 104           the older ISA bus.  The EISA bus saw limited use between 1988 and
 105           1995 when it was made obsolete by the PCI bus.
 106
 107           Say Y here if you are building a kernel for an EISA-based machine.
 108
 109           Otherwise, say N.
 110
 111 config SBUS
 112         bool
 113
 114 config STACKTRACE_SUPPORT
 115         bool
 116         default y
 117
 118 config HAVE_LATENCYTOP_SUPPORT
 119         bool
 120         depends on !SMP
 121         default y
 122
 123 config LOCKDEP_SUPPORT
 124         bool
 125         default y
 126
 127 config TRACE_IRQFLAGS_SUPPORT
 128         bool
 129         default y
 130
 131 config RWSEM_GENERIC_SPINLOCK
 132         bool
 133         default y
 134
 135 config RWSEM_XCHGADD_ALGORITHM
 136         bool
 137
 138 config ARCH_HAS_ILOG2_U32
 139         bool
 140
 141 config ARCH_HAS_ILOG2_U64
 142         bool
 143
 144 config ARCH_HAS_CPUFREQ
 145         bool
 146         help
 147           Internal node to signify that the ARCH has CPUFREQ support
 148           and that the relevant menu configurations are displayed for
 149           it.
 150
 151 config GENERIC_HWEIGHT
 152         bool
 153         default y
 154
 155 config GENERIC_CALIBRATE_DELAY
 156         bool
 157         default y
 158
 159 config ARCH_MAY_HAVE_PC_FDC
 160         bool
 161
 162 config ZONE_DMA
 163         bool
 164
 165 config NEED_DMA_MAP_STATE
 166        def_bool y
 167
 168 config ARCH_HAS_DMA_SET_COHERENT_MASK
 169         bool
 170
 171 config GENERIC_ISA_DMA
 172         bool
 173
 174 config FIQ
 175         bool
 176
 177 config NEED_RET_TO_USER
 178         bool
 179
 180 config ARCH_MTD_XIP
 181         bool
 182
 183 config VECTORS_BASE
 184         hex
 185         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 186         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 187         default 0x00000000
 188         help
 189           The base address of exception vectors.
 190
 191 config ARM_PATCH_PHYS_VIRT
 192         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 193         default y
 194         depends on !XIP_KERNEL && MMU
 195         depends on !ARCH_REALVIEW || !SPARSEMEM
 196         help
 197           Patch phys-to-virt and virt-to-phys translation functions at
 198           boot and module load time according to the position of the
 199           kernel in system memory.
 200
 201           This can only be used with non-XIP MMU kernels where the base
 202           of physical memory is at a 16MB boundary.
 203
 204           Only disable this option if you know that you do not require
 205           this feature (eg, building a kernel for a single machine) and
 206           you need to shrink the kernel to the minimal size.
 207
 208 config NEED_MACH_GPIO_H
 209         bool
 210         help
 211           Select this when mach/gpio.h is required to provide special
 212           definitions for this platform. The need for mach/gpio.h should
 213           be avoided when possible.
 214
 215 config NEED_MACH_IO_H
 216         bool
 217         help
 218           Select this when mach/io.h is required to provide special
 219           definitions for this platform.  The need for mach/io.h should
 220           be avoided when possible.
 221
 222 config NEED_MACH_MEMORY_H
 223         bool
 224         help
 225           Select this when mach/memory.h is required to provide special
 226           definitions for this platform.  The need for mach/memory.h should
 227           be avoided when possible.
 228
 229 config PHYS_OFFSET
 230         hex "Physical address of main memory" if MMU
 231         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 232         default DRAM_BASE if !MMU
 233         help
 234           Please provide the physical address corresponding to the
 235           location of main memory in your system.
 236
 237 config GENERIC_BUG
 238         def_bool y
 239         depends on BUG
 240
 241 source "init/Kconfig"
 242
 243 source "kernel/Kconfig.freezer"
 244
 245 menu "System Type"
 246
 247 config MMU
 248         bool "MMU-based Paged Memory Management Support"
 249         default y
 250         help
 251           Select if you want MMU-based virtualised addressing space
 252           support by paged memory management. If unsure, say 'Y'.
 253
 254 #
 255 # The "ARM system type" choice list is ordered alphabetically by option
 256 # text.  Please add new entries in the option alphabetic order.
 257 #
 258 choice
 259         prompt "ARM system type"
 260         default ARCH_MULTIPLATFORM
 261
 262 config ARCH_MULTIPLATFORM
 263         bool "Allow multiple platforms to be selected"
 264         select ARM_PATCH_PHYS_VIRT
 265         select AUTO_ZRELADDR
 266         select COMMON_CLK
 267         select MULTI_IRQ_HANDLER
 268         select SPARSE_IRQ
 269         select USE_OF
 270         depends on MMU
 271
 272 config ARCH_INTEGRATOR
 273         bool "ARM Ltd. Integrator family"
 274         select ARM_AMBA
 275         select ARCH_HAS_CPUFREQ
 276         select COMMON_CLK
 277         select COMMON_CLK_VERSATILE
 278         select HAVE_TCM
 279         select ICST
 280         select GENERIC_CLOCKEVENTS
 281         select PLAT_VERSATILE
 282         select PLAT_VERSATILE_FPGA_IRQ
 283         select NEED_MACH_MEMORY_H
 284         select SPARSE_IRQ
 285         select MULTI_IRQ_HANDLER
 286         help
 287           Support for ARM's Integrator platform.
 288
 289 config ARCH_REALVIEW
 290         bool "ARM Ltd. RealView family"
 291         select ARM_AMBA
 292         select COMMON_CLK
 293         select COMMON_CLK_VERSATILE
 294         select ICST
 295         select GENERIC_CLOCKEVENTS
 296         select ARCH_WANT_OPTIONAL_GPIOLIB
 297         select PLAT_VERSATILE
 298         select PLAT_VERSATILE_CLCD
 299         select ARM_TIMER_SP804
 300         select GPIO_PL061 if GPIOLIB
 301         select NEED_MACH_MEMORY_H
 302         help
 303           This enables support for ARM Ltd RealView boards.
 304
 305 config ARCH_VERSATILE
 306         bool "ARM Ltd. Versatile family"
 307         select ARM_AMBA
 308         select ARM_VIC
 309         select CLKDEV_LOOKUP
 310         select HAVE_MACH_CLKDEV
 311         select ICST
 312         select GENERIC_CLOCKEVENTS
 313         select ARCH_WANT_OPTIONAL_GPIOLIB
 314         select PLAT_VERSATILE
 315         select PLAT_VERSATILE_CLOCK
 316         select PLAT_VERSATILE_CLCD
 317         select PLAT_VERSATILE_FPGA_IRQ
 318         select ARM_TIMER_SP804
 319         help
 320           This enables support for ARM Ltd Versatile board.
 321
 322 config ARCH_AT91
 323         bool "Atmel AT91"
 324         select ARCH_REQUIRE_GPIOLIB
 325         select HAVE_CLK
 326         select CLKDEV_LOOKUP
 327         select IRQ_DOMAIN
 328         select NEED_MACH_GPIO_H
 329         select NEED_MACH_IO_H if PCCARD
 330         help
 331           This enables support for systems based on Atmel
 332           AT91RM9200 and AT91SAM9* processors.
 333
 334 config ARCH_BCM2835
 335         bool "Broadcom BCM2835 family"
 336         select ARCH_WANT_OPTIONAL_GPIOLIB
 337         select ARM_AMBA
 338         select ARM_ERRATA_411920
 339         select ARM_TIMER_SP804
 340         select CLKDEV_LOOKUP
 341         select COMMON_CLK
 342         select CPU_V6
 343         select GENERIC_CLOCKEVENTS
 344         select MULTI_IRQ_HANDLER
 345         select SPARSE_IRQ
 346         select USE_OF
 347         help
 348           This enables support for the Broadcom BCM2835 SoC. This SoC is
 349           use in the Raspberry Pi, and Roku 2 devices.
 350
 351 config ARCH_CLPS711X
 352         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 353         select CPU_ARM720T
 354         select ARCH_USES_GETTIMEOFFSET
 355         select COMMON_CLK
 356         select CLKDEV_LOOKUP
 357         select NEED_MACH_MEMORY_H
 358         help
 359           Support for Cirrus Logic 711x/721x/731x based boards.
 360
 361 config ARCH_CNS3XXX
 362         bool "Cavium Networks CNS3XXX family"
 363         select CPU_V6K
 364         select GENERIC_CLOCKEVENTS
 365         select ARM_GIC
 366         select MIGHT_HAVE_CACHE_L2X0
 367         select MIGHT_HAVE_PCI
 368         select PCI_DOMAINS if PCI
 369         help
 370           Support for Cavium Networks CNS3XXX platform.
 371
 372 config ARCH_GEMINI
 373         bool "Cortina Systems Gemini"
 374         select CPU_FA526
 375         select ARCH_REQUIRE_GPIOLIB
 376         select ARCH_USES_GETTIMEOFFSET
 377         help
 378           Support for the Cortina Systems Gemini family SoCs
 379
 380 config ARCH_SIRF
 381         bool "CSR SiRF"
 382         select NO_IOPORT
 383         select ARCH_REQUIRE_GPIOLIB
 384         select GENERIC_CLOCKEVENTS
 385         select COMMON_CLK
 386         select GENERIC_IRQ_CHIP
 387         select MIGHT_HAVE_CACHE_L2X0
 388         select PINCTRL
 389         select PINCTRL_SIRF
 390         select USE_OF
 391         help
 392           Support for CSR SiRFprimaII/Marco/Polo platforms
 393
 394 config ARCH_EBSA110
 395         bool "EBSA-110"
 396         select CPU_SA110
 397         select ISA
 398         select NO_IOPORT
 399         select ARCH_USES_GETTIMEOFFSET
 400         select NEED_MACH_IO_H
 401         select NEED_MACH_MEMORY_H
 402         help
 403           This is an evaluation board for the StrongARM processor available
 404           from Digital. It has limited hardware on-board, including an
 405           Ethernet interface, two PCMCIA sockets, two serial ports and a
 406           parallel port.
 407
 408 config ARCH_EP93XX
 409         bool "EP93xx-based"
 410         select CPU_ARM920T
 411         select ARM_AMBA
 412         select ARM_VIC
 413         select CLKDEV_LOOKUP
 414         select ARCH_REQUIRE_GPIOLIB
 415         select ARCH_HAS_HOLES_MEMORYMODEL
 416         select ARCH_USES_GETTIMEOFFSET
 417         select NEED_MACH_MEMORY_H
 418         help
 419           This enables support for the Cirrus EP93xx series of CPUs.
 420
 421 config ARCH_FOOTBRIDGE
 422         bool "FootBridge"
 423         select CPU_SA110
 424         select FOOTBRIDGE
 425         select GENERIC_CLOCKEVENTS
 426         select HAVE_IDE
 427         select NEED_MACH_IO_H if !MMU
 428         select NEED_MACH_MEMORY_H
 429         help
 430           Support for systems based on the DC21285 companion chip
 431           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 432
 433 config ARCH_MXC
 434         bool "Freescale MXC/iMX-based"
 435         select GENERIC_CLOCKEVENTS
 436         select ARCH_REQUIRE_GPIOLIB
 437         select CLKDEV_LOOKUP
 438         select CLKSRC_MMIO
 439         select GENERIC_IRQ_CHIP
 440         select MULTI_IRQ_HANDLER
 441         select SPARSE_IRQ
 442         select USE_OF
 443         help
 444           Support for Freescale MXC/iMX-based family of processors
 445
 446 config ARCH_MXS
 447         bool "Freescale MXS-based"
 448         select GENERIC_CLOCKEVENTS
 449         select ARCH_REQUIRE_GPIOLIB
 450         select CLKDEV_LOOKUP
 451         select CLKSRC_MMIO
 452         select COMMON_CLK
 453         select HAVE_CLK_PREPARE
 454         select MULTI_IRQ_HANDLER
 455         select PINCTRL
 456         select SPARSE_IRQ
 457         select USE_OF
 458         help
 459           Support for Freescale MXS-based family of processors
 460
 461 config ARCH_NETX
 462         bool "Hilscher NetX based"
 463         select CLKSRC_MMIO
 464         select CPU_ARM926T
 465         select ARM_VIC
 466         select GENERIC_CLOCKEVENTS
 467         help
 468           This enables support for systems based on the Hilscher NetX Soc
 469
 470 config ARCH_H720X
 471         bool "Hynix HMS720x-based"
 472         select CPU_ARM720T
 473         select ISA_DMA_API
 474         select ARCH_USES_GETTIMEOFFSET
 475         help
 476           This enables support for systems based on the Hynix HMS720x
 477
 478 config ARCH_IOP13XX
 479         bool "IOP13xx-based"
 480         depends on MMU
 481         select CPU_XSC3
 482         select PLAT_IOP
 483         select PCI
 484         select ARCH_SUPPORTS_MSI
 485         select VMSPLIT_1G
 486         select NEED_MACH_MEMORY_H
 487         select NEED_RET_TO_USER
 488         help
 489           Support for Intel's IOP13XX (XScale) family of processors.
 490
 491 config ARCH_IOP32X
 492         bool "IOP32x-based"
 493         depends on MMU
 494         select CPU_XSCALE
 495         select NEED_MACH_GPIO_H
 496         select NEED_MACH_IO_H
 497         select NEED_RET_TO_USER
 498         select PLAT_IOP
 499         select PCI
 500         select ARCH_REQUIRE_GPIOLIB
 501         help
 502           Support for Intel's 80219 and IOP32X (XScale) family of
 503           processors.
 504
 505 config ARCH_IOP33X
 506         bool "IOP33x-based"
 507         depends on MMU
 508         select CPU_XSCALE
 509         select NEED_MACH_GPIO_H
 510         select NEED_MACH_IO_H
 511         select NEED_RET_TO_USER
 512         select PLAT_IOP
 513         select PCI
 514         select ARCH_REQUIRE_GPIOLIB
 515         help
 516           Support for Intel's IOP33X (XScale) family of processors.
 517
 518 config ARCH_IXP4XX
 519         bool "IXP4xx-based"
 520         depends on MMU
 521         select ARCH_HAS_DMA_SET_COHERENT_MASK
 522         select CLKSRC_MMIO
 523         select CPU_XSCALE
 524         select ARCH_REQUIRE_GPIOLIB
 525         select GENERIC_CLOCKEVENTS
 526         select MIGHT_HAVE_PCI
 527         select NEED_MACH_IO_H
 528         select DMABOUNCE if PCI
 529         help
 530           Support for Intel's IXP4XX (XScale) family of processors.
 531
 532 config ARCH_DOVE
 533         bool "Marvell Dove"
 534         select CPU_V7
 535         select ARCH_REQUIRE_GPIOLIB
 536         select GENERIC_CLOCKEVENTS
 537         select MIGHT_HAVE_PCI
 538         select PLAT_ORION_LEGACY
 539         select USB_ARCH_HAS_EHCI
 540         help
 541           Support for the Marvell Dove SoC 88AP510
 542
 543 config ARCH_KIRKWOOD
 544         bool "Marvell Kirkwood"
 545         select CPU_FEROCEON
 546         select PCI
 547         select ARCH_REQUIRE_GPIOLIB
 548         select GENERIC_CLOCKEVENTS
 549         select PLAT_ORION_LEGACY
 550         help
 551           Support for the following Marvell Kirkwood series SoCs:
 552           88F6180, 88F6192 and 88F6281.
 553
 554 config ARCH_LPC32XX
 555         bool "NXP LPC32XX"
 556         select CLKSRC_MMIO
 557         select CPU_ARM926T
 558         select ARCH_REQUIRE_GPIOLIB
 559         select HAVE_IDE
 560         select ARM_AMBA
 561         select USB_ARCH_HAS_OHCI
 562         select CLKDEV_LOOKUP
 563         select GENERIC_CLOCKEVENTS
 564         select USE_OF
 565         select HAVE_PWM
 566         help
 567           Support for the NXP LPC32XX family of processors
 568
 569 config ARCH_MV78XX0
 570         bool "Marvell MV78xx0"
 571         select CPU_FEROCEON
 572         select PCI
 573         select ARCH_REQUIRE_GPIOLIB
 574         select GENERIC_CLOCKEVENTS
 575         select PLAT_ORION_LEGACY
 576         help
 577           Support for the following Marvell MV78xx0 series SoCs:
 578           MV781x0, MV782x0.
 579
 580 config ARCH_ORION5X
 581         bool "Marvell Orion"
 582         depends on MMU
 583         select CPU_FEROCEON
 584         select PCI
 585         select ARCH_REQUIRE_GPIOLIB
 586         select GENERIC_CLOCKEVENTS
 587         select PLAT_ORION_LEGACY
 588         help
 589           Support for the following Marvell Orion 5x series SoCs:
 590           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 591           Orion-2 (5281), Orion-1-90 (6183).
 592
 593 config ARCH_MMP
 594         bool "Marvell PXA168/910/MMP2"
 595         depends on MMU
 596         select ARCH_REQUIRE_GPIOLIB
 597         select CLKDEV_LOOKUP
 598         select GENERIC_CLOCKEVENTS
 599         select GPIO_PXA
 600         select IRQ_DOMAIN
 601         select PLAT_PXA
 602         select SPARSE_IRQ
 603         select GENERIC_ALLOCATOR
 604         select NEED_MACH_GPIO_H
 605         help
 606           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 607
 608 config ARCH_KS8695
 609         bool "Micrel/Kendin KS8695"
 610         select CPU_ARM922T
 611         select ARCH_REQUIRE_GPIOLIB
 612         select NEED_MACH_MEMORY_H
 613         select CLKSRC_MMIO
 614         select GENERIC_CLOCKEVENTS
 615         help
 616           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 617           System-on-Chip devices.
 618
 619 config ARCH_W90X900
 620         bool "Nuvoton W90X900 CPU"
 621         select CPU_ARM926T
 622         select ARCH_REQUIRE_GPIOLIB
 623         select CLKDEV_LOOKUP
 624         select CLKSRC_MMIO
 625         select GENERIC_CLOCKEVENTS
 626         help
 627           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 628           At present, the w90x900 has been renamed nuc900, regarding
 629           the ARM series product line, you can login the following
 630           link address to know more.
 631
 632           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 633                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 634
 635 config ARCH_TEGRA
 636         bool "NVIDIA Tegra"
 637         select CLKDEV_LOOKUP
 638         select CLKSRC_MMIO
 639         select GENERIC_CLOCKEVENTS
 640         select GENERIC_GPIO
 641         select HAVE_CLK
 642         select HAVE_SMP
 643         select MIGHT_HAVE_CACHE_L2X0
 644         select ARCH_HAS_CPUFREQ
 645         select USE_OF
 646         select COMMON_CLK
 647         help
 648           This enables support for NVIDIA Tegra based systems (Tegra APX,
 649           Tegra 6xx and Tegra 2 series).
 650
 651 config ARCH_PXA
 652         bool "PXA2xx/PXA3xx-based"
 653         depends on MMU
 654         select ARCH_MTD_XIP
 655         select ARCH_HAS_CPUFREQ
 656         select CLKDEV_LOOKUP
 657         select CLKSRC_MMIO
 658         select ARCH_REQUIRE_GPIOLIB
 659         select GENERIC_CLOCKEVENTS
 660         select GPIO_PXA
 661         select PLAT_PXA
 662         select SPARSE_IRQ
 663         select AUTO_ZRELADDR
 664         select MULTI_IRQ_HANDLER
 665         select ARM_CPU_SUSPEND if PM
 666         select HAVE_IDE
 667         select NEED_MACH_GPIO_H
 668         help
 669           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 670
 671 config ARCH_MSM
 672         bool "Qualcomm MSM"
 673         select HAVE_CLK
 674         select GENERIC_CLOCKEVENTS
 675         select ARCH_REQUIRE_GPIOLIB
 676         select CLKDEV_LOOKUP
 677         help
 678           Support for Qualcomm MSM/QSD based systems.  This runs on the
 679           apps processor of the MSM/QSD and depends on a shared memory
 680           interface to the modem processor which runs the baseband
 681           stack and controls some vital subsystems
 682           (clock and power control, etc).
 683
 684 config ARCH_SHMOBILE
 685         bool "Renesas SH-Mobile / R-Mobile"
 686         select HAVE_CLK
 687         select CLKDEV_LOOKUP
 688         select HAVE_MACH_CLKDEV
 689         select HAVE_SMP
 690         select GENERIC_CLOCKEVENTS
 691         select MIGHT_HAVE_CACHE_L2X0
 692         select NO_IOPORT
 693         select SPARSE_IRQ
 694         select MULTI_IRQ_HANDLER
 695         select PM_GENERIC_DOMAINS if PM
 696         select NEED_MACH_MEMORY_H
 697         help
 698           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 699
 700 config ARCH_RPC
 701         bool "RiscPC"
 702         select ARCH_ACORN
 703         select FIQ
 704         select ARCH_MAY_HAVE_PC_FDC
 705         select HAVE_PATA_PLATFORM
 706         select ISA_DMA_API
 707         select NO_IOPORT
 708         select ARCH_SPARSEMEM_ENABLE
 709         select ARCH_USES_GETTIMEOFFSET
 710         select HAVE_IDE
 711         select NEED_MACH_IO_H
 712         select NEED_MACH_MEMORY_H
 713         help
 714           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 715           CD-ROM interface, serial and parallel port, and the floppy drive.
 716
 717 config ARCH_SA1100
 718         bool "SA1100-based"
 719         select CLKSRC_MMIO
 720         select CPU_SA1100
 721         select ISA
 722         select ARCH_SPARSEMEM_ENABLE
 723         select ARCH_MTD_XIP
 724         select ARCH_HAS_CPUFREQ
 725         select CPU_FREQ
 726         select GENERIC_CLOCKEVENTS
 727         select CLKDEV_LOOKUP
 728         select ARCH_REQUIRE_GPIOLIB
 729         select HAVE_IDE
 730         select NEED_MACH_GPIO_H
 731         select NEED_MACH_MEMORY_H
 732         select SPARSE_IRQ
 733         help
 734           Support for StrongARM 11x0 based boards.
 735
 736 config ARCH_S3C24XX
 737         bool "Samsung S3C24XX SoCs"
 738         select GENERIC_GPIO
 739         select ARCH_HAS_CPUFREQ
 740         select HAVE_CLK
 741         select CLKDEV_LOOKUP
 742         select ARCH_USES_GETTIMEOFFSET
 743         select HAVE_S3C2410_I2C if I2C
 744         select HAVE_S3C_RTC if RTC_CLASS
 745         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 746         select NEED_MACH_GPIO_H
 747         select NEED_MACH_IO_H
 748         help
 749           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 750           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 751           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 752           Samsung SMDK2410 development board (and derivatives).
 753
 754 config ARCH_S3C64XX
 755         bool "Samsung S3C64XX"
 756         select PLAT_SAMSUNG
 757         select CPU_V6
 758         select ARM_VIC
 759         select HAVE_CLK
 760         select HAVE_TCM
 761         select CLKDEV_LOOKUP
 762         select NO_IOPORT
 763         select ARCH_USES_GETTIMEOFFSET
 764         select ARCH_HAS_CPUFREQ
 765         select ARCH_REQUIRE_GPIOLIB
 766         select SAMSUNG_CLKSRC
 767         select SAMSUNG_IRQ_VIC_TIMER
 768         select S3C_GPIO_TRACK
 769         select S3C_DEV_NAND
 770         select USB_ARCH_HAS_OHCI
 771         select SAMSUNG_GPIOLIB_4BIT
 772         select HAVE_S3C2410_I2C if I2C
 773         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 774         select NEED_MACH_GPIO_H
 775         help
 776           Samsung S3C64XX series based systems
 777
 778 config ARCH_S5P64X0
 779         bool "Samsung S5P6440 S5P6450"
 780         select CPU_V6
 781         select GENERIC_GPIO
 782         select HAVE_CLK
 783         select CLKDEV_LOOKUP
 784         select CLKSRC_MMIO
 785         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 786         select GENERIC_CLOCKEVENTS
 787         select HAVE_S3C2410_I2C if I2C
 788         select HAVE_S3C_RTC if RTC_CLASS
 789         select NEED_MACH_GPIO_H
 790         help
 791           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 792           SMDK6450.
 793
 794 config ARCH_S5PC100
 795         bool "Samsung S5PC100"
 796         select GENERIC_GPIO
 797         select HAVE_CLK
 798         select CLKDEV_LOOKUP
 799         select CPU_V7
 800         select ARCH_USES_GETTIMEOFFSET
 801         select HAVE_S3C2410_I2C if I2C
 802         select HAVE_S3C_RTC if RTC_CLASS
 803         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 804         select NEED_MACH_GPIO_H
 805         help
 806           Samsung S5PC100 series based systems
 807
 808 config ARCH_S5PV210
 809         bool "Samsung S5PV210/S5PC110"
 810         select CPU_V7
 811         select ARCH_SPARSEMEM_ENABLE
 812         select ARCH_HAS_HOLES_MEMORYMODEL
 813         select GENERIC_GPIO
 814         select HAVE_CLK
 815         select CLKDEV_LOOKUP
 816         select CLKSRC_MMIO
 817         select ARCH_HAS_CPUFREQ
 818         select GENERIC_CLOCKEVENTS
 819         select HAVE_S3C2410_I2C if I2C
 820         select HAVE_S3C_RTC if RTC_CLASS
 821         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 822         select NEED_MACH_GPIO_H
 823         select NEED_MACH_MEMORY_H
 824         help
 825           Samsung S5PV210/S5PC110 series based systems
 826
 827 config ARCH_EXYNOS
 828         bool "SAMSUNG EXYNOS"
 829         select CPU_V7
 830         select ARCH_SPARSEMEM_ENABLE
 831         select ARCH_HAS_HOLES_MEMORYMODEL
 832         select GENERIC_GPIO
 833         select HAVE_CLK
 834         select CLKDEV_LOOKUP
 835         select ARCH_HAS_CPUFREQ
 836         select GENERIC_CLOCKEVENTS
 837         select HAVE_S3C_RTC if RTC_CLASS
 838         select HAVE_S3C2410_I2C if I2C
 839         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 840         select NEED_MACH_GPIO_H
 841         select NEED_MACH_MEMORY_H
 842         help
 843           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 844
 845 config ARCH_SHARK
 846         bool "Shark"
 847         select CPU_SA110
 848         select ISA
 849         select ISA_DMA
 850         select ZONE_DMA
 851         select PCI
 852         select ARCH_USES_GETTIMEOFFSET
 853         select NEED_MACH_MEMORY_H
 854         help
 855           Support for the StrongARM based Digital DNARD machine, also known
 856           as "Shark" (<http://www.shark-linux.de/shark.html>).
 857
 858 config ARCH_U300
 859         bool "ST-Ericsson U300 Series"
 860         depends on MMU
 861         select CLKSRC_MMIO
 862         select CPU_ARM926T
 863         select HAVE_TCM
 864         select ARM_AMBA
 865         select ARM_PATCH_PHYS_VIRT
 866         select ARM_VIC
 867         select GENERIC_CLOCKEVENTS
 868         select CLKDEV_LOOKUP
 869         select COMMON_CLK
 870         select GENERIC_GPIO
 871         select ARCH_REQUIRE_GPIOLIB
 872         select SPARSE_IRQ
 873         help
 874           Support for ST-Ericsson U300 series mobile platforms.
 875
 876 config ARCH_U8500
 877         bool "ST-Ericsson U8500 Series"
 878         depends on MMU
 879         select CPU_V7
 880         select ARM_AMBA
 881         select GENERIC_CLOCKEVENTS
 882         select CLKDEV_LOOKUP
 883         select ARCH_REQUIRE_GPIOLIB
 884         select ARCH_HAS_CPUFREQ
 885         select HAVE_SMP
 886         select MIGHT_HAVE_CACHE_L2X0
 887         help
 888           Support for ST-Ericsson's Ux500 architecture
 889
 890 config ARCH_NOMADIK
 891         bool "STMicroelectronics Nomadik"
 892         select ARM_AMBA
 893         select ARM_VIC
 894         select CPU_ARM926T
 895         select COMMON_CLK
 896         select GENERIC_CLOCKEVENTS
 897         select PINCTRL
 898         select PINCTRL_STN8815
 899         select MIGHT_HAVE_CACHE_L2X0
 900         select ARCH_REQUIRE_GPIOLIB
 901         help
 902           Support for the Nomadik platform by ST-Ericsson
 903
 904 config ARCH_DAVINCI
 905         bool "TI DaVinci"
 906         select GENERIC_CLOCKEVENTS
 907         select ARCH_REQUIRE_GPIOLIB
 908         select ZONE_DMA
 909         select HAVE_IDE
 910         select CLKDEV_LOOKUP
 911         select GENERIC_ALLOCATOR
 912         select GENERIC_IRQ_CHIP
 913         select ARCH_HAS_HOLES_MEMORYMODEL
 914         select NEED_MACH_GPIO_H
 915         help
 916           Support for TI's DaVinci platform.
 917
 918 config ARCH_OMAP
 919         bool "TI OMAP"
 920         depends on MMU
 921         select HAVE_CLK
 922         select ARCH_REQUIRE_GPIOLIB
 923         select ARCH_HAS_CPUFREQ
 924         select CLKSRC_MMIO
 925         select GENERIC_CLOCKEVENTS
 926         select ARCH_HAS_HOLES_MEMORYMODEL
 927         select NEED_MACH_GPIO_H
 928         help
 929           Support for TI's OMAP platform (OMAP1/2/3/4).
 930
 931 config PLAT_SPEAR
 932         bool "ST SPEAr"
 933         select ARM_AMBA
 934         select ARCH_REQUIRE_GPIOLIB
 935         select CLKDEV_LOOKUP
 936         select COMMON_CLK
 937         select CLKSRC_MMIO
 938         select GENERIC_CLOCKEVENTS
 939         select HAVE_CLK
 940         help
 941           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 942
 943 config ARCH_VT8500
 944         bool "VIA/WonderMedia 85xx"
 945         select CPU_ARM926T
 946         select GENERIC_GPIO
 947         select ARCH_HAS_CPUFREQ
 948         select GENERIC_CLOCKEVENTS
 949         select ARCH_REQUIRE_GPIOLIB
 950         select USE_OF
 951         select COMMON_CLK
 952         select HAVE_CLK
 953         select CLKDEV_LOOKUP
 954         help
 955           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 956
 957 config ARCH_ZYNQ
 958         bool "Xilinx Zynq ARM Cortex A9 Platform"
 959         select CPU_V7
 960         select GENERIC_CLOCKEVENTS
 961         select CLKDEV_LOOKUP
 962         select ARM_GIC
 963         select ARM_AMBA
 964         select ICST
 965         select MIGHT_HAVE_CACHE_L2X0
 966         select USE_OF
 967         help
 968           Support for Xilinx Zynq ARM Cortex A9 Platform
 969 endchoice
 970
 971 menu "Multiple platform selection"
 972         depends on ARCH_MULTIPLATFORM
 973
 974 comment "CPU Core family selection"
 975
 976 config ARCH_MULTI_V4
 977         bool "ARMv4 based platforms (FA526, StrongARM)"
 978         select ARCH_MULTI_V4_V5
 979         depends on !ARCH_MULTI_V6_V7
 980
 981 config ARCH_MULTI_V4T
 982         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 983         select ARCH_MULTI_V4_V5
 984         depends on !ARCH_MULTI_V6_V7
 985
 986 config ARCH_MULTI_V5
 987         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 988         select ARCH_MULTI_V4_V5
 989         depends on !ARCH_MULTI_V6_V7
 990
 991 config ARCH_MULTI_V4_V5
 992         bool
 993
 994 config ARCH_MULTI_V6
 995         bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
 996         select CPU_V6
 997         select ARCH_MULTI_V6_V7
 998
 999 config ARCH_MULTI_V7
1000         bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1001         select CPU_V7
1002         select ARCH_VEXPRESS
1003         default y
1004         select ARCH_MULTI_V6_V7
1005
1006 config ARCH_MULTI_V6_V7
1007         bool
1008
1009 config ARCH_MULTI_CPU_AUTO
1010         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1011         select ARCH_MULTI_V5
1012
1013 endmenu
1014
1015 #
1016 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1017 # Kconfigs may be included either alphabetically (according to the
1018 # plat- suffix) or along side the corresponding mach-* source.
1019 #
1020 source "arch/arm/mach-mvebu/Kconfig"
1021
1022 source "arch/arm/mach-at91/Kconfig"
1023
1024 source "arch/arm/mach-clps711x/Kconfig"
1025
1026 source "arch/arm/mach-cns3xxx/Kconfig"
1027
1028 source "arch/arm/mach-davinci/Kconfig"
1029
1030 source "arch/arm/mach-dove/Kconfig"
1031
1032 source "arch/arm/mach-ep93xx/Kconfig"
1033
1034 source "arch/arm/mach-footbridge/Kconfig"
1035
1036 source "arch/arm/mach-gemini/Kconfig"
1037
1038 source "arch/arm/mach-h720x/Kconfig"
1039
1040 source "arch/arm/mach-highbank/Kconfig"
1041
1042 source "arch/arm/mach-integrator/Kconfig"
1043
1044 source "arch/arm/mach-iop32x/Kconfig"
1045
1046 source "arch/arm/mach-iop33x/Kconfig"
1047
1048 source "arch/arm/mach-iop13xx/Kconfig"
1049
1050 source "arch/arm/mach-ixp4xx/Kconfig"
1051
1052 source "arch/arm/mach-kirkwood/Kconfig"
1053
1054 source "arch/arm/mach-ks8695/Kconfig"
1055
1056 source "arch/arm/mach-msm/Kconfig"
1057
1058 source "arch/arm/mach-mv78xx0/Kconfig"
1059
1060 source "arch/arm/plat-mxc/Kconfig"
1061
1062 source "arch/arm/mach-mxs/Kconfig"
1063
1064 source "arch/arm/mach-netx/Kconfig"
1065
1066 source "arch/arm/mach-nomadik/Kconfig"
1067 source "arch/arm/plat-nomadik/Kconfig"
1068
1069 source "arch/arm/plat-omap/Kconfig"
1070
1071 source "arch/arm/mach-omap1/Kconfig"
1072
1073 source "arch/arm/mach-omap2/Kconfig"
1074
1075 source "arch/arm/mach-orion5x/Kconfig"
1076
1077 source "arch/arm/mach-picoxcell/Kconfig"
1078
1079 source "arch/arm/mach-pxa/Kconfig"
1080 source "arch/arm/plat-pxa/Kconfig"
1081
1082 source "arch/arm/mach-mmp/Kconfig"
1083
1084 source "arch/arm/mach-realview/Kconfig"
1085
1086 source "arch/arm/mach-sa1100/Kconfig"
1087
1088 source "arch/arm/plat-samsung/Kconfig"
1089 source "arch/arm/plat-s3c24xx/Kconfig"
1090
1091 source "arch/arm/mach-socfpga/Kconfig"
1092
1093 source "arch/arm/plat-spear/Kconfig"
1094
1095 source "arch/arm/mach-s3c24xx/Kconfig"
1096 if ARCH_S3C24XX
1097 source "arch/arm/mach-s3c2412/Kconfig"
1098 source "arch/arm/mach-s3c2440/Kconfig"
1099 endif
1100
1101 if ARCH_S3C64XX
1102 source "arch/arm/mach-s3c64xx/Kconfig"
1103 endif
1104
1105 source "arch/arm/mach-s5p64x0/Kconfig"
1106
1107 source "arch/arm/mach-s5pc100/Kconfig"
1108
1109 source "arch/arm/mach-s5pv210/Kconfig"
1110
1111 source "arch/arm/mach-exynos/Kconfig"
1112
1113 source "arch/arm/mach-shmobile/Kconfig"
1114
1115 source "arch/arm/mach-prima2/Kconfig"
1116
1117 source "arch/arm/mach-tegra/Kconfig"
1118
1119 source "arch/arm/mach-u300/Kconfig"
1120
1121 source "arch/arm/mach-ux500/Kconfig"
1122
1123 source "arch/arm/mach-versatile/Kconfig"
1124
1125 source "arch/arm/mach-vexpress/Kconfig"
1126 source "arch/arm/plat-versatile/Kconfig"
1127
1128 source "arch/arm/mach-w90x900/Kconfig"
1129
1130 # Definitions to make life easier
1131 config ARCH_ACORN
1132         bool
1133
1134 config PLAT_IOP
1135         bool
1136         select GENERIC_CLOCKEVENTS
1137
1138 config PLAT_ORION
1139         bool
1140         select CLKSRC_MMIO
1141         select GENERIC_IRQ_CHIP
1142         select IRQ_DOMAIN
1143         select COMMON_CLK
1144
1145 config PLAT_ORION_LEGACY
1146         bool
1147         select PLAT_ORION
1148
1149 config PLAT_PXA
1150         bool
1151
1152 config PLAT_VERSATILE
1153         bool
1154
1155 config ARM_TIMER_SP804
1156         bool
1157         select CLKSRC_MMIO
1158         select HAVE_SCHED_CLOCK
1159
1160 source arch/arm/mm/Kconfig
1161
1162 config ARM_NR_BANKS
1163         int
1164         default 16 if ARCH_EP93XX
1165         default 8
1166
1167 config IWMMXT
1168         bool "Enable iWMMXt support"
1169         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1170         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1171         help
1172           Enable support for iWMMXt context switching at run time if
1173           running on a CPU that supports it.
1174
1175 config XSCALE_PMU
1176         bool
1177         depends on CPU_XSCALE
1178         default y
1179
1180 config MULTI_IRQ_HANDLER
1181         bool
1182         help
1183           Allow each machine to specify it's own IRQ handler at run time.
1184
1185 if !MMU
1186 source "arch/arm/Kconfig-nommu"
1187 endif
1188
1189 config ARM_ERRATA_326103
1190         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1191         depends on CPU_V6
1192         help
1193           Executing a SWP instruction to read-only memory does not set bit 11
1194           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1195           treat the access as a read, preventing a COW from occurring and
1196           causing the faulting task to livelock.
1197
1198 config ARM_ERRATA_411920
1199         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1200         depends on CPU_V6 || CPU_V6K
1201         help
1202           Invalidation of the Instruction Cache operation can
1203           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1204           It does not affect the MPCore. This option enables the ARM Ltd.
1205           recommended workaround.
1206
1207 config ARM_ERRATA_430973
1208         bool "ARM errata: Stale prediction on replaced interworking branch"
1209         depends on CPU_V7
1210         help
1211           This option enables the workaround for the 430973 Cortex-A8
1212           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1213           interworking branch is replaced with another code sequence at the
1214           same virtual address, whether due to self-modifying code or virtual
1215           to physical address re-mapping, Cortex-A8 does not recover from the
1216           stale interworking branch prediction. This results in Cortex-A8
1217           executing the new code sequence in the incorrect ARM or Thumb state.
1218           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1219           and also flushes the branch target cache at every context switch.
1220           Note that setting specific bits in the ACTLR register may not be
1221           available in non-secure mode.
1222
1223 config ARM_ERRATA_458693
1224         bool "ARM errata: Processor deadlock when a false hazard is created"
1225         depends on CPU_V7
1226         help
1227           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1228           erratum. For very specific sequences of memory operations, it is
1229           possible for a hazard condition intended for a cache line to instead
1230           be incorrectly associated with a different cache line. This false
1231           hazard might then cause a processor deadlock. The workaround enables
1232           the L1 caching of the NEON accesses and disables the PLD instruction
1233           in the ACTLR register. Note that setting specific bits in the ACTLR
1234           register may not be available in non-secure mode.
1235
1236 config ARM_ERRATA_460075
1237         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1238         depends on CPU_V7
1239         help
1240           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1241           erratum. Any asynchronous access to the L2 cache may encounter a
1242           situation in which recent store transactions to the L2 cache are lost
1243           and overwritten with stale memory contents from external memory. The
1244           workaround disables the write-allocate mode for the L2 cache via the
1245           ACTLR register. Note that setting specific bits in the ACTLR register
1246           may not be available in non-secure mode.
1247
1248 config ARM_ERRATA_742230
1249         bool "ARM errata: DMB operation may be faulty"
1250         depends on CPU_V7 && SMP
1251         help
1252           This option enables the workaround for the 742230 Cortex-A9
1253           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1254           between two write operations may not ensure the correct visibility
1255           ordering of the two writes. This workaround sets a specific bit in
1256           the diagnostic register of the Cortex-A9 which causes the DMB
1257           instruction to behave as a DSB, ensuring the correct behaviour of
1258           the two writes.
1259
1260 config ARM_ERRATA_742231
1261         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1262         depends on CPU_V7 && SMP
1263         help
1264           This option enables the workaround for the 742231 Cortex-A9
1265           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1266           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1267           accessing some data located in the same cache line, may get corrupted
1268           data due to bad handling of the address hazard when the line gets
1269           replaced from one of the CPUs at the same time as another CPU is
1270           accessing it. This workaround sets specific bits in the diagnostic
1271           register of the Cortex-A9 which reduces the linefill issuing
1272           capabilities of the processor.
1273
1274 config PL310_ERRATA_588369
1275         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1276         depends on CACHE_L2X0
1277         help
1278            The PL310 L2 cache controller implements three types of Clean &
1279            Invalidate maintenance operations: by Physical Address
1280            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1281            They are architecturally defined to behave as the execution of a
1282            clean operation followed immediately by an invalidate operation,
1283            both performing to the same memory location. This functionality
1284            is not correctly implemented in PL310 as clean lines are not
1285            invalidated as a result of these operations.
1286
1287 config ARM_ERRATA_720789
1288         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1289         depends on CPU_V7
1290         help
1291           This option enables the workaround for the 720789 Cortex-A9 (prior to
1292           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1293           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1294           As a consequence of this erratum, some TLB entries which should be
1295           invalidated are not, resulting in an incoherency in the system page
1296           tables. The workaround changes the TLB flushing routines to invalidate
1297           entries regardless of the ASID.
1298
1299 config PL310_ERRATA_727915
1300         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1301         depends on CACHE_L2X0
1302         help
1303           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1304           operation (offset 0x7FC). This operation runs in background so that
1305           PL310 can handle normal accesses while it is in progress. Under very
1306           rare circumstances, due to this erratum, write data can be lost when
1307           PL310 treats a cacheable write transaction during a Clean &
1308           Invalidate by Way operation.
1309
1310 config ARM_ERRATA_743622
1311         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1312         depends on CPU_V7
1313         help
1314           This option enables the workaround for the 743622 Cortex-A9
1315           (r2p*) erratum. Under very rare conditions, a faulty
1316           optimisation in the Cortex-A9 Store Buffer may lead to data
1317           corruption. This workaround sets a specific bit in the diagnostic
1318           register of the Cortex-A9 which disables the Store Buffer
1319           optimisation, preventing the defect from occurring. This has no
1320           visible impact on the overall performance or power consumption of the
1321           processor.
1322
1323 config ARM_ERRATA_751472
1324         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1325         depends on CPU_V7
1326         help
1327           This option enables the workaround for the 751472 Cortex-A9 (prior
1328           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1329           completion of a following broadcasted operation if the second
1330           operation is received by a CPU before the ICIALLUIS has completed,
1331           potentially leading to corrupted entries in the cache or TLB.
1332
1333 config PL310_ERRATA_753970
1334         bool "PL310 errata: cache sync operation may be faulty"
1335         depends on CACHE_PL310
1336         help
1337           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1338
1339           Under some condition the effect of cache sync operation on
1340           the store buffer still remains when the operation completes.
1341           This means that the store buffer is always asked to drain and
1342           this prevents it from merging any further writes. The workaround
1343           is to replace the normal offset of cache sync operation (0x730)
1344           by another offset targeting an unmapped PL310 register 0x740.
1345           This has the same effect as the cache sync operation: store buffer
1346           drain and waiting for all buffers empty.
1347
1348 config ARM_ERRATA_754322
1349         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1350         depends on CPU_V7
1351         help
1352           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1353           r3p*) erratum. A speculative memory access may cause a page table walk
1354           which starts prior to an ASID switch but completes afterwards. This
1355           can populate the micro-TLB with a stale entry which may be hit with
1356           the new ASID. This workaround places two dsb instructions in the mm
1357           switching code so that no page table walks can cross the ASID switch.
1358
1359 config ARM_ERRATA_754327
1360         bool "ARM errata: no automatic Store Buffer drain"
1361         depends on CPU_V7 && SMP
1362         help
1363           This option enables the workaround for the 754327 Cortex-A9 (prior to
1364           r2p0) erratum. The Store Buffer does not have any automatic draining
1365           mechanism and therefore a livelock may occur if an external agent
1366           continuously polls a memory location waiting to observe an update.
1367           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1368           written polling loops from denying visibility of updates to memory.
1369
1370 config ARM_ERRATA_364296
1371         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1372         depends on CPU_V6 && !SMP
1373         help
1374           This options enables the workaround for the 364296 ARM1136
1375           r0p2 erratum (possible cache data corruption with
1376           hit-under-miss enabled). It sets the undocumented bit 31 in
1377           the auxiliary control register and the FI bit in the control
1378           register, thus disabling hit-under-miss without putting the
1379           processor into full low interrupt latency mode. ARM11MPCore
1380           is not affected.
1381
1382 config ARM_ERRATA_764369
1383         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1384         depends on CPU_V7 && SMP
1385         help
1386           This option enables the workaround for erratum 764369
1387           affecting Cortex-A9 MPCore with two or more processors (all
1388           current revisions). Under certain timing circumstances, a data
1389           cache line maintenance operation by MVA targeting an Inner
1390           Shareable memory region may fail to proceed up to either the
1391           Point of Coherency or to the Point of Unification of the
1392           system. This workaround adds a DSB instruction before the
1393           relevant cache maintenance functions and sets a specific bit
1394           in the diagnostic control register of the SCU.
1395
1396 config PL310_ERRATA_769419
1397         bool "PL310 errata: no automatic Store Buffer drain"
1398         depends on CACHE_L2X0
1399         help
1400           On revisions of the PL310 prior to r3p2, the Store Buffer does
1401           not automatically drain. This can cause normal, non-cacheable
1402           writes to be retained when the memory system is idle, leading
1403           to suboptimal I/O performance for drivers using coherent DMA.
1404           This option adds a write barrier to the cpu_idle loop so that,
1405           on systems with an outer cache, the store buffer is drained
1406           explicitly.
1407
1408 config ARM_ERRATA_775420
1409        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1410        depends on CPU_V7
1411        help
1412          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1413          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1414          operation aborts with MMU exception, it might cause the processor
1415          to deadlock. This workaround puts DSB before executing ISB if
1416          an abort may occur on cache maintenance.
1417
1418 endmenu
1419
1420 source "arch/arm/common/Kconfig"
1421
1422 menu "Bus support"
1423
1424 config ARM_AMBA
1425         bool
1426
1427 config ISA
1428         bool
1429         help
1430           Find out whether you have ISA slots on your motherboard.  ISA is the
1431           name of a bus system, i.e. the way the CPU talks to the other stuff
1432           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1433           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1434           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1435
1436 # Select ISA DMA controller support
1437 config ISA_DMA
1438         bool
1439         select ISA_DMA_API
1440
1441 # Select ISA DMA interface
1442 config ISA_DMA_API
1443         bool
1444
1445 config PCI
1446         bool "PCI support" if MIGHT_HAVE_PCI
1447         help
1448           Find out whether you have a PCI motherboard. PCI is the name of a
1449           bus system, i.e. the way the CPU talks to the other stuff inside
1450           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1451           VESA. If you have PCI, say Y, otherwise N.
1452
1453 config PCI_DOMAINS
1454         bool
1455         depends on PCI
1456
1457 config PCI_NANOENGINE
1458         bool "BSE nanoEngine PCI support"
1459         depends on SA1100_NANOENGINE
1460         help
1461           Enable PCI on the BSE nanoEngine board.
1462
1463 config PCI_SYSCALL
1464         def_bool PCI
1465
1466 # Select the host bridge type
1467 config PCI_HOST_VIA82C505
1468         bool
1469         depends on PCI && ARCH_SHARK
1470         default y
1471
1472 config PCI_HOST_ITE8152
1473         bool
1474         depends on PCI && MACH_ARMCORE
1475         default y
1476         select DMABOUNCE
1477
1478 source "drivers/pci/Kconfig"
1479
1480 source "drivers/pcmcia/Kconfig"
1481
1482 endmenu
1483
1484 menu "Kernel Features"
1485
1486 config HAVE_SMP
1487         bool
1488         help
1489           This option should be selected by machines which have an SMP-
1490           capable CPU.
1491
1492           The only effect of this option is to make the SMP-related
1493           options available to the user for configuration.
1494
1495 config SMP
1496         bool "Symmetric Multi-Processing"
1497         depends on CPU_V6K || CPU_V7
1498         depends on GENERIC_CLOCKEVENTS
1499         depends on HAVE_SMP
1500         depends on MMU
1501         select USE_GENERIC_SMP_HELPERS
1502         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1503         help
1504           This enables support for systems with more than one CPU. If you have
1505           a system with only one CPU, like most personal computers, say N. If
1506           you have a system with more than one CPU, say Y.
1507
1508           If you say N here, the kernel will run on single and multiprocessor
1509           machines, but will use only one CPU of a multiprocessor machine. If
1510           you say Y here, the kernel will run on many, but not all, single
1511           processor machines. On a single processor machine, the kernel will
1512           run faster if you say N here.
1513
1514           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1515           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1516           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1517
1518           If you don't know what to do here, say N.
1519
1520 config SMP_ON_UP
1521         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1522         depends on EXPERIMENTAL
1523         depends on SMP && !XIP_KERNEL
1524         default y
1525         help
1526           SMP kernels contain instructions which fail on non-SMP processors.
1527           Enabling this option allows the kernel to modify itself to make
1528           these instructions safe.  Disabling it allows about 1K of space
1529           savings.
1530
1531           If you don't know what to do here, say Y.
1532
1533 config ARM_CPU_TOPOLOGY
1534         bool "Support cpu topology definition"
1535         depends on SMP && CPU_V7
1536         default y
1537         help
1538           Support ARM cpu topology definition. The MPIDR register defines
1539           affinity between processors which is then used to describe the cpu
1540           topology of an ARM System.
1541
1542 config SCHED_MC
1543         bool "Multi-core scheduler support"
1544         depends on ARM_CPU_TOPOLOGY
1545         help
1546           Multi-core scheduler support improves the CPU scheduler's decision
1547           making when dealing with multi-core CPU chips at a cost of slightly
1548           increased overhead in some places. If unsure say N here.
1549
1550 config SCHED_SMT
1551         bool "SMT scheduler support"
1552         depends on ARM_CPU_TOPOLOGY
1553         help
1554           Improves the CPU scheduler's decision making when dealing with
1555           MultiThreading at a cost of slightly increased overhead in some
1556           places. If unsure say N here.
1557
1558 config HAVE_ARM_SCU
1559         bool
1560         help
1561           This option enables support for the ARM system coherency unit
1562
1563 config ARM_ARCH_TIMER
1564         bool "Architected timer support"
1565         depends on CPU_V7
1566         help
1567           This option enables support for the ARM architected timer
1568
1569 config HAVE_ARM_TWD
1570         bool
1571         depends on SMP
1572         help
1573           This options enables support for the ARM timer and watchdog unit
1574
1575 choice
1576         prompt "Memory split"
1577         default VMSPLIT_3G
1578         help
1579           Select the desired split between kernel and user memory.
1580
1581           If you are not absolutely sure what you are doing, leave this
1582           option alone!
1583
1584         config VMSPLIT_3G
1585                 bool "3G/1G user/kernel split"
1586         config VMSPLIT_2G
1587                 bool "2G/2G user/kernel split"
1588         config VMSPLIT_1G
1589                 bool "1G/3G user/kernel split"
1590 endchoice
1591
1592 config PAGE_OFFSET
1593         hex
1594         default 0x40000000 if VMSPLIT_1G
1595         default 0x80000000 if VMSPLIT_2G
1596         default 0xC0000000
1597
1598 config NR_CPUS
1599         int "Maximum number of CPUs (2-32)"
1600         range 2 32
1601         depends on SMP
1602         default "4"
1603
1604 config HOTPLUG_CPU
1605         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1606         depends on SMP && HOTPLUG && EXPERIMENTAL
1607         help
1608           Say Y here to experiment with turning CPUs off and on.  CPUs
1609           can be controlled through /sys/devices/system/cpu.
1610
1611 config LOCAL_TIMERS
1612         bool "Use local timer interrupts"
1613         depends on SMP
1614         default y
1615         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1616         help
1617           Enable support for local timers on SMP platforms, rather then the
1618           legacy IPI broadcast method.  Local timers allows the system
1619           accounting to be spread across the timer interval, preventing a
1620           "thundering herd" at every timer tick.
1621
1622 config ARCH_NR_GPIO
1623         int
1624         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1625         default 355 if ARCH_U8500
1626         default 264 if MACH_H4700
1627         default 512 if SOC_OMAP5
1628         default 288 if ARCH_VT8500
1629         default 0
1630         help
1631           Maximum number of GPIOs in the system.
1632
1633           If unsure, leave the default value.
1634
1635 source kernel/Kconfig.preempt
1636
1637 config HZ
1638         int
1639         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1640                 ARCH_S5PV210 || ARCH_EXYNOS4
1641         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1642         default AT91_TIMER_HZ if ARCH_AT91
1643         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1644         default 100
1645
1646 config THUMB2_KERNEL
1647         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1648         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1649         select AEABI
1650         select ARM_ASM_UNIFIED
1651         select ARM_UNWIND
1652         help
1653           By enabling this option, the kernel will be compiled in
1654           Thumb-2 mode. A compiler/assembler that understand the unified
1655           ARM-Thumb syntax is needed.
1656
1657           If unsure, say N.
1658
1659 config THUMB2_AVOID_R_ARM_THM_JUMP11
1660         bool "Work around buggy Thumb-2 short branch relocations in gas"
1661         depends on THUMB2_KERNEL && MODULES
1662         default y
1663         help
1664           Various binutils versions can resolve Thumb-2 branches to
1665           locally-defined, preemptible global symbols as short-range "b.n"
1666           branch instructions.
1667
1668           This is a problem, because there's no guarantee the final
1669           destination of the symbol, or any candidate locations for a
1670           trampoline, are within range of the branch.  For this reason, the
1671           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1672           relocation in modules at all, and it makes little sense to add
1673           support.
1674
1675           The symptom is that the kernel fails with an "unsupported
1676           relocation" error when loading some modules.
1677
1678           Until fixed tools are available, passing
1679           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1680           code which hits this problem, at the cost of a bit of extra runtime
1681           stack usage in some cases.
1682
1683           The problem is described in more detail at:
1684               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1685
1686           Only Thumb-2 kernels are affected.
1687
1688           Unless you are sure your tools don't have this problem, say Y.
1689
1690 config ARM_ASM_UNIFIED
1691         bool
1692
1693 config AEABI
1694         bool "Use the ARM EABI to compile the kernel"
1695         help
1696           This option allows for the kernel to be compiled using the latest
1697           ARM ABI (aka EABI).  This is only useful if you are using a user
1698           space environment that is also compiled with EABI.
1699
1700           Since there are major incompatibilities between the legacy ABI and
1701           EABI, especially with regard to structure member alignment, this
1702           option also changes the kernel syscall calling convention to
1703           disambiguate both ABIs and allow for backward compatibility support
1704           (selected with CONFIG_OABI_COMPAT).
1705
1706           To use this you need GCC version 4.0.0 or later.
1707
1708 config OABI_COMPAT
1709         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1710         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1711         default y
1712         help
1713           This option preserves the old syscall interface along with the
1714           new (ARM EABI) one. It also provides a compatibility layer to
1715           intercept syscalls that have structure arguments which layout
1716           in memory differs between the legacy ABI and the new ARM EABI
1717           (only for non "thumb" binaries). This option adds a tiny
1718           overhead to all syscalls and produces a slightly larger kernel.
1719           If you know you'll be using only pure EABI user space then you
1720           can say N here. If this option is not selected and you attempt
1721           to execute a legacy ABI binary then the result will be
1722           UNPREDICTABLE (in fact it can be predicted that it won't work
1723           at all). If in doubt say Y.
1724
1725 config ARCH_HAS_HOLES_MEMORYMODEL
1726         bool
1727
1728 config ARCH_SPARSEMEM_ENABLE
1729         bool
1730
1731 config ARCH_SPARSEMEM_DEFAULT
1732         def_bool ARCH_SPARSEMEM_ENABLE
1733
1734 config ARCH_SELECT_MEMORY_MODEL
1735         def_bool ARCH_SPARSEMEM_ENABLE
1736
1737 config HAVE_ARCH_PFN_VALID
1738         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1739
1740 config HIGHMEM
1741         bool "High Memory Support"
1742         depends on MMU
1743         help
1744           The address space of ARM processors is only 4 Gigabytes large
1745           and it has to accommodate user address space, kernel address
1746           space as well as some memory mapped IO. That means that, if you
1747           have a large amount of physical memory and/or IO, not all of the
1748           memory can be "permanently mapped" by the kernel. The physical
1749           memory that is not permanently mapped is called "high memory".
1750
1751           Depending on the selected kernel/user memory split, minimum
1752           vmalloc space and actual amount of RAM, you may not need this
1753           option which should result in a slightly faster kernel.
1754
1755           If unsure, say n.
1756
1757 config HIGHPTE
1758         bool "Allocate 2nd-level pagetables from highmem"
1759         depends on HIGHMEM
1760
1761 config HW_PERF_EVENTS
1762         bool "Enable hardware performance counter support for perf events"
1763         depends on PERF_EVENTS
1764         default y
1765         help
1766           Enable hardware performance counter support for perf events. If
1767           disabled, perf events will use software events only.
1768
1769 source "mm/Kconfig"
1770
1771 config FORCE_MAX_ZONEORDER
1772         int "Maximum zone order" if ARCH_SHMOBILE
1773         range 11 64 if ARCH_SHMOBILE
1774         default "9" if SA1111
1775         default "11"
1776         help
1777           The kernel memory allocator divides physically contiguous memory
1778           blocks into "zones", where each zone is a power of two number of
1779           pages.  This option selects the largest power of two that the kernel
1780           keeps in the memory allocator.  If you need to allocate very large
1781           blocks of physically contiguous memory, then you may need to
1782           increase this value.
1783
1784           This config option is actually maximum order plus one. For example,
1785           a value of 11 means that the largest free memory block is 2^10 pages.
1786
1787 config ALIGNMENT_TRAP
1788         bool
1789         depends on CPU_CP15_MMU
1790         default y if !ARCH_EBSA110
1791         select HAVE_PROC_CPU if PROC_FS
1792         help
1793           ARM processors cannot fetch/store information which is not
1794           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1795           address divisible by 4. On 32-bit ARM processors, these non-aligned
1796           fetch/store instructions will be emulated in software if you say
1797           here, which has a severe performance impact. This is necessary for
1798           correct operation of some network protocols. With an IP-only
1799           configuration it is safe to say N, otherwise say Y.
1800
1801 config UACCESS_WITH_MEMCPY
1802         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1803         depends on MMU
1804         default y if CPU_FEROCEON
1805         help
1806           Implement faster copy_to_user and clear_user methods for CPU
1807           cores where a 8-word STM instruction give significantly higher
1808           memory write throughput than a sequence of individual 32bit stores.
1809
1810           A possible side effect is a slight increase in scheduling latency
1811           between threads sharing the same address space if they invoke
1812           such copy operations with large buffers.
1813
1814           However, if the CPU data cache is using a write-allocate mode,
1815           this option is unlikely to provide any performance gain.
1816
1817 config SECCOMP
1818         bool
1819         prompt "Enable seccomp to safely compute untrusted bytecode"
1820         ---help---
1821           This kernel feature is useful for number crunching applications
1822           that may need to compute untrusted bytecode during their
1823           execution. By using pipes or other transports made available to
1824           the process as file descriptors supporting the read/write
1825           syscalls, it's possible to isolate those applications in
1826           their own address space using seccomp. Once seccomp is
1827           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1828           and the task is only allowed to execute a few safe syscalls
1829           defined by each seccomp mode.
1830
1831 config CC_STACKPROTECTOR
1832         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1833         depends on EXPERIMENTAL
1834         help
1835           This option turns on the -fstack-protector GCC feature. This
1836           feature puts, at the beginning of functions, a canary value on
1837           the stack just before the return address, and validates
1838           the value just before actually returning.  Stack based buffer
1839           overflows (that need to overwrite this return address) now also
1840           overwrite the canary, which gets detected and the attack is then
1841           neutralized via a kernel panic.
1842           This feature requires gcc version 4.2 or above.
1843
1844 config XEN_DOM0
1845         def_bool y
1846         depends on XEN
1847
1848 config XEN
1849         bool "Xen guest support on ARM (EXPERIMENTAL)"
1850         depends on EXPERIMENTAL && ARM && OF
1851         help
1852           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1853
1854 endmenu
1855
1856 menu "Boot options"
1857
1858 config USE_OF
1859         bool "Flattened Device Tree support"
1860         select OF
1861         select OF_EARLY_FLATTREE
1862         select IRQ_DOMAIN
1863         help
1864           Include support for flattened device tree machine descriptions.
1865
1866 config ATAGS
1867         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1868         default y
1869         help
1870           This is the traditional way of passing data to the kernel at boot
1871           time. If you are solely relying on the flattened device tree (or
1872           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1873           to remove ATAGS support from your kernel binary.  If unsure,
1874           leave this to y.
1875
1876 config DEPRECATED_PARAM_STRUCT
1877         bool "Provide old way to pass kernel parameters"
1878         depends on ATAGS
1879         help
1880           This was deprecated in 2001 and announced to live on for 5 years.
1881           Some old boot loaders still use this way.
1882
1883 # Compressed boot loader in ROM.  Yes, we really want to ask about
1884 # TEXT and BSS so we preserve their values in the config files.
1885 config ZBOOT_ROM_TEXT
1886         hex "Compressed ROM boot loader base address"
1887         default "0"
1888         help
1889           The physical address at which the ROM-able zImage is to be
1890           placed in the target.  Platforms which normally make use of
1891           ROM-able zImage formats normally set this to a suitable
1892           value in their defconfig file.
1893
1894           If ZBOOT_ROM is not enabled, this has no effect.
1895
1896 config ZBOOT_ROM_BSS
1897         hex "Compressed ROM boot loader BSS address"
1898         default "0"
1899         help
1900           The base address of an area of read/write memory in the target
1901           for the ROM-able zImage which must be available while the
1902           decompressor is running. It must be large enough to hold the
1903           entire decompressed kernel plus an additional 128 KiB.
1904           Platforms which normally make use of ROM-able zImage formats
1905           normally set this to a suitable value in their defconfig file.
1906
1907           If ZBOOT_ROM is not enabled, this has no effect.
1908
1909 config ZBOOT_ROM
1910         bool "Compressed boot loader in ROM/flash"
1911         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1912         help
1913           Say Y here if you intend to execute your compressed kernel image
1914           (zImage) directly from ROM or flash.  If unsure, say N.
1915
1916 choice
1917         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1918         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1919         default ZBOOT_ROM_NONE
1920         help
1921           Include experimental SD/MMC loading code in the ROM-able zImage.
1922           With this enabled it is possible to write the ROM-able zImage
1923           kernel image to an MMC or SD card and boot the kernel straight
1924           from the reset vector. At reset the processor Mask ROM will load
1925           the first part of the ROM-able zImage which in turn loads the
1926           rest the kernel image to RAM.
1927
1928 config ZBOOT_ROM_NONE
1929         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1930         help
1931           Do not load image from SD or MMC
1932
1933 config ZBOOT_ROM_MMCIF
1934         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1935         help
1936           Load image from MMCIF hardware block.
1937
1938 config ZBOOT_ROM_SH_MOBILE_SDHI
1939         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1940         help
1941           Load image from SDHI hardware block
1942
1943 endchoice
1944
1945 config ARM_APPENDED_DTB
1946         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1947         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1948         help
1949           With this option, the boot code will look for a device tree binary
1950           (DTB) appended to zImage
1951           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1952
1953           This is meant as a backward compatibility convenience for those
1954           systems with a bootloader that can't be upgraded to accommodate
1955           the documented boot protocol using a device tree.
1956
1957           Beware that there is very little in terms of protection against
1958           this option being confused by leftover garbage in memory that might
1959           look like a DTB header after a reboot if no actual DTB is appended
1960           to zImage.  Do not leave this option active in a production kernel
1961           if you don't intend to always append a DTB.  Proper passing of the
1962           location into r2 of a bootloader provided DTB is always preferable
1963           to this option.
1964
1965 config ARM_ATAG_DTB_COMPAT
1966         bool "Supplement the appended DTB with traditional ATAG information"
1967         depends on ARM_APPENDED_DTB
1968         help
1969           Some old bootloaders can't be updated to a DTB capable one, yet
1970           they provide ATAGs with memory configuration, the ramdisk address,
1971           the kernel cmdline string, etc.  Such information is dynamically
1972           provided by the bootloader and can't always be stored in a static
1973           DTB.  To allow a device tree enabled kernel to be used with such
1974           bootloaders, this option allows zImage to extract the information
1975           from the ATAG list and store it at run time into the appended DTB.
1976
1977 choice
1978         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1979         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1980
1981 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1982         bool "Use bootloader kernel arguments if available"
1983         help
1984           Uses the command-line options passed by the boot loader instead of
1985           the device tree bootargs property. If the boot loader doesn't provide
1986           any, the device tree bootargs property will be used.
1987
1988 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1989         bool "Extend with bootloader kernel arguments"
1990         help
1991           The command-line arguments provided by the boot loader will be
1992           appended to the the device tree bootargs property.
1993
1994 endchoice
1995
1996 config CMDLINE
1997         string "Default kernel command string"
1998         default ""
1999         help
2000           On some architectures (EBSA110 and CATS), there is currently no way
2001           for the boot loader to pass arguments to the kernel. For these
2002           architectures, you should supply some command-line options at build
2003           time by entering them here. As a minimum, you should specify the
2004           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2005
2006 choice
2007         prompt "Kernel command line type" if CMDLINE != ""
2008         default CMDLINE_FROM_BOOTLOADER
2009         depends on ATAGS
2010
2011 config CMDLINE_FROM_BOOTLOADER
2012         bool "Use bootloader kernel arguments if available"
2013         help
2014           Uses the command-line options passed by the boot loader. If
2015           the boot loader doesn't provide any, the default kernel command
2016           string provided in CMDLINE will be used.
2017
2018 config CMDLINE_EXTEND
2019         bool "Extend bootloader kernel arguments"
2020         help
2021           The command-line arguments provided by the boot loader will be
2022           appended to the default kernel command string.
2023
2024 config CMDLINE_FORCE
2025         bool "Always use the default kernel command string"
2026         help
2027           Always use the default kernel command string, even if the boot
2028           loader passes other arguments to the kernel.
2029           This is useful if you cannot or don't want to change the
2030           command-line options your boot loader passes to the kernel.
2031 endchoice
2032
2033 config XIP_KERNEL
2034         bool "Kernel Execute-In-Place from ROM"
2035         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2036         help
2037           Execute-In-Place allows the kernel to run from non-volatile storage
2038           directly addressable by the CPU, such as NOR flash. This saves RAM
2039           space since the text section of the kernel is not loaded from flash
2040           to RAM.  Read-write sections, such as the data section and stack,
2041           are still copied to RAM.  The XIP kernel is not compressed since
2042           it has to run directly from flash, so it will take more space to
2043           store it.  The flash address used to link the kernel object files,
2044           and for storing it, is configuration dependent. Therefore, if you
2045           say Y here, you must know the proper physical address where to
2046           store the kernel image depending on your own flash memory usage.
2047
2048           Also note that the make target becomes "make xipImage" rather than
2049           "make zImage" or "make Image".  The final kernel binary to put in
2050           ROM memory will be arch/arm/boot/xipImage.
2051
2052           If unsure, say N.
2053
2054 config XIP_PHYS_ADDR
2055         hex "XIP Kernel Physical Location"
2056         depends on XIP_KERNEL
2057         default "0x00080000"
2058         help
2059           This is the physical address in your flash memory the kernel will
2060           be linked for and stored to.  This address is dependent on your
2061           own flash usage.
2062
2063 config KEXEC
2064         bool "Kexec system call (EXPERIMENTAL)"
2065         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2066         help
2067           kexec is a system call that implements the ability to shutdown your
2068           current kernel, and to start another kernel.  It is like a reboot
2069           but it is independent of the system firmware.   And like a reboot
2070           you can start any kernel with it, not just Linux.
2071
2072           It is an ongoing process to be certain the hardware in a machine
2073           is properly shutdown, so do not be surprised if this code does not
2074           initially work for you.  It may help to enable device hotplugging
2075           support.
2076
2077 config ATAGS_PROC
2078         bool "Export atags in procfs"
2079         depends on ATAGS && KEXEC
2080         default y
2081         help
2082           Should the atags used to boot the kernel be exported in an "atags"
2083           file in procfs. Useful with kexec.
2084
2085 config CRASH_DUMP
2086         bool "Build kdump crash kernel (EXPERIMENTAL)"
2087         depends on EXPERIMENTAL
2088         help
2089           Generate crash dump after being started by kexec. This should
2090           be normally only set in special crash dump kernels which are
2091           loaded in the main kernel with kexec-tools into a specially
2092           reserved region and then later executed after a crash by
2093           kdump/kexec. The crash dump kernel must be compiled to a
2094           memory address not used by the main kernel
2095
2096           For more details see Documentation/kdump/kdump.txt
2097
2098 config AUTO_ZRELADDR
2099         bool "Auto calculation of the decompressed kernel image address"
2100         depends on !ZBOOT_ROM && !ARCH_U300
2101         help
2102           ZRELADDR is the physical address where the decompressed kernel
2103           image will be placed. If AUTO_ZRELADDR is selected, the address
2104           will be determined at run-time by masking the current IP with
2105           0xf8000000. This assumes the zImage being placed in the first 128MB
2106           from start of memory.
2107
2108 endmenu
2109
2110 menu "CPU Power Management"
2111
2112 if ARCH_HAS_CPUFREQ
2113
2114 source "drivers/cpufreq/Kconfig"
2115
2116 config CPU_FREQ_IMX
2117         tristate "CPUfreq driver for i.MX CPUs"
2118         depends on ARCH_MXC && CPU_FREQ
2119         select CPU_FREQ_TABLE
2120         help
2121           This enables the CPUfreq driver for i.MX CPUs.
2122
2123 config CPU_FREQ_SA1100
2124         bool
2125
2126 config CPU_FREQ_SA1110
2127         bool
2128
2129 config CPU_FREQ_INTEGRATOR
2130         tristate "CPUfreq driver for ARM Integrator CPUs"
2131         depends on ARCH_INTEGRATOR && CPU_FREQ
2132         default y
2133         help
2134           This enables the CPUfreq driver for ARM Integrator CPUs.
2135
2136           For details, take a look at <file:Documentation/cpu-freq>.
2137
2138           If in doubt, say Y.
2139
2140 config CPU_FREQ_PXA
2141         bool
2142         depends on CPU_FREQ && ARCH_PXA && PXA25x
2143         default y
2144         select CPU_FREQ_TABLE
2145         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2146
2147 config CPU_FREQ_S3C
2148         bool
2149         help
2150           Internal configuration node for common cpufreq on Samsung SoC
2151
2152 config CPU_FREQ_S3C24XX
2153         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2154         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2155         select CPU_FREQ_S3C
2156         help
2157           This enables the CPUfreq driver for the Samsung S3C24XX family
2158           of CPUs.
2159
2160           For details, take a look at <file:Documentation/cpu-freq>.
2161
2162           If in doubt, say N.
2163
2164 config CPU_FREQ_S3C24XX_PLL
2165         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2166         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2167         help
2168           Compile in support for changing the PLL frequency from the
2169           S3C24XX series CPUfreq driver. The PLL takes time to settle
2170           after a frequency change, so by default it is not enabled.
2171
2172           This also means that the PLL tables for the selected CPU(s) will
2173           be built which may increase the size of the kernel image.
2174
2175 config CPU_FREQ_S3C24XX_DEBUG
2176         bool "Debug CPUfreq Samsung driver core"
2177         depends on CPU_FREQ_S3C24XX
2178         help
2179           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2180
2181 config CPU_FREQ_S3C24XX_IODEBUG
2182         bool "Debug CPUfreq Samsung driver IO timing"
2183         depends on CPU_FREQ_S3C24XX
2184         help
2185           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2186
2187 config CPU_FREQ_S3C24XX_DEBUGFS
2188         bool "Export debugfs for CPUFreq"
2189         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2190         help
2191           Export status information via debugfs.
2192
2193 endif
2194
2195 source "drivers/cpuidle/Kconfig"
2196
2197 endmenu
2198
2199 menu "Floating point emulation"
2200
2201 comment "At least one emulation must be selected"
2202
2203 config FPE_NWFPE
2204         bool "NWFPE math emulation"
2205         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2206         ---help---
2207           Say Y to include the NWFPE floating point emulator in the kernel.
2208           This is necessary to run most binaries. Linux does not currently
2209           support floating point hardware so you need to say Y here even if
2210           your machine has an FPA or floating point co-processor podule.
2211
2212           You may say N here if you are going to load the Acorn FPEmulator
2213           early in the bootup.
2214
2215 config FPE_NWFPE_XP
2216         bool "Support extended precision"
2217         depends on FPE_NWFPE
2218         help
2219           Say Y to include 80-bit support in the kernel floating-point
2220           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2221           Note that gcc does not generate 80-bit operations by default,
2222           so in most cases this option only enlarges the size of the
2223           floating point emulator without any good reason.
2224
2225           You almost surely want to say N here.
2226
2227 config FPE_FASTFPE
2228         bool "FastFPE math emulation (EXPERIMENTAL)"
2229         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2230         ---help---
2231           Say Y here to include the FAST floating point emulator in the kernel.
2232           This is an experimental much faster emulator which now also has full
2233           precision for the mantissa.  It does not support any exceptions.
2234           It is very simple, and approximately 3-6 times faster than NWFPE.
2235
2236           It should be sufficient for most programs.  It may be not suitable
2237           for scientific calculations, but you have to check this for yourself.
2238           If you do not feel you need a faster FP emulation you should better
2239           choose NWFPE.
2240
2241 config VFP
2242         bool "VFP-format floating point maths"
2243         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2244         help
2245           Say Y to include VFP support code in the kernel. This is needed
2246           if your hardware includes a VFP unit.
2247
2248           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2249           release notes and additional status information.
2250
2251           Say N if your target does not have VFP hardware.
2252
2253 config VFPv3
2254         bool
2255         depends on VFP
2256         default y if CPU_V7
2257
2258 config NEON
2259         bool "Advanced SIMD (NEON) Extension support"
2260         depends on VFPv3 && CPU_V7
2261         help
2262           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2263           Extension.
2264
2265 endmenu
2266
2267 menu "Userspace binary formats"
2268
2269 source "fs/Kconfig.binfmt"
2270
2271 config ARTHUR
2272         tristate "RISC OS personality"
2273         depends on !AEABI
2274         help
2275           Say Y here to include the kernel code necessary if you want to run
2276           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2277           experimental; if this sounds frightening, say N and sleep in peace.
2278           You can also say M here to compile this support as a module (which
2279           will be called arthur).
2280
2281 endmenu
2282
2283 menu "Power management options"
2284
2285 source "kernel/power/Kconfig"
2286
2287 config ARCH_SUSPEND_POSSIBLE
2288         depends on !ARCH_S5PC100
2289         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2290                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2291         def_bool y
2292
2293 config ARM_CPU_SUSPEND
2294         def_bool PM_SLEEP
2295
2296 endmenu
2297
2298 source "net/Kconfig"
2299
2300 source "drivers/Kconfig"
2301
2302 source "fs/Kconfig"
2303
2304 source "arch/arm/Kconfig.debug"
2305
2306 source "security/Kconfig"
2307
2308 source "crypto/Kconfig"
2309
2310 source "lib/Kconfig"