arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAVE_CUSTOM_GPIO_H
   5         select HAVE_AOUT
   6         select HAVE_DMA_API_DEBUG
   7         select HAVE_IDE if PCI || ISA || PCMCIA
   8         select HAVE_DMA_ATTRS
   9         select HAVE_DMA_CONTIGUOUS if MMU
  10         select HAVE_MEMBLOCK
  11         select RTC_LIB
  12         select SYS_SUPPORTS_APM_EMULATION
  13         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  15         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  16         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  17         select HAVE_ARCH_KGDB
  18         select HAVE_ARCH_TRACEHOOK
  19         select HAVE_KPROBES if !XIP_KERNEL
  20         select HAVE_KRETPROBES if (HAVE_KPROBES)
  21         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  22         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  23         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  24         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  25         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  26         select HAVE_GENERIC_DMA_COHERENT
  27         select HAVE_KERNEL_GZIP
  28         select HAVE_KERNEL_LZO
  29         select HAVE_KERNEL_LZMA
  30         select HAVE_KERNEL_XZ
  31         select HAVE_IRQ_WORK
  32         select HAVE_PERF_EVENTS
  33         select PERF_USE_VMALLOC
  34         select HAVE_REGS_AND_STACK_ACCESS_API
  35         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  36         select HAVE_C_RECORDMCOUNT
  37         select HAVE_GENERIC_HARDIRQS
  38         select HARDIRQS_SW_RESEND
  39         select GENERIC_IRQ_PROBE
  40         select GENERIC_IRQ_SHOW
  41         select ARCH_WANT_IPC_PARSE_VERSION
  42         select HARDIRQS_SW_RESEND
  43         select CPU_PM if (SUSPEND || CPU_IDLE)
  44         select GENERIC_PCI_IOMAP
  45         select HAVE_BPF_JIT
  46         select GENERIC_SMP_IDLE_THREAD
  47         select KTIME_SCALAR
  48         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  49         select GENERIC_STRNCPY_FROM_USER
  50         select GENERIC_STRNLEN_USER
  51         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
  52         help
  53           The ARM series is a line of low-power-consumption RISC chip designs
  54           licensed by ARM Ltd and targeted at embedded applications and
  55           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  56           manufactured, but legacy ARM-based PC hardware remains popular in
  57           Europe.  There is an ARM Linux project with a web page at
  58           <http://www.arm.linux.org.uk/>.
  59
  60 config ARM_HAS_SG_CHAIN
  61         bool
  62
  63 config NEED_SG_DMA_LENGTH
  64         bool
  65
  66 config ARM_DMA_USE_IOMMU
  67         select NEED_SG_DMA_LENGTH
  68         select ARM_HAS_SG_CHAIN
  69         bool
  70
  71 config HAVE_PWM
  72         bool
  73
  74 config MIGHT_HAVE_PCI
  75         bool
  76
  77 config SYS_SUPPORTS_APM_EMULATION
  78         bool
  79
  80 config GENERIC_GPIO
  81         bool
  82
  83 config HAVE_TCM
  84         bool
  85         select GENERIC_ALLOCATOR
  86
  87 config HAVE_PROC_CPU
  88         bool
  89
  90 config NO_IOPORT
  91         bool
  92
  93 config EISA
  94         bool
  95         ---help---
  96           The Extended Industry Standard Architecture (EISA) bus was
  97           developed as an open alternative to the IBM MicroChannel bus.
  98
  99           The EISA bus provided some of the features of the IBM MicroChannel
 100           bus while maintaining backward compatibility with cards made for
 101           the older ISA bus.  The EISA bus saw limited use between 1988 and
 102           1995 when it was made obsolete by the PCI bus.
 103
 104           Say Y here if you are building a kernel for an EISA-based machine.
 105
 106           Otherwise, say N.
 107
 108 config SBUS
 109         bool
 110
 111 config STACKTRACE_SUPPORT
 112         bool
 113         default y
 114
 115 config HAVE_LATENCYTOP_SUPPORT
 116         bool
 117         depends on !SMP
 118         default y
 119
 120 config LOCKDEP_SUPPORT
 121         bool
 122         default y
 123
 124 config TRACE_IRQFLAGS_SUPPORT
 125         bool
 126         default y
 127
 128 config RWSEM_GENERIC_SPINLOCK
 129         bool
 130         default y
 131
 132 config RWSEM_XCHGADD_ALGORITHM
 133         bool
 134
 135 config ARCH_HAS_ILOG2_U32
 136         bool
 137
 138 config ARCH_HAS_ILOG2_U64
 139         bool
 140
 141 config ARCH_HAS_CPUFREQ
 142         bool
 143         help
 144           Internal node to signify that the ARCH has CPUFREQ support
 145           and that the relevant menu configurations are displayed for
 146           it.
 147
 148 config GENERIC_HWEIGHT
 149         bool
 150         default y
 151
 152 config GENERIC_CALIBRATE_DELAY
 153         bool
 154         default y
 155
 156 config ARCH_MAY_HAVE_PC_FDC
 157         bool
 158
 159 config ZONE_DMA
 160         bool
 161
 162 config NEED_DMA_MAP_STATE
 163        def_bool y
 164
 165 config ARCH_HAS_DMA_SET_COHERENT_MASK
 166         bool
 167
 168 config GENERIC_ISA_DMA
 169         bool
 170
 171 config FIQ
 172         bool
 173
 174 config NEED_RET_TO_USER
 175         bool
 176
 177 config ARCH_MTD_XIP
 178         bool
 179
 180 config VECTORS_BASE
 181         hex
 182         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 183         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 184         default 0x00000000
 185         help
 186           The base address of exception vectors.
 187
 188 config ARM_PATCH_PHYS_VIRT
 189         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 190         default y
 191         depends on !XIP_KERNEL && MMU
 192         depends on !ARCH_REALVIEW || !SPARSEMEM
 193         help
 194           Patch phys-to-virt and virt-to-phys translation functions at
 195           boot and module load time according to the position of the
 196           kernel in system memory.
 197
 198           This can only be used with non-XIP MMU kernels where the base
 199           of physical memory is at a 16MB boundary.
 200
 201           Only disable this option if you know that you do not require
 202           this feature (eg, building a kernel for a single machine) and
 203           you need to shrink the kernel to the minimal size.
 204
 205 config NEED_MACH_GPIO_H
 206         bool
 207         help
 208           Select this when mach/gpio.h is required to provide special
 209           definitions for this platform. The need for mach/gpio.h should
 210           be avoided when possible.
 211
 212 config NEED_MACH_IO_H
 213         bool
 214         help
 215           Select this when mach/io.h is required to provide special
 216           definitions for this platform.  The need for mach/io.h should
 217           be avoided when possible.
 218
 219 config NEED_MACH_MEMORY_H
 220         bool
 221         help
 222           Select this when mach/memory.h is required to provide special
 223           definitions for this platform.  The need for mach/memory.h should
 224           be avoided when possible.
 225
 226 config PHYS_OFFSET
 227         hex "Physical address of main memory" if MMU
 228         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 229         default DRAM_BASE if !MMU
 230         help
 231           Please provide the physical address corresponding to the
 232           location of main memory in your system.
 233
 234 config GENERIC_BUG
 235         def_bool y
 236         depends on BUG
 237
 238 source "init/Kconfig"
 239
 240 source "kernel/Kconfig.freezer"
 241
 242 menu "System Type"
 243
 244 config MMU
 245         bool "MMU-based Paged Memory Management Support"
 246         default y
 247         help
 248           Select if you want MMU-based virtualised addressing space
 249           support by paged memory management. If unsure, say 'Y'.
 250
 251 #
 252 # The "ARM system type" choice list is ordered alphabetically by option
 253 # text.  Please add new entries in the option alphabetic order.
 254 #
 255 choice
 256         prompt "ARM system type"
 257         default ARCH_MULTIPLATFORM
 258
 259 config ARCH_MULTIPLATFORM
 260         bool "Allow multiple platforms to be selected"
 261         select ARM_PATCH_PHYS_VIRT
 262         select AUTO_ZRELADDR
 263         select COMMON_CLK
 264         select MULTI_IRQ_HANDLER
 265         select SPARSE_IRQ
 266         select USE_OF
 267         depends on MMU
 268
 269 config ARCH_INTEGRATOR
 270         bool "ARM Ltd. Integrator family"
 271         select ARM_AMBA
 272         select ARCH_HAS_CPUFREQ
 273         select COMMON_CLK
 274         select COMMON_CLK_VERSATILE
 275         select HAVE_TCM
 276         select ICST
 277         select GENERIC_CLOCKEVENTS
 278         select PLAT_VERSATILE
 279         select PLAT_VERSATILE_FPGA_IRQ
 280         select NEED_MACH_MEMORY_H
 281         select SPARSE_IRQ
 282         select MULTI_IRQ_HANDLER
 283         help
 284           Support for ARM's Integrator platform.
 285
 286 config ARCH_REALVIEW
 287         bool "ARM Ltd. RealView family"
 288         select ARM_AMBA
 289         select COMMON_CLK
 290         select COMMON_CLK_VERSATILE
 291         select ICST
 292         select GENERIC_CLOCKEVENTS
 293         select ARCH_WANT_OPTIONAL_GPIOLIB
 294         select PLAT_VERSATILE
 295         select PLAT_VERSATILE_CLCD
 296         select ARM_TIMER_SP804
 297         select GPIO_PL061 if GPIOLIB
 298         select NEED_MACH_MEMORY_H
 299         help
 300           This enables support for ARM Ltd RealView boards.
 301
 302 config ARCH_VERSATILE
 303         bool "ARM Ltd. Versatile family"
 304         select ARM_AMBA
 305         select ARM_VIC
 306         select CLKDEV_LOOKUP
 307         select HAVE_MACH_CLKDEV
 308         select ICST
 309         select GENERIC_CLOCKEVENTS
 310         select ARCH_WANT_OPTIONAL_GPIOLIB
 311         select PLAT_VERSATILE
 312         select PLAT_VERSATILE_CLOCK
 313         select PLAT_VERSATILE_CLCD
 314         select PLAT_VERSATILE_FPGA_IRQ
 315         select ARM_TIMER_SP804
 316         help
 317           This enables support for ARM Ltd Versatile board.
 318
 319 config ARCH_AT91
 320         bool "Atmel AT91"
 321         select ARCH_REQUIRE_GPIOLIB
 322         select HAVE_CLK
 323         select CLKDEV_LOOKUP
 324         select IRQ_DOMAIN
 325         select NEED_MACH_GPIO_H
 326         select NEED_MACH_IO_H if PCCARD
 327         help
 328           This enables support for systems based on Atmel
 329           AT91RM9200 and AT91SAM9* processors.
 330
 331 config ARCH_BCM2835
 332         bool "Broadcom BCM2835 family"
 333         select ARCH_WANT_OPTIONAL_GPIOLIB
 334         select ARM_AMBA
 335         select ARM_ERRATA_411920
 336         select ARM_TIMER_SP804
 337         select CLKDEV_LOOKUP
 338         select COMMON_CLK
 339         select CPU_V6
 340         select GENERIC_CLOCKEVENTS
 341         select MULTI_IRQ_HANDLER
 342         select SPARSE_IRQ
 343         select USE_OF
 344         help
 345           This enables support for the Broadcom BCM2835 SoC. This SoC is
 346           use in the Raspberry Pi, and Roku 2 devices.
 347
 348 config ARCH_CLPS711X
 349         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 350         select CPU_ARM720T
 351         select ARCH_USES_GETTIMEOFFSET
 352         select COMMON_CLK
 353         select CLKDEV_LOOKUP
 354         select NEED_MACH_MEMORY_H
 355         help
 356           Support for Cirrus Logic 711x/721x/731x based boards.
 357
 358 config ARCH_CNS3XXX
 359         bool "Cavium Networks CNS3XXX family"
 360         select CPU_V6K
 361         select GENERIC_CLOCKEVENTS
 362         select ARM_GIC
 363         select MIGHT_HAVE_CACHE_L2X0
 364         select MIGHT_HAVE_PCI
 365         select PCI_DOMAINS if PCI
 366         help
 367           Support for Cavium Networks CNS3XXX platform.
 368
 369 config ARCH_GEMINI
 370         bool "Cortina Systems Gemini"
 371         select CPU_FA526
 372         select ARCH_REQUIRE_GPIOLIB
 373         select ARCH_USES_GETTIMEOFFSET
 374         help
 375           Support for the Cortina Systems Gemini family SoCs
 376
 377 config ARCH_SIRF
 378         bool "CSR SiRF"
 379         select NO_IOPORT
 380         select ARCH_REQUIRE_GPIOLIB
 381         select GENERIC_CLOCKEVENTS
 382         select COMMON_CLK
 383         select GENERIC_IRQ_CHIP
 384         select MIGHT_HAVE_CACHE_L2X0
 385         select PINCTRL
 386         select PINCTRL_SIRF
 387         select USE_OF
 388         help
 389           Support for CSR SiRFprimaII/Marco/Polo platforms
 390
 391 config ARCH_EBSA110
 392         bool "EBSA-110"
 393         select CPU_SA110
 394         select ISA
 395         select NO_IOPORT
 396         select ARCH_USES_GETTIMEOFFSET
 397         select NEED_MACH_IO_H
 398         select NEED_MACH_MEMORY_H
 399         help
 400           This is an evaluation board for the StrongARM processor available
 401           from Digital. It has limited hardware on-board, including an
 402           Ethernet interface, two PCMCIA sockets, two serial ports and a
 403           parallel port.
 404
 405 config ARCH_EP93XX
 406         bool "EP93xx-based"
 407         select CPU_ARM920T
 408         select ARM_AMBA
 409         select ARM_VIC
 410         select CLKDEV_LOOKUP
 411         select ARCH_REQUIRE_GPIOLIB
 412         select ARCH_HAS_HOLES_MEMORYMODEL
 413         select ARCH_USES_GETTIMEOFFSET
 414         select NEED_MACH_MEMORY_H
 415         help
 416           This enables support for the Cirrus EP93xx series of CPUs.
 417
 418 config ARCH_FOOTBRIDGE
 419         bool "FootBridge"
 420         select CPU_SA110
 421         select FOOTBRIDGE
 422         select GENERIC_CLOCKEVENTS
 423         select HAVE_IDE
 424         select NEED_MACH_IO_H if !MMU
 425         select NEED_MACH_MEMORY_H
 426         help
 427           Support for systems based on the DC21285 companion chip
 428           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 429
 430 config ARCH_MXC
 431         bool "Freescale MXC/iMX-based"
 432         select GENERIC_CLOCKEVENTS
 433         select ARCH_REQUIRE_GPIOLIB
 434         select CLKDEV_LOOKUP
 435         select CLKSRC_MMIO
 436         select GENERIC_IRQ_CHIP
 437         select MULTI_IRQ_HANDLER
 438         select SPARSE_IRQ
 439         select USE_OF
 440         help
 441           Support for Freescale MXC/iMX-based family of processors
 442
 443 config ARCH_MXS
 444         bool "Freescale MXS-based"
 445         select GENERIC_CLOCKEVENTS
 446         select ARCH_REQUIRE_GPIOLIB
 447         select CLKDEV_LOOKUP
 448         select CLKSRC_MMIO
 449         select COMMON_CLK
 450         select HAVE_CLK_PREPARE
 451         select MULTI_IRQ_HANDLER
 452         select PINCTRL
 453         select SPARSE_IRQ
 454         select USE_OF
 455         help
 456           Support for Freescale MXS-based family of processors
 457
 458 config ARCH_NETX
 459         bool "Hilscher NetX based"
 460         select CLKSRC_MMIO
 461         select CPU_ARM926T
 462         select ARM_VIC
 463         select GENERIC_CLOCKEVENTS
 464         help
 465           This enables support for systems based on the Hilscher NetX Soc
 466
 467 config ARCH_H720X
 468         bool "Hynix HMS720x-based"
 469         select CPU_ARM720T
 470         select ISA_DMA_API
 471         select ARCH_USES_GETTIMEOFFSET
 472         help
 473           This enables support for systems based on the Hynix HMS720x
 474
 475 config ARCH_IOP13XX
 476         bool "IOP13xx-based"
 477         depends on MMU
 478         select CPU_XSC3
 479         select PLAT_IOP
 480         select PCI
 481         select ARCH_SUPPORTS_MSI
 482         select VMSPLIT_1G
 483         select NEED_MACH_MEMORY_H
 484         select NEED_RET_TO_USER
 485         help
 486           Support for Intel's IOP13XX (XScale) family of processors.
 487
 488 config ARCH_IOP32X
 489         bool "IOP32x-based"
 490         depends on MMU
 491         select CPU_XSCALE
 492         select NEED_MACH_GPIO_H
 493         select NEED_MACH_IO_H
 494         select NEED_RET_TO_USER
 495         select PLAT_IOP
 496         select PCI
 497         select ARCH_REQUIRE_GPIOLIB
 498         help
 499           Support for Intel's 80219 and IOP32X (XScale) family of
 500           processors.
 501
 502 config ARCH_IOP33X
 503         bool "IOP33x-based"
 504         depends on MMU
 505         select CPU_XSCALE
 506         select NEED_MACH_GPIO_H
 507         select NEED_MACH_IO_H
 508         select NEED_RET_TO_USER
 509         select PLAT_IOP
 510         select PCI
 511         select ARCH_REQUIRE_GPIOLIB
 512         help
 513           Support for Intel's IOP33X (XScale) family of processors.
 514
 515 config ARCH_IXP4XX
 516         bool "IXP4xx-based"
 517         depends on MMU
 518         select ARCH_HAS_DMA_SET_COHERENT_MASK
 519         select CLKSRC_MMIO
 520         select CPU_XSCALE
 521         select ARCH_REQUIRE_GPIOLIB
 522         select GENERIC_CLOCKEVENTS
 523         select MIGHT_HAVE_PCI
 524         select NEED_MACH_IO_H
 525         select DMABOUNCE if PCI
 526         help
 527           Support for Intel's IXP4XX (XScale) family of processors.
 528
 529 config ARCH_DOVE
 530         bool "Marvell Dove"
 531         select CPU_V7
 532         select PCI
 533         select ARCH_REQUIRE_GPIOLIB
 534         select GENERIC_CLOCKEVENTS
 535         select PLAT_ORION
 536         help
 537           Support for the Marvell Dove SoC 88AP510
 538
 539 config ARCH_KIRKWOOD
 540         bool "Marvell Kirkwood"
 541         select CPU_FEROCEON
 542         select PCI
 543         select ARCH_REQUIRE_GPIOLIB
 544         select GENERIC_CLOCKEVENTS
 545         select PLAT_ORION
 546         help
 547           Support for the following Marvell Kirkwood series SoCs:
 548           88F6180, 88F6192 and 88F6281.
 549
 550 config ARCH_LPC32XX
 551         bool "NXP LPC32XX"
 552         select CLKSRC_MMIO
 553         select CPU_ARM926T
 554         select ARCH_REQUIRE_GPIOLIB
 555         select HAVE_IDE
 556         select ARM_AMBA
 557         select USB_ARCH_HAS_OHCI
 558         select CLKDEV_LOOKUP
 559         select GENERIC_CLOCKEVENTS
 560         select USE_OF
 561         select HAVE_PWM
 562         help
 563           Support for the NXP LPC32XX family of processors
 564
 565 config ARCH_MV78XX0
 566         bool "Marvell MV78xx0"
 567         select CPU_FEROCEON
 568         select PCI
 569         select ARCH_REQUIRE_GPIOLIB
 570         select GENERIC_CLOCKEVENTS
 571         select PLAT_ORION
 572         help
 573           Support for the following Marvell MV78xx0 series SoCs:
 574           MV781x0, MV782x0.
 575
 576 config ARCH_ORION5X
 577         bool "Marvell Orion"
 578         depends on MMU
 579         select CPU_FEROCEON
 580         select PCI
 581         select ARCH_REQUIRE_GPIOLIB
 582         select GENERIC_CLOCKEVENTS
 583         select PLAT_ORION
 584         help
 585           Support for the following Marvell Orion 5x series SoCs:
 586           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 587           Orion-2 (5281), Orion-1-90 (6183).
 588
 589 config ARCH_MMP
 590         bool "Marvell PXA168/910/MMP2"
 591         depends on MMU
 592         select ARCH_REQUIRE_GPIOLIB
 593         select CLKDEV_LOOKUP
 594         select GENERIC_CLOCKEVENTS
 595         select GPIO_PXA
 596         select IRQ_DOMAIN
 597         select PLAT_PXA
 598         select SPARSE_IRQ
 599         select GENERIC_ALLOCATOR
 600         select NEED_MACH_GPIO_H
 601         help
 602           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 603
 604 config ARCH_KS8695
 605         bool "Micrel/Kendin KS8695"
 606         select CPU_ARM922T
 607         select ARCH_REQUIRE_GPIOLIB
 608         select NEED_MACH_MEMORY_H
 609         select CLKSRC_MMIO
 610         select GENERIC_CLOCKEVENTS
 611         help
 612           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 613           System-on-Chip devices.
 614
 615 config ARCH_W90X900
 616         bool "Nuvoton W90X900 CPU"
 617         select CPU_ARM926T
 618         select ARCH_REQUIRE_GPIOLIB
 619         select CLKDEV_LOOKUP
 620         select CLKSRC_MMIO
 621         select GENERIC_CLOCKEVENTS
 622         help
 623           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 624           At present, the w90x900 has been renamed nuc900, regarding
 625           the ARM series product line, you can login the following
 626           link address to know more.
 627
 628           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 629                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 630
 631 config ARCH_TEGRA
 632         bool "NVIDIA Tegra"
 633         select CLKDEV_LOOKUP
 634         select CLKSRC_MMIO
 635         select GENERIC_CLOCKEVENTS
 636         select GENERIC_GPIO
 637         select HAVE_CLK
 638         select HAVE_SMP
 639         select MIGHT_HAVE_CACHE_L2X0
 640         select ARCH_HAS_CPUFREQ
 641         select USE_OF
 642         select COMMON_CLK
 643         help
 644           This enables support for NVIDIA Tegra based systems (Tegra APX,
 645           Tegra 6xx and Tegra 2 series).
 646
 647 config ARCH_PXA
 648         bool "PXA2xx/PXA3xx-based"
 649         depends on MMU
 650         select ARCH_MTD_XIP
 651         select ARCH_HAS_CPUFREQ
 652         select CLKDEV_LOOKUP
 653         select CLKSRC_MMIO
 654         select ARCH_REQUIRE_GPIOLIB
 655         select GENERIC_CLOCKEVENTS
 656         select GPIO_PXA
 657         select PLAT_PXA
 658         select SPARSE_IRQ
 659         select AUTO_ZRELADDR
 660         select MULTI_IRQ_HANDLER
 661         select ARM_CPU_SUSPEND if PM
 662         select HAVE_IDE
 663         select NEED_MACH_GPIO_H
 664         help
 665           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 666
 667 config ARCH_MSM
 668         bool "Qualcomm MSM"
 669         select HAVE_CLK
 670         select GENERIC_CLOCKEVENTS
 671         select ARCH_REQUIRE_GPIOLIB
 672         select CLKDEV_LOOKUP
 673         help
 674           Support for Qualcomm MSM/QSD based systems.  This runs on the
 675           apps processor of the MSM/QSD and depends on a shared memory
 676           interface to the modem processor which runs the baseband
 677           stack and controls some vital subsystems
 678           (clock and power control, etc).
 679
 680 config ARCH_SHMOBILE
 681         bool "Renesas SH-Mobile / R-Mobile"
 682         select HAVE_CLK
 683         select CLKDEV_LOOKUP
 684         select HAVE_MACH_CLKDEV
 685         select HAVE_SMP
 686         select GENERIC_CLOCKEVENTS
 687         select MIGHT_HAVE_CACHE_L2X0
 688         select NO_IOPORT
 689         select SPARSE_IRQ
 690         select MULTI_IRQ_HANDLER
 691         select PM_GENERIC_DOMAINS if PM
 692         select NEED_MACH_MEMORY_H
 693         help
 694           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 695
 696 config ARCH_RPC
 697         bool "RiscPC"
 698         select ARCH_ACORN
 699         select FIQ
 700         select ARCH_MAY_HAVE_PC_FDC
 701         select HAVE_PATA_PLATFORM
 702         select ISA_DMA_API
 703         select NO_IOPORT
 704         select ARCH_SPARSEMEM_ENABLE
 705         select ARCH_USES_GETTIMEOFFSET
 706         select HAVE_IDE
 707         select NEED_MACH_IO_H
 708         select NEED_MACH_MEMORY_H
 709         help
 710           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 711           CD-ROM interface, serial and parallel port, and the floppy drive.
 712
 713 config ARCH_SA1100
 714         bool "SA1100-based"
 715         select CLKSRC_MMIO
 716         select CPU_SA1100
 717         select ISA
 718         select ARCH_SPARSEMEM_ENABLE
 719         select ARCH_MTD_XIP
 720         select ARCH_HAS_CPUFREQ
 721         select CPU_FREQ
 722         select GENERIC_CLOCKEVENTS
 723         select CLKDEV_LOOKUP
 724         select ARCH_REQUIRE_GPIOLIB
 725         select HAVE_IDE
 726         select NEED_MACH_GPIO_H
 727         select NEED_MACH_MEMORY_H
 728         select SPARSE_IRQ
 729         help
 730           Support for StrongARM 11x0 based boards.
 731
 732 config ARCH_S3C24XX
 733         bool "Samsung S3C24XX SoCs"
 734         select GENERIC_GPIO
 735         select ARCH_HAS_CPUFREQ
 736         select HAVE_CLK
 737         select CLKDEV_LOOKUP
 738         select ARCH_USES_GETTIMEOFFSET
 739         select HAVE_S3C2410_I2C if I2C
 740         select HAVE_S3C_RTC if RTC_CLASS
 741         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 742         select NEED_MACH_GPIO_H
 743         select NEED_MACH_IO_H
 744         help
 745           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 746           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 747           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 748           Samsung SMDK2410 development board (and derivatives).
 749
 750 config ARCH_S3C64XX
 751         bool "Samsung S3C64XX"
 752         select PLAT_SAMSUNG
 753         select CPU_V6
 754         select ARM_VIC
 755         select HAVE_CLK
 756         select HAVE_TCM
 757         select CLKDEV_LOOKUP
 758         select NO_IOPORT
 759         select ARCH_USES_GETTIMEOFFSET
 760         select ARCH_HAS_CPUFREQ
 761         select ARCH_REQUIRE_GPIOLIB
 762         select SAMSUNG_CLKSRC
 763         select SAMSUNG_IRQ_VIC_TIMER
 764         select S3C_GPIO_TRACK
 765         select S3C_DEV_NAND
 766         select USB_ARCH_HAS_OHCI
 767         select SAMSUNG_GPIOLIB_4BIT
 768         select HAVE_S3C2410_I2C if I2C
 769         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 770         select NEED_MACH_GPIO_H
 771         help
 772           Samsung S3C64XX series based systems
 773
 774 config ARCH_S5P64X0
 775         bool "Samsung S5P6440 S5P6450"
 776         select CPU_V6
 777         select GENERIC_GPIO
 778         select HAVE_CLK
 779         select CLKDEV_LOOKUP
 780         select CLKSRC_MMIO
 781         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 782         select GENERIC_CLOCKEVENTS
 783         select HAVE_S3C2410_I2C if I2C
 784         select HAVE_S3C_RTC if RTC_CLASS
 785         select NEED_MACH_GPIO_H
 786         help
 787           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 788           SMDK6450.
 789
 790 config ARCH_S5PC100
 791         bool "Samsung S5PC100"
 792         select GENERIC_GPIO
 793         select HAVE_CLK
 794         select CLKDEV_LOOKUP
 795         select CPU_V7
 796         select ARCH_USES_GETTIMEOFFSET
 797         select HAVE_S3C2410_I2C if I2C
 798         select HAVE_S3C_RTC if RTC_CLASS
 799         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 800         select NEED_MACH_GPIO_H
 801         help
 802           Samsung S5PC100 series based systems
 803
 804 config ARCH_S5PV210
 805         bool "Samsung S5PV210/S5PC110"
 806         select CPU_V7
 807         select ARCH_SPARSEMEM_ENABLE
 808         select ARCH_HAS_HOLES_MEMORYMODEL
 809         select GENERIC_GPIO
 810         select HAVE_CLK
 811         select CLKDEV_LOOKUP
 812         select CLKSRC_MMIO
 813         select ARCH_HAS_CPUFREQ
 814         select GENERIC_CLOCKEVENTS
 815         select HAVE_S3C2410_I2C if I2C
 816         select HAVE_S3C_RTC if RTC_CLASS
 817         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 818         select NEED_MACH_GPIO_H
 819         select NEED_MACH_MEMORY_H
 820         help
 821           Samsung S5PV210/S5PC110 series based systems
 822
 823 config ARCH_EXYNOS
 824         bool "SAMSUNG EXYNOS"
 825         select CPU_V7
 826         select ARCH_SPARSEMEM_ENABLE
 827         select ARCH_HAS_HOLES_MEMORYMODEL
 828         select GENERIC_GPIO
 829         select HAVE_CLK
 830         select CLKDEV_LOOKUP
 831         select ARCH_HAS_CPUFREQ
 832         select GENERIC_CLOCKEVENTS
 833         select HAVE_S3C_RTC if RTC_CLASS
 834         select HAVE_S3C2410_I2C if I2C
 835         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 836         select NEED_MACH_GPIO_H
 837         select NEED_MACH_MEMORY_H
 838         help
 839           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 840
 841 config ARCH_SHARK
 842         bool "Shark"
 843         select CPU_SA110
 844         select ISA
 845         select ISA_DMA
 846         select ZONE_DMA
 847         select PCI
 848         select ARCH_USES_GETTIMEOFFSET
 849         select NEED_MACH_MEMORY_H
 850         help
 851           Support for the StrongARM based Digital DNARD machine, also known
 852           as "Shark" (<http://www.shark-linux.de/shark.html>).
 853
 854 config ARCH_U300
 855         bool "ST-Ericsson U300 Series"
 856         depends on MMU
 857         select CLKSRC_MMIO
 858         select CPU_ARM926T
 859         select HAVE_TCM
 860         select ARM_AMBA
 861         select ARM_PATCH_PHYS_VIRT
 862         select ARM_VIC
 863         select GENERIC_CLOCKEVENTS
 864         select CLKDEV_LOOKUP
 865         select COMMON_CLK
 866         select GENERIC_GPIO
 867         select ARCH_REQUIRE_GPIOLIB
 868         select SPARSE_IRQ
 869         help
 870           Support for ST-Ericsson U300 series mobile platforms.
 871
 872 config ARCH_U8500
 873         bool "ST-Ericsson U8500 Series"
 874         depends on MMU
 875         select CPU_V7
 876         select ARM_AMBA
 877         select GENERIC_CLOCKEVENTS
 878         select CLKDEV_LOOKUP
 879         select ARCH_REQUIRE_GPIOLIB
 880         select ARCH_HAS_CPUFREQ
 881         select HAVE_SMP
 882         select MIGHT_HAVE_CACHE_L2X0
 883         help
 884           Support for ST-Ericsson's Ux500 architecture
 885
 886 config ARCH_NOMADIK
 887         bool "STMicroelectronics Nomadik"
 888         select ARM_AMBA
 889         select ARM_VIC
 890         select CPU_ARM926T
 891         select COMMON_CLK
 892         select GENERIC_CLOCKEVENTS
 893         select PINCTRL
 894         select MIGHT_HAVE_CACHE_L2X0
 895         select ARCH_REQUIRE_GPIOLIB
 896         help
 897           Support for the Nomadik platform by ST-Ericsson
 898
 899 config ARCH_DAVINCI
 900         bool "TI DaVinci"
 901         select GENERIC_CLOCKEVENTS
 902         select ARCH_REQUIRE_GPIOLIB
 903         select ZONE_DMA
 904         select HAVE_IDE
 905         select CLKDEV_LOOKUP
 906         select GENERIC_ALLOCATOR
 907         select GENERIC_IRQ_CHIP
 908         select ARCH_HAS_HOLES_MEMORYMODEL
 909         select NEED_MACH_GPIO_H
 910         help
 911           Support for TI's DaVinci platform.
 912
 913 config ARCH_OMAP
 914         bool "TI OMAP"
 915         depends on MMU
 916         select HAVE_CLK
 917         select ARCH_REQUIRE_GPIOLIB
 918         select ARCH_HAS_CPUFREQ
 919         select CLKSRC_MMIO
 920         select GENERIC_CLOCKEVENTS
 921         select ARCH_HAS_HOLES_MEMORYMODEL
 922         select NEED_MACH_GPIO_H
 923         help
 924           Support for TI's OMAP platform (OMAP1/2/3/4).
 925
 926 config PLAT_SPEAR
 927         bool "ST SPEAr"
 928         select ARM_AMBA
 929         select ARCH_REQUIRE_GPIOLIB
 930         select CLKDEV_LOOKUP
 931         select COMMON_CLK
 932         select CLKSRC_MMIO
 933         select GENERIC_CLOCKEVENTS
 934         select HAVE_CLK
 935         help
 936           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 937
 938 config ARCH_VT8500
 939         bool "VIA/WonderMedia 85xx"
 940         select CPU_ARM926T
 941         select GENERIC_GPIO
 942         select ARCH_HAS_CPUFREQ
 943         select GENERIC_CLOCKEVENTS
 944         select ARCH_REQUIRE_GPIOLIB
 945         select USE_OF
 946         select COMMON_CLK
 947         select HAVE_CLK
 948         select CLKDEV_LOOKUP
 949         help
 950           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 951
 952 config ARCH_ZYNQ
 953         bool "Xilinx Zynq ARM Cortex A9 Platform"
 954         select CPU_V7
 955         select GENERIC_CLOCKEVENTS
 956         select CLKDEV_LOOKUP
 957         select ARM_GIC
 958         select ARM_AMBA
 959         select ICST
 960         select MIGHT_HAVE_CACHE_L2X0
 961         select USE_OF
 962         help
 963           Support for Xilinx Zynq ARM Cortex A9 Platform
 964 endchoice
 965
 966 menu "Multiple platform selection"
 967         depends on ARCH_MULTIPLATFORM
 968
 969 comment "CPU Core family selection"
 970
 971 config ARCH_MULTI_V4
 972         bool "ARMv4 based platforms (FA526, StrongARM)"
 973         select ARCH_MULTI_V4_V5
 974         depends on !ARCH_MULTI_V6_V7
 975
 976 config ARCH_MULTI_V4T
 977         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 978         select ARCH_MULTI_V4_V5
 979         depends on !ARCH_MULTI_V6_V7
 980
 981 config ARCH_MULTI_V5
 982         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 983         select ARCH_MULTI_V4_V5
 984         depends on !ARCH_MULTI_V6_V7
 985
 986 config ARCH_MULTI_V4_V5
 987         bool
 988
 989 config ARCH_MULTI_V6
 990         bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
 991         select CPU_V6
 992         select ARCH_MULTI_V6_V7
 993
 994 config ARCH_MULTI_V7
 995         bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
 996         select CPU_V7
 997         select ARCH_VEXPRESS
 998         default y
 999         select ARCH_MULTI_V6_V7
1000
1001 config ARCH_MULTI_V6_V7
1002         bool
1003
1004 config ARCH_MULTI_CPU_AUTO
1005         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1006         select ARCH_MULTI_V5
1007
1008 endmenu
1009
1010 #
1011 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1012 # Kconfigs may be included either alphabetically (according to the
1013 # plat- suffix) or along side the corresponding mach-* source.
1014 #
1015 source "arch/arm/mach-mvebu/Kconfig"
1016
1017 source "arch/arm/mach-at91/Kconfig"
1018
1019 source "arch/arm/mach-clps711x/Kconfig"
1020
1021 source "arch/arm/mach-cns3xxx/Kconfig"
1022
1023 source "arch/arm/mach-davinci/Kconfig"
1024
1025 source "arch/arm/mach-dove/Kconfig"
1026
1027 source "arch/arm/mach-ep93xx/Kconfig"
1028
1029 source "arch/arm/mach-footbridge/Kconfig"
1030
1031 source "arch/arm/mach-gemini/Kconfig"
1032
1033 source "arch/arm/mach-h720x/Kconfig"
1034
1035 source "arch/arm/mach-highbank/Kconfig"
1036
1037 source "arch/arm/mach-integrator/Kconfig"
1038
1039 source "arch/arm/mach-iop32x/Kconfig"
1040
1041 source "arch/arm/mach-iop33x/Kconfig"
1042
1043 source "arch/arm/mach-iop13xx/Kconfig"
1044
1045 source "arch/arm/mach-ixp4xx/Kconfig"
1046
1047 source "arch/arm/mach-kirkwood/Kconfig"
1048
1049 source "arch/arm/mach-ks8695/Kconfig"
1050
1051 source "arch/arm/mach-msm/Kconfig"
1052
1053 source "arch/arm/mach-mv78xx0/Kconfig"
1054
1055 source "arch/arm/plat-mxc/Kconfig"
1056
1057 source "arch/arm/mach-mxs/Kconfig"
1058
1059 source "arch/arm/mach-netx/Kconfig"
1060
1061 source "arch/arm/mach-nomadik/Kconfig"
1062 source "arch/arm/plat-nomadik/Kconfig"
1063
1064 source "arch/arm/plat-omap/Kconfig"
1065
1066 source "arch/arm/mach-omap1/Kconfig"
1067
1068 source "arch/arm/mach-omap2/Kconfig"
1069
1070 source "arch/arm/mach-orion5x/Kconfig"
1071
1072 source "arch/arm/mach-picoxcell/Kconfig"
1073
1074 source "arch/arm/mach-pxa/Kconfig"
1075 source "arch/arm/plat-pxa/Kconfig"
1076
1077 source "arch/arm/mach-mmp/Kconfig"
1078
1079 source "arch/arm/mach-realview/Kconfig"
1080
1081 source "arch/arm/mach-sa1100/Kconfig"
1082
1083 source "arch/arm/plat-samsung/Kconfig"
1084 source "arch/arm/plat-s3c24xx/Kconfig"
1085
1086 source "arch/arm/mach-socfpga/Kconfig"
1087
1088 source "arch/arm/plat-spear/Kconfig"
1089
1090 source "arch/arm/mach-s3c24xx/Kconfig"
1091 if ARCH_S3C24XX
1092 source "arch/arm/mach-s3c2412/Kconfig"
1093 source "arch/arm/mach-s3c2440/Kconfig"
1094 endif
1095
1096 if ARCH_S3C64XX
1097 source "arch/arm/mach-s3c64xx/Kconfig"
1098 endif
1099
1100 source "arch/arm/mach-s5p64x0/Kconfig"
1101
1102 source "arch/arm/mach-s5pc100/Kconfig"
1103
1104 source "arch/arm/mach-s5pv210/Kconfig"
1105
1106 source "arch/arm/mach-exynos/Kconfig"
1107
1108 source "arch/arm/mach-shmobile/Kconfig"
1109
1110 source "arch/arm/mach-prima2/Kconfig"
1111
1112 source "arch/arm/mach-tegra/Kconfig"
1113
1114 source "arch/arm/mach-u300/Kconfig"
1115
1116 source "arch/arm/mach-ux500/Kconfig"
1117
1118 source "arch/arm/mach-versatile/Kconfig"
1119
1120 source "arch/arm/mach-vexpress/Kconfig"
1121 source "arch/arm/plat-versatile/Kconfig"
1122
1123 source "arch/arm/mach-w90x900/Kconfig"
1124
1125 # Definitions to make life easier
1126 config ARCH_ACORN
1127         bool
1128
1129 config PLAT_IOP
1130         bool
1131         select GENERIC_CLOCKEVENTS
1132
1133 config PLAT_ORION
1134         bool
1135         select CLKSRC_MMIO
1136         select GENERIC_IRQ_CHIP
1137         select IRQ_DOMAIN
1138         select COMMON_CLK
1139
1140 config PLAT_PXA
1141         bool
1142
1143 config PLAT_VERSATILE
1144         bool
1145
1146 config ARM_TIMER_SP804
1147         bool
1148         select CLKSRC_MMIO
1149         select HAVE_SCHED_CLOCK
1150
1151 source arch/arm/mm/Kconfig
1152
1153 config ARM_NR_BANKS
1154         int
1155         default 16 if ARCH_EP93XX
1156         default 8
1157
1158 config IWMMXT
1159         bool "Enable iWMMXt support"
1160         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1161         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1162         help
1163           Enable support for iWMMXt context switching at run time if
1164           running on a CPU that supports it.
1165
1166 config XSCALE_PMU
1167         bool
1168         depends on CPU_XSCALE
1169         default y
1170
1171 config MULTI_IRQ_HANDLER
1172         bool
1173         help
1174           Allow each machine to specify it's own IRQ handler at run time.
1175
1176 if !MMU
1177 source "arch/arm/Kconfig-nommu"
1178 endif
1179
1180 config ARM_ERRATA_326103
1181         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1182         depends on CPU_V6
1183         help
1184           Executing a SWP instruction to read-only memory does not set bit 11
1185           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1186           treat the access as a read, preventing a COW from occurring and
1187           causing the faulting task to livelock.
1188
1189 config ARM_ERRATA_411920
1190         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1191         depends on CPU_V6 || CPU_V6K
1192         help
1193           Invalidation of the Instruction Cache operation can
1194           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1195           It does not affect the MPCore. This option enables the ARM Ltd.
1196           recommended workaround.
1197
1198 config ARM_ERRATA_430973
1199         bool "ARM errata: Stale prediction on replaced interworking branch"
1200         depends on CPU_V7
1201         help
1202           This option enables the workaround for the 430973 Cortex-A8
1203           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1204           interworking branch is replaced with another code sequence at the
1205           same virtual address, whether due to self-modifying code or virtual
1206           to physical address re-mapping, Cortex-A8 does not recover from the
1207           stale interworking branch prediction. This results in Cortex-A8
1208           executing the new code sequence in the incorrect ARM or Thumb state.
1209           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1210           and also flushes the branch target cache at every context switch.
1211           Note that setting specific bits in the ACTLR register may not be
1212           available in non-secure mode.
1213
1214 config ARM_ERRATA_458693
1215         bool "ARM errata: Processor deadlock when a false hazard is created"
1216         depends on CPU_V7
1217         help
1218           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1219           erratum. For very specific sequences of memory operations, it is
1220           possible for a hazard condition intended for a cache line to instead
1221           be incorrectly associated with a different cache line. This false
1222           hazard might then cause a processor deadlock. The workaround enables
1223           the L1 caching of the NEON accesses and disables the PLD instruction
1224           in the ACTLR register. Note that setting specific bits in the ACTLR
1225           register may not be available in non-secure mode.
1226
1227 config ARM_ERRATA_460075
1228         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1229         depends on CPU_V7
1230         help
1231           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1232           erratum. Any asynchronous access to the L2 cache may encounter a
1233           situation in which recent store transactions to the L2 cache are lost
1234           and overwritten with stale memory contents from external memory. The
1235           workaround disables the write-allocate mode for the L2 cache via the
1236           ACTLR register. Note that setting specific bits in the ACTLR register
1237           may not be available in non-secure mode.
1238
1239 config ARM_ERRATA_742230
1240         bool "ARM errata: DMB operation may be faulty"
1241         depends on CPU_V7 && SMP
1242         help
1243           This option enables the workaround for the 742230 Cortex-A9
1244           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1245           between two write operations may not ensure the correct visibility
1246           ordering of the two writes. This workaround sets a specific bit in
1247           the diagnostic register of the Cortex-A9 which causes the DMB
1248           instruction to behave as a DSB, ensuring the correct behaviour of
1249           the two writes.
1250
1251 config ARM_ERRATA_742231
1252         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1253         depends on CPU_V7 && SMP
1254         help
1255           This option enables the workaround for the 742231 Cortex-A9
1256           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1257           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1258           accessing some data located in the same cache line, may get corrupted
1259           data due to bad handling of the address hazard when the line gets
1260           replaced from one of the CPUs at the same time as another CPU is
1261           accessing it. This workaround sets specific bits in the diagnostic
1262           register of the Cortex-A9 which reduces the linefill issuing
1263           capabilities of the processor.
1264
1265 config PL310_ERRATA_588369
1266         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1267         depends on CACHE_L2X0
1268         help
1269            The PL310 L2 cache controller implements three types of Clean &
1270            Invalidate maintenance operations: by Physical Address
1271            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1272            They are architecturally defined to behave as the execution of a
1273            clean operation followed immediately by an invalidate operation,
1274            both performing to the same memory location. This functionality
1275            is not correctly implemented in PL310 as clean lines are not
1276            invalidated as a result of these operations.
1277
1278 config ARM_ERRATA_720789
1279         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1280         depends on CPU_V7
1281         help
1282           This option enables the workaround for the 720789 Cortex-A9 (prior to
1283           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1284           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1285           As a consequence of this erratum, some TLB entries which should be
1286           invalidated are not, resulting in an incoherency in the system page
1287           tables. The workaround changes the TLB flushing routines to invalidate
1288           entries regardless of the ASID.
1289
1290 config PL310_ERRATA_727915
1291         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1292         depends on CACHE_L2X0
1293         help
1294           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1295           operation (offset 0x7FC). This operation runs in background so that
1296           PL310 can handle normal accesses while it is in progress. Under very
1297           rare circumstances, due to this erratum, write data can be lost when
1298           PL310 treats a cacheable write transaction during a Clean &
1299           Invalidate by Way operation.
1300
1301 config ARM_ERRATA_743622
1302         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1303         depends on CPU_V7
1304         help
1305           This option enables the workaround for the 743622 Cortex-A9
1306           (r2p*) erratum. Under very rare conditions, a faulty
1307           optimisation in the Cortex-A9 Store Buffer may lead to data
1308           corruption. This workaround sets a specific bit in the diagnostic
1309           register of the Cortex-A9 which disables the Store Buffer
1310           optimisation, preventing the defect from occurring. This has no
1311           visible impact on the overall performance or power consumption of the
1312           processor.
1313
1314 config ARM_ERRATA_751472
1315         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1316         depends on CPU_V7
1317         help
1318           This option enables the workaround for the 751472 Cortex-A9 (prior
1319           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1320           completion of a following broadcasted operation if the second
1321           operation is received by a CPU before the ICIALLUIS has completed,
1322           potentially leading to corrupted entries in the cache or TLB.
1323
1324 config PL310_ERRATA_753970
1325         bool "PL310 errata: cache sync operation may be faulty"
1326         depends on CACHE_PL310
1327         help
1328           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1329
1330           Under some condition the effect of cache sync operation on
1331           the store buffer still remains when the operation completes.
1332           This means that the store buffer is always asked to drain and
1333           this prevents it from merging any further writes. The workaround
1334           is to replace the normal offset of cache sync operation (0x730)
1335           by another offset targeting an unmapped PL310 register 0x740.
1336           This has the same effect as the cache sync operation: store buffer
1337           drain and waiting for all buffers empty.
1338
1339 config ARM_ERRATA_754322
1340         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1341         depends on CPU_V7
1342         help
1343           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1344           r3p*) erratum. A speculative memory access may cause a page table walk
1345           which starts prior to an ASID switch but completes afterwards. This
1346           can populate the micro-TLB with a stale entry which may be hit with
1347           the new ASID. This workaround places two dsb instructions in the mm
1348           switching code so that no page table walks can cross the ASID switch.
1349
1350 config ARM_ERRATA_754327
1351         bool "ARM errata: no automatic Store Buffer drain"
1352         depends on CPU_V7 && SMP
1353         help
1354           This option enables the workaround for the 754327 Cortex-A9 (prior to
1355           r2p0) erratum. The Store Buffer does not have any automatic draining
1356           mechanism and therefore a livelock may occur if an external agent
1357           continuously polls a memory location waiting to observe an update.
1358           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1359           written polling loops from denying visibility of updates to memory.
1360
1361 config ARM_ERRATA_364296
1362         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1363         depends on CPU_V6 && !SMP
1364         help
1365           This options enables the workaround for the 364296 ARM1136
1366           r0p2 erratum (possible cache data corruption with
1367           hit-under-miss enabled). It sets the undocumented bit 31 in
1368           the auxiliary control register and the FI bit in the control
1369           register, thus disabling hit-under-miss without putting the
1370           processor into full low interrupt latency mode. ARM11MPCore
1371           is not affected.
1372
1373 config ARM_ERRATA_764369
1374         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1375         depends on CPU_V7 && SMP
1376         help
1377           This option enables the workaround for erratum 764369
1378           affecting Cortex-A9 MPCore with two or more processors (all
1379           current revisions). Under certain timing circumstances, a data
1380           cache line maintenance operation by MVA targeting an Inner
1381           Shareable memory region may fail to proceed up to either the
1382           Point of Coherency or to the Point of Unification of the
1383           system. This workaround adds a DSB instruction before the
1384           relevant cache maintenance functions and sets a specific bit
1385           in the diagnostic control register of the SCU.
1386
1387 config PL310_ERRATA_769419
1388         bool "PL310 errata: no automatic Store Buffer drain"
1389         depends on CACHE_L2X0
1390         help
1391           On revisions of the PL310 prior to r3p2, the Store Buffer does
1392           not automatically drain. This can cause normal, non-cacheable
1393           writes to be retained when the memory system is idle, leading
1394           to suboptimal I/O performance for drivers using coherent DMA.
1395           This option adds a write barrier to the cpu_idle loop so that,
1396           on systems with an outer cache, the store buffer is drained
1397           explicitly.
1398
1399 endmenu
1400
1401 source "arch/arm/common/Kconfig"
1402
1403 menu "Bus support"
1404
1405 config ARM_AMBA
1406         bool
1407
1408 config ISA
1409         bool
1410         help
1411           Find out whether you have ISA slots on your motherboard.  ISA is the
1412           name of a bus system, i.e. the way the CPU talks to the other stuff
1413           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1414           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1415           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1416
1417 # Select ISA DMA controller support
1418 config ISA_DMA
1419         bool
1420         select ISA_DMA_API
1421
1422 # Select ISA DMA interface
1423 config ISA_DMA_API
1424         bool
1425
1426 config PCI
1427         bool "PCI support" if MIGHT_HAVE_PCI
1428         help
1429           Find out whether you have a PCI motherboard. PCI is the name of a
1430           bus system, i.e. the way the CPU talks to the other stuff inside
1431           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1432           VESA. If you have PCI, say Y, otherwise N.
1433
1434 config PCI_DOMAINS
1435         bool
1436         depends on PCI
1437
1438 config PCI_NANOENGINE
1439         bool "BSE nanoEngine PCI support"
1440         depends on SA1100_NANOENGINE
1441         help
1442           Enable PCI on the BSE nanoEngine board.
1443
1444 config PCI_SYSCALL
1445         def_bool PCI
1446
1447 # Select the host bridge type
1448 config PCI_HOST_VIA82C505
1449         bool
1450         depends on PCI && ARCH_SHARK
1451         default y
1452
1453 config PCI_HOST_ITE8152
1454         bool
1455         depends on PCI && MACH_ARMCORE
1456         default y
1457         select DMABOUNCE
1458
1459 source "drivers/pci/Kconfig"
1460
1461 source "drivers/pcmcia/Kconfig"
1462
1463 endmenu
1464
1465 menu "Kernel Features"
1466
1467 config HAVE_SMP
1468         bool
1469         help
1470           This option should be selected by machines which have an SMP-
1471           capable CPU.
1472
1473           The only effect of this option is to make the SMP-related
1474           options available to the user for configuration.
1475
1476 config SMP
1477         bool "Symmetric Multi-Processing"
1478         depends on CPU_V6K || CPU_V7
1479         depends on GENERIC_CLOCKEVENTS
1480         depends on HAVE_SMP
1481         depends on MMU
1482         select USE_GENERIC_SMP_HELPERS
1483         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1484         help
1485           This enables support for systems with more than one CPU. If you have
1486           a system with only one CPU, like most personal computers, say N. If
1487           you have a system with more than one CPU, say Y.
1488
1489           If you say N here, the kernel will run on single and multiprocessor
1490           machines, but will use only one CPU of a multiprocessor machine. If
1491           you say Y here, the kernel will run on many, but not all, single
1492           processor machines. On a single processor machine, the kernel will
1493           run faster if you say N here.
1494
1495           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1496           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1497           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1498
1499           If you don't know what to do here, say N.
1500
1501 config SMP_ON_UP
1502         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1503         depends on EXPERIMENTAL
1504         depends on SMP && !XIP_KERNEL
1505         default y
1506         help
1507           SMP kernels contain instructions which fail on non-SMP processors.
1508           Enabling this option allows the kernel to modify itself to make
1509           these instructions safe.  Disabling it allows about 1K of space
1510           savings.
1511
1512           If you don't know what to do here, say Y.
1513
1514 config ARM_CPU_TOPOLOGY
1515         bool "Support cpu topology definition"
1516         depends on SMP && CPU_V7
1517         default y
1518         help
1519           Support ARM cpu topology definition. The MPIDR register defines
1520           affinity between processors which is then used to describe the cpu
1521           topology of an ARM System.
1522
1523 config SCHED_MC
1524         bool "Multi-core scheduler support"
1525         depends on ARM_CPU_TOPOLOGY
1526         help
1527           Multi-core scheduler support improves the CPU scheduler's decision
1528           making when dealing with multi-core CPU chips at a cost of slightly
1529           increased overhead in some places. If unsure say N here.
1530
1531 config SCHED_SMT
1532         bool "SMT scheduler support"
1533         depends on ARM_CPU_TOPOLOGY
1534         help
1535           Improves the CPU scheduler's decision making when dealing with
1536           MultiThreading at a cost of slightly increased overhead in some
1537           places. If unsure say N here.
1538
1539 config HAVE_ARM_SCU
1540         bool
1541         help
1542           This option enables support for the ARM system coherency unit
1543
1544 config ARM_ARCH_TIMER
1545         bool "Architected timer support"
1546         depends on CPU_V7
1547         help
1548           This option enables support for the ARM architected timer
1549
1550 config HAVE_ARM_TWD
1551         bool
1552         depends on SMP
1553         help
1554           This options enables support for the ARM timer and watchdog unit
1555
1556 choice
1557         prompt "Memory split"
1558         default VMSPLIT_3G
1559         help
1560           Select the desired split between kernel and user memory.
1561
1562           If you are not absolutely sure what you are doing, leave this
1563           option alone!
1564
1565         config VMSPLIT_3G
1566                 bool "3G/1G user/kernel split"
1567         config VMSPLIT_2G
1568                 bool "2G/2G user/kernel split"
1569         config VMSPLIT_1G
1570                 bool "1G/3G user/kernel split"
1571 endchoice
1572
1573 config PAGE_OFFSET
1574         hex
1575         default 0x40000000 if VMSPLIT_1G
1576         default 0x80000000 if VMSPLIT_2G
1577         default 0xC0000000
1578
1579 config NR_CPUS
1580         int "Maximum number of CPUs (2-32)"
1581         range 2 32
1582         depends on SMP
1583         default "4"
1584
1585 config HOTPLUG_CPU
1586         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1587         depends on SMP && HOTPLUG && EXPERIMENTAL
1588         help
1589           Say Y here to experiment with turning CPUs off and on.  CPUs
1590           can be controlled through /sys/devices/system/cpu.
1591
1592 config LOCAL_TIMERS
1593         bool "Use local timer interrupts"
1594         depends on SMP
1595         default y
1596         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1597         help
1598           Enable support for local timers on SMP platforms, rather then the
1599           legacy IPI broadcast method.  Local timers allows the system
1600           accounting to be spread across the timer interval, preventing a
1601           "thundering herd" at every timer tick.
1602
1603 config ARCH_NR_GPIO
1604         int
1605         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1606         default 355 if ARCH_U8500
1607         default 264 if MACH_H4700
1608         default 512 if SOC_OMAP5
1609         default 288 if ARCH_VT8500
1610         default 0
1611         help
1612           Maximum number of GPIOs in the system.
1613
1614           If unsure, leave the default value.
1615
1616 source kernel/Kconfig.preempt
1617
1618 config HZ
1619         int
1620         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1621                 ARCH_S5PV210 || ARCH_EXYNOS4
1622         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1623         default AT91_TIMER_HZ if ARCH_AT91
1624         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1625         default 100
1626
1627 config THUMB2_KERNEL
1628         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1629         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1630         select AEABI
1631         select ARM_ASM_UNIFIED
1632         select ARM_UNWIND
1633         help
1634           By enabling this option, the kernel will be compiled in
1635           Thumb-2 mode. A compiler/assembler that understand the unified
1636           ARM-Thumb syntax is needed.
1637
1638           If unsure, say N.
1639
1640 config THUMB2_AVOID_R_ARM_THM_JUMP11
1641         bool "Work around buggy Thumb-2 short branch relocations in gas"
1642         depends on THUMB2_KERNEL && MODULES
1643         default y
1644         help
1645           Various binutils versions can resolve Thumb-2 branches to
1646           locally-defined, preemptible global symbols as short-range "b.n"
1647           branch instructions.
1648
1649           This is a problem, because there's no guarantee the final
1650           destination of the symbol, or any candidate locations for a
1651           trampoline, are within range of the branch.  For this reason, the
1652           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1653           relocation in modules at all, and it makes little sense to add
1654           support.
1655
1656           The symptom is that the kernel fails with an "unsupported
1657           relocation" error when loading some modules.
1658
1659           Until fixed tools are available, passing
1660           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1661           code which hits this problem, at the cost of a bit of extra runtime
1662           stack usage in some cases.
1663
1664           The problem is described in more detail at:
1665               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1666
1667           Only Thumb-2 kernels are affected.
1668
1669           Unless you are sure your tools don't have this problem, say Y.
1670
1671 config ARM_ASM_UNIFIED
1672         bool
1673
1674 config AEABI
1675         bool "Use the ARM EABI to compile the kernel"
1676         help
1677           This option allows for the kernel to be compiled using the latest
1678           ARM ABI (aka EABI).  This is only useful if you are using a user
1679           space environment that is also compiled with EABI.
1680
1681           Since there are major incompatibilities between the legacy ABI and
1682           EABI, especially with regard to structure member alignment, this
1683           option also changes the kernel syscall calling convention to
1684           disambiguate both ABIs and allow for backward compatibility support
1685           (selected with CONFIG_OABI_COMPAT).
1686
1687           To use this you need GCC version 4.0.0 or later.
1688
1689 config OABI_COMPAT
1690         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1691         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1692         default y
1693         help
1694           This option preserves the old syscall interface along with the
1695           new (ARM EABI) one. It also provides a compatibility layer to
1696           intercept syscalls that have structure arguments which layout
1697           in memory differs between the legacy ABI and the new ARM EABI
1698           (only for non "thumb" binaries). This option adds a tiny
1699           overhead to all syscalls and produces a slightly larger kernel.
1700           If you know you'll be using only pure EABI user space then you
1701           can say N here. If this option is not selected and you attempt
1702           to execute a legacy ABI binary then the result will be
1703           UNPREDICTABLE (in fact it can be predicted that it won't work
1704           at all). If in doubt say Y.
1705
1706 config ARCH_HAS_HOLES_MEMORYMODEL
1707         bool
1708
1709 config ARCH_SPARSEMEM_ENABLE
1710         bool
1711
1712 config ARCH_SPARSEMEM_DEFAULT
1713         def_bool ARCH_SPARSEMEM_ENABLE
1714
1715 config ARCH_SELECT_MEMORY_MODEL
1716         def_bool ARCH_SPARSEMEM_ENABLE
1717
1718 config HAVE_ARCH_PFN_VALID
1719         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1720
1721 config HIGHMEM
1722         bool "High Memory Support"
1723         depends on MMU
1724         help
1725           The address space of ARM processors is only 4 Gigabytes large
1726           and it has to accommodate user address space, kernel address
1727           space as well as some memory mapped IO. That means that, if you
1728           have a large amount of physical memory and/or IO, not all of the
1729           memory can be "permanently mapped" by the kernel. The physical
1730           memory that is not permanently mapped is called "high memory".
1731
1732           Depending on the selected kernel/user memory split, minimum
1733           vmalloc space and actual amount of RAM, you may not need this
1734           option which should result in a slightly faster kernel.
1735
1736           If unsure, say n.
1737
1738 config HIGHPTE
1739         bool "Allocate 2nd-level pagetables from highmem"
1740         depends on HIGHMEM
1741
1742 config HW_PERF_EVENTS
1743         bool "Enable hardware performance counter support for perf events"
1744         depends on PERF_EVENTS
1745         default y
1746         help
1747           Enable hardware performance counter support for perf events. If
1748           disabled, perf events will use software events only.
1749
1750 source "mm/Kconfig"
1751
1752 config FORCE_MAX_ZONEORDER
1753         int "Maximum zone order" if ARCH_SHMOBILE
1754         range 11 64 if ARCH_SHMOBILE
1755         default "9" if SA1111
1756         default "11"
1757         help
1758           The kernel memory allocator divides physically contiguous memory
1759           blocks into "zones", where each zone is a power of two number of
1760           pages.  This option selects the largest power of two that the kernel
1761           keeps in the memory allocator.  If you need to allocate very large
1762           blocks of physically contiguous memory, then you may need to
1763           increase this value.
1764
1765           This config option is actually maximum order plus one. For example,
1766           a value of 11 means that the largest free memory block is 2^10 pages.
1767
1768 config ALIGNMENT_TRAP
1769         bool
1770         depends on CPU_CP15_MMU
1771         default y if !ARCH_EBSA110
1772         select HAVE_PROC_CPU if PROC_FS
1773         help
1774           ARM processors cannot fetch/store information which is not
1775           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1776           address divisible by 4. On 32-bit ARM processors, these non-aligned
1777           fetch/store instructions will be emulated in software if you say
1778           here, which has a severe performance impact. This is necessary for
1779           correct operation of some network protocols. With an IP-only
1780           configuration it is safe to say N, otherwise say Y.
1781
1782 config UACCESS_WITH_MEMCPY
1783         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1784         depends on MMU && EXPERIMENTAL
1785         default y if CPU_FEROCEON
1786         help
1787           Implement faster copy_to_user and clear_user methods for CPU
1788           cores where a 8-word STM instruction give significantly higher
1789           memory write throughput than a sequence of individual 32bit stores.
1790
1791           A possible side effect is a slight increase in scheduling latency
1792           between threads sharing the same address space if they invoke
1793           such copy operations with large buffers.
1794
1795           However, if the CPU data cache is using a write-allocate mode,
1796           this option is unlikely to provide any performance gain.
1797
1798 config SECCOMP
1799         bool
1800         prompt "Enable seccomp to safely compute untrusted bytecode"
1801         ---help---
1802           This kernel feature is useful for number crunching applications
1803           that may need to compute untrusted bytecode during their
1804           execution. By using pipes or other transports made available to
1805           the process as file descriptors supporting the read/write
1806           syscalls, it's possible to isolate those applications in
1807           their own address space using seccomp. Once seccomp is
1808           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1809           and the task is only allowed to execute a few safe syscalls
1810           defined by each seccomp mode.
1811
1812 config CC_STACKPROTECTOR
1813         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1814         depends on EXPERIMENTAL
1815         help
1816           This option turns on the -fstack-protector GCC feature. This
1817           feature puts, at the beginning of functions, a canary value on
1818           the stack just before the return address, and validates
1819           the value just before actually returning.  Stack based buffer
1820           overflows (that need to overwrite this return address) now also
1821           overwrite the canary, which gets detected and the attack is then
1822           neutralized via a kernel panic.
1823           This feature requires gcc version 4.2 or above.
1824
1825 config DEPRECATED_PARAM_STRUCT
1826         bool "Provide old way to pass kernel parameters"
1827         help
1828           This was deprecated in 2001 and announced to live on for 5 years.
1829           Some old boot loaders still use this way.
1830
1831 endmenu
1832
1833 menu "Boot options"
1834
1835 config USE_OF
1836         bool "Flattened Device Tree support"
1837         select OF
1838         select OF_EARLY_FLATTREE
1839         select IRQ_DOMAIN
1840         help
1841           Include support for flattened device tree machine descriptions.
1842
1843 # Compressed boot loader in ROM.  Yes, we really want to ask about
1844 # TEXT and BSS so we preserve their values in the config files.
1845 config ZBOOT_ROM_TEXT
1846         hex "Compressed ROM boot loader base address"
1847         default "0"
1848         help
1849           The physical address at which the ROM-able zImage is to be
1850           placed in the target.  Platforms which normally make use of
1851           ROM-able zImage formats normally set this to a suitable
1852           value in their defconfig file.
1853
1854           If ZBOOT_ROM is not enabled, this has no effect.
1855
1856 config ZBOOT_ROM_BSS
1857         hex "Compressed ROM boot loader BSS address"
1858         default "0"
1859         help
1860           The base address of an area of read/write memory in the target
1861           for the ROM-able zImage which must be available while the
1862           decompressor is running. It must be large enough to hold the
1863           entire decompressed kernel plus an additional 128 KiB.
1864           Platforms which normally make use of ROM-able zImage formats
1865           normally set this to a suitable value in their defconfig file.
1866
1867           If ZBOOT_ROM is not enabled, this has no effect.
1868
1869 config ZBOOT_ROM
1870         bool "Compressed boot loader in ROM/flash"
1871         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1872         help
1873           Say Y here if you intend to execute your compressed kernel image
1874           (zImage) directly from ROM or flash.  If unsure, say N.
1875
1876 choice
1877         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1878         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1879         default ZBOOT_ROM_NONE
1880         help
1881           Include experimental SD/MMC loading code in the ROM-able zImage.
1882           With this enabled it is possible to write the ROM-able zImage
1883           kernel image to an MMC or SD card and boot the kernel straight
1884           from the reset vector. At reset the processor Mask ROM will load
1885           the first part of the ROM-able zImage which in turn loads the
1886           rest the kernel image to RAM.
1887
1888 config ZBOOT_ROM_NONE
1889         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1890         help
1891           Do not load image from SD or MMC
1892
1893 config ZBOOT_ROM_MMCIF
1894         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1895         help
1896           Load image from MMCIF hardware block.
1897
1898 config ZBOOT_ROM_SH_MOBILE_SDHI
1899         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1900         help
1901           Load image from SDHI hardware block
1902
1903 endchoice
1904
1905 config ARM_APPENDED_DTB
1906         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1907         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1908         help
1909           With this option, the boot code will look for a device tree binary
1910           (DTB) appended to zImage
1911           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1912
1913           This is meant as a backward compatibility convenience for those
1914           systems with a bootloader that can't be upgraded to accommodate
1915           the documented boot protocol using a device tree.
1916
1917           Beware that there is very little in terms of protection against
1918           this option being confused by leftover garbage in memory that might
1919           look like a DTB header after a reboot if no actual DTB is appended
1920           to zImage.  Do not leave this option active in a production kernel
1921           if you don't intend to always append a DTB.  Proper passing of the
1922           location into r2 of a bootloader provided DTB is always preferable
1923           to this option.
1924
1925 config ARM_ATAG_DTB_COMPAT
1926         bool "Supplement the appended DTB with traditional ATAG information"
1927         depends on ARM_APPENDED_DTB
1928         help
1929           Some old bootloaders can't be updated to a DTB capable one, yet
1930           they provide ATAGs with memory configuration, the ramdisk address,
1931           the kernel cmdline string, etc.  Such information is dynamically
1932           provided by the bootloader and can't always be stored in a static
1933           DTB.  To allow a device tree enabled kernel to be used with such
1934           bootloaders, this option allows zImage to extract the information
1935           from the ATAG list and store it at run time into the appended DTB.
1936
1937 choice
1938         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1939         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1940
1941 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1942         bool "Use bootloader kernel arguments if available"
1943         help
1944           Uses the command-line options passed by the boot loader instead of
1945           the device tree bootargs property. If the boot loader doesn't provide
1946           any, the device tree bootargs property will be used.
1947
1948 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1949         bool "Extend with bootloader kernel arguments"
1950         help
1951           The command-line arguments provided by the boot loader will be
1952           appended to the the device tree bootargs property.
1953
1954 endchoice
1955
1956 config CMDLINE
1957         string "Default kernel command string"
1958         default ""
1959         help
1960           On some architectures (EBSA110 and CATS), there is currently no way
1961           for the boot loader to pass arguments to the kernel. For these
1962           architectures, you should supply some command-line options at build
1963           time by entering them here. As a minimum, you should specify the
1964           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1965
1966 choice
1967         prompt "Kernel command line type" if CMDLINE != ""
1968         default CMDLINE_FROM_BOOTLOADER
1969
1970 config CMDLINE_FROM_BOOTLOADER
1971         bool "Use bootloader kernel arguments if available"
1972         help
1973           Uses the command-line options passed by the boot loader. If
1974           the boot loader doesn't provide any, the default kernel command
1975           string provided in CMDLINE will be used.
1976
1977 config CMDLINE_EXTEND
1978         bool "Extend bootloader kernel arguments"
1979         help
1980           The command-line arguments provided by the boot loader will be
1981           appended to the default kernel command string.
1982
1983 config CMDLINE_FORCE
1984         bool "Always use the default kernel command string"
1985         help
1986           Always use the default kernel command string, even if the boot
1987           loader passes other arguments to the kernel.
1988           This is useful if you cannot or don't want to change the
1989           command-line options your boot loader passes to the kernel.
1990 endchoice
1991
1992 config XIP_KERNEL
1993         bool "Kernel Execute-In-Place from ROM"
1994         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
1995         help
1996           Execute-In-Place allows the kernel to run from non-volatile storage
1997           directly addressable by the CPU, such as NOR flash. This saves RAM
1998           space since the text section of the kernel is not loaded from flash
1999           to RAM.  Read-write sections, such as the data section and stack,
2000           are still copied to RAM.  The XIP kernel is not compressed since
2001           it has to run directly from flash, so it will take more space to
2002           store it.  The flash address used to link the kernel object files,
2003           and for storing it, is configuration dependent. Therefore, if you
2004           say Y here, you must know the proper physical address where to
2005           store the kernel image depending on your own flash memory usage.
2006
2007           Also note that the make target becomes "make xipImage" rather than
2008           "make zImage" or "make Image".  The final kernel binary to put in
2009           ROM memory will be arch/arm/boot/xipImage.
2010
2011           If unsure, say N.
2012
2013 config XIP_PHYS_ADDR
2014         hex "XIP Kernel Physical Location"
2015         depends on XIP_KERNEL
2016         default "0x00080000"
2017         help
2018           This is the physical address in your flash memory the kernel will
2019           be linked for and stored to.  This address is dependent on your
2020           own flash usage.
2021
2022 config KEXEC
2023         bool "Kexec system call (EXPERIMENTAL)"
2024         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2025         help
2026           kexec is a system call that implements the ability to shutdown your
2027           current kernel, and to start another kernel.  It is like a reboot
2028           but it is independent of the system firmware.   And like a reboot
2029           you can start any kernel with it, not just Linux.
2030
2031           It is an ongoing process to be certain the hardware in a machine
2032           is properly shutdown, so do not be surprised if this code does not
2033           initially work for you.  It may help to enable device hotplugging
2034           support.
2035
2036 config ATAGS_PROC
2037         bool "Export atags in procfs"
2038         depends on KEXEC
2039         default y
2040         help
2041           Should the atags used to boot the kernel be exported in an "atags"
2042           file in procfs. Useful with kexec.
2043
2044 config CRASH_DUMP
2045         bool "Build kdump crash kernel (EXPERIMENTAL)"
2046         depends on EXPERIMENTAL
2047         help
2048           Generate crash dump after being started by kexec. This should
2049           be normally only set in special crash dump kernels which are
2050           loaded in the main kernel with kexec-tools into a specially
2051           reserved region and then later executed after a crash by
2052           kdump/kexec. The crash dump kernel must be compiled to a
2053           memory address not used by the main kernel
2054
2055           For more details see Documentation/kdump/kdump.txt
2056
2057 config AUTO_ZRELADDR
2058         bool "Auto calculation of the decompressed kernel image address"
2059         depends on !ZBOOT_ROM && !ARCH_U300
2060         help
2061           ZRELADDR is the physical address where the decompressed kernel
2062           image will be placed. If AUTO_ZRELADDR is selected, the address
2063           will be determined at run-time by masking the current IP with
2064           0xf8000000. This assumes the zImage being placed in the first 128MB
2065           from start of memory.
2066
2067 endmenu
2068
2069 menu "CPU Power Management"
2070
2071 if ARCH_HAS_CPUFREQ
2072
2073 source "drivers/cpufreq/Kconfig"
2074
2075 config CPU_FREQ_IMX
2076         tristate "CPUfreq driver for i.MX CPUs"
2077         depends on ARCH_MXC && CPU_FREQ
2078         select CPU_FREQ_TABLE
2079         help
2080           This enables the CPUfreq driver for i.MX CPUs.
2081
2082 config CPU_FREQ_SA1100
2083         bool
2084
2085 config CPU_FREQ_SA1110
2086         bool
2087
2088 config CPU_FREQ_INTEGRATOR
2089         tristate "CPUfreq driver for ARM Integrator CPUs"
2090         depends on ARCH_INTEGRATOR && CPU_FREQ
2091         default y
2092         help
2093           This enables the CPUfreq driver for ARM Integrator CPUs.
2094
2095           For details, take a look at <file:Documentation/cpu-freq>.
2096
2097           If in doubt, say Y.
2098
2099 config CPU_FREQ_PXA
2100         bool
2101         depends on CPU_FREQ && ARCH_PXA && PXA25x
2102         default y
2103         select CPU_FREQ_TABLE
2104         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2105
2106 config CPU_FREQ_S3C
2107         bool
2108         help
2109           Internal configuration node for common cpufreq on Samsung SoC
2110
2111 config CPU_FREQ_S3C24XX
2112         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2113         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2114         select CPU_FREQ_S3C
2115         help
2116           This enables the CPUfreq driver for the Samsung S3C24XX family
2117           of CPUs.
2118
2119           For details, take a look at <file:Documentation/cpu-freq>.
2120
2121           If in doubt, say N.
2122
2123 config CPU_FREQ_S3C24XX_PLL
2124         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2125         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2126         help
2127           Compile in support for changing the PLL frequency from the
2128           S3C24XX series CPUfreq driver. The PLL takes time to settle
2129           after a frequency change, so by default it is not enabled.
2130
2131           This also means that the PLL tables for the selected CPU(s) will
2132           be built which may increase the size of the kernel image.
2133
2134 config CPU_FREQ_S3C24XX_DEBUG
2135         bool "Debug CPUfreq Samsung driver core"
2136         depends on CPU_FREQ_S3C24XX
2137         help
2138           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2139
2140 config CPU_FREQ_S3C24XX_IODEBUG
2141         bool "Debug CPUfreq Samsung driver IO timing"
2142         depends on CPU_FREQ_S3C24XX
2143         help
2144           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2145
2146 config CPU_FREQ_S3C24XX_DEBUGFS
2147         bool "Export debugfs for CPUFreq"
2148         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2149         help
2150           Export status information via debugfs.
2151
2152 endif
2153
2154 source "drivers/cpuidle/Kconfig"
2155
2156 endmenu
2157
2158 menu "Floating point emulation"
2159
2160 comment "At least one emulation must be selected"
2161
2162 config FPE_NWFPE
2163         bool "NWFPE math emulation"
2164         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2165         ---help---
2166           Say Y to include the NWFPE floating point emulator in the kernel.
2167           This is necessary to run most binaries. Linux does not currently
2168           support floating point hardware so you need to say Y here even if
2169           your machine has an FPA or floating point co-processor podule.
2170
2171           You may say N here if you are going to load the Acorn FPEmulator
2172           early in the bootup.
2173
2174 config FPE_NWFPE_XP
2175         bool "Support extended precision"
2176         depends on FPE_NWFPE
2177         help
2178           Say Y to include 80-bit support in the kernel floating-point
2179           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2180           Note that gcc does not generate 80-bit operations by default,
2181           so in most cases this option only enlarges the size of the
2182           floating point emulator without any good reason.
2183
2184           You almost surely want to say N here.
2185
2186 config FPE_FASTFPE
2187         bool "FastFPE math emulation (EXPERIMENTAL)"
2188         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2189         ---help---
2190           Say Y here to include the FAST floating point emulator in the kernel.
2191           This is an experimental much faster emulator which now also has full
2192           precision for the mantissa.  It does not support any exceptions.
2193           It is very simple, and approximately 3-6 times faster than NWFPE.
2194
2195           It should be sufficient for most programs.  It may be not suitable
2196           for scientific calculations, but you have to check this for yourself.
2197           If you do not feel you need a faster FP emulation you should better
2198           choose NWFPE.
2199
2200 config VFP
2201         bool "VFP-format floating point maths"
2202         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2203         help
2204           Say Y to include VFP support code in the kernel. This is needed
2205           if your hardware includes a VFP unit.
2206
2207           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2208           release notes and additional status information.
2209
2210           Say N if your target does not have VFP hardware.
2211
2212 config VFPv3
2213         bool
2214         depends on VFP
2215         default y if CPU_V7
2216
2217 config NEON
2218         bool "Advanced SIMD (NEON) Extension support"
2219         depends on VFPv3 && CPU_V7
2220         help
2221           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2222           Extension.
2223
2224 endmenu
2225
2226 menu "Userspace binary formats"
2227
2228 source "fs/Kconfig.binfmt"
2229
2230 config ARTHUR
2231         tristate "RISC OS personality"
2232         depends on !AEABI
2233         help
2234           Say Y here to include the kernel code necessary if you want to run
2235           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2236           experimental; if this sounds frightening, say N and sleep in peace.
2237           You can also say M here to compile this support as a module (which
2238           will be called arthur).
2239
2240 endmenu
2241
2242 menu "Power management options"
2243
2244 source "kernel/power/Kconfig"
2245
2246 config ARCH_SUSPEND_POSSIBLE
2247         depends on !ARCH_S5PC100
2248         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2249                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2250         def_bool y
2251
2252 config ARM_CPU_SUSPEND
2253         def_bool PM_SLEEP
2254
2255 endmenu
2256
2257 source "net/Kconfig"
2258
2259 source "drivers/Kconfig"
2260
2261 source "fs/Kconfig"
2262
2263 source "arch/arm/Kconfig.debug"
2264
2265 source "security/Kconfig"
2266
2267 source "crypto/Kconfig"
2268
2269 source "lib/Kconfig"