arch/arm/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0
   2 config ARM
   3         bool
   4         default y
   5         select ARCH_32BIT_OFF_T
   6         select ARCH_HAS_BINFMT_FLAT
   7         select ARCH_HAS_DEBUG_VIRTUAL if MMU
   8         select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
   9         select ARCH_HAS_ELF_RANDOMIZE
  10         select ARCH_HAS_FORTIFY_SOURCE
  11         select ARCH_HAS_KEEPINITRD
  12         select ARCH_HAS_KCOV
  13         select ARCH_HAS_MEMBARRIER_SYNC_CORE
  14         select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
  15         select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
  16         select ARCH_HAS_PHYS_TO_DMA
  17         select ARCH_HAS_SETUP_DMA_OPS
  18         select ARCH_HAS_SET_MEMORY
  19         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  20         select ARCH_HAS_STRICT_MODULE_RWX if MMU
  21         select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
  22         select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
  23         select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
  24         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  25         select ARCH_HAVE_CUSTOM_GPIO_H
  26         select ARCH_HAS_GCOV_PROFILE_ALL
  27         select ARCH_KEEP_MEMBLOCK
  28         select ARCH_MIGHT_HAVE_PC_PARPORT
  29         select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
  30         select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  31         select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  32         select ARCH_SUPPORTS_ATOMIC_RMW
  33         select ARCH_USE_BUILTIN_BSWAP
  34         select ARCH_USE_CMPXCHG_LOCKREF
  35         select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
  36         select ARCH_WANT_IPC_PARSE_VERSION
  37         select ARCH_WANT_LD_ORPHAN_WARN
  38         select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
  39         select BUILDTIME_TABLE_SORT if MMU
  40         select CLONE_BACKWARDS
  41         select CPU_PM if SUSPEND || CPU_IDLE
  42         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  43         select DMA_DECLARE_COHERENT
  44         select DMA_OPS
  45         select DMA_REMAP if MMU
  46         select EDAC_SUPPORT
  47         select EDAC_ATOMIC_SCRUB
  48         select GENERIC_ALLOCATOR
  49         select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  50         select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
  51         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  52         select GENERIC_IRQ_IPI if SMP
  53         select GENERIC_CPU_AUTOPROBE
  54         select GENERIC_EARLY_IOREMAP
  55         select GENERIC_IDLE_POLL_SETUP
  56         select GENERIC_IRQ_PROBE
  57         select GENERIC_IRQ_SHOW
  58         select GENERIC_IRQ_SHOW_LEVEL
  59         select GENERIC_LIB_DEVMEM_IS_ALLOWED
  60         select GENERIC_PCI_IOMAP
  61         select GENERIC_SCHED_CLOCK
  62         select GENERIC_SMP_IDLE_THREAD
  63         select GENERIC_STRNCPY_FROM_USER
  64         select GENERIC_STRNLEN_USER
  65         select HANDLE_DOMAIN_IRQ
  66         select HARDIRQS_SW_RESEND
  67         select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
  68         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  69         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  70         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  71         select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
  72         select HAVE_ARCH_MMAP_RND_BITS if MMU
  73         select HAVE_ARCH_PFN_VALID
  74         select HAVE_ARCH_SECCOMP
  75         select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
  76         select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  77         select HAVE_ARCH_TRACEHOOK
  78         select HAVE_ARM_SMCCC if CPU_V7
  79         select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  80         select HAVE_CONTEXT_TRACKING
  81         select HAVE_C_RECORDMCOUNT
  82         select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
  83         select HAVE_DMA_CONTIGUOUS if MMU
  84         select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  85         select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  86         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  87         select HAVE_EXIT_THREAD
  88         select HAVE_FAST_GUP if ARM_LPAE
  89         select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
  90         select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
  91         select HAVE_FUNCTION_TRACER if !XIP_KERNEL
  92         select HAVE_GCC_PLUGINS
  93         select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
  94         select HAVE_IDE if PCI || ISA || PCMCIA
  95         select HAVE_IRQ_TIME_ACCOUNTING
  96         select HAVE_KERNEL_GZIP
  97         select HAVE_KERNEL_LZ4
  98         select HAVE_KERNEL_LZMA
  99         select HAVE_KERNEL_LZO
 100         select HAVE_KERNEL_XZ
 101         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
 102         select HAVE_KRETPROBES if HAVE_KPROBES
 103         select HAVE_MOD_ARCH_SPECIFIC
 104         select HAVE_NMI
 105         select HAVE_OPROFILE if HAVE_PERF_EVENTS
 106         select HAVE_OPTPROBES if !THUMB2_KERNEL
 107         select HAVE_PERF_EVENTS
 108         select HAVE_PERF_REGS
 109         select HAVE_PERF_USER_STACK_DUMP
 110         select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
 111         select HAVE_REGS_AND_STACK_ACCESS_API
 112         select HAVE_RSEQ
 113         select HAVE_STACKPROTECTOR
 114         select HAVE_SYSCALL_TRACEPOINTS
 115         select HAVE_UID16
 116         select HAVE_VIRT_CPU_ACCOUNTING_GEN
 117         select IRQ_FORCED_THREADING
 118         select MODULES_USE_ELF_REL
 119         select NEED_DMA_MAP_STATE
 120         select OF_EARLY_FLATTREE if OF
 121         select OLD_SIGACTION
 122         select OLD_SIGSUSPEND3
 123         select PCI_SYSCALL if PCI
 124         select PERF_USE_VMALLOC
 125         select RTC_LIB
 126         select SET_FS
 127         select SYS_SUPPORTS_APM_EMULATION
 128         # Above selects are sorted alphabetically; please add new ones
 129         # according to that.  Thanks.
 130         help
 131           The ARM series is a line of low-power-consumption RISC chip designs
 132           licensed by ARM Ltd and targeted at embedded applications and
 133           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 134           manufactured, but legacy ARM-based PC hardware remains popular in
 135           Europe.  There is an ARM Linux project with a web page at
 136           <http://www.arm.linux.org.uk/>.
 137
 138 config ARM_HAS_SG_CHAIN
 139         bool
 140
 141 config ARM_DMA_USE_IOMMU
 142         bool
 143         select ARM_HAS_SG_CHAIN
 144         select NEED_SG_DMA_LENGTH
 145
 146 if ARM_DMA_USE_IOMMU
 147
 148 config ARM_DMA_IOMMU_ALIGNMENT
 149         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 150         range 4 9
 151         default 8
 152         help
 153           DMA mapping framework by default aligns all buffers to the smallest
 154           PAGE_SIZE order which is greater than or equal to the requested buffer
 155           size. This works well for buffers up to a few hundreds kilobytes, but
 156           for larger buffers it just a waste of address space. Drivers which has
 157           relatively small addressing window (like 64Mib) might run out of
 158           virtual space with just a few allocations.
 159
 160           With this parameter you can specify the maximum PAGE_SIZE order for
 161           DMA IOMMU buffers. Larger buffers will be aligned only to this
 162           specified order. The order is expressed as a power of two multiplied
 163           by the PAGE_SIZE.
 164
 165 endif
 166
 167 config SYS_SUPPORTS_APM_EMULATION
 168         bool
 169
 170 config HAVE_TCM
 171         bool
 172         select GENERIC_ALLOCATOR
 173
 174 config HAVE_PROC_CPU
 175         bool
 176
 177 config NO_IOPORT_MAP
 178         bool
 179
 180 config SBUS
 181         bool
 182
 183 config STACKTRACE_SUPPORT
 184         bool
 185         default y
 186
 187 config LOCKDEP_SUPPORT
 188         bool
 189         default y
 190
 191 config TRACE_IRQFLAGS_SUPPORT
 192         bool
 193         default !CPU_V7M
 194
 195 config ARCH_HAS_ILOG2_U32
 196         bool
 197
 198 config ARCH_HAS_ILOG2_U64
 199         bool
 200
 201 config ARCH_HAS_BANDGAP
 202         bool
 203
 204 config FIX_EARLYCON_MEM
 205         def_bool y if MMU
 206
 207 config GENERIC_HWEIGHT
 208         bool
 209         default y
 210
 211 config GENERIC_CALIBRATE_DELAY
 212         bool
 213         default y
 214
 215 config ARCH_MAY_HAVE_PC_FDC
 216         bool
 217
 218 config ZONE_DMA
 219         bool
 220
 221 config ARCH_SUPPORTS_UPROBES
 222         def_bool y
 223
 224 config ARCH_HAS_DMA_SET_COHERENT_MASK
 225         bool
 226
 227 config GENERIC_ISA_DMA
 228         bool
 229
 230 config FIQ
 231         bool
 232
 233 config NEED_RET_TO_USER
 234         bool
 235
 236 config ARCH_MTD_XIP
 237         bool
 238
 239 config ARM_PATCH_PHYS_VIRT
 240         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 241         default y
 242         depends on !XIP_KERNEL && MMU
 243         help
 244           Patch phys-to-virt and virt-to-phys translation functions at
 245           boot and module load time according to the position of the
 246           kernel in system memory.
 247
 248           This can only be used with non-XIP MMU kernels where the base
 249           of physical memory is at a 2 MiB boundary.
 250
 251           Only disable this option if you know that you do not require
 252           this feature (eg, building a kernel for a single machine) and
 253           you need to shrink the kernel to the minimal size.
 254
 255 config NEED_MACH_IO_H
 256         bool
 257         help
 258           Select this when mach/io.h is required to provide special
 259           definitions for this platform.  The need for mach/io.h should
 260           be avoided when possible.
 261
 262 config NEED_MACH_MEMORY_H
 263         bool
 264         help
 265           Select this when mach/memory.h is required to provide special
 266           definitions for this platform.  The need for mach/memory.h should
 267           be avoided when possible.
 268
 269 config PHYS_OFFSET
 270         hex "Physical address of main memory" if MMU
 271         depends on !ARM_PATCH_PHYS_VIRT
 272         default DRAM_BASE if !MMU
 273         default 0x00000000 if ARCH_FOOTBRIDGE
 274         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 275         default 0x20000000 if ARCH_S5PV210
 276         default 0xc0000000 if ARCH_SA1100
 277         help
 278           Please provide the physical address corresponding to the
 279           location of main memory in your system.
 280
 281 config GENERIC_BUG
 282         def_bool y
 283         depends on BUG
 284
 285 config PGTABLE_LEVELS
 286         int
 287         default 3 if ARM_LPAE
 288         default 2
 289
 290 menu "System Type"
 291
 292 config MMU
 293         bool "MMU-based Paged Memory Management Support"
 294         default y
 295         help
 296           Select if you want MMU-based virtualised addressing space
 297           support by paged memory management. If unsure, say 'Y'.
 298
 299 config ARCH_MMAP_RND_BITS_MIN
 300         default 8
 301
 302 config ARCH_MMAP_RND_BITS_MAX
 303         default 14 if PAGE_OFFSET=0x40000000
 304         default 15 if PAGE_OFFSET=0x80000000
 305         default 16
 306
 307 #
 308 # The "ARM system type" choice list is ordered alphabetically by option
 309 # text.  Please add new entries in the option alphabetic order.
 310 #
 311 choice
 312         prompt "ARM system type"
 313         default ARM_SINGLE_ARMV7M if !MMU
 314         default ARCH_MULTIPLATFORM if MMU
 315
 316 config ARCH_MULTIPLATFORM
 317         bool "Allow multiple platforms to be selected"
 318         depends on MMU
 319         select ARCH_FLATMEM_ENABLE
 320         select ARCH_SPARSEMEM_ENABLE
 321         select ARCH_SELECT_MEMORY_MODEL
 322         select ARM_HAS_SG_CHAIN
 323         select ARM_PATCH_PHYS_VIRT
 324         select AUTO_ZRELADDR
 325         select TIMER_OF
 326         select COMMON_CLK
 327         select GENERIC_IRQ_MULTI_HANDLER
 328         select HAVE_PCI
 329         select PCI_DOMAINS_GENERIC if PCI
 330         select SPARSE_IRQ
 331         select USE_OF
 332
 333 config ARM_SINGLE_ARMV7M
 334         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 335         depends on !MMU
 336         select ARM_NVIC
 337         select AUTO_ZRELADDR
 338         select TIMER_OF
 339         select COMMON_CLK
 340         select CPU_V7M
 341         select NO_IOPORT_MAP
 342         select SPARSE_IRQ
 343         select USE_OF
 344
 345 config ARCH_EP93XX
 346         bool "EP93xx-based"
 347         select ARCH_SPARSEMEM_ENABLE
 348         select ARM_AMBA
 349         imply ARM_PATCH_PHYS_VIRT
 350         select ARM_VIC
 351         select AUTO_ZRELADDR
 352         select CLKDEV_LOOKUP
 353         select CLKSRC_MMIO
 354         select CPU_ARM920T
 355         select GPIOLIB
 356         select HAVE_LEGACY_CLK
 357         help
 358           This enables support for the Cirrus EP93xx series of CPUs.
 359
 360 config ARCH_FOOTBRIDGE
 361         bool "FootBridge"
 362         select CPU_SA110
 363         select FOOTBRIDGE
 364         select HAVE_IDE
 365         select NEED_MACH_IO_H if !MMU
 366         select NEED_MACH_MEMORY_H
 367         help
 368           Support for systems based on the DC21285 companion chip
 369           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 370
 371 config ARCH_IOP32X
 372         bool "IOP32x-based"
 373         depends on MMU
 374         select CPU_XSCALE
 375         select GPIO_IOP
 376         select GPIOLIB
 377         select NEED_RET_TO_USER
 378         select FORCE_PCI
 379         select PLAT_IOP
 380         help
 381           Support for Intel's 80219 and IOP32X (XScale) family of
 382           processors.
 383
 384 config ARCH_IXP4XX
 385         bool "IXP4xx-based"
 386         depends on MMU
 387         select ARCH_HAS_DMA_SET_COHERENT_MASK
 388         select ARCH_SUPPORTS_BIG_ENDIAN
 389         select CPU_XSCALE
 390         select DMABOUNCE if PCI
 391         select GENERIC_IRQ_MULTI_HANDLER
 392         select GPIO_IXP4XX
 393         select GPIOLIB
 394         select HAVE_PCI
 395         select IXP4XX_IRQ
 396         select IXP4XX_TIMER
 397         select NEED_MACH_IO_H
 398         select USB_EHCI_BIG_ENDIAN_DESC
 399         select USB_EHCI_BIG_ENDIAN_MMIO
 400         help
 401           Support for Intel's IXP4XX (XScale) family of processors.
 402
 403 config ARCH_DOVE
 404         bool "Marvell Dove"
 405         select CPU_PJ4
 406         select GENERIC_IRQ_MULTI_HANDLER
 407         select GPIOLIB
 408         select HAVE_PCI
 409         select MVEBU_MBUS
 410         select PINCTRL
 411         select PINCTRL_DOVE
 412         select PLAT_ORION_LEGACY
 413         select SPARSE_IRQ
 414         select PM_GENERIC_DOMAINS if PM
 415         help
 416           Support for the Marvell Dove SoC 88AP510
 417
 418 config ARCH_PXA
 419         bool "PXA2xx/PXA3xx-based"
 420         depends on MMU
 421         select ARCH_MTD_XIP
 422         select ARM_CPU_SUSPEND if PM
 423         select AUTO_ZRELADDR
 424         select COMMON_CLK
 425         select CLKSRC_PXA
 426         select CLKSRC_MMIO
 427         select TIMER_OF
 428         select CPU_XSCALE if !CPU_XSC3
 429         select GENERIC_IRQ_MULTI_HANDLER
 430         select GPIO_PXA
 431         select GPIOLIB
 432         select HAVE_IDE
 433         select IRQ_DOMAIN
 434         select PLAT_PXA
 435         select SPARSE_IRQ
 436         help
 437           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 438
 439 config ARCH_RPC
 440         bool "RiscPC"
 441         depends on MMU
 442         select ARCH_ACORN
 443         select ARCH_MAY_HAVE_PC_FDC
 444         select ARCH_SPARSEMEM_ENABLE
 445         select ARM_HAS_SG_CHAIN
 446         select CPU_SA110
 447         select FIQ
 448         select HAVE_IDE
 449         select HAVE_PATA_PLATFORM
 450         select ISA_DMA_API
 451         select LEGACY_TIMER_TICK
 452         select NEED_MACH_IO_H
 453         select NEED_MACH_MEMORY_H
 454         select NO_IOPORT_MAP
 455         help
 456           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 457           CD-ROM interface, serial and parallel port, and the floppy drive.
 458
 459 config ARCH_SA1100
 460         bool "SA1100-based"
 461         select ARCH_MTD_XIP
 462         select ARCH_SPARSEMEM_ENABLE
 463         select CLKSRC_MMIO
 464         select CLKSRC_PXA
 465         select TIMER_OF if OF
 466         select COMMON_CLK
 467         select CPU_FREQ
 468         select CPU_SA1100
 469         select GENERIC_IRQ_MULTI_HANDLER
 470         select GPIOLIB
 471         select HAVE_IDE
 472         select IRQ_DOMAIN
 473         select ISA
 474         select NEED_MACH_MEMORY_H
 475         select SPARSE_IRQ
 476         help
 477           Support for StrongARM 11x0 based boards.
 478
 479 config ARCH_S3C24XX
 480         bool "Samsung S3C24XX SoCs"
 481         select ATAGS
 482         select CLKSRC_SAMSUNG_PWM
 483         select GPIO_SAMSUNG
 484         select GPIOLIB
 485         select GENERIC_IRQ_MULTI_HANDLER
 486         select HAVE_S3C2410_I2C if I2C
 487         select HAVE_S3C_RTC if RTC_CLASS
 488         select NEED_MACH_IO_H
 489         select S3C2410_WATCHDOG
 490         select SAMSUNG_ATAGS
 491         select USE_OF
 492         select WATCHDOG
 493         help
 494           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 495           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 496           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 497           Samsung SMDK2410 development board (and derivatives).
 498
 499 config ARCH_OMAP1
 500         bool "TI OMAP1"
 501         depends on MMU
 502         select ARCH_OMAP
 503         select CLKDEV_LOOKUP
 504         select CLKSRC_MMIO
 505         select GENERIC_IRQ_CHIP
 506         select GENERIC_IRQ_MULTI_HANDLER
 507         select GPIOLIB
 508         select HAVE_IDE
 509         select HAVE_LEGACY_CLK
 510         select IRQ_DOMAIN
 511         select NEED_MACH_IO_H if PCCARD
 512         select NEED_MACH_MEMORY_H
 513         select SPARSE_IRQ
 514         help
 515           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 516
 517 endchoice
 518
 519 menu "Multiple platform selection"
 520         depends on ARCH_MULTIPLATFORM
 521
 522 comment "CPU Core family selection"
 523
 524 config ARCH_MULTI_V4
 525         bool "ARMv4 based platforms (FA526)"
 526         depends on !ARCH_MULTI_V6_V7
 527         select ARCH_MULTI_V4_V5
 528         select CPU_FA526
 529
 530 config ARCH_MULTI_V4T
 531         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 532         depends on !ARCH_MULTI_V6_V7
 533         select ARCH_MULTI_V4_V5
 534         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 535                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 536                 CPU_ARM925T || CPU_ARM940T)
 537
 538 config ARCH_MULTI_V5
 539         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 540         depends on !ARCH_MULTI_V6_V7
 541         select ARCH_MULTI_V4_V5
 542         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 543                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 544                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 545
 546 config ARCH_MULTI_V4_V5
 547         bool
 548
 549 config ARCH_MULTI_V6
 550         bool "ARMv6 based platforms (ARM11)"
 551         select ARCH_MULTI_V6_V7
 552         select CPU_V6K
 553
 554 config ARCH_MULTI_V7
 555         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 556         default y
 557         select ARCH_MULTI_V6_V7
 558         select CPU_V7
 559         select HAVE_SMP
 560
 561 config ARCH_MULTI_V6_V7
 562         bool
 563         select MIGHT_HAVE_CACHE_L2X0
 564
 565 config ARCH_MULTI_CPU_AUTO
 566         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 567         select ARCH_MULTI_V5
 568
 569 endmenu
 570
 571 config ARCH_VIRT
 572         bool "Dummy Virtual Machine"
 573         depends on ARCH_MULTI_V7
 574         select ARM_AMBA
 575         select ARM_GIC
 576         select ARM_GIC_V2M if PCI
 577         select ARM_GIC_V3
 578         select ARM_GIC_V3_ITS if PCI
 579         select ARM_PSCI
 580         select HAVE_ARM_ARCH_TIMER
 581         select ARCH_SUPPORTS_BIG_ENDIAN
 582
 583 #
 584 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 585 # Kconfigs may be included either alphabetically (according to the
 586 # plat- suffix) or along side the corresponding mach-* source.
 587 #
 588 source "arch/arm/mach-actions/Kconfig"
 589
 590 source "arch/arm/mach-alpine/Kconfig"
 591
 592 source "arch/arm/mach-artpec/Kconfig"
 593
 594 source "arch/arm/mach-asm9260/Kconfig"
 595
 596 source "arch/arm/mach-aspeed/Kconfig"
 597
 598 source "arch/arm/mach-at91/Kconfig"
 599
 600 source "arch/arm/mach-axxia/Kconfig"
 601
 602 source "arch/arm/mach-bcm/Kconfig"
 603
 604 source "arch/arm/mach-berlin/Kconfig"
 605
 606 source "arch/arm/mach-clps711x/Kconfig"
 607
 608 source "arch/arm/mach-cns3xxx/Kconfig"
 609
 610 source "arch/arm/mach-davinci/Kconfig"
 611
 612 source "arch/arm/mach-digicolor/Kconfig"
 613
 614 source "arch/arm/mach-dove/Kconfig"
 615
 616 source "arch/arm/mach-ep93xx/Kconfig"
 617
 618 source "arch/arm/mach-exynos/Kconfig"
 619
 620 source "arch/arm/mach-footbridge/Kconfig"
 621
 622 source "arch/arm/mach-gemini/Kconfig"
 623
 624 source "arch/arm/mach-highbank/Kconfig"
 625
 626 source "arch/arm/mach-hisi/Kconfig"
 627
 628 source "arch/arm/mach-imx/Kconfig"
 629
 630 source "arch/arm/mach-integrator/Kconfig"
 631
 632 source "arch/arm/mach-iop32x/Kconfig"
 633
 634 source "arch/arm/mach-ixp4xx/Kconfig"
 635
 636 source "arch/arm/mach-keystone/Kconfig"
 637
 638 source "arch/arm/mach-lpc32xx/Kconfig"
 639
 640 source "arch/arm/mach-mediatek/Kconfig"
 641
 642 source "arch/arm/mach-meson/Kconfig"
 643
 644 source "arch/arm/mach-milbeaut/Kconfig"
 645
 646 source "arch/arm/mach-mmp/Kconfig"
 647
 648 source "arch/arm/mach-moxart/Kconfig"
 649
 650 source "arch/arm/mach-mstar/Kconfig"
 651
 652 source "arch/arm/mach-mv78xx0/Kconfig"
 653
 654 source "arch/arm/mach-mvebu/Kconfig"
 655
 656 source "arch/arm/mach-mxs/Kconfig"
 657
 658 source "arch/arm/mach-nomadik/Kconfig"
 659
 660 source "arch/arm/mach-npcm/Kconfig"
 661
 662 source "arch/arm/mach-nspire/Kconfig"
 663
 664 source "arch/arm/plat-omap/Kconfig"
 665
 666 source "arch/arm/mach-omap1/Kconfig"
 667
 668 source "arch/arm/mach-omap2/Kconfig"
 669
 670 source "arch/arm/mach-orion5x/Kconfig"
 671
 672 source "arch/arm/mach-oxnas/Kconfig"
 673
 674 source "arch/arm/mach-picoxcell/Kconfig"
 675
 676 source "arch/arm/mach-prima2/Kconfig"
 677
 678 source "arch/arm/mach-pxa/Kconfig"
 679 source "arch/arm/plat-pxa/Kconfig"
 680
 681 source "arch/arm/mach-qcom/Kconfig"
 682
 683 source "arch/arm/mach-rda/Kconfig"
 684
 685 source "arch/arm/mach-realtek/Kconfig"
 686
 687 source "arch/arm/mach-realview/Kconfig"
 688
 689 source "arch/arm/mach-rockchip/Kconfig"
 690
 691 source "arch/arm/mach-s3c/Kconfig"
 692
 693 source "arch/arm/mach-s5pv210/Kconfig"
 694
 695 source "arch/arm/mach-sa1100/Kconfig"
 696
 697 source "arch/arm/mach-shmobile/Kconfig"
 698
 699 source "arch/arm/mach-socfpga/Kconfig"
 700
 701 source "arch/arm/mach-spear/Kconfig"
 702
 703 source "arch/arm/mach-sti/Kconfig"
 704
 705 source "arch/arm/mach-stm32/Kconfig"
 706
 707 source "arch/arm/mach-sunxi/Kconfig"
 708
 709 source "arch/arm/mach-tango/Kconfig"
 710
 711 source "arch/arm/mach-tegra/Kconfig"
 712
 713 source "arch/arm/mach-u300/Kconfig"
 714
 715 source "arch/arm/mach-uniphier/Kconfig"
 716
 717 source "arch/arm/mach-ux500/Kconfig"
 718
 719 source "arch/arm/mach-versatile/Kconfig"
 720
 721 source "arch/arm/mach-vexpress/Kconfig"
 722
 723 source "arch/arm/mach-vt8500/Kconfig"
 724
 725 source "arch/arm/mach-zx/Kconfig"
 726
 727 source "arch/arm/mach-zynq/Kconfig"
 728
 729 # ARMv7-M architecture
 730 config ARCH_EFM32
 731         bool "Energy Micro efm32"
 732         depends on ARM_SINGLE_ARMV7M
 733         select GPIOLIB
 734         help
 735           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 736           processors.
 737
 738 config ARCH_LPC18XX
 739         bool "NXP LPC18xx/LPC43xx"
 740         depends on ARM_SINGLE_ARMV7M
 741         select ARCH_HAS_RESET_CONTROLLER
 742         select ARM_AMBA
 743         select CLKSRC_LPC32XX
 744         select PINCTRL
 745         help
 746           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 747           high performance microcontrollers.
 748
 749 config ARCH_MPS2
 750         bool "ARM MPS2 platform"
 751         depends on ARM_SINGLE_ARMV7M
 752         select ARM_AMBA
 753         select CLKSRC_MPS2
 754         help
 755           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 756           with a range of available cores like Cortex-M3/M4/M7.
 757
 758           Please, note that depends which Application Note is used memory map
 759           for the platform may vary, so adjustment of RAM base might be needed.
 760
 761 # Definitions to make life easier
 762 config ARCH_ACORN
 763         bool
 764
 765 config PLAT_IOP
 766         bool
 767
 768 config PLAT_ORION
 769         bool
 770         select CLKSRC_MMIO
 771         select COMMON_CLK
 772         select GENERIC_IRQ_CHIP
 773         select IRQ_DOMAIN
 774
 775 config PLAT_ORION_LEGACY
 776         bool
 777         select PLAT_ORION
 778
 779 config PLAT_PXA
 780         bool
 781
 782 config PLAT_VERSATILE
 783         bool
 784
 785 source "arch/arm/mm/Kconfig"
 786
 787 config IWMMXT
 788         bool "Enable iWMMXt support"
 789         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 790         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 791         help
 792           Enable support for iWMMXt context switching at run time if
 793           running on a CPU that supports it.
 794
 795 if !MMU
 796 source "arch/arm/Kconfig-nommu"
 797 endif
 798
 799 config PJ4B_ERRATA_4742
 800         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 801         depends on CPU_PJ4B && MACH_ARMADA_370
 802         default y
 803         help
 804           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 805           Event (WFE) IDLE states, a specific timing sensitivity exists between
 806           the retiring WFI/WFE instructions and the newly issued subsequent
 807           instructions.  This sensitivity can result in a CPU hang scenario.
 808           Workaround:
 809           The software must insert either a Data Synchronization Barrier (DSB)
 810           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 811           instruction
 812
 813 config ARM_ERRATA_326103
 814         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 815         depends on CPU_V6
 816         help
 817           Executing a SWP instruction to read-only memory does not set bit 11
 818           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 819           treat the access as a read, preventing a COW from occurring and
 820           causing the faulting task to livelock.
 821
 822 config ARM_ERRATA_411920
 823         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 824         depends on CPU_V6 || CPU_V6K
 825         help
 826           Invalidation of the Instruction Cache operation can
 827           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 828           It does not affect the MPCore. This option enables the ARM Ltd.
 829           recommended workaround.
 830
 831 config ARM_ERRATA_430973
 832         bool "ARM errata: Stale prediction on replaced interworking branch"
 833         depends on CPU_V7
 834         help
 835           This option enables the workaround for the 430973 Cortex-A8
 836           r1p* erratum. If a code sequence containing an ARM/Thumb
 837           interworking branch is replaced with another code sequence at the
 838           same virtual address, whether due to self-modifying code or virtual
 839           to physical address re-mapping, Cortex-A8 does not recover from the
 840           stale interworking branch prediction. This results in Cortex-A8
 841           executing the new code sequence in the incorrect ARM or Thumb state.
 842           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 843           and also flushes the branch target cache at every context switch.
 844           Note that setting specific bits in the ACTLR register may not be
 845           available in non-secure mode.
 846
 847 config ARM_ERRATA_458693
 848         bool "ARM errata: Processor deadlock when a false hazard is created"
 849         depends on CPU_V7
 850         depends on !ARCH_MULTIPLATFORM
 851         help
 852           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 853           erratum. For very specific sequences of memory operations, it is
 854           possible for a hazard condition intended for a cache line to instead
 855           be incorrectly associated with a different cache line. This false
 856           hazard might then cause a processor deadlock. The workaround enables
 857           the L1 caching of the NEON accesses and disables the PLD instruction
 858           in the ACTLR register. Note that setting specific bits in the ACTLR
 859           register may not be available in non-secure mode.
 860
 861 config ARM_ERRATA_460075
 862         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
 863         depends on CPU_V7
 864         depends on !ARCH_MULTIPLATFORM
 865         help
 866           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
 867           erratum. Any asynchronous access to the L2 cache may encounter a
 868           situation in which recent store transactions to the L2 cache are lost
 869           and overwritten with stale memory contents from external memory. The
 870           workaround disables the write-allocate mode for the L2 cache via the
 871           ACTLR register. Note that setting specific bits in the ACTLR register
 872           may not be available in non-secure mode.
 873
 874 config ARM_ERRATA_742230
 875         bool "ARM errata: DMB operation may be faulty"
 876         depends on CPU_V7 && SMP
 877         depends on !ARCH_MULTIPLATFORM
 878         help
 879           This option enables the workaround for the 742230 Cortex-A9
 880           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
 881           between two write operations may not ensure the correct visibility
 882           ordering of the two writes. This workaround sets a specific bit in
 883           the diagnostic register of the Cortex-A9 which causes the DMB
 884           instruction to behave as a DSB, ensuring the correct behaviour of
 885           the two writes.
 886
 887 config ARM_ERRATA_742231
 888         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
 889         depends on CPU_V7 && SMP
 890         depends on !ARCH_MULTIPLATFORM
 891         help
 892           This option enables the workaround for the 742231 Cortex-A9
 893           (r2p0..r2p2) erratum. Under certain conditions, specific to the
 894           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
 895           accessing some data located in the same cache line, may get corrupted
 896           data due to bad handling of the address hazard when the line gets
 897           replaced from one of the CPUs at the same time as another CPU is
 898           accessing it. This workaround sets specific bits in the diagnostic
 899           register of the Cortex-A9 which reduces the linefill issuing
 900           capabilities of the processor.
 901
 902 config ARM_ERRATA_643719
 903         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
 904         depends on CPU_V7 && SMP
 905         default y
 906         help
 907           This option enables the workaround for the 643719 Cortex-A9 (prior to
 908           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
 909           register returns zero when it should return one. The workaround
 910           corrects this value, ensuring cache maintenance operations which use
 911           it behave as intended and avoiding data corruption.
 912
 913 config ARM_ERRATA_720789
 914         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
 915         depends on CPU_V7
 916         help
 917           This option enables the workaround for the 720789 Cortex-A9 (prior to
 918           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
 919           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
 920           As a consequence of this erratum, some TLB entries which should be
 921           invalidated are not, resulting in an incoherency in the system page
 922           tables. The workaround changes the TLB flushing routines to invalidate
 923           entries regardless of the ASID.
 924
 925 config ARM_ERRATA_743622
 926         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
 927         depends on CPU_V7
 928         depends on !ARCH_MULTIPLATFORM
 929         help
 930           This option enables the workaround for the 743622 Cortex-A9
 931           (r2p*) erratum. Under very rare conditions, a faulty
 932           optimisation in the Cortex-A9 Store Buffer may lead to data
 933           corruption. This workaround sets a specific bit in the diagnostic
 934           register of the Cortex-A9 which disables the Store Buffer
 935           optimisation, preventing the defect from occurring. This has no
 936           visible impact on the overall performance or power consumption of the
 937           processor.
 938
 939 config ARM_ERRATA_751472
 940         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
 941         depends on CPU_V7
 942         depends on !ARCH_MULTIPLATFORM
 943         help
 944           This option enables the workaround for the 751472 Cortex-A9 (prior
 945           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
 946           completion of a following broadcasted operation if the second
 947           operation is received by a CPU before the ICIALLUIS has completed,
 948           potentially leading to corrupted entries in the cache or TLB.
 949
 950 config ARM_ERRATA_754322
 951         bool "ARM errata: possible faulty MMU translations following an ASID switch"
 952         depends on CPU_V7
 953         help
 954           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
 955           r3p*) erratum. A speculative memory access may cause a page table walk
 956           which starts prior to an ASID switch but completes afterwards. This
 957           can populate the micro-TLB with a stale entry which may be hit with
 958           the new ASID. This workaround places two dsb instructions in the mm
 959           switching code so that no page table walks can cross the ASID switch.
 960
 961 config ARM_ERRATA_754327
 962         bool "ARM errata: no automatic Store Buffer drain"
 963         depends on CPU_V7 && SMP
 964         help
 965           This option enables the workaround for the 754327 Cortex-A9 (prior to
 966           r2p0) erratum. The Store Buffer does not have any automatic draining
 967           mechanism and therefore a livelock may occur if an external agent
 968           continuously polls a memory location waiting to observe an update.
 969           This workaround defines cpu_relax() as smp_mb(), preventing correctly
 970           written polling loops from denying visibility of updates to memory.
 971
 972 config ARM_ERRATA_364296
 973         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
 974         depends on CPU_V6
 975         help
 976           This options enables the workaround for the 364296 ARM1136
 977           r0p2 erratum (possible cache data corruption with
 978           hit-under-miss enabled). It sets the undocumented bit 31 in
 979           the auxiliary control register and the FI bit in the control
 980           register, thus disabling hit-under-miss without putting the
 981           processor into full low interrupt latency mode. ARM11MPCore
 982           is not affected.
 983
 984 config ARM_ERRATA_764369
 985         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
 986         depends on CPU_V7 && SMP
 987         help
 988           This option enables the workaround for erratum 764369
 989           affecting Cortex-A9 MPCore with two or more processors (all
 990           current revisions). Under certain timing circumstances, a data
 991           cache line maintenance operation by MVA targeting an Inner
 992           Shareable memory region may fail to proceed up to either the
 993           Point of Coherency or to the Point of Unification of the
 994           system. This workaround adds a DSB instruction before the
 995           relevant cache maintenance functions and sets a specific bit
 996           in the diagnostic control register of the SCU.
 997
 998 config ARM_ERRATA_775420
 999        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1000        depends on CPU_V7
1001        help
1002          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1003          r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1004          operation aborts with MMU exception, it might cause the processor
1005          to deadlock. This workaround puts DSB before executing ISB if
1006          an abort may occur on cache maintenance.
1007
1008 config ARM_ERRATA_798181
1009         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1010         depends on CPU_V7 && SMP
1011         help
1012           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1013           adequately shooting down all use of the old entries. This
1014           option enables the Linux kernel workaround for this erratum
1015           which sends an IPI to the CPUs that are running the same ASID
1016           as the one being invalidated.
1017
1018 config ARM_ERRATA_773022
1019         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1020         depends on CPU_V7
1021         help
1022           This option enables the workaround for the 773022 Cortex-A15
1023           (up to r0p4) erratum. In certain rare sequences of code, the
1024           loop buffer may deliver incorrect instructions. This
1025           workaround disables the loop buffer to avoid the erratum.
1026
1027 config ARM_ERRATA_818325_852422
1028         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1029         depends on CPU_V7
1030         help
1031           This option enables the workaround for:
1032           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1033             instruction might deadlock.  Fixed in r0p1.
1034           - Cortex-A12 852422: Execution of a sequence of instructions might
1035             lead to either a data corruption or a CPU deadlock.  Not fixed in
1036             any Cortex-A12 cores yet.
1037           This workaround for all both errata involves setting bit[12] of the
1038           Feature Register. This bit disables an optimisation applied to a
1039           sequence of 2 instructions that use opposing condition codes.
1040
1041 config ARM_ERRATA_821420
1042         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1043         depends on CPU_V7
1044         help
1045           This option enables the workaround for the 821420 Cortex-A12
1046           (all revs) erratum. In very rare timing conditions, a sequence
1047           of VMOV to Core registers instructions, for which the second
1048           one is in the shadow of a branch or abort, can lead to a
1049           deadlock when the VMOV instructions are issued out-of-order.
1050
1051 config ARM_ERRATA_825619
1052         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1053         depends on CPU_V7
1054         help
1055           This option enables the workaround for the 825619 Cortex-A12
1056           (all revs) erratum. Within rare timing constraints, executing a
1057           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1058           and Device/Strongly-Ordered loads and stores might cause deadlock
1059
1060 config ARM_ERRATA_857271
1061         bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1062         depends on CPU_V7
1063         help
1064           This option enables the workaround for the 857271 Cortex-A12
1065           (all revs) erratum. Under very rare timing conditions, the CPU might
1066           hang. The workaround is expected to have a < 1% performance impact.
1067
1068 config ARM_ERRATA_852421
1069         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1070         depends on CPU_V7
1071         help
1072           This option enables the workaround for the 852421 Cortex-A17
1073           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1074           execution of a DMB ST instruction might fail to properly order
1075           stores from GroupA and stores from GroupB.
1076
1077 config ARM_ERRATA_852423
1078         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1079         depends on CPU_V7
1080         help
1081           This option enables the workaround for:
1082           - Cortex-A17 852423: Execution of a sequence of instructions might
1083             lead to either a data corruption or a CPU deadlock.  Not fixed in
1084             any Cortex-A17 cores yet.
1085           This is identical to Cortex-A12 erratum 852422.  It is a separate
1086           config option from the A12 erratum due to the way errata are checked
1087           for and handled.
1088
1089 config ARM_ERRATA_857272
1090         bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1091         depends on CPU_V7
1092         help
1093           This option enables the workaround for the 857272 Cortex-A17 erratum.
1094           This erratum is not known to be fixed in any A17 revision.
1095           This is identical to Cortex-A12 erratum 857271.  It is a separate
1096           config option from the A12 erratum due to the way errata are checked
1097           for and handled.
1098
1099 endmenu
1100
1101 source "arch/arm/common/Kconfig"
1102
1103 menu "Bus support"
1104
1105 config ISA
1106         bool
1107         help
1108           Find out whether you have ISA slots on your motherboard.  ISA is the
1109           name of a bus system, i.e. the way the CPU talks to the other stuff
1110           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1111           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1112           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1113
1114 # Select ISA DMA controller support
1115 config ISA_DMA
1116         bool
1117         select ISA_DMA_API
1118
1119 # Select ISA DMA interface
1120 config ISA_DMA_API
1121         bool
1122
1123 config PCI_NANOENGINE
1124         bool "BSE nanoEngine PCI support"
1125         depends on SA1100_NANOENGINE
1126         help
1127           Enable PCI on the BSE nanoEngine board.
1128
1129 config ARM_ERRATA_814220
1130         bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1131         depends on CPU_V7
1132         help
1133           The v7 ARM states that all cache and branch predictor maintenance
1134           operations that do not specify an address execute, relative to
1135           each other, in program order.
1136           However, because of this erratum, an L2 set/way cache maintenance
1137           operation can overtake an L1 set/way cache maintenance operation.
1138           This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1139           r0p4, r0p5.
1140
1141 endmenu
1142
1143 menu "Kernel Features"
1144
1145 config HAVE_SMP
1146         bool
1147         help
1148           This option should be selected by machines which have an SMP-
1149           capable CPU.
1150
1151           The only effect of this option is to make the SMP-related
1152           options available to the user for configuration.
1153
1154 config SMP
1155         bool "Symmetric Multi-Processing"
1156         depends on CPU_V6K || CPU_V7
1157         depends on HAVE_SMP
1158         depends on MMU || ARM_MPU
1159         select IRQ_WORK
1160         help
1161           This enables support for systems with more than one CPU. If you have
1162           a system with only one CPU, say N. If you have a system with more
1163           than one CPU, say Y.
1164
1165           If you say N here, the kernel will run on uni- and multiprocessor
1166           machines, but will use only one CPU of a multiprocessor machine. If
1167           you say Y here, the kernel will run on many, but not all,
1168           uniprocessor machines. On a uniprocessor machine, the kernel
1169           will run faster if you say N here.
1170
1171           See also <file:Documentation/x86/i386/IO-APIC.rst>,
1172           <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1173           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1174
1175           If you don't know what to do here, say N.
1176
1177 config SMP_ON_UP
1178         bool "Allow booting SMP kernel on uniprocessor systems"
1179         depends on SMP && !XIP_KERNEL && MMU
1180         default y
1181         help
1182           SMP kernels contain instructions which fail on non-SMP processors.
1183           Enabling this option allows the kernel to modify itself to make
1184           these instructions safe.  Disabling it allows about 1K of space
1185           savings.
1186
1187           If you don't know what to do here, say Y.
1188
1189 config ARM_CPU_TOPOLOGY
1190         bool "Support cpu topology definition"
1191         depends on SMP && CPU_V7
1192         default y
1193         help
1194           Support ARM cpu topology definition. The MPIDR register defines
1195           affinity between processors which is then used to describe the cpu
1196           topology of an ARM System.
1197
1198 config SCHED_MC
1199         bool "Multi-core scheduler support"
1200         depends on ARM_CPU_TOPOLOGY
1201         help
1202           Multi-core scheduler support improves the CPU scheduler's decision
1203           making when dealing with multi-core CPU chips at a cost of slightly
1204           increased overhead in some places. If unsure say N here.
1205
1206 config SCHED_SMT
1207         bool "SMT scheduler support"
1208         depends on ARM_CPU_TOPOLOGY
1209         help
1210           Improves the CPU scheduler's decision making when dealing with
1211           MultiThreading at a cost of slightly increased overhead in some
1212           places. If unsure say N here.
1213
1214 config HAVE_ARM_SCU
1215         bool
1216         help
1217           This option enables support for the ARM snoop control unit
1218
1219 config HAVE_ARM_ARCH_TIMER
1220         bool "Architected timer support"
1221         depends on CPU_V7
1222         select ARM_ARCH_TIMER
1223         help
1224           This option enables support for the ARM architected timer
1225
1226 config HAVE_ARM_TWD
1227         bool
1228         help
1229           This options enables support for the ARM timer and watchdog unit
1230
1231 config MCPM
1232         bool "Multi-Cluster Power Management"
1233         depends on CPU_V7 && SMP
1234         help
1235           This option provides the common power management infrastructure
1236           for (multi-)cluster based systems, such as big.LITTLE based
1237           systems.
1238
1239 config MCPM_QUAD_CLUSTER
1240         bool
1241         depends on MCPM
1242         help
1243           To avoid wasting resources unnecessarily, MCPM only supports up
1244           to 2 clusters by default.
1245           Platforms with 3 or 4 clusters that use MCPM must select this
1246           option to allow the additional clusters to be managed.
1247
1248 config BIG_LITTLE
1249         bool "big.LITTLE support (Experimental)"
1250         depends on CPU_V7 && SMP
1251         select MCPM
1252         help
1253           This option enables support selections for the big.LITTLE
1254           system architecture.
1255
1256 config BL_SWITCHER
1257         bool "big.LITTLE switcher support"
1258         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1259         select CPU_PM
1260         help
1261           The big.LITTLE "switcher" provides the core functionality to
1262           transparently handle transition between a cluster of A15's
1263           and a cluster of A7's in a big.LITTLE system.
1264
1265 config BL_SWITCHER_DUMMY_IF
1266         tristate "Simple big.LITTLE switcher user interface"
1267         depends on BL_SWITCHER && DEBUG_KERNEL
1268         help
1269           This is a simple and dummy char dev interface to control
1270           the big.LITTLE switcher core code.  It is meant for
1271           debugging purposes only.
1272
1273 choice
1274         prompt "Memory split"
1275         depends on MMU
1276         default VMSPLIT_3G
1277         help
1278           Select the desired split between kernel and user memory.
1279
1280           If you are not absolutely sure what you are doing, leave this
1281           option alone!
1282
1283         config VMSPLIT_3G
1284                 bool "3G/1G user/kernel split"
1285         config VMSPLIT_3G_OPT
1286                 depends on !ARM_LPAE
1287                 bool "3G/1G user/kernel split (for full 1G low memory)"
1288         config VMSPLIT_2G
1289                 bool "2G/2G user/kernel split"
1290         config VMSPLIT_1G
1291                 bool "1G/3G user/kernel split"
1292 endchoice
1293
1294 config PAGE_OFFSET
1295         hex
1296         default PHYS_OFFSET if !MMU
1297         default 0x40000000 if VMSPLIT_1G
1298         default 0x80000000 if VMSPLIT_2G
1299         default 0xB0000000 if VMSPLIT_3G_OPT
1300         default 0xC0000000
1301
1302 config KASAN_SHADOW_OFFSET
1303         hex
1304         depends on KASAN
1305         default 0x1f000000 if PAGE_OFFSET=0x40000000
1306         default 0x5f000000 if PAGE_OFFSET=0x80000000
1307         default 0x9f000000 if PAGE_OFFSET=0xC0000000
1308         default 0x8f000000 if PAGE_OFFSET=0xB0000000
1309         default 0xffffffff
1310
1311 config NR_CPUS
1312         int "Maximum number of CPUs (2-32)"
1313         range 2 16 if DEBUG_KMAP_LOCAL
1314         range 2 32 if !DEBUG_KMAP_LOCAL
1315         depends on SMP
1316         default "4"
1317         help
1318           The maximum number of CPUs that the kernel can support.
1319           Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1320           debugging is enabled, which uses half of the per-CPU fixmap
1321           slots as guard regions.
1322
1323 config HOTPLUG_CPU
1324         bool "Support for hot-pluggable CPUs"
1325         depends on SMP
1326         select GENERIC_IRQ_MIGRATION
1327         help
1328           Say Y here to experiment with turning CPUs off and on.  CPUs
1329           can be controlled through /sys/devices/system/cpu.
1330
1331 config ARM_PSCI
1332         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1333         depends on HAVE_ARM_SMCCC
1334         select ARM_PSCI_FW
1335         help
1336           Say Y here if you want Linux to communicate with system firmware
1337           implementing the PSCI specification for CPU-centric power
1338           management operations described in ARM document number ARM DEN
1339           0022A ("Power State Coordination Interface System Software on
1340           ARM processors").
1341
1342 # The GPIO number here must be sorted by descending number. In case of
1343 # a multiplatform kernel, we just want the highest value required by the
1344 # selected platforms.
1345 config ARCH_NR_GPIO
1346         int
1347         default 2048 if ARCH_SOCFPGA
1348         default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1349                 ARCH_ZYNQ || ARCH_ASPEED
1350         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1351                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1352         default 416 if ARCH_SUNXI
1353         default 392 if ARCH_U8500
1354         default 352 if ARCH_VT8500
1355         default 288 if ARCH_ROCKCHIP
1356         default 264 if MACH_H4700
1357         default 0
1358         help
1359           Maximum number of GPIOs in the system.
1360
1361           If unsure, leave the default value.
1362
1363 config HZ_FIXED
1364         int
1365         default 128 if SOC_AT91RM9200
1366         default 0
1367
1368 choice
1369         depends on HZ_FIXED = 0
1370         prompt "Timer frequency"
1371
1372 config HZ_100
1373         bool "100 Hz"
1374
1375 config HZ_200
1376         bool "200 Hz"
1377
1378 config HZ_250
1379         bool "250 Hz"
1380
1381 config HZ_300
1382         bool "300 Hz"
1383
1384 config HZ_500
1385         bool "500 Hz"
1386
1387 config HZ_1000
1388         bool "1000 Hz"
1389
1390 endchoice
1391
1392 config HZ
1393         int
1394         default HZ_FIXED if HZ_FIXED != 0
1395         default 100 if HZ_100
1396         default 200 if HZ_200
1397         default 250 if HZ_250
1398         default 300 if HZ_300
1399         default 500 if HZ_500
1400         default 1000
1401
1402 config SCHED_HRTICK
1403         def_bool HIGH_RES_TIMERS
1404
1405 config THUMB2_KERNEL
1406         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1407         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1408         default y if CPU_THUMBONLY
1409         select ARM_UNWIND
1410         help
1411           By enabling this option, the kernel will be compiled in
1412           Thumb-2 mode.
1413
1414           If unsure, say N.
1415
1416 config ARM_PATCH_IDIV
1417         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1418         depends on CPU_32v7 && !XIP_KERNEL
1419         default y
1420         help
1421           The ARM compiler inserts calls to __aeabi_idiv() and
1422           __aeabi_uidiv() when it needs to perform division on signed
1423           and unsigned integers. Some v7 CPUs have support for the sdiv
1424           and udiv instructions that can be used to implement those
1425           functions.
1426
1427           Enabling this option allows the kernel to modify itself to
1428           replace the first two instructions of these library functions
1429           with the sdiv or udiv plus "bx lr" instructions when the CPU
1430           it is running on supports them. Typically this will be faster
1431           and less power intensive than running the original library
1432           code to do integer division.
1433
1434 config AEABI
1435         bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1436                 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1437         default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1438         help
1439           This option allows for the kernel to be compiled using the latest
1440           ARM ABI (aka EABI).  This is only useful if you are using a user
1441           space environment that is also compiled with EABI.
1442
1443           Since there are major incompatibilities between the legacy ABI and
1444           EABI, especially with regard to structure member alignment, this
1445           option also changes the kernel syscall calling convention to
1446           disambiguate both ABIs and allow for backward compatibility support
1447           (selected with CONFIG_OABI_COMPAT).
1448
1449           To use this you need GCC version 4.0.0 or later.
1450
1451 config OABI_COMPAT
1452         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1453         depends on AEABI && !THUMB2_KERNEL
1454         help
1455           This option preserves the old syscall interface along with the
1456           new (ARM EABI) one. It also provides a compatibility layer to
1457           intercept syscalls that have structure arguments which layout
1458           in memory differs between the legacy ABI and the new ARM EABI
1459           (only for non "thumb" binaries). This option adds a tiny
1460           overhead to all syscalls and produces a slightly larger kernel.
1461
1462           The seccomp filter system will not be available when this is
1463           selected, since there is no way yet to sensibly distinguish
1464           between calling conventions during filtering.
1465
1466           If you know you'll be using only pure EABI user space then you
1467           can say N here. If this option is not selected and you attempt
1468           to execute a legacy ABI binary then the result will be
1469           UNPREDICTABLE (in fact it can be predicted that it won't work
1470           at all). If in doubt say N.
1471
1472 config ARCH_SELECT_MEMORY_MODEL
1473         bool
1474
1475 config ARCH_FLATMEM_ENABLE
1476         bool
1477
1478 config ARCH_SPARSEMEM_ENABLE
1479         bool
1480         select SPARSEMEM_STATIC if SPARSEMEM
1481
1482 config HIGHMEM
1483         bool "High Memory Support"
1484         depends on MMU
1485         select KMAP_LOCAL
1486         help
1487           The address space of ARM processors is only 4 Gigabytes large
1488           and it has to accommodate user address space, kernel address
1489           space as well as some memory mapped IO. That means that, if you
1490           have a large amount of physical memory and/or IO, not all of the
1491           memory can be "permanently mapped" by the kernel. The physical
1492           memory that is not permanently mapped is called "high memory".
1493
1494           Depending on the selected kernel/user memory split, minimum
1495           vmalloc space and actual amount of RAM, you may not need this
1496           option which should result in a slightly faster kernel.
1497
1498           If unsure, say n.
1499
1500 config HIGHPTE
1501         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1502         depends on HIGHMEM
1503         default y
1504         help
1505           The VM uses one page of physical memory for each page table.
1506           For systems with a lot of processes, this can use a lot of
1507           precious low memory, eventually leading to low memory being
1508           consumed by page tables.  Setting this option will allow
1509           user-space 2nd level page tables to reside in high memory.
1510
1511 config CPU_SW_DOMAIN_PAN
1512         bool "Enable use of CPU domains to implement privileged no-access"
1513         depends on MMU && !ARM_LPAE
1514         default y
1515         help
1516           Increase kernel security by ensuring that normal kernel accesses
1517           are unable to access userspace addresses.  This can help prevent
1518           use-after-free bugs becoming an exploitable privilege escalation
1519           by ensuring that magic values (such as LIST_POISON) will always
1520           fault when dereferenced.
1521
1522           CPUs with low-vector mappings use a best-efforts implementation.
1523           Their lower 1MB needs to remain accessible for the vectors, but
1524           the remainder of userspace will become appropriately inaccessible.
1525
1526 config HW_PERF_EVENTS
1527         def_bool y
1528         depends on ARM_PMU
1529
1530 config SYS_SUPPORTS_HUGETLBFS
1531        def_bool y
1532        depends on ARM_LPAE
1533
1534 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1535        def_bool y
1536        depends on ARM_LPAE
1537
1538 config ARCH_WANT_GENERAL_HUGETLB
1539         def_bool y
1540
1541 config ARM_MODULE_PLTS
1542         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1543         depends on MODULES
1544         default y
1545         help
1546           Allocate PLTs when loading modules so that jumps and calls whose
1547           targets are too far away for their relative offsets to be encoded
1548           in the instructions themselves can be bounced via veneers in the
1549           module's PLT. This allows modules to be allocated in the generic
1550           vmalloc area after the dedicated module memory area has been
1551           exhausted. The modules will use slightly more memory, but after
1552           rounding up to page size, the actual memory footprint is usually
1553           the same.
1554
1555           Disabling this is usually safe for small single-platform
1556           configurations. If unsure, say y.
1557
1558 config FORCE_MAX_ZONEORDER
1559         int "Maximum zone order"
1560         default "12" if SOC_AM33XX
1561         default "9" if SA1111 || ARCH_EFM32
1562         default "11"
1563         help
1564           The kernel memory allocator divides physically contiguous memory
1565           blocks into "zones", where each zone is a power of two number of
1566           pages.  This option selects the largest power of two that the kernel
1567           keeps in the memory allocator.  If you need to allocate very large
1568           blocks of physically contiguous memory, then you may need to
1569           increase this value.
1570
1571           This config option is actually maximum order plus one. For example,
1572           a value of 11 means that the largest free memory block is 2^10 pages.
1573
1574 config ALIGNMENT_TRAP
1575         def_bool CPU_CP15_MMU
1576         select HAVE_PROC_CPU if PROC_FS
1577         help
1578           ARM processors cannot fetch/store information which is not
1579           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1580           address divisible by 4. On 32-bit ARM processors, these non-aligned
1581           fetch/store instructions will be emulated in software if you say
1582           here, which has a severe performance impact. This is necessary for
1583           correct operation of some network protocols. With an IP-only
1584           configuration it is safe to say N, otherwise say Y.
1585
1586 config UACCESS_WITH_MEMCPY
1587         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1588         depends on MMU
1589         default y if CPU_FEROCEON
1590         help
1591           Implement faster copy_to_user and clear_user methods for CPU
1592           cores where a 8-word STM instruction give significantly higher
1593           memory write throughput than a sequence of individual 32bit stores.
1594
1595           A possible side effect is a slight increase in scheduling latency
1596           between threads sharing the same address space if they invoke
1597           such copy operations with large buffers.
1598
1599           However, if the CPU data cache is using a write-allocate mode,
1600           this option is unlikely to provide any performance gain.
1601
1602 config PARAVIRT
1603         bool "Enable paravirtualization code"
1604         help
1605           This changes the kernel so it can modify itself when it is run
1606           under a hypervisor, potentially improving performance significantly
1607           over full virtualization.
1608
1609 config PARAVIRT_TIME_ACCOUNTING
1610         bool "Paravirtual steal time accounting"
1611         select PARAVIRT
1612         help
1613           Select this option to enable fine granularity task steal time
1614           accounting. Time spent executing other tasks in parallel with
1615           the current vCPU is discounted from the vCPU power. To account for
1616           that, there can be a small performance impact.
1617
1618           If in doubt, say N here.
1619
1620 config XEN_DOM0
1621         def_bool y
1622         depends on XEN
1623
1624 config XEN
1625         bool "Xen guest support on ARM"
1626         depends on ARM && AEABI && OF
1627         depends on CPU_V7 && !CPU_V6
1628         depends on !GENERIC_ATOMIC64
1629         depends on MMU
1630         select ARCH_DMA_ADDR_T_64BIT
1631         select ARM_PSCI
1632         select SWIOTLB
1633         select SWIOTLB_XEN
1634         select PARAVIRT
1635         help
1636           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1637
1638 config STACKPROTECTOR_PER_TASK
1639         bool "Use a unique stack canary value for each task"
1640         depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1641         select GCC_PLUGIN_ARM_SSP_PER_TASK
1642         default y
1643         help
1644           Due to the fact that GCC uses an ordinary symbol reference from
1645           which to load the value of the stack canary, this value can only
1646           change at reboot time on SMP systems, and all tasks running in the
1647           kernel's address space are forced to use the same canary value for
1648           the entire duration that the system is up.
1649
1650           Enable this option to switch to a different method that uses a
1651           different canary value for each task.
1652
1653 endmenu
1654
1655 menu "Boot options"
1656
1657 config USE_OF
1658         bool "Flattened Device Tree support"
1659         select IRQ_DOMAIN
1660         select OF
1661         help
1662           Include support for flattened device tree machine descriptions.
1663
1664 config ATAGS
1665         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1666         default y
1667         help
1668           This is the traditional way of passing data to the kernel at boot
1669           time. If you are solely relying on the flattened device tree (or
1670           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1671           to remove ATAGS support from your kernel binary.  If unsure,
1672           leave this to y.
1673
1674 config DEPRECATED_PARAM_STRUCT
1675         bool "Provide old way to pass kernel parameters"
1676         depends on ATAGS
1677         help
1678           This was deprecated in 2001 and announced to live on for 5 years.
1679           Some old boot loaders still use this way.
1680
1681 # Compressed boot loader in ROM.  Yes, we really want to ask about
1682 # TEXT and BSS so we preserve their values in the config files.
1683 config ZBOOT_ROM_TEXT
1684         hex "Compressed ROM boot loader base address"
1685         default 0x0
1686         help
1687           The physical address at which the ROM-able zImage is to be
1688           placed in the target.  Platforms which normally make use of
1689           ROM-able zImage formats normally set this to a suitable
1690           value in their defconfig file.
1691
1692           If ZBOOT_ROM is not enabled, this has no effect.
1693
1694 config ZBOOT_ROM_BSS
1695         hex "Compressed ROM boot loader BSS address"
1696         default 0x0
1697         help
1698           The base address of an area of read/write memory in the target
1699           for the ROM-able zImage which must be available while the
1700           decompressor is running. It must be large enough to hold the
1701           entire decompressed kernel plus an additional 128 KiB.
1702           Platforms which normally make use of ROM-able zImage formats
1703           normally set this to a suitable value in their defconfig file.
1704
1705           If ZBOOT_ROM is not enabled, this has no effect.
1706
1707 config ZBOOT_ROM
1708         bool "Compressed boot loader in ROM/flash"
1709         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1710         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1711         help
1712           Say Y here if you intend to execute your compressed kernel image
1713           (zImage) directly from ROM or flash.  If unsure, say N.
1714
1715 config ARM_APPENDED_DTB
1716         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1717         depends on OF
1718         help
1719           With this option, the boot code will look for a device tree binary
1720           (DTB) appended to zImage
1721           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1722
1723           This is meant as a backward compatibility convenience for those
1724           systems with a bootloader that can't be upgraded to accommodate
1725           the documented boot protocol using a device tree.
1726
1727           Beware that there is very little in terms of protection against
1728           this option being confused by leftover garbage in memory that might
1729           look like a DTB header after a reboot if no actual DTB is appended
1730           to zImage.  Do not leave this option active in a production kernel
1731           if you don't intend to always append a DTB.  Proper passing of the
1732           location into r2 of a bootloader provided DTB is always preferable
1733           to this option.
1734
1735 config ARM_ATAG_DTB_COMPAT
1736         bool "Supplement the appended DTB with traditional ATAG information"
1737         depends on ARM_APPENDED_DTB
1738         help
1739           Some old bootloaders can't be updated to a DTB capable one, yet
1740           they provide ATAGs with memory configuration, the ramdisk address,
1741           the kernel cmdline string, etc.  Such information is dynamically
1742           provided by the bootloader and can't always be stored in a static
1743           DTB.  To allow a device tree enabled kernel to be used with such
1744           bootloaders, this option allows zImage to extract the information
1745           from the ATAG list and store it at run time into the appended DTB.
1746
1747 choice
1748         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1749         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1750
1751 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1752         bool "Use bootloader kernel arguments if available"
1753         help
1754           Uses the command-line options passed by the boot loader instead of
1755           the device tree bootargs property. If the boot loader doesn't provide
1756           any, the device tree bootargs property will be used.
1757
1758 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1759         bool "Extend with bootloader kernel arguments"
1760         help
1761           The command-line arguments provided by the boot loader will be
1762           appended to the the device tree bootargs property.
1763
1764 endchoice
1765
1766 config CMDLINE
1767         string "Default kernel command string"
1768         default ""
1769         help
1770           On some architectures (e.g. CATS), there is currently no way
1771           for the boot loader to pass arguments to the kernel. For these
1772           architectures, you should supply some command-line options at build
1773           time by entering them here. As a minimum, you should specify the
1774           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1775
1776 choice
1777         prompt "Kernel command line type" if CMDLINE != ""
1778         default CMDLINE_FROM_BOOTLOADER
1779         depends on ATAGS
1780
1781 config CMDLINE_FROM_BOOTLOADER
1782         bool "Use bootloader kernel arguments if available"
1783         help
1784           Uses the command-line options passed by the boot loader. If
1785           the boot loader doesn't provide any, the default kernel command
1786           string provided in CMDLINE will be used.
1787
1788 config CMDLINE_EXTEND
1789         bool "Extend bootloader kernel arguments"
1790         help
1791           The command-line arguments provided by the boot loader will be
1792           appended to the default kernel command string.
1793
1794 config CMDLINE_FORCE
1795         bool "Always use the default kernel command string"
1796         help
1797           Always use the default kernel command string, even if the boot
1798           loader passes other arguments to the kernel.
1799           This is useful if you cannot or don't want to change the
1800           command-line options your boot loader passes to the kernel.
1801 endchoice
1802
1803 config XIP_KERNEL
1804         bool "Kernel Execute-In-Place from ROM"
1805         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1806         help
1807           Execute-In-Place allows the kernel to run from non-volatile storage
1808           directly addressable by the CPU, such as NOR flash. This saves RAM
1809           space since the text section of the kernel is not loaded from flash
1810           to RAM.  Read-write sections, such as the data section and stack,
1811           are still copied to RAM.  The XIP kernel is not compressed since
1812           it has to run directly from flash, so it will take more space to
1813           store it.  The flash address used to link the kernel object files,
1814           and for storing it, is configuration dependent. Therefore, if you
1815           say Y here, you must know the proper physical address where to
1816           store the kernel image depending on your own flash memory usage.
1817
1818           Also note that the make target becomes "make xipImage" rather than
1819           "make zImage" or "make Image".  The final kernel binary to put in
1820           ROM memory will be arch/arm/boot/xipImage.
1821
1822           If unsure, say N.
1823
1824 config XIP_PHYS_ADDR
1825         hex "XIP Kernel Physical Location"
1826         depends on XIP_KERNEL
1827         default "0x00080000"
1828         help
1829           This is the physical address in your flash memory the kernel will
1830           be linked for and stored to.  This address is dependent on your
1831           own flash usage.
1832
1833 config XIP_DEFLATED_DATA
1834         bool "Store kernel .data section compressed in ROM"
1835         depends on XIP_KERNEL
1836         select ZLIB_INFLATE
1837         help
1838           Before the kernel is actually executed, its .data section has to be
1839           copied to RAM from ROM. This option allows for storing that data
1840           in compressed form and decompressed to RAM rather than merely being
1841           copied, saving some precious ROM space. A possible drawback is a
1842           slightly longer boot delay.
1843
1844 config KEXEC
1845         bool "Kexec system call (EXPERIMENTAL)"
1846         depends on (!SMP || PM_SLEEP_SMP)
1847         depends on MMU
1848         select KEXEC_CORE
1849         help
1850           kexec is a system call that implements the ability to shutdown your
1851           current kernel, and to start another kernel.  It is like a reboot
1852           but it is independent of the system firmware.   And like a reboot
1853           you can start any kernel with it, not just Linux.
1854
1855           It is an ongoing process to be certain the hardware in a machine
1856           is properly shutdown, so do not be surprised if this code does not
1857           initially work for you.
1858
1859 config ATAGS_PROC
1860         bool "Export atags in procfs"
1861         depends on ATAGS && KEXEC
1862         default y
1863         help
1864           Should the atags used to boot the kernel be exported in an "atags"
1865           file in procfs. Useful with kexec.
1866
1867 config CRASH_DUMP
1868         bool "Build kdump crash kernel (EXPERIMENTAL)"
1869         help
1870           Generate crash dump after being started by kexec. This should
1871           be normally only set in special crash dump kernels which are
1872           loaded in the main kernel with kexec-tools into a specially
1873           reserved region and then later executed after a crash by
1874           kdump/kexec. The crash dump kernel must be compiled to a
1875           memory address not used by the main kernel
1876
1877           For more details see Documentation/admin-guide/kdump/kdump.rst
1878
1879 config AUTO_ZRELADDR
1880         bool "Auto calculation of the decompressed kernel image address"
1881         help
1882           ZRELADDR is the physical address where the decompressed kernel
1883           image will be placed. If AUTO_ZRELADDR is selected, the address
1884           will be determined at run-time by masking the current IP with
1885           0xf8000000. This assumes the zImage being placed in the first 128MB
1886           from start of memory.
1887
1888 config EFI_STUB
1889         bool
1890
1891 config EFI
1892         bool "UEFI runtime support"
1893         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1894         select UCS2_STRING
1895         select EFI_PARAMS_FROM_FDT
1896         select EFI_STUB
1897         select EFI_GENERIC_STUB
1898         select EFI_RUNTIME_WRAPPERS
1899         help
1900           This option provides support for runtime services provided
1901           by UEFI firmware (such as non-volatile variables, realtime
1902           clock, and platform reset). A UEFI stub is also provided to
1903           allow the kernel to be booted as an EFI application. This
1904           is only useful for kernels that may run on systems that have
1905           UEFI firmware.
1906
1907 config DMI
1908         bool "Enable support for SMBIOS (DMI) tables"
1909         depends on EFI
1910         default y
1911         help
1912           This enables SMBIOS/DMI feature for systems.
1913
1914           This option is only useful on systems that have UEFI firmware.
1915           However, even with this option, the resultant kernel should
1916           continue to boot on existing non-UEFI platforms.
1917
1918           NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1919           i.e., the the practice of identifying the platform via DMI to
1920           decide whether certain workarounds for buggy hardware and/or
1921           firmware need to be enabled. This would require the DMI subsystem
1922           to be enabled much earlier than we do on ARM, which is non-trivial.
1923
1924 endmenu
1925
1926 menu "CPU Power Management"
1927
1928 source "drivers/cpufreq/Kconfig"
1929
1930 source "drivers/cpuidle/Kconfig"
1931
1932 endmenu
1933
1934 menu "Floating point emulation"
1935
1936 comment "At least one emulation must be selected"
1937
1938 config FPE_NWFPE
1939         bool "NWFPE math emulation"
1940         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1941         help
1942           Say Y to include the NWFPE floating point emulator in the kernel.
1943           This is necessary to run most binaries. Linux does not currently
1944           support floating point hardware so you need to say Y here even if
1945           your machine has an FPA or floating point co-processor podule.
1946
1947           You may say N here if you are going to load the Acorn FPEmulator
1948           early in the bootup.
1949
1950 config FPE_NWFPE_XP
1951         bool "Support extended precision"
1952         depends on FPE_NWFPE
1953         help
1954           Say Y to include 80-bit support in the kernel floating-point
1955           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
1956           Note that gcc does not generate 80-bit operations by default,
1957           so in most cases this option only enlarges the size of the
1958           floating point emulator without any good reason.
1959
1960           You almost surely want to say N here.
1961
1962 config FPE_FASTFPE
1963         bool "FastFPE math emulation (EXPERIMENTAL)"
1964         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1965         help
1966           Say Y here to include the FAST floating point emulator in the kernel.
1967           This is an experimental much faster emulator which now also has full
1968           precision for the mantissa.  It does not support any exceptions.
1969           It is very simple, and approximately 3-6 times faster than NWFPE.
1970
1971           It should be sufficient for most programs.  It may be not suitable
1972           for scientific calculations, but you have to check this for yourself.
1973           If you do not feel you need a faster FP emulation you should better
1974           choose NWFPE.
1975
1976 config VFP
1977         bool "VFP-format floating point maths"
1978         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1979         help
1980           Say Y to include VFP support code in the kernel. This is needed
1981           if your hardware includes a VFP unit.
1982
1983           Please see <file:Documentation/arm/vfp/release-notes.rst> for
1984           release notes and additional status information.
1985
1986           Say N if your target does not have VFP hardware.
1987
1988 config VFPv3
1989         bool
1990         depends on VFP
1991         default y if CPU_V7
1992
1993 config NEON
1994         bool "Advanced SIMD (NEON) Extension support"
1995         depends on VFPv3 && CPU_V7
1996         help
1997           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1998           Extension.
1999
2000 config KERNEL_MODE_NEON
2001         bool "Support for NEON in kernel mode"
2002         depends on NEON && AEABI
2003         help
2004           Say Y to include support for NEON in kernel mode.
2005
2006 endmenu
2007
2008 menu "Power management options"
2009
2010 source "kernel/power/Kconfig"
2011
2012 config ARCH_SUSPEND_POSSIBLE
2013         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2014                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2015         def_bool y
2016
2017 config ARM_CPU_SUSPEND
2018         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2019         depends on ARCH_SUSPEND_POSSIBLE
2020
2021 config ARCH_HIBERNATION_POSSIBLE
2022         bool
2023         depends on MMU
2024         default y if ARCH_SUSPEND_POSSIBLE
2025
2026 endmenu
2027
2028 source "drivers/firmware/Kconfig"
2029
2030 if CRYPTO
2031 source "arch/arm/crypto/Kconfig"
2032 endif
2033
2034 source "arch/arm/Kconfig.assembler"