arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select EDAC_SUPPORT
  19         select EDAC_ATOMIC_SCRUB
  20         select GENERIC_ALLOCATOR
  21         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  22         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  23         select GENERIC_IDLE_POLL_SETUP
  24         select GENERIC_IRQ_PROBE
  25         select GENERIC_IRQ_SHOW
  26         select GENERIC_IRQ_SHOW_LEVEL
  27         select GENERIC_PCI_IOMAP
  28         select GENERIC_SCHED_CLOCK
  29         select GENERIC_SMP_IDLE_THREAD
  30         select GENERIC_STRNCPY_FROM_USER
  31         select GENERIC_STRNLEN_USER
  32         select HANDLE_DOMAIN_IRQ
  33         select HARDIRQS_SW_RESEND
  34         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  35         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  36         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
  37         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
  38         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  39         select HAVE_ARCH_TRACEHOOK
  40         select HAVE_BPF_JIT
  41         select HAVE_CC_STACKPROTECTOR
  42         select HAVE_CONTEXT_TRACKING
  43         select HAVE_C_RECORDMCOUNT
  44         select HAVE_DEBUG_KMEMLEAK
  45         select HAVE_DMA_API_DEBUG
  46         select HAVE_DMA_ATTRS
  47         select HAVE_DMA_CONTIGUOUS if MMU
  48         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
  49         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  50         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  51         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  52         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  53         select HAVE_GENERIC_DMA_COHERENT
  54         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  55         select HAVE_IDE if PCI || ISA || PCMCIA
  56         select HAVE_IRQ_TIME_ACCOUNTING
  57         select HAVE_KERNEL_GZIP
  58         select HAVE_KERNEL_LZ4
  59         select HAVE_KERNEL_LZMA
  60         select HAVE_KERNEL_LZO
  61         select HAVE_KERNEL_XZ
  62         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  63         select HAVE_KRETPROBES if (HAVE_KPROBES)
  64         select HAVE_MEMBLOCK
  65         select HAVE_MOD_ARCH_SPECIFIC
  66         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  67         select HAVE_OPTPROBES if !THUMB2_KERNEL
  68         select HAVE_PERF_EVENTS
  69         select HAVE_PERF_REGS
  70         select HAVE_PERF_USER_STACK_DUMP
  71         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  72         select HAVE_REGS_AND_STACK_ACCESS_API
  73         select HAVE_SYSCALL_TRACEPOINTS
  74         select HAVE_UID16
  75         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  76         select IRQ_FORCED_THREADING
  77         select MODULES_USE_ELF_REL
  78         select NO_BOOTMEM
  79         select OLD_SIGACTION
  80         select OLD_SIGSUSPEND3
  81         select PERF_USE_VMALLOC
  82         select RTC_LIB
  83         select SYS_SUPPORTS_APM_EMULATION
  84         # Above selects are sorted alphabetically; please add new ones
  85         # according to that.  Thanks.
  86         help
  87           The ARM series is a line of low-power-consumption RISC chip designs
  88           licensed by ARM Ltd and targeted at embedded applications and
  89           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  90           manufactured, but legacy ARM-based PC hardware remains popular in
  91           Europe.  There is an ARM Linux project with a web page at
  92           <http://www.arm.linux.org.uk/>.
  93
  94 config ARM_HAS_SG_CHAIN
  95         select ARCH_HAS_SG_CHAIN
  96         bool
  97
  98 config NEED_SG_DMA_LENGTH
  99         bool
 100
 101 config ARM_DMA_USE_IOMMU
 102         bool
 103         select ARM_HAS_SG_CHAIN
 104         select NEED_SG_DMA_LENGTH
 105
 106 if ARM_DMA_USE_IOMMU
 107
 108 config ARM_DMA_IOMMU_ALIGNMENT
 109         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 110         range 4 9
 111         default 8
 112         help
 113           DMA mapping framework by default aligns all buffers to the smallest
 114           PAGE_SIZE order which is greater than or equal to the requested buffer
 115           size. This works well for buffers up to a few hundreds kilobytes, but
 116           for larger buffers it just a waste of address space. Drivers which has
 117           relatively small addressing window (like 64Mib) might run out of
 118           virtual space with just a few allocations.
 119
 120           With this parameter you can specify the maximum PAGE_SIZE order for
 121           DMA IOMMU buffers. Larger buffers will be aligned only to this
 122           specified order. The order is expressed as a power of two multiplied
 123           by the PAGE_SIZE.
 124
 125 endif
 126
 127 config MIGHT_HAVE_PCI
 128         bool
 129
 130 config SYS_SUPPORTS_APM_EMULATION
 131         bool
 132
 133 config HAVE_TCM
 134         bool
 135         select GENERIC_ALLOCATOR
 136
 137 config HAVE_PROC_CPU
 138         bool
 139
 140 config NO_IOPORT_MAP
 141         bool
 142
 143 config EISA
 144         bool
 145         ---help---
 146           The Extended Industry Standard Architecture (EISA) bus was
 147           developed as an open alternative to the IBM MicroChannel bus.
 148
 149           The EISA bus provided some of the features of the IBM MicroChannel
 150           bus while maintaining backward compatibility with cards made for
 151           the older ISA bus.  The EISA bus saw limited use between 1988 and
 152           1995 when it was made obsolete by the PCI bus.
 153
 154           Say Y here if you are building a kernel for an EISA-based machine.
 155
 156           Otherwise, say N.
 157
 158 config SBUS
 159         bool
 160
 161 config STACKTRACE_SUPPORT
 162         bool
 163         default y
 164
 165 config HAVE_LATENCYTOP_SUPPORT
 166         bool
 167         depends on !SMP
 168         default y
 169
 170 config LOCKDEP_SUPPORT
 171         bool
 172         default y
 173
 174 config TRACE_IRQFLAGS_SUPPORT
 175         bool
 176         default !CPU_V7M
 177
 178 config RWSEM_XCHGADD_ALGORITHM
 179         bool
 180         default y
 181
 182 config ARCH_HAS_ILOG2_U32
 183         bool
 184
 185 config ARCH_HAS_ILOG2_U64
 186         bool
 187
 188 config ARCH_HAS_BANDGAP
 189         bool
 190
 191 config FIX_EARLYCON_MEM
 192         def_bool y if MMU
 193
 194 config GENERIC_HWEIGHT
 195         bool
 196         default y
 197
 198 config GENERIC_CALIBRATE_DELAY
 199         bool
 200         default y
 201
 202 config ARCH_MAY_HAVE_PC_FDC
 203         bool
 204
 205 config ZONE_DMA
 206         bool
 207
 208 config NEED_DMA_MAP_STATE
 209        def_bool y
 210
 211 config ARCH_SUPPORTS_UPROBES
 212         def_bool y
 213
 214 config ARCH_HAS_DMA_SET_COHERENT_MASK
 215         bool
 216
 217 config GENERIC_ISA_DMA
 218         bool
 219
 220 config FIQ
 221         bool
 222
 223 config NEED_RET_TO_USER
 224         bool
 225
 226 config ARCH_MTD_XIP
 227         bool
 228
 229 config VECTORS_BASE
 230         hex
 231         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 232         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 233         default 0x00000000
 234         help
 235           The base address of exception vectors.  This must be two pages
 236           in size.
 237
 238 config ARM_PATCH_PHYS_VIRT
 239         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 240         default y
 241         depends on !XIP_KERNEL && MMU
 242         depends on !ARCH_REALVIEW || !SPARSEMEM
 243         help
 244           Patch phys-to-virt and virt-to-phys translation functions at
 245           boot and module load time according to the position of the
 246           kernel in system memory.
 247
 248           This can only be used with non-XIP MMU kernels where the base
 249           of physical memory is at a 16MB boundary.
 250
 251           Only disable this option if you know that you do not require
 252           this feature (eg, building a kernel for a single machine) and
 253           you need to shrink the kernel to the minimal size.
 254
 255 config NEED_MACH_IO_H
 256         bool
 257         help
 258           Select this when mach/io.h is required to provide special
 259           definitions for this platform.  The need for mach/io.h should
 260           be avoided when possible.
 261
 262 config NEED_MACH_MEMORY_H
 263         bool
 264         help
 265           Select this when mach/memory.h is required to provide special
 266           definitions for this platform.  The need for mach/memory.h should
 267           be avoided when possible.
 268
 269 config PHYS_OFFSET
 270         hex "Physical address of main memory" if MMU
 271         depends on !ARM_PATCH_PHYS_VIRT
 272         default DRAM_BASE if !MMU
 273         default 0x00000000 if ARCH_EBSA110 || \
 274                         ARCH_FOOTBRIDGE || \
 275                         ARCH_INTEGRATOR || \
 276                         ARCH_IOP13XX || \
 277                         ARCH_KS8695 || \
 278                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 279         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 280         default 0x20000000 if ARCH_S5PV210
 281         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 282         default 0xc0000000 if ARCH_SA1100
 283         help
 284           Please provide the physical address corresponding to the
 285           location of main memory in your system.
 286
 287 config GENERIC_BUG
 288         def_bool y
 289         depends on BUG
 290
 291 config PGTABLE_LEVELS
 292         int
 293         default 3 if ARM_LPAE
 294         default 2
 295
 296 source "init/Kconfig"
 297
 298 source "kernel/Kconfig.freezer"
 299
 300 menu "System Type"
 301
 302 config MMU
 303         bool "MMU-based Paged Memory Management Support"
 304         default y
 305         help
 306           Select if you want MMU-based virtualised addressing space
 307           support by paged memory management. If unsure, say 'Y'.
 308
 309 #
 310 # The "ARM system type" choice list is ordered alphabetically by option
 311 # text.  Please add new entries in the option alphabetic order.
 312 #
 313 choice
 314         prompt "ARM system type"
 315         default ARCH_VERSATILE if !MMU
 316         default ARCH_MULTIPLATFORM if MMU
 317
 318 config ARCH_MULTIPLATFORM
 319         bool "Allow multiple platforms to be selected"
 320         depends on MMU
 321         select ARCH_WANT_OPTIONAL_GPIOLIB
 322         select ARM_HAS_SG_CHAIN
 323         select ARM_PATCH_PHYS_VIRT
 324         select AUTO_ZRELADDR
 325         select CLKSRC_OF
 326         select COMMON_CLK
 327         select GENERIC_CLOCKEVENTS
 328         select MIGHT_HAVE_PCI
 329         select MULTI_IRQ_HANDLER
 330         select SPARSE_IRQ
 331         select USE_OF
 332
 333 config ARM_SINGLE_ARMV7M
 334         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 335         depends on !MMU
 336         select ARCH_WANT_OPTIONAL_GPIOLIB
 337         select ARM_NVIC
 338         select AUTO_ZRELADDR
 339         select CLKSRC_OF
 340         select COMMON_CLK
 341         select CPU_V7M
 342         select GENERIC_CLOCKEVENTS
 343         select NO_IOPORT_MAP
 344         select SPARSE_IRQ
 345         select USE_OF
 346
 347 config ARCH_REALVIEW
 348         bool "ARM Ltd. RealView family"
 349         select ARCH_WANT_OPTIONAL_GPIOLIB
 350         select ARM_AMBA
 351         select ARM_TIMER_SP804
 352         select COMMON_CLK
 353         select COMMON_CLK_VERSATILE
 354         select GENERIC_CLOCKEVENTS
 355         select GPIO_PL061 if GPIOLIB
 356         select ICST
 357         select NEED_MACH_MEMORY_H
 358         select PLAT_VERSATILE
 359         select PLAT_VERSATILE_SCHED_CLOCK
 360         help
 361           This enables support for ARM Ltd RealView boards.
 362
 363 config ARCH_VERSATILE
 364         bool "ARM Ltd. Versatile family"
 365         select ARCH_WANT_OPTIONAL_GPIOLIB
 366         select ARM_AMBA
 367         select ARM_TIMER_SP804
 368         select ARM_VIC
 369         select CLKDEV_LOOKUP
 370         select GENERIC_CLOCKEVENTS
 371         select HAVE_MACH_CLKDEV
 372         select ICST
 373         select PLAT_VERSATILE
 374         select PLAT_VERSATILE_CLOCK
 375         select PLAT_VERSATILE_SCHED_CLOCK
 376         select VERSATILE_FPGA_IRQ
 377         help
 378           This enables support for ARM Ltd Versatile board.
 379
 380 config ARCH_CLPS711X
 381         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 382         select ARCH_REQUIRE_GPIOLIB
 383         select AUTO_ZRELADDR
 384         select CLKSRC_MMIO
 385         select COMMON_CLK
 386         select CPU_ARM720T
 387         select GENERIC_CLOCKEVENTS
 388         select MFD_SYSCON
 389         select SOC_BUS
 390         help
 391           Support for Cirrus Logic 711x/721x/731x based boards.
 392
 393 config ARCH_GEMINI
 394         bool "Cortina Systems Gemini"
 395         select ARCH_REQUIRE_GPIOLIB
 396         select CLKSRC_MMIO
 397         select CPU_FA526
 398         select GENERIC_CLOCKEVENTS
 399         help
 400           Support for the Cortina Systems Gemini family SoCs
 401
 402 config ARCH_EBSA110
 403         bool "EBSA-110"
 404         select ARCH_USES_GETTIMEOFFSET
 405         select CPU_SA110
 406         select ISA
 407         select NEED_MACH_IO_H
 408         select NEED_MACH_MEMORY_H
 409         select NO_IOPORT_MAP
 410         help
 411           This is an evaluation board for the StrongARM processor available
 412           from Digital. It has limited hardware on-board, including an
 413           Ethernet interface, two PCMCIA sockets, two serial ports and a
 414           parallel port.
 415
 416 config ARCH_EP93XX
 417         bool "EP93xx-based"
 418         select ARCH_HAS_HOLES_MEMORYMODEL
 419         select ARCH_REQUIRE_GPIOLIB
 420         select ARM_AMBA
 421         select ARM_PATCH_PHYS_VIRT
 422         select ARM_VIC
 423         select AUTO_ZRELADDR
 424         select CLKDEV_LOOKUP
 425         select CLKSRC_MMIO
 426         select CPU_ARM920T
 427         select GENERIC_CLOCKEVENTS
 428         help
 429           This enables support for the Cirrus EP93xx series of CPUs.
 430
 431 config ARCH_FOOTBRIDGE
 432         bool "FootBridge"
 433         select CPU_SA110
 434         select FOOTBRIDGE
 435         select GENERIC_CLOCKEVENTS
 436         select HAVE_IDE
 437         select NEED_MACH_IO_H if !MMU
 438         select NEED_MACH_MEMORY_H
 439         help
 440           Support for systems based on the DC21285 companion chip
 441           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 442
 443 config ARCH_NETX
 444         bool "Hilscher NetX based"
 445         select ARM_VIC
 446         select CLKSRC_MMIO
 447         select CPU_ARM926T
 448         select GENERIC_CLOCKEVENTS
 449         help
 450           This enables support for systems based on the Hilscher NetX Soc
 451
 452 config ARCH_IOP13XX
 453         bool "IOP13xx-based"
 454         depends on MMU
 455         select CPU_XSC3
 456         select NEED_MACH_MEMORY_H
 457         select NEED_RET_TO_USER
 458         select PCI
 459         select PLAT_IOP
 460         select VMSPLIT_1G
 461         select SPARSE_IRQ
 462         help
 463           Support for Intel's IOP13XX (XScale) family of processors.
 464
 465 config ARCH_IOP32X
 466         bool "IOP32x-based"
 467         depends on MMU
 468         select ARCH_REQUIRE_GPIOLIB
 469         select CPU_XSCALE
 470         select GPIO_IOP
 471         select NEED_RET_TO_USER
 472         select PCI
 473         select PLAT_IOP
 474         help
 475           Support for Intel's 80219 and IOP32X (XScale) family of
 476           processors.
 477
 478 config ARCH_IOP33X
 479         bool "IOP33x-based"
 480         depends on MMU
 481         select ARCH_REQUIRE_GPIOLIB
 482         select CPU_XSCALE
 483         select GPIO_IOP
 484         select NEED_RET_TO_USER
 485         select PCI
 486         select PLAT_IOP
 487         help
 488           Support for Intel's IOP33X (XScale) family of processors.
 489
 490 config ARCH_IXP4XX
 491         bool "IXP4xx-based"
 492         depends on MMU
 493         select ARCH_HAS_DMA_SET_COHERENT_MASK
 494         select ARCH_REQUIRE_GPIOLIB
 495         select ARCH_SUPPORTS_BIG_ENDIAN
 496         select CLKSRC_MMIO
 497         select CPU_XSCALE
 498         select DMABOUNCE if PCI
 499         select GENERIC_CLOCKEVENTS
 500         select MIGHT_HAVE_PCI
 501         select NEED_MACH_IO_H
 502         select USB_EHCI_BIG_ENDIAN_DESC
 503         select USB_EHCI_BIG_ENDIAN_MMIO
 504         help
 505           Support for Intel's IXP4XX (XScale) family of processors.
 506
 507 config ARCH_DOVE
 508         bool "Marvell Dove"
 509         select ARCH_REQUIRE_GPIOLIB
 510         select CPU_PJ4
 511         select GENERIC_CLOCKEVENTS
 512         select MIGHT_HAVE_PCI
 513         select MVEBU_MBUS
 514         select PINCTRL
 515         select PINCTRL_DOVE
 516         select PLAT_ORION_LEGACY
 517         help
 518           Support for the Marvell Dove SoC 88AP510
 519
 520 config ARCH_MV78XX0
 521         bool "Marvell MV78xx0"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_FEROCEON
 524         select GENERIC_CLOCKEVENTS
 525         select MVEBU_MBUS
 526         select PCI
 527         select PLAT_ORION_LEGACY
 528         help
 529           Support for the following Marvell MV78xx0 series SoCs:
 530           MV781x0, MV782x0.
 531
 532 config ARCH_ORION5X
 533         bool "Marvell Orion"
 534         depends on MMU
 535         select ARCH_REQUIRE_GPIOLIB
 536         select CPU_FEROCEON
 537         select GENERIC_CLOCKEVENTS
 538         select MVEBU_MBUS
 539         select PCI
 540         select PLAT_ORION_LEGACY
 541         select MULTI_IRQ_HANDLER
 542         help
 543           Support for the following Marvell Orion 5x series SoCs:
 544           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 545           Orion-2 (5281), Orion-1-90 (6183).
 546
 547 config ARCH_MMP
 548         bool "Marvell PXA168/910/MMP2"
 549         depends on MMU
 550         select ARCH_REQUIRE_GPIOLIB
 551         select CLKDEV_LOOKUP
 552         select GENERIC_ALLOCATOR
 553         select GENERIC_CLOCKEVENTS
 554         select GPIO_PXA
 555         select IRQ_DOMAIN
 556         select MULTI_IRQ_HANDLER
 557         select PINCTRL
 558         select PLAT_PXA
 559         select SPARSE_IRQ
 560         help
 561           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 562
 563 config ARCH_KS8695
 564         bool "Micrel/Kendin KS8695"
 565         select ARCH_REQUIRE_GPIOLIB
 566         select CLKSRC_MMIO
 567         select CPU_ARM922T
 568         select GENERIC_CLOCKEVENTS
 569         select NEED_MACH_MEMORY_H
 570         help
 571           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 572           System-on-Chip devices.
 573
 574 config ARCH_W90X900
 575         bool "Nuvoton W90X900 CPU"
 576         select ARCH_REQUIRE_GPIOLIB
 577         select CLKDEV_LOOKUP
 578         select CLKSRC_MMIO
 579         select CPU_ARM926T
 580         select GENERIC_CLOCKEVENTS
 581         help
 582           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 583           At present, the w90x900 has been renamed nuc900, regarding
 584           the ARM series product line, you can login the following
 585           link address to know more.
 586
 587           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 588                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 589
 590 config ARCH_LPC32XX
 591         bool "NXP LPC32XX"
 592         select ARCH_REQUIRE_GPIOLIB
 593         select ARM_AMBA
 594         select CLKDEV_LOOKUP
 595         select CLKSRC_MMIO
 596         select CPU_ARM926T
 597         select GENERIC_CLOCKEVENTS
 598         select HAVE_IDE
 599         select USE_OF
 600         help
 601           Support for the NXP LPC32XX family of processors
 602
 603 config ARCH_PXA
 604         bool "PXA2xx/PXA3xx-based"
 605         depends on MMU
 606         select ARCH_MTD_XIP
 607         select ARCH_REQUIRE_GPIOLIB
 608         select ARM_CPU_SUSPEND if PM
 609         select AUTO_ZRELADDR
 610         select COMMON_CLK
 611         select CLKDEV_LOOKUP
 612         select CLKSRC_MMIO
 613         select CLKSRC_OF
 614         select GENERIC_CLOCKEVENTS
 615         select GPIO_PXA
 616         select HAVE_IDE
 617         select IRQ_DOMAIN
 618         select MULTI_IRQ_HANDLER
 619         select PLAT_PXA
 620         select SPARSE_IRQ
 621         help
 622           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 623
 624 config ARCH_RPC
 625         bool "RiscPC"
 626         depends on MMU
 627         select ARCH_ACORN
 628         select ARCH_MAY_HAVE_PC_FDC
 629         select ARCH_SPARSEMEM_ENABLE
 630         select ARCH_USES_GETTIMEOFFSET
 631         select CPU_SA110
 632         select FIQ
 633         select HAVE_IDE
 634         select HAVE_PATA_PLATFORM
 635         select ISA_DMA_API
 636         select NEED_MACH_IO_H
 637         select NEED_MACH_MEMORY_H
 638         select NO_IOPORT_MAP
 639         select VIRT_TO_BUS
 640         help
 641           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 642           CD-ROM interface, serial and parallel port, and the floppy drive.
 643
 644 config ARCH_SA1100
 645         bool "SA1100-based"
 646         select ARCH_MTD_XIP
 647         select ARCH_REQUIRE_GPIOLIB
 648         select ARCH_SPARSEMEM_ENABLE
 649         select CLKDEV_LOOKUP
 650         select CLKSRC_MMIO
 651         select CPU_FREQ
 652         select CPU_SA1100
 653         select GENERIC_CLOCKEVENTS
 654         select HAVE_IDE
 655         select IRQ_DOMAIN
 656         select ISA
 657         select MULTI_IRQ_HANDLER
 658         select NEED_MACH_MEMORY_H
 659         select SPARSE_IRQ
 660         help
 661           Support for StrongARM 11x0 based boards.
 662
 663 config ARCH_S3C24XX
 664         bool "Samsung S3C24XX SoCs"
 665         select ARCH_REQUIRE_GPIOLIB
 666         select ATAGS
 667         select CLKDEV_LOOKUP
 668         select CLKSRC_SAMSUNG_PWM
 669         select GENERIC_CLOCKEVENTS
 670         select GPIO_SAMSUNG
 671         select HAVE_S3C2410_I2C if I2C
 672         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 673         select HAVE_S3C_RTC if RTC_CLASS
 674         select MULTI_IRQ_HANDLER
 675         select NEED_MACH_IO_H
 676         select SAMSUNG_ATAGS
 677         help
 678           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 679           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 680           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 681           Samsung SMDK2410 development board (and derivatives).
 682
 683 config ARCH_S3C64XX
 684         bool "Samsung S3C64XX"
 685         select ARCH_REQUIRE_GPIOLIB
 686         select ARM_AMBA
 687         select ARM_VIC
 688         select ATAGS
 689         select CLKDEV_LOOKUP
 690         select CLKSRC_SAMSUNG_PWM
 691         select COMMON_CLK_SAMSUNG
 692         select CPU_V6K
 693         select GENERIC_CLOCKEVENTS
 694         select GPIO_SAMSUNG
 695         select HAVE_S3C2410_I2C if I2C
 696         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 697         select HAVE_TCM
 698         select NO_IOPORT_MAP
 699         select PLAT_SAMSUNG
 700         select PM_GENERIC_DOMAINS if PM
 701         select S3C_DEV_NAND
 702         select S3C_GPIO_TRACK
 703         select SAMSUNG_ATAGS
 704         select SAMSUNG_WAKEMASK
 705         select SAMSUNG_WDT_RESET
 706         help
 707           Samsung S3C64XX series based systems
 708
 709 config ARCH_DAVINCI
 710         bool "TI DaVinci"
 711         select ARCH_HAS_HOLES_MEMORYMODEL
 712         select ARCH_REQUIRE_GPIOLIB
 713         select CLKDEV_LOOKUP
 714         select GENERIC_ALLOCATOR
 715         select GENERIC_CLOCKEVENTS
 716         select GENERIC_IRQ_CHIP
 717         select HAVE_IDE
 718         select USE_OF
 719         select ZONE_DMA
 720         help
 721           Support for TI's DaVinci platform.
 722
 723 config ARCH_OMAP1
 724         bool "TI OMAP1"
 725         depends on MMU
 726         select ARCH_HAS_HOLES_MEMORYMODEL
 727         select ARCH_OMAP
 728         select ARCH_REQUIRE_GPIOLIB
 729         select CLKDEV_LOOKUP
 730         select CLKSRC_MMIO
 731         select GENERIC_CLOCKEVENTS
 732         select GENERIC_IRQ_CHIP
 733         select HAVE_IDE
 734         select IRQ_DOMAIN
 735         select MULTI_IRQ_HANDLER
 736         select NEED_MACH_IO_H if PCCARD
 737         select NEED_MACH_MEMORY_H
 738         select SPARSE_IRQ
 739         help
 740           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 741
 742 endchoice
 743
 744 menu "Multiple platform selection"
 745         depends on ARCH_MULTIPLATFORM
 746
 747 comment "CPU Core family selection"
 748
 749 config ARCH_MULTI_V4
 750         bool "ARMv4 based platforms (FA526)"
 751         depends on !ARCH_MULTI_V6_V7
 752         select ARCH_MULTI_V4_V5
 753         select CPU_FA526
 754
 755 config ARCH_MULTI_V4T
 756         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 757         depends on !ARCH_MULTI_V6_V7
 758         select ARCH_MULTI_V4_V5
 759         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 760                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 761                 CPU_ARM925T || CPU_ARM940T)
 762
 763 config ARCH_MULTI_V5
 764         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 765         depends on !ARCH_MULTI_V6_V7
 766         select ARCH_MULTI_V4_V5
 767         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 768                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 769                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 770
 771 config ARCH_MULTI_V4_V5
 772         bool
 773
 774 config ARCH_MULTI_V6
 775         bool "ARMv6 based platforms (ARM11)"
 776         select ARCH_MULTI_V6_V7
 777         select CPU_V6K
 778
 779 config ARCH_MULTI_V7
 780         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 781         default y
 782         select ARCH_MULTI_V6_V7
 783         select CPU_V7
 784         select HAVE_SMP
 785
 786 config ARCH_MULTI_V6_V7
 787         bool
 788         select MIGHT_HAVE_CACHE_L2X0
 789
 790 config ARCH_MULTI_CPU_AUTO
 791         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 792         select ARCH_MULTI_V5
 793
 794 endmenu
 795
 796 config ARCH_VIRT
 797         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 798         select ARM_AMBA
 799         select ARM_GIC
 800         select ARM_GIC_V3
 801         select ARM_PSCI
 802         select HAVE_ARM_ARCH_TIMER
 803
 804 #
 805 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 806 # Kconfigs may be included either alphabetically (according to the
 807 # plat- suffix) or along side the corresponding mach-* source.
 808 #
 809 source "arch/arm/mach-mvebu/Kconfig"
 810
 811 source "arch/arm/mach-alpine/Kconfig"
 812
 813 source "arch/arm/mach-asm9260/Kconfig"
 814
 815 source "arch/arm/mach-at91/Kconfig"
 816
 817 source "arch/arm/mach-axxia/Kconfig"
 818
 819 source "arch/arm/mach-bcm/Kconfig"
 820
 821 source "arch/arm/mach-berlin/Kconfig"
 822
 823 source "arch/arm/mach-clps711x/Kconfig"
 824
 825 source "arch/arm/mach-cns3xxx/Kconfig"
 826
 827 source "arch/arm/mach-davinci/Kconfig"
 828
 829 source "arch/arm/mach-digicolor/Kconfig"
 830
 831 source "arch/arm/mach-dove/Kconfig"
 832
 833 source "arch/arm/mach-ep93xx/Kconfig"
 834
 835 source "arch/arm/mach-footbridge/Kconfig"
 836
 837 source "arch/arm/mach-gemini/Kconfig"
 838
 839 source "arch/arm/mach-highbank/Kconfig"
 840
 841 source "arch/arm/mach-hisi/Kconfig"
 842
 843 source "arch/arm/mach-integrator/Kconfig"
 844
 845 source "arch/arm/mach-iop32x/Kconfig"
 846
 847 source "arch/arm/mach-iop33x/Kconfig"
 848
 849 source "arch/arm/mach-iop13xx/Kconfig"
 850
 851 source "arch/arm/mach-ixp4xx/Kconfig"
 852
 853 source "arch/arm/mach-keystone/Kconfig"
 854
 855 source "arch/arm/mach-ks8695/Kconfig"
 856
 857 source "arch/arm/mach-meson/Kconfig"
 858
 859 source "arch/arm/mach-moxart/Kconfig"
 860
 861 source "arch/arm/mach-mv78xx0/Kconfig"
 862
 863 source "arch/arm/mach-imx/Kconfig"
 864
 865 source "arch/arm/mach-mediatek/Kconfig"
 866
 867 source "arch/arm/mach-mxs/Kconfig"
 868
 869 source "arch/arm/mach-netx/Kconfig"
 870
 871 source "arch/arm/mach-nomadik/Kconfig"
 872
 873 source "arch/arm/mach-nspire/Kconfig"
 874
 875 source "arch/arm/plat-omap/Kconfig"
 876
 877 source "arch/arm/mach-omap1/Kconfig"
 878
 879 source "arch/arm/mach-omap2/Kconfig"
 880
 881 source "arch/arm/mach-orion5x/Kconfig"
 882
 883 source "arch/arm/mach-picoxcell/Kconfig"
 884
 885 source "arch/arm/mach-pxa/Kconfig"
 886 source "arch/arm/plat-pxa/Kconfig"
 887
 888 source "arch/arm/mach-mmp/Kconfig"
 889
 890 source "arch/arm/mach-qcom/Kconfig"
 891
 892 source "arch/arm/mach-realview/Kconfig"
 893
 894 source "arch/arm/mach-rockchip/Kconfig"
 895
 896 source "arch/arm/mach-sa1100/Kconfig"
 897
 898 source "arch/arm/mach-socfpga/Kconfig"
 899
 900 source "arch/arm/mach-spear/Kconfig"
 901
 902 source "arch/arm/mach-sti/Kconfig"
 903
 904 source "arch/arm/mach-s3c24xx/Kconfig"
 905
 906 source "arch/arm/mach-s3c64xx/Kconfig"
 907
 908 source "arch/arm/mach-s5pv210/Kconfig"
 909
 910 source "arch/arm/mach-exynos/Kconfig"
 911 source "arch/arm/plat-samsung/Kconfig"
 912
 913 source "arch/arm/mach-shmobile/Kconfig"
 914
 915 source "arch/arm/mach-sunxi/Kconfig"
 916
 917 source "arch/arm/mach-prima2/Kconfig"
 918
 919 source "arch/arm/mach-tegra/Kconfig"
 920
 921 source "arch/arm/mach-u300/Kconfig"
 922
 923 source "arch/arm/mach-uniphier/Kconfig"
 924
 925 source "arch/arm/mach-ux500/Kconfig"
 926
 927 source "arch/arm/mach-versatile/Kconfig"
 928
 929 source "arch/arm/mach-vexpress/Kconfig"
 930 source "arch/arm/plat-versatile/Kconfig"
 931
 932 source "arch/arm/mach-vt8500/Kconfig"
 933
 934 source "arch/arm/mach-w90x900/Kconfig"
 935
 936 source "arch/arm/mach-zx/Kconfig"
 937
 938 source "arch/arm/mach-zynq/Kconfig"
 939
 940 # ARMv7-M architecture
 941 config ARCH_EFM32
 942         bool "Energy Micro efm32"
 943         depends on ARM_SINGLE_ARMV7M
 944         select ARCH_REQUIRE_GPIOLIB
 945         help
 946           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 947           processors.
 948
 949 config ARCH_LPC18XX
 950         bool "NXP LPC18xx/LPC43xx"
 951         depends on ARM_SINGLE_ARMV7M
 952         select ARCH_HAS_RESET_CONTROLLER
 953         select ARM_AMBA
 954         select CLKSRC_LPC32XX
 955         select PINCTRL
 956         help
 957           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 958           high performance microcontrollers.
 959
 960 config ARCH_STM32
 961         bool "STMicrolectronics STM32"
 962         depends on ARM_SINGLE_ARMV7M
 963         select ARCH_HAS_RESET_CONTROLLER
 964         select ARMV7M_SYSTICK
 965         select CLKSRC_STM32
 966         select RESET_CONTROLLER
 967         help
 968           Support for STMicroelectronics STM32 processors.
 969
 970 # Definitions to make life easier
 971 config ARCH_ACORN
 972         bool
 973
 974 config PLAT_IOP
 975         bool
 976         select GENERIC_CLOCKEVENTS
 977
 978 config PLAT_ORION
 979         bool
 980         select CLKSRC_MMIO
 981         select COMMON_CLK
 982         select GENERIC_IRQ_CHIP
 983         select IRQ_DOMAIN
 984
 985 config PLAT_ORION_LEGACY
 986         bool
 987         select PLAT_ORION
 988
 989 config PLAT_PXA
 990         bool
 991
 992 config PLAT_VERSATILE
 993         bool
 994
 995 source "arch/arm/firmware/Kconfig"
 996
 997 source arch/arm/mm/Kconfig
 998
 999 config IWMMXT
1000         bool "Enable iWMMXt support"
1001         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1002         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1003         help
1004           Enable support for iWMMXt context switching at run time if
1005           running on a CPU that supports it.
1006
1007 config MULTI_IRQ_HANDLER
1008         bool
1009         help
1010           Allow each machine to specify it's own IRQ handler at run time.
1011
1012 if !MMU
1013 source "arch/arm/Kconfig-nommu"
1014 endif
1015
1016 config PJ4B_ERRATA_4742
1017         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1018         depends on CPU_PJ4B && MACH_ARMADA_370
1019         default y
1020         help
1021           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1022           Event (WFE) IDLE states, a specific timing sensitivity exists between
1023           the retiring WFI/WFE instructions and the newly issued subsequent
1024           instructions.  This sensitivity can result in a CPU hang scenario.
1025           Workaround:
1026           The software must insert either a Data Synchronization Barrier (DSB)
1027           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1028           instruction
1029
1030 config ARM_ERRATA_326103
1031         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1032         depends on CPU_V6
1033         help
1034           Executing a SWP instruction to read-only memory does not set bit 11
1035           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1036           treat the access as a read, preventing a COW from occurring and
1037           causing the faulting task to livelock.
1038
1039 config ARM_ERRATA_411920
1040         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1041         depends on CPU_V6 || CPU_V6K
1042         help
1043           Invalidation of the Instruction Cache operation can
1044           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1045           It does not affect the MPCore. This option enables the ARM Ltd.
1046           recommended workaround.
1047
1048 config ARM_ERRATA_430973
1049         bool "ARM errata: Stale prediction on replaced interworking branch"
1050         depends on CPU_V7
1051         help
1052           This option enables the workaround for the 430973 Cortex-A8
1053           r1p* erratum. If a code sequence containing an ARM/Thumb
1054           interworking branch is replaced with another code sequence at the
1055           same virtual address, whether due to self-modifying code or virtual
1056           to physical address re-mapping, Cortex-A8 does not recover from the
1057           stale interworking branch prediction. This results in Cortex-A8
1058           executing the new code sequence in the incorrect ARM or Thumb state.
1059           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1060           and also flushes the branch target cache at every context switch.
1061           Note that setting specific bits in the ACTLR register may not be
1062           available in non-secure mode.
1063
1064 config ARM_ERRATA_458693
1065         bool "ARM errata: Processor deadlock when a false hazard is created"
1066         depends on CPU_V7
1067         depends on !ARCH_MULTIPLATFORM
1068         help
1069           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1070           erratum. For very specific sequences of memory operations, it is
1071           possible for a hazard condition intended for a cache line to instead
1072           be incorrectly associated with a different cache line. This false
1073           hazard might then cause a processor deadlock. The workaround enables
1074           the L1 caching of the NEON accesses and disables the PLD instruction
1075           in the ACTLR register. Note that setting specific bits in the ACTLR
1076           register may not be available in non-secure mode.
1077
1078 config ARM_ERRATA_460075
1079         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1080         depends on CPU_V7
1081         depends on !ARCH_MULTIPLATFORM
1082         help
1083           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1084           erratum. Any asynchronous access to the L2 cache may encounter a
1085           situation in which recent store transactions to the L2 cache are lost
1086           and overwritten with stale memory contents from external memory. The
1087           workaround disables the write-allocate mode for the L2 cache via the
1088           ACTLR register. Note that setting specific bits in the ACTLR register
1089           may not be available in non-secure mode.
1090
1091 config ARM_ERRATA_742230
1092         bool "ARM errata: DMB operation may be faulty"
1093         depends on CPU_V7 && SMP
1094         depends on !ARCH_MULTIPLATFORM
1095         help
1096           This option enables the workaround for the 742230 Cortex-A9
1097           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1098           between two write operations may not ensure the correct visibility
1099           ordering of the two writes. This workaround sets a specific bit in
1100           the diagnostic register of the Cortex-A9 which causes the DMB
1101           instruction to behave as a DSB, ensuring the correct behaviour of
1102           the two writes.
1103
1104 config ARM_ERRATA_742231
1105         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1106         depends on CPU_V7 && SMP
1107         depends on !ARCH_MULTIPLATFORM
1108         help
1109           This option enables the workaround for the 742231 Cortex-A9
1110           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1111           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1112           accessing some data located in the same cache line, may get corrupted
1113           data due to bad handling of the address hazard when the line gets
1114           replaced from one of the CPUs at the same time as another CPU is
1115           accessing it. This workaround sets specific bits in the diagnostic
1116           register of the Cortex-A9 which reduces the linefill issuing
1117           capabilities of the processor.
1118
1119 config ARM_ERRATA_643719
1120         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1121         depends on CPU_V7 && SMP
1122         default y
1123         help
1124           This option enables the workaround for the 643719 Cortex-A9 (prior to
1125           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1126           register returns zero when it should return one. The workaround
1127           corrects this value, ensuring cache maintenance operations which use
1128           it behave as intended and avoiding data corruption.
1129
1130 config ARM_ERRATA_720789
1131         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1132         depends on CPU_V7
1133         help
1134           This option enables the workaround for the 720789 Cortex-A9 (prior to
1135           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1136           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1137           As a consequence of this erratum, some TLB entries which should be
1138           invalidated are not, resulting in an incoherency in the system page
1139           tables. The workaround changes the TLB flushing routines to invalidate
1140           entries regardless of the ASID.
1141
1142 config ARM_ERRATA_743622
1143         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1144         depends on CPU_V7
1145         depends on !ARCH_MULTIPLATFORM
1146         help
1147           This option enables the workaround for the 743622 Cortex-A9
1148           (r2p*) erratum. Under very rare conditions, a faulty
1149           optimisation in the Cortex-A9 Store Buffer may lead to data
1150           corruption. This workaround sets a specific bit in the diagnostic
1151           register of the Cortex-A9 which disables the Store Buffer
1152           optimisation, preventing the defect from occurring. This has no
1153           visible impact on the overall performance or power consumption of the
1154           processor.
1155
1156 config ARM_ERRATA_751472
1157         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1158         depends on CPU_V7
1159         depends on !ARCH_MULTIPLATFORM
1160         help
1161           This option enables the workaround for the 751472 Cortex-A9 (prior
1162           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1163           completion of a following broadcasted operation if the second
1164           operation is received by a CPU before the ICIALLUIS has completed,
1165           potentially leading to corrupted entries in the cache or TLB.
1166
1167 config ARM_ERRATA_754322
1168         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1169         depends on CPU_V7
1170         help
1171           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1172           r3p*) erratum. A speculative memory access may cause a page table walk
1173           which starts prior to an ASID switch but completes afterwards. This
1174           can populate the micro-TLB with a stale entry which may be hit with
1175           the new ASID. This workaround places two dsb instructions in the mm
1176           switching code so that no page table walks can cross the ASID switch.
1177
1178 config ARM_ERRATA_754327
1179         bool "ARM errata: no automatic Store Buffer drain"
1180         depends on CPU_V7 && SMP
1181         help
1182           This option enables the workaround for the 754327 Cortex-A9 (prior to
1183           r2p0) erratum. The Store Buffer does not have any automatic draining
1184           mechanism and therefore a livelock may occur if an external agent
1185           continuously polls a memory location waiting to observe an update.
1186           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1187           written polling loops from denying visibility of updates to memory.
1188
1189 config ARM_ERRATA_364296
1190         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1191         depends on CPU_V6
1192         help
1193           This options enables the workaround for the 364296 ARM1136
1194           r0p2 erratum (possible cache data corruption with
1195           hit-under-miss enabled). It sets the undocumented bit 31 in
1196           the auxiliary control register and the FI bit in the control
1197           register, thus disabling hit-under-miss without putting the
1198           processor into full low interrupt latency mode. ARM11MPCore
1199           is not affected.
1200
1201 config ARM_ERRATA_764369
1202         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1203         depends on CPU_V7 && SMP
1204         help
1205           This option enables the workaround for erratum 764369
1206           affecting Cortex-A9 MPCore with two or more processors (all
1207           current revisions). Under certain timing circumstances, a data
1208           cache line maintenance operation by MVA targeting an Inner
1209           Shareable memory region may fail to proceed up to either the
1210           Point of Coherency or to the Point of Unification of the
1211           system. This workaround adds a DSB instruction before the
1212           relevant cache maintenance functions and sets a specific bit
1213           in the diagnostic control register of the SCU.
1214
1215 config ARM_ERRATA_775420
1216        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1217        depends on CPU_V7
1218        help
1219          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1220          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1221          operation aborts with MMU exception, it might cause the processor
1222          to deadlock. This workaround puts DSB before executing ISB if
1223          an abort may occur on cache maintenance.
1224
1225 config ARM_ERRATA_798181
1226         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1227         depends on CPU_V7 && SMP
1228         help
1229           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1230           adequately shooting down all use of the old entries. This
1231           option enables the Linux kernel workaround for this erratum
1232           which sends an IPI to the CPUs that are running the same ASID
1233           as the one being invalidated.
1234
1235 config ARM_ERRATA_773022
1236         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1237         depends on CPU_V7
1238         help
1239           This option enables the workaround for the 773022 Cortex-A15
1240           (up to r0p4) erratum. In certain rare sequences of code, the
1241           loop buffer may deliver incorrect instructions. This
1242           workaround disables the loop buffer to avoid the erratum.
1243
1244 endmenu
1245
1246 source "arch/arm/common/Kconfig"
1247
1248 menu "Bus support"
1249
1250 config ISA
1251         bool
1252         help
1253           Find out whether you have ISA slots on your motherboard.  ISA is the
1254           name of a bus system, i.e. the way the CPU talks to the other stuff
1255           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1256           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1257           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1258
1259 # Select ISA DMA controller support
1260 config ISA_DMA
1261         bool
1262         select ISA_DMA_API
1263
1264 # Select ISA DMA interface
1265 config ISA_DMA_API
1266         bool
1267
1268 config PCI
1269         bool "PCI support" if MIGHT_HAVE_PCI
1270         help
1271           Find out whether you have a PCI motherboard. PCI is the name of a
1272           bus system, i.e. the way the CPU talks to the other stuff inside
1273           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1274           VESA. If you have PCI, say Y, otherwise N.
1275
1276 config PCI_DOMAINS
1277         bool
1278         depends on PCI
1279
1280 config PCI_DOMAINS_GENERIC
1281         def_bool PCI_DOMAINS
1282
1283 config PCI_NANOENGINE
1284         bool "BSE nanoEngine PCI support"
1285         depends on SA1100_NANOENGINE
1286         help
1287           Enable PCI on the BSE nanoEngine board.
1288
1289 config PCI_SYSCALL
1290         def_bool PCI
1291
1292 config PCI_HOST_ITE8152
1293         bool
1294         depends on PCI && MACH_ARMCORE
1295         default y
1296         select DMABOUNCE
1297
1298 source "drivers/pci/Kconfig"
1299 source "drivers/pci/pcie/Kconfig"
1300
1301 source "drivers/pcmcia/Kconfig"
1302
1303 endmenu
1304
1305 menu "Kernel Features"
1306
1307 config HAVE_SMP
1308         bool
1309         help
1310           This option should be selected by machines which have an SMP-
1311           capable CPU.
1312
1313           The only effect of this option is to make the SMP-related
1314           options available to the user for configuration.
1315
1316 config SMP
1317         bool "Symmetric Multi-Processing"
1318         depends on CPU_V6K || CPU_V7
1319         depends on GENERIC_CLOCKEVENTS
1320         depends on HAVE_SMP
1321         depends on MMU || ARM_MPU
1322         select IRQ_WORK
1323         help
1324           This enables support for systems with more than one CPU. If you have
1325           a system with only one CPU, say N. If you have a system with more
1326           than one CPU, say Y.
1327
1328           If you say N here, the kernel will run on uni- and multiprocessor
1329           machines, but will use only one CPU of a multiprocessor machine. If
1330           you say Y here, the kernel will run on many, but not all,
1331           uniprocessor machines. On a uniprocessor machine, the kernel
1332           will run faster if you say N here.
1333
1334           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1335           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1336           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1337
1338           If you don't know what to do here, say N.
1339
1340 config SMP_ON_UP
1341         bool "Allow booting SMP kernel on uniprocessor systems"
1342         depends on SMP && !XIP_KERNEL && MMU
1343         default y
1344         help
1345           SMP kernels contain instructions which fail on non-SMP processors.
1346           Enabling this option allows the kernel to modify itself to make
1347           these instructions safe.  Disabling it allows about 1K of space
1348           savings.
1349
1350           If you don't know what to do here, say Y.
1351
1352 config ARM_CPU_TOPOLOGY
1353         bool "Support cpu topology definition"
1354         depends on SMP && CPU_V7
1355         default y
1356         help
1357           Support ARM cpu topology definition. The MPIDR register defines
1358           affinity between processors which is then used to describe the cpu
1359           topology of an ARM System.
1360
1361 config SCHED_MC
1362         bool "Multi-core scheduler support"
1363         depends on ARM_CPU_TOPOLOGY
1364         help
1365           Multi-core scheduler support improves the CPU scheduler's decision
1366           making when dealing with multi-core CPU chips at a cost of slightly
1367           increased overhead in some places. If unsure say N here.
1368
1369 config SCHED_SMT
1370         bool "SMT scheduler support"
1371         depends on ARM_CPU_TOPOLOGY
1372         help
1373           Improves the CPU scheduler's decision making when dealing with
1374           MultiThreading at a cost of slightly increased overhead in some
1375           places. If unsure say N here.
1376
1377 config HAVE_ARM_SCU
1378         bool
1379         help
1380           This option enables support for the ARM system coherency unit
1381
1382 config HAVE_ARM_ARCH_TIMER
1383         bool "Architected timer support"
1384         depends on CPU_V7
1385         select ARM_ARCH_TIMER
1386         select GENERIC_CLOCKEVENTS
1387         help
1388           This option enables support for the ARM architected timer
1389
1390 config HAVE_ARM_TWD
1391         bool
1392         select CLKSRC_OF if OF
1393         help
1394           This options enables support for the ARM timer and watchdog unit
1395
1396 config MCPM
1397         bool "Multi-Cluster Power Management"
1398         depends on CPU_V7 && SMP
1399         help
1400           This option provides the common power management infrastructure
1401           for (multi-)cluster based systems, such as big.LITTLE based
1402           systems.
1403
1404 config MCPM_QUAD_CLUSTER
1405         bool
1406         depends on MCPM
1407         help
1408           To avoid wasting resources unnecessarily, MCPM only supports up
1409           to 2 clusters by default.
1410           Platforms with 3 or 4 clusters that use MCPM must select this
1411           option to allow the additional clusters to be managed.
1412
1413 config BIG_LITTLE
1414         bool "big.LITTLE support (Experimental)"
1415         depends on CPU_V7 && SMP
1416         select MCPM
1417         help
1418           This option enables support selections for the big.LITTLE
1419           system architecture.
1420
1421 config BL_SWITCHER
1422         bool "big.LITTLE switcher support"
1423         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1424         select ARM_CPU_SUSPEND
1425         select CPU_PM
1426         help
1427           The big.LITTLE "switcher" provides the core functionality to
1428           transparently handle transition between a cluster of A15's
1429           and a cluster of A7's in a big.LITTLE system.
1430
1431 config BL_SWITCHER_DUMMY_IF
1432         tristate "Simple big.LITTLE switcher user interface"
1433         depends on BL_SWITCHER && DEBUG_KERNEL
1434         help
1435           This is a simple and dummy char dev interface to control
1436           the big.LITTLE switcher core code.  It is meant for
1437           debugging purposes only.
1438
1439 choice
1440         prompt "Memory split"
1441         depends on MMU
1442         default VMSPLIT_3G
1443         help
1444           Select the desired split between kernel and user memory.
1445
1446           If you are not absolutely sure what you are doing, leave this
1447           option alone!
1448
1449         config VMSPLIT_3G
1450                 bool "3G/1G user/kernel split"
1451         config VMSPLIT_3G_OPT
1452                 bool "3G/1G user/kernel split (for full 1G low memory)"
1453         config VMSPLIT_2G
1454                 bool "2G/2G user/kernel split"
1455         config VMSPLIT_1G
1456                 bool "1G/3G user/kernel split"
1457 endchoice
1458
1459 config PAGE_OFFSET
1460         hex
1461         default PHYS_OFFSET if !MMU
1462         default 0x40000000 if VMSPLIT_1G
1463         default 0x80000000 if VMSPLIT_2G
1464         default 0xB0000000 if VMSPLIT_3G_OPT
1465         default 0xC0000000
1466
1467 config NR_CPUS
1468         int "Maximum number of CPUs (2-32)"
1469         range 2 32
1470         depends on SMP
1471         default "4"
1472
1473 config HOTPLUG_CPU
1474         bool "Support for hot-pluggable CPUs"
1475         depends on SMP
1476         help
1477           Say Y here to experiment with turning CPUs off and on.  CPUs
1478           can be controlled through /sys/devices/system/cpu.
1479
1480 config ARM_PSCI
1481         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1482         depends on CPU_V7
1483         select ARM_PSCI_FW
1484         help
1485           Say Y here if you want Linux to communicate with system firmware
1486           implementing the PSCI specification for CPU-centric power
1487           management operations described in ARM document number ARM DEN
1488           0022A ("Power State Coordination Interface System Software on
1489           ARM processors").
1490
1491 # The GPIO number here must be sorted by descending number. In case of
1492 # a multiplatform kernel, we just want the highest value required by the
1493 # selected platforms.
1494 config ARCH_NR_GPIO
1495         int
1496         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1497                 ARCH_ZYNQ
1498         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1499                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1500         default 416 if ARCH_SUNXI
1501         default 392 if ARCH_U8500
1502         default 352 if ARCH_VT8500
1503         default 288 if ARCH_ROCKCHIP
1504         default 264 if MACH_H4700
1505         default 0
1506         help
1507           Maximum number of GPIOs in the system.
1508
1509           If unsure, leave the default value.
1510
1511 source kernel/Kconfig.preempt
1512
1513 config HZ_FIXED
1514         int
1515         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1516                 ARCH_S5PV210 || ARCH_EXYNOS4
1517         default 128 if SOC_AT91RM9200
1518         default 0
1519
1520 choice
1521         depends on HZ_FIXED = 0
1522         prompt "Timer frequency"
1523
1524 config HZ_100
1525         bool "100 Hz"
1526
1527 config HZ_200
1528         bool "200 Hz"
1529
1530 config HZ_250
1531         bool "250 Hz"
1532
1533 config HZ_300
1534         bool "300 Hz"
1535
1536 config HZ_500
1537         bool "500 Hz"
1538
1539 config HZ_1000
1540         bool "1000 Hz"
1541
1542 endchoice
1543
1544 config HZ
1545         int
1546         default HZ_FIXED if HZ_FIXED != 0
1547         default 100 if HZ_100
1548         default 200 if HZ_200
1549         default 250 if HZ_250
1550         default 300 if HZ_300
1551         default 500 if HZ_500
1552         default 1000
1553
1554 config SCHED_HRTICK
1555         def_bool HIGH_RES_TIMERS
1556
1557 config THUMB2_KERNEL
1558         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1559         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1560         default y if CPU_THUMBONLY
1561         select AEABI
1562         select ARM_ASM_UNIFIED
1563         select ARM_UNWIND
1564         help
1565           By enabling this option, the kernel will be compiled in
1566           Thumb-2 mode. A compiler/assembler that understand the unified
1567           ARM-Thumb syntax is needed.
1568
1569           If unsure, say N.
1570
1571 config THUMB2_AVOID_R_ARM_THM_JUMP11
1572         bool "Work around buggy Thumb-2 short branch relocations in gas"
1573         depends on THUMB2_KERNEL && MODULES
1574         default y
1575         help
1576           Various binutils versions can resolve Thumb-2 branches to
1577           locally-defined, preemptible global symbols as short-range "b.n"
1578           branch instructions.
1579
1580           This is a problem, because there's no guarantee the final
1581           destination of the symbol, or any candidate locations for a
1582           trampoline, are within range of the branch.  For this reason, the
1583           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1584           relocation in modules at all, and it makes little sense to add
1585           support.
1586
1587           The symptom is that the kernel fails with an "unsupported
1588           relocation" error when loading some modules.
1589
1590           Until fixed tools are available, passing
1591           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1592           code which hits this problem, at the cost of a bit of extra runtime
1593           stack usage in some cases.
1594
1595           The problem is described in more detail at:
1596               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1597
1598           Only Thumb-2 kernels are affected.
1599
1600           Unless you are sure your tools don't have this problem, say Y.
1601
1602 config ARM_ASM_UNIFIED
1603         bool
1604
1605 config AEABI
1606         bool "Use the ARM EABI to compile the kernel"
1607         help
1608           This option allows for the kernel to be compiled using the latest
1609           ARM ABI (aka EABI).  This is only useful if you are using a user
1610           space environment that is also compiled with EABI.
1611
1612           Since there are major incompatibilities between the legacy ABI and
1613           EABI, especially with regard to structure member alignment, this
1614           option also changes the kernel syscall calling convention to
1615           disambiguate both ABIs and allow for backward compatibility support
1616           (selected with CONFIG_OABI_COMPAT).
1617
1618           To use this you need GCC version 4.0.0 or later.
1619
1620 config OABI_COMPAT
1621         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1622         depends on AEABI && !THUMB2_KERNEL
1623         help
1624           This option preserves the old syscall interface along with the
1625           new (ARM EABI) one. It also provides a compatibility layer to
1626           intercept syscalls that have structure arguments which layout
1627           in memory differs between the legacy ABI and the new ARM EABI
1628           (only for non "thumb" binaries). This option adds a tiny
1629           overhead to all syscalls and produces a slightly larger kernel.
1630
1631           The seccomp filter system will not be available when this is
1632           selected, since there is no way yet to sensibly distinguish
1633           between calling conventions during filtering.
1634
1635           If you know you'll be using only pure EABI user space then you
1636           can say N here. If this option is not selected and you attempt
1637           to execute a legacy ABI binary then the result will be
1638           UNPREDICTABLE (in fact it can be predicted that it won't work
1639           at all). If in doubt say N.
1640
1641 config ARCH_HAS_HOLES_MEMORYMODEL
1642         bool
1643
1644 config ARCH_SPARSEMEM_ENABLE
1645         bool
1646
1647 config ARCH_SPARSEMEM_DEFAULT
1648         def_bool ARCH_SPARSEMEM_ENABLE
1649
1650 config ARCH_SELECT_MEMORY_MODEL
1651         def_bool ARCH_SPARSEMEM_ENABLE
1652
1653 config HAVE_ARCH_PFN_VALID
1654         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1655
1656 config HAVE_GENERIC_RCU_GUP
1657         def_bool y
1658         depends on ARM_LPAE
1659
1660 config HIGHMEM
1661         bool "High Memory Support"
1662         depends on MMU
1663         help
1664           The address space of ARM processors is only 4 Gigabytes large
1665           and it has to accommodate user address space, kernel address
1666           space as well as some memory mapped IO. That means that, if you
1667           have a large amount of physical memory and/or IO, not all of the
1668           memory can be "permanently mapped" by the kernel. The physical
1669           memory that is not permanently mapped is called "high memory".
1670
1671           Depending on the selected kernel/user memory split, minimum
1672           vmalloc space and actual amount of RAM, you may not need this
1673           option which should result in a slightly faster kernel.
1674
1675           If unsure, say n.
1676
1677 config HIGHPTE
1678         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1679         depends on HIGHMEM
1680         default y
1681         help
1682           The VM uses one page of physical memory for each page table.
1683           For systems with a lot of processes, this can use a lot of
1684           precious low memory, eventually leading to low memory being
1685           consumed by page tables.  Setting this option will allow
1686           user-space 2nd level page tables to reside in high memory.
1687
1688 config CPU_SW_DOMAIN_PAN
1689         bool "Enable use of CPU domains to implement privileged no-access"
1690         depends on MMU && !ARM_LPAE
1691         default y
1692         help
1693           Increase kernel security by ensuring that normal kernel accesses
1694           are unable to access userspace addresses.  This can help prevent
1695           use-after-free bugs becoming an exploitable privilege escalation
1696           by ensuring that magic values (such as LIST_POISON) will always
1697           fault when dereferenced.
1698
1699           CPUs with low-vector mappings use a best-efforts implementation.
1700           Their lower 1MB needs to remain accessible for the vectors, but
1701           the remainder of userspace will become appropriately inaccessible.
1702
1703 config HW_PERF_EVENTS
1704         def_bool y
1705         depends on ARM_PMU
1706
1707 config SYS_SUPPORTS_HUGETLBFS
1708        def_bool y
1709        depends on ARM_LPAE
1710
1711 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1712        def_bool y
1713        depends on ARM_LPAE
1714
1715 config ARCH_WANT_GENERAL_HUGETLB
1716         def_bool y
1717
1718 config ARM_MODULE_PLTS
1719         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1720         depends on MODULES
1721         help
1722           Allocate PLTs when loading modules so that jumps and calls whose
1723           targets are too far away for their relative offsets to be encoded
1724           in the instructions themselves can be bounced via veneers in the
1725           module's PLT. This allows modules to be allocated in the generic
1726           vmalloc area after the dedicated module memory area has been
1727           exhausted. The modules will use slightly more memory, but after
1728           rounding up to page size, the actual memory footprint is usually
1729           the same.
1730
1731           Say y if you are getting out of memory errors while loading modules
1732
1733 source "mm/Kconfig"
1734
1735 config FORCE_MAX_ZONEORDER
1736         int "Maximum zone order"
1737         default "12" if SOC_AM33XX
1738         default "9" if SA1111 || ARCH_EFM32
1739         default "11"
1740         help
1741           The kernel memory allocator divides physically contiguous memory
1742           blocks into "zones", where each zone is a power of two number of
1743           pages.  This option selects the largest power of two that the kernel
1744           keeps in the memory allocator.  If you need to allocate very large
1745           blocks of physically contiguous memory, then you may need to
1746           increase this value.
1747
1748           This config option is actually maximum order plus one. For example,
1749           a value of 11 means that the largest free memory block is 2^10 pages.
1750
1751 config ALIGNMENT_TRAP
1752         bool
1753         depends on CPU_CP15_MMU
1754         default y if !ARCH_EBSA110
1755         select HAVE_PROC_CPU if PROC_FS
1756         help
1757           ARM processors cannot fetch/store information which is not
1758           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1759           address divisible by 4. On 32-bit ARM processors, these non-aligned
1760           fetch/store instructions will be emulated in software if you say
1761           here, which has a severe performance impact. This is necessary for
1762           correct operation of some network protocols. With an IP-only
1763           configuration it is safe to say N, otherwise say Y.
1764
1765 config UACCESS_WITH_MEMCPY
1766         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1767         depends on MMU
1768         default y if CPU_FEROCEON
1769         help
1770           Implement faster copy_to_user and clear_user methods for CPU
1771           cores where a 8-word STM instruction give significantly higher
1772           memory write throughput than a sequence of individual 32bit stores.
1773
1774           A possible side effect is a slight increase in scheduling latency
1775           between threads sharing the same address space if they invoke
1776           such copy operations with large buffers.
1777
1778           However, if the CPU data cache is using a write-allocate mode,
1779           this option is unlikely to provide any performance gain.
1780
1781 config SECCOMP
1782         bool
1783         prompt "Enable seccomp to safely compute untrusted bytecode"
1784         ---help---
1785           This kernel feature is useful for number crunching applications
1786           that may need to compute untrusted bytecode during their
1787           execution. By using pipes or other transports made available to
1788           the process as file descriptors supporting the read/write
1789           syscalls, it's possible to isolate those applications in
1790           their own address space using seccomp. Once seccomp is
1791           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1792           and the task is only allowed to execute a few safe syscalls
1793           defined by each seccomp mode.
1794
1795 config SWIOTLB
1796         def_bool y
1797
1798 config IOMMU_HELPER
1799         def_bool SWIOTLB
1800
1801 config XEN_DOM0
1802         def_bool y
1803         depends on XEN
1804
1805 config XEN
1806         bool "Xen guest support on ARM"
1807         depends on ARM && AEABI && OF
1808         depends on CPU_V7 && !CPU_V6
1809         depends on !GENERIC_ATOMIC64
1810         depends on MMU
1811         select ARCH_DMA_ADDR_T_64BIT
1812         select ARM_PSCI
1813         select SWIOTLB_XEN
1814         help
1815           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1816
1817 endmenu
1818
1819 menu "Boot options"
1820
1821 config USE_OF
1822         bool "Flattened Device Tree support"
1823         select IRQ_DOMAIN
1824         select OF
1825         select OF_EARLY_FLATTREE
1826         select OF_RESERVED_MEM
1827         help
1828           Include support for flattened device tree machine descriptions.
1829
1830 config ATAGS
1831         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1832         default y
1833         help
1834           This is the traditional way of passing data to the kernel at boot
1835           time. If you are solely relying on the flattened device tree (or
1836           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1837           to remove ATAGS support from your kernel binary.  If unsure,
1838           leave this to y.
1839
1840 config DEPRECATED_PARAM_STRUCT
1841         bool "Provide old way to pass kernel parameters"
1842         depends on ATAGS
1843         help
1844           This was deprecated in 2001 and announced to live on for 5 years.
1845           Some old boot loaders still use this way.
1846
1847 # Compressed boot loader in ROM.  Yes, we really want to ask about
1848 # TEXT and BSS so we preserve their values in the config files.
1849 config ZBOOT_ROM_TEXT
1850         hex "Compressed ROM boot loader base address"
1851         default "0"
1852         help
1853           The physical address at which the ROM-able zImage is to be
1854           placed in the target.  Platforms which normally make use of
1855           ROM-able zImage formats normally set this to a suitable
1856           value in their defconfig file.
1857
1858           If ZBOOT_ROM is not enabled, this has no effect.
1859
1860 config ZBOOT_ROM_BSS
1861         hex "Compressed ROM boot loader BSS address"
1862         default "0"
1863         help
1864           The base address of an area of read/write memory in the target
1865           for the ROM-able zImage which must be available while the
1866           decompressor is running. It must be large enough to hold the
1867           entire decompressed kernel plus an additional 128 KiB.
1868           Platforms which normally make use of ROM-able zImage formats
1869           normally set this to a suitable value in their defconfig file.
1870
1871           If ZBOOT_ROM is not enabled, this has no effect.
1872
1873 config ZBOOT_ROM
1874         bool "Compressed boot loader in ROM/flash"
1875         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1876         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1877         help
1878           Say Y here if you intend to execute your compressed kernel image
1879           (zImage) directly from ROM or flash.  If unsure, say N.
1880
1881 config ARM_APPENDED_DTB
1882         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1883         depends on OF
1884         help
1885           With this option, the boot code will look for a device tree binary
1886           (DTB) appended to zImage
1887           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1888
1889           This is meant as a backward compatibility convenience for those
1890           systems with a bootloader that can't be upgraded to accommodate
1891           the documented boot protocol using a device tree.
1892
1893           Beware that there is very little in terms of protection against
1894           this option being confused by leftover garbage in memory that might
1895           look like a DTB header after a reboot if no actual DTB is appended
1896           to zImage.  Do not leave this option active in a production kernel
1897           if you don't intend to always append a DTB.  Proper passing of the
1898           location into r2 of a bootloader provided DTB is always preferable
1899           to this option.
1900
1901 config ARM_ATAG_DTB_COMPAT
1902         bool "Supplement the appended DTB with traditional ATAG information"
1903         depends on ARM_APPENDED_DTB
1904         help
1905           Some old bootloaders can't be updated to a DTB capable one, yet
1906           they provide ATAGs with memory configuration, the ramdisk address,
1907           the kernel cmdline string, etc.  Such information is dynamically
1908           provided by the bootloader and can't always be stored in a static
1909           DTB.  To allow a device tree enabled kernel to be used with such
1910           bootloaders, this option allows zImage to extract the information
1911           from the ATAG list and store it at run time into the appended DTB.
1912
1913 choice
1914         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1915         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1916
1917 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1918         bool "Use bootloader kernel arguments if available"
1919         help
1920           Uses the command-line options passed by the boot loader instead of
1921           the device tree bootargs property. If the boot loader doesn't provide
1922           any, the device tree bootargs property will be used.
1923
1924 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1925         bool "Extend with bootloader kernel arguments"
1926         help
1927           The command-line arguments provided by the boot loader will be
1928           appended to the the device tree bootargs property.
1929
1930 endchoice
1931
1932 config CMDLINE
1933         string "Default kernel command string"
1934         default ""
1935         help
1936           On some architectures (EBSA110 and CATS), there is currently no way
1937           for the boot loader to pass arguments to the kernel. For these
1938           architectures, you should supply some command-line options at build
1939           time by entering them here. As a minimum, you should specify the
1940           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1941
1942 choice
1943         prompt "Kernel command line type" if CMDLINE != ""
1944         default CMDLINE_FROM_BOOTLOADER
1945         depends on ATAGS
1946
1947 config CMDLINE_FROM_BOOTLOADER
1948         bool "Use bootloader kernel arguments if available"
1949         help
1950           Uses the command-line options passed by the boot loader. If
1951           the boot loader doesn't provide any, the default kernel command
1952           string provided in CMDLINE will be used.
1953
1954 config CMDLINE_EXTEND
1955         bool "Extend bootloader kernel arguments"
1956         help
1957           The command-line arguments provided by the boot loader will be
1958           appended to the default kernel command string.
1959
1960 config CMDLINE_FORCE
1961         bool "Always use the default kernel command string"
1962         help
1963           Always use the default kernel command string, even if the boot
1964           loader passes other arguments to the kernel.
1965           This is useful if you cannot or don't want to change the
1966           command-line options your boot loader passes to the kernel.
1967 endchoice
1968
1969 config XIP_KERNEL
1970         bool "Kernel Execute-In-Place from ROM"
1971         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1972         help
1973           Execute-In-Place allows the kernel to run from non-volatile storage
1974           directly addressable by the CPU, such as NOR flash. This saves RAM
1975           space since the text section of the kernel is not loaded from flash
1976           to RAM.  Read-write sections, such as the data section and stack,
1977           are still copied to RAM.  The XIP kernel is not compressed since
1978           it has to run directly from flash, so it will take more space to
1979           store it.  The flash address used to link the kernel object files,
1980           and for storing it, is configuration dependent. Therefore, if you
1981           say Y here, you must know the proper physical address where to
1982           store the kernel image depending on your own flash memory usage.
1983
1984           Also note that the make target becomes "make xipImage" rather than
1985           "make zImage" or "make Image".  The final kernel binary to put in
1986           ROM memory will be arch/arm/boot/xipImage.
1987
1988           If unsure, say N.
1989
1990 config XIP_PHYS_ADDR
1991         hex "XIP Kernel Physical Location"
1992         depends on XIP_KERNEL
1993         default "0x00080000"
1994         help
1995           This is the physical address in your flash memory the kernel will
1996           be linked for and stored to.  This address is dependent on your
1997           own flash usage.
1998
1999 config KEXEC
2000         bool "Kexec system call (EXPERIMENTAL)"
2001         depends on (!SMP || PM_SLEEP_SMP)
2002         depends on !CPU_V7M
2003         select KEXEC_CORE
2004         help
2005           kexec is a system call that implements the ability to shutdown your
2006           current kernel, and to start another kernel.  It is like a reboot
2007           but it is independent of the system firmware.   And like a reboot
2008           you can start any kernel with it, not just Linux.
2009
2010           It is an ongoing process to be certain the hardware in a machine
2011           is properly shutdown, so do not be surprised if this code does not
2012           initially work for you.
2013
2014 config ATAGS_PROC
2015         bool "Export atags in procfs"
2016         depends on ATAGS && KEXEC
2017         default y
2018         help
2019           Should the atags used to boot the kernel be exported in an "atags"
2020           file in procfs. Useful with kexec.
2021
2022 config CRASH_DUMP
2023         bool "Build kdump crash kernel (EXPERIMENTAL)"
2024         help
2025           Generate crash dump after being started by kexec. This should
2026           be normally only set in special crash dump kernels which are
2027           loaded in the main kernel with kexec-tools into a specially
2028           reserved region and then later executed after a crash by
2029           kdump/kexec. The crash dump kernel must be compiled to a
2030           memory address not used by the main kernel
2031
2032           For more details see Documentation/kdump/kdump.txt
2033
2034 config AUTO_ZRELADDR
2035         bool "Auto calculation of the decompressed kernel image address"
2036         help
2037           ZRELADDR is the physical address where the decompressed kernel
2038           image will be placed. If AUTO_ZRELADDR is selected, the address
2039           will be determined at run-time by masking the current IP with
2040           0xf8000000. This assumes the zImage being placed in the first 128MB
2041           from start of memory.
2042
2043 endmenu
2044
2045 menu "CPU Power Management"
2046
2047 source "drivers/cpufreq/Kconfig"
2048
2049 source "drivers/cpuidle/Kconfig"
2050
2051 endmenu
2052
2053 menu "Floating point emulation"
2054
2055 comment "At least one emulation must be selected"
2056
2057 config FPE_NWFPE
2058         bool "NWFPE math emulation"
2059         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2060         ---help---
2061           Say Y to include the NWFPE floating point emulator in the kernel.
2062           This is necessary to run most binaries. Linux does not currently
2063           support floating point hardware so you need to say Y here even if
2064           your machine has an FPA or floating point co-processor podule.
2065
2066           You may say N here if you are going to load the Acorn FPEmulator
2067           early in the bootup.
2068
2069 config FPE_NWFPE_XP
2070         bool "Support extended precision"
2071         depends on FPE_NWFPE
2072         help
2073           Say Y to include 80-bit support in the kernel floating-point
2074           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2075           Note that gcc does not generate 80-bit operations by default,
2076           so in most cases this option only enlarges the size of the
2077           floating point emulator without any good reason.
2078
2079           You almost surely want to say N here.
2080
2081 config FPE_FASTFPE
2082         bool "FastFPE math emulation (EXPERIMENTAL)"
2083         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2084         ---help---
2085           Say Y here to include the FAST floating point emulator in the kernel.
2086           This is an experimental much faster emulator which now also has full
2087           precision for the mantissa.  It does not support any exceptions.
2088           It is very simple, and approximately 3-6 times faster than NWFPE.
2089
2090           It should be sufficient for most programs.  It may be not suitable
2091           for scientific calculations, but you have to check this for yourself.
2092           If you do not feel you need a faster FP emulation you should better
2093           choose NWFPE.
2094
2095 config VFP
2096         bool "VFP-format floating point maths"
2097         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2098         help
2099           Say Y to include VFP support code in the kernel. This is needed
2100           if your hardware includes a VFP unit.
2101
2102           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2103           release notes and additional status information.
2104
2105           Say N if your target does not have VFP hardware.
2106
2107 config VFPv3
2108         bool
2109         depends on VFP
2110         default y if CPU_V7
2111
2112 config NEON
2113         bool "Advanced SIMD (NEON) Extension support"
2114         depends on VFPv3 && CPU_V7
2115         help
2116           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2117           Extension.
2118
2119 config KERNEL_MODE_NEON
2120         bool "Support for NEON in kernel mode"
2121         depends on NEON && AEABI
2122         help
2123           Say Y to include support for NEON in kernel mode.
2124
2125 endmenu
2126
2127 menu "Userspace binary formats"
2128
2129 source "fs/Kconfig.binfmt"
2130
2131 endmenu
2132
2133 menu "Power management options"
2134
2135 source "kernel/power/Kconfig"
2136
2137 config ARCH_SUSPEND_POSSIBLE
2138         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2139                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2140         def_bool y
2141
2142 config ARM_CPU_SUSPEND
2143         def_bool PM_SLEEP
2144
2145 config ARCH_HIBERNATION_POSSIBLE
2146         bool
2147         depends on MMU
2148         default y if ARCH_SUSPEND_POSSIBLE
2149
2150 endmenu
2151
2152 source "net/Kconfig"
2153
2154 source "drivers/Kconfig"
2155
2156 source "drivers/firmware/Kconfig"
2157
2158 source "fs/Kconfig"
2159
2160 source "arch/arm/Kconfig.debug"
2161
2162 source "security/Kconfig"
2163
2164 source "crypto/Kconfig"
2165 if CRYPTO
2166 source "arch/arm/crypto/Kconfig"
2167 endif
2168
2169 source "lib/Kconfig"
2170
2171 source "arch/arm/kvm/Kconfig"