arch/arm/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0
   2 config ARM
   3         bool
   4         default y
   5         select ARCH_CLOCKSOURCE_DATA
   6         select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
   7         select ARCH_HAS_DEBUG_VIRTUAL if MMU
   8         select ARCH_HAS_DEVMEM_IS_ALLOWED
   9         select ARCH_HAS_ELF_RANDOMIZE
  10         select ARCH_HAS_FORTIFY_SOURCE
  11         select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
  12         select ARCH_HAS_SET_MEMORY
  13         select ARCH_HAS_PHYS_TO_DMA
  14         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  15         select ARCH_HAS_STRICT_MODULE_RWX if MMU
  16         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  17         select ARCH_HAVE_CUSTOM_GPIO_H
  18         select ARCH_HAS_GCOV_PROFILE_ALL
  19         select ARCH_MIGHT_HAVE_PC_PARPORT
  20         select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  21         select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  22         select ARCH_SUPPORTS_ATOMIC_RMW
  23         select ARCH_USE_BUILTIN_BSWAP
  24         select ARCH_USE_CMPXCHG_LOCKREF
  25         select ARCH_WANT_IPC_PARSE_VERSION
  26         select BUILDTIME_EXTABLE_SORT if MMU
  27         select CLONE_BACKWARDS
  28         select CPU_PM if (SUSPEND || CPU_IDLE)
  29         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  30         select DMA_DIRECT_OPS if !MMU
  31         select EDAC_SUPPORT
  32         select EDAC_ATOMIC_SCRUB
  33         select GENERIC_ALLOCATOR
  34         select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  35         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  36         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  37         select GENERIC_CPU_AUTOPROBE
  38         select GENERIC_EARLY_IOREMAP
  39         select GENERIC_IDLE_POLL_SETUP
  40         select GENERIC_IRQ_PROBE
  41         select GENERIC_IRQ_SHOW
  42         select GENERIC_IRQ_SHOW_LEVEL
  43         select GENERIC_PCI_IOMAP
  44         select GENERIC_SCHED_CLOCK
  45         select GENERIC_SMP_IDLE_THREAD
  46         select GENERIC_STRNCPY_FROM_USER
  47         select GENERIC_STRNLEN_USER
  48         select HANDLE_DOMAIN_IRQ
  49         select HARDIRQS_SW_RESEND
  50         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  51         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  52         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  53         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  54         select HAVE_ARCH_MMAP_RND_BITS if MMU
  55         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  56         select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  57         select HAVE_ARCH_TRACEHOOK
  58         select HAVE_ARM_SMCCC if CPU_V7
  59         select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  60         select HAVE_CC_STACKPROTECTOR
  61         select HAVE_CONTEXT_TRACKING
  62         select HAVE_C_RECORDMCOUNT
  63         select HAVE_DEBUG_KMEMLEAK
  64         select HAVE_DMA_CONTIGUOUS if MMU
  65         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  66         select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  67         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  68         select HAVE_EXIT_THREAD
  69         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  70         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  71         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  72         select HAVE_GCC_PLUGINS
  73         select HAVE_GENERIC_DMA_COHERENT
  74         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  75         select HAVE_IDE if PCI || ISA || PCMCIA
  76         select HAVE_IRQ_TIME_ACCOUNTING
  77         select HAVE_KERNEL_GZIP
  78         select HAVE_KERNEL_LZ4
  79         select HAVE_KERNEL_LZMA
  80         select HAVE_KERNEL_LZO
  81         select HAVE_KERNEL_XZ
  82         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  83         select HAVE_KRETPROBES if (HAVE_KPROBES)
  84         select HAVE_MEMBLOCK
  85         select HAVE_MOD_ARCH_SPECIFIC
  86         select HAVE_NMI
  87         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  88         select HAVE_OPTPROBES if !THUMB2_KERNEL
  89         select HAVE_PERF_EVENTS
  90         select HAVE_PERF_REGS
  91         select HAVE_PERF_USER_STACK_DUMP
  92         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  93         select HAVE_REGS_AND_STACK_ACCESS_API
  94         select HAVE_SYSCALL_TRACEPOINTS
  95         select HAVE_UID16
  96         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  97         select IRQ_FORCED_THREADING
  98         select MODULES_USE_ELF_REL
  99         select NEED_DMA_MAP_STATE
 100         select NO_BOOTMEM
 101         select OF_EARLY_FLATTREE if OF
 102         select OF_RESERVED_MEM if OF
 103         select OLD_SIGACTION
 104         select OLD_SIGSUSPEND3
 105         select PERF_USE_VMALLOC
 106         select REFCOUNT_FULL
 107         select RTC_LIB
 108         select SYS_SUPPORTS_APM_EMULATION
 109         # Above selects are sorted alphabetically; please add new ones
 110         # according to that.  Thanks.
 111         help
 112           The ARM series is a line of low-power-consumption RISC chip designs
 113           licensed by ARM Ltd and targeted at embedded applications and
 114           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 115           manufactured, but legacy ARM-based PC hardware remains popular in
 116           Europe.  There is an ARM Linux project with a web page at
 117           <http://www.arm.linux.org.uk/>.
 118
 119 config ARM_HAS_SG_CHAIN
 120         select ARCH_HAS_SG_CHAIN
 121         bool
 122
 123 config ARM_DMA_USE_IOMMU
 124         bool
 125         select ARM_HAS_SG_CHAIN
 126         select NEED_SG_DMA_LENGTH
 127
 128 if ARM_DMA_USE_IOMMU
 129
 130 config ARM_DMA_IOMMU_ALIGNMENT
 131         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 132         range 4 9
 133         default 8
 134         help
 135           DMA mapping framework by default aligns all buffers to the smallest
 136           PAGE_SIZE order which is greater than or equal to the requested buffer
 137           size. This works well for buffers up to a few hundreds kilobytes, but
 138           for larger buffers it just a waste of address space. Drivers which has
 139           relatively small addressing window (like 64Mib) might run out of
 140           virtual space with just a few allocations.
 141
 142           With this parameter you can specify the maximum PAGE_SIZE order for
 143           DMA IOMMU buffers. Larger buffers will be aligned only to this
 144           specified order. The order is expressed as a power of two multiplied
 145           by the PAGE_SIZE.
 146
 147 endif
 148
 149 config MIGHT_HAVE_PCI
 150         bool
 151
 152 config SYS_SUPPORTS_APM_EMULATION
 153         bool
 154
 155 config HAVE_TCM
 156         bool
 157         select GENERIC_ALLOCATOR
 158
 159 config HAVE_PROC_CPU
 160         bool
 161
 162 config NO_IOPORT_MAP
 163         bool
 164
 165 config EISA
 166         bool
 167         ---help---
 168           The Extended Industry Standard Architecture (EISA) bus was
 169           developed as an open alternative to the IBM MicroChannel bus.
 170
 171           The EISA bus provided some of the features of the IBM MicroChannel
 172           bus while maintaining backward compatibility with cards made for
 173           the older ISA bus.  The EISA bus saw limited use between 1988 and
 174           1995 when it was made obsolete by the PCI bus.
 175
 176           Say Y here if you are building a kernel for an EISA-based machine.
 177
 178           Otherwise, say N.
 179
 180 config SBUS
 181         bool
 182
 183 config STACKTRACE_SUPPORT
 184         bool
 185         default y
 186
 187 config LOCKDEP_SUPPORT
 188         bool
 189         default y
 190
 191 config TRACE_IRQFLAGS_SUPPORT
 192         bool
 193         default !CPU_V7M
 194
 195 config RWSEM_XCHGADD_ALGORITHM
 196         bool
 197         default y
 198
 199 config ARCH_HAS_ILOG2_U32
 200         bool
 201
 202 config ARCH_HAS_ILOG2_U64
 203         bool
 204
 205 config ARCH_HAS_BANDGAP
 206         bool
 207
 208 config FIX_EARLYCON_MEM
 209         def_bool y if MMU
 210
 211 config GENERIC_HWEIGHT
 212         bool
 213         default y
 214
 215 config GENERIC_CALIBRATE_DELAY
 216         bool
 217         default y
 218
 219 config ARCH_MAY_HAVE_PC_FDC
 220         bool
 221
 222 config ZONE_DMA
 223         bool
 224
 225 config ARCH_SUPPORTS_UPROBES
 226         def_bool y
 227
 228 config ARCH_HAS_DMA_SET_COHERENT_MASK
 229         bool
 230
 231 config GENERIC_ISA_DMA
 232         bool
 233
 234 config FIQ
 235         bool
 236
 237 config NEED_RET_TO_USER
 238         bool
 239
 240 config ARCH_MTD_XIP
 241         bool
 242
 243 config ARM_PATCH_PHYS_VIRT
 244         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 245         default y
 246         depends on !XIP_KERNEL && MMU
 247         help
 248           Patch phys-to-virt and virt-to-phys translation functions at
 249           boot and module load time according to the position of the
 250           kernel in system memory.
 251
 252           This can only be used with non-XIP MMU kernels where the base
 253           of physical memory is at a 16MB boundary.
 254
 255           Only disable this option if you know that you do not require
 256           this feature (eg, building a kernel for a single machine) and
 257           you need to shrink the kernel to the minimal size.
 258
 259 config NEED_MACH_IO_H
 260         bool
 261         help
 262           Select this when mach/io.h is required to provide special
 263           definitions for this platform.  The need for mach/io.h should
 264           be avoided when possible.
 265
 266 config NEED_MACH_MEMORY_H
 267         bool
 268         help
 269           Select this when mach/memory.h is required to provide special
 270           definitions for this platform.  The need for mach/memory.h should
 271           be avoided when possible.
 272
 273 config PHYS_OFFSET
 274         hex "Physical address of main memory" if MMU
 275         depends on !ARM_PATCH_PHYS_VIRT
 276         default DRAM_BASE if !MMU
 277         default 0x00000000 if ARCH_EBSA110 || \
 278                         ARCH_FOOTBRIDGE || \
 279                         ARCH_INTEGRATOR || \
 280                         ARCH_IOP13XX || \
 281                         ARCH_KS8695 || \
 282                         ARCH_REALVIEW
 283         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 284         default 0x20000000 if ARCH_S5PV210
 285         default 0xc0000000 if ARCH_SA1100
 286         help
 287           Please provide the physical address corresponding to the
 288           location of main memory in your system.
 289
 290 config GENERIC_BUG
 291         def_bool y
 292         depends on BUG
 293
 294 config PGTABLE_LEVELS
 295         int
 296         default 3 if ARM_LPAE
 297         default 2
 298
 299 source "init/Kconfig"
 300
 301 source "kernel/Kconfig.freezer"
 302
 303 menu "System Type"
 304
 305 config MMU
 306         bool "MMU-based Paged Memory Management Support"
 307         default y
 308         help
 309           Select if you want MMU-based virtualised addressing space
 310           support by paged memory management. If unsure, say 'Y'.
 311
 312 config ARCH_MMAP_RND_BITS_MIN
 313         default 8
 314
 315 config ARCH_MMAP_RND_BITS_MAX
 316         default 14 if PAGE_OFFSET=0x40000000
 317         default 15 if PAGE_OFFSET=0x80000000
 318         default 16
 319
 320 #
 321 # The "ARM system type" choice list is ordered alphabetically by option
 322 # text.  Please add new entries in the option alphabetic order.
 323 #
 324 choice
 325         prompt "ARM system type"
 326         default ARM_SINGLE_ARMV7M if !MMU
 327         default ARCH_MULTIPLATFORM if MMU
 328
 329 config ARCH_MULTIPLATFORM
 330         bool "Allow multiple platforms to be selected"
 331         depends on MMU
 332         select ARM_HAS_SG_CHAIN
 333         select ARM_PATCH_PHYS_VIRT
 334         select AUTO_ZRELADDR
 335         select TIMER_OF
 336         select COMMON_CLK
 337         select GENERIC_CLOCKEVENTS
 338         select MIGHT_HAVE_PCI
 339         select MULTI_IRQ_HANDLER
 340         select PCI_DOMAINS if PCI
 341         select SPARSE_IRQ
 342         select USE_OF
 343
 344 config ARM_SINGLE_ARMV7M
 345         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 346         depends on !MMU
 347         select ARM_NVIC
 348         select AUTO_ZRELADDR
 349         select TIMER_OF
 350         select COMMON_CLK
 351         select CPU_V7M
 352         select GENERIC_CLOCKEVENTS
 353         select NO_IOPORT_MAP
 354         select SPARSE_IRQ
 355         select USE_OF
 356
 357 config ARCH_EBSA110
 358         bool "EBSA-110"
 359         select ARCH_USES_GETTIMEOFFSET
 360         select CPU_SA110
 361         select ISA
 362         select NEED_MACH_IO_H
 363         select NEED_MACH_MEMORY_H
 364         select NO_IOPORT_MAP
 365         help
 366           This is an evaluation board for the StrongARM processor available
 367           from Digital. It has limited hardware on-board, including an
 368           Ethernet interface, two PCMCIA sockets, two serial ports and a
 369           parallel port.
 370
 371 config ARCH_EP93XX
 372         bool "EP93xx-based"
 373         select ARCH_SPARSEMEM_ENABLE
 374         select ARM_AMBA
 375         imply ARM_PATCH_PHYS_VIRT
 376         select ARM_VIC
 377         select AUTO_ZRELADDR
 378         select CLKDEV_LOOKUP
 379         select CLKSRC_MMIO
 380         select CPU_ARM920T
 381         select GENERIC_CLOCKEVENTS
 382         select GPIOLIB
 383         help
 384           This enables support for the Cirrus EP93xx series of CPUs.
 385
 386 config ARCH_FOOTBRIDGE
 387         bool "FootBridge"
 388         select CPU_SA110
 389         select FOOTBRIDGE
 390         select GENERIC_CLOCKEVENTS
 391         select HAVE_IDE
 392         select NEED_MACH_IO_H if !MMU
 393         select NEED_MACH_MEMORY_H
 394         help
 395           Support for systems based on the DC21285 companion chip
 396           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 397
 398 config ARCH_NETX
 399         bool "Hilscher NetX based"
 400         select ARM_VIC
 401         select CLKSRC_MMIO
 402         select CPU_ARM926T
 403         select GENERIC_CLOCKEVENTS
 404         help
 405           This enables support for systems based on the Hilscher NetX Soc
 406
 407 config ARCH_IOP13XX
 408         bool "IOP13xx-based"
 409         depends on MMU
 410         select CPU_XSC3
 411         select NEED_MACH_MEMORY_H
 412         select NEED_RET_TO_USER
 413         select PCI
 414         select PLAT_IOP
 415         select VMSPLIT_1G
 416         select SPARSE_IRQ
 417         help
 418           Support for Intel's IOP13XX (XScale) family of processors.
 419
 420 config ARCH_IOP32X
 421         bool "IOP32x-based"
 422         depends on MMU
 423         select CPU_XSCALE
 424         select GPIO_IOP
 425         select GPIOLIB
 426         select NEED_RET_TO_USER
 427         select PCI
 428         select PLAT_IOP
 429         help
 430           Support for Intel's 80219 and IOP32X (XScale) family of
 431           processors.
 432
 433 config ARCH_IOP33X
 434         bool "IOP33x-based"
 435         depends on MMU
 436         select CPU_XSCALE
 437         select GPIO_IOP
 438         select GPIOLIB
 439         select NEED_RET_TO_USER
 440         select PCI
 441         select PLAT_IOP
 442         help
 443           Support for Intel's IOP33X (XScale) family of processors.
 444
 445 config ARCH_IXP4XX
 446         bool "IXP4xx-based"
 447         depends on MMU
 448         select ARCH_HAS_DMA_SET_COHERENT_MASK
 449         select ARCH_SUPPORTS_BIG_ENDIAN
 450         select CLKSRC_MMIO
 451         select CPU_XSCALE
 452         select DMABOUNCE if PCI
 453         select GENERIC_CLOCKEVENTS
 454         select GPIOLIB
 455         select MIGHT_HAVE_PCI
 456         select NEED_MACH_IO_H
 457         select USB_EHCI_BIG_ENDIAN_DESC
 458         select USB_EHCI_BIG_ENDIAN_MMIO
 459         help
 460           Support for Intel's IXP4XX (XScale) family of processors.
 461
 462 config ARCH_DOVE
 463         bool "Marvell Dove"
 464         select CPU_PJ4
 465         select GENERIC_CLOCKEVENTS
 466         select GPIOLIB
 467         select MIGHT_HAVE_PCI
 468         select MULTI_IRQ_HANDLER
 469         select MVEBU_MBUS
 470         select PINCTRL
 471         select PINCTRL_DOVE
 472         select PLAT_ORION_LEGACY
 473         select SPARSE_IRQ
 474         select PM_GENERIC_DOMAINS if PM
 475         help
 476           Support for the Marvell Dove SoC 88AP510
 477
 478 config ARCH_KS8695
 479         bool "Micrel/Kendin KS8695"
 480         select CLKSRC_MMIO
 481         select CPU_ARM922T
 482         select GENERIC_CLOCKEVENTS
 483         select GPIOLIB
 484         select NEED_MACH_MEMORY_H
 485         help
 486           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 487           System-on-Chip devices.
 488
 489 config ARCH_W90X900
 490         bool "Nuvoton W90X900 CPU"
 491         select CLKDEV_LOOKUP
 492         select CLKSRC_MMIO
 493         select CPU_ARM926T
 494         select GENERIC_CLOCKEVENTS
 495         select GPIOLIB
 496         help
 497           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 498           At present, the w90x900 has been renamed nuc900, regarding
 499           the ARM series product line, you can login the following
 500           link address to know more.
 501
 502           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 503                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 504
 505 config ARCH_LPC32XX
 506         bool "NXP LPC32XX"
 507         select ARM_AMBA
 508         select CLKDEV_LOOKUP
 509         select CLKSRC_LPC32XX
 510         select COMMON_CLK
 511         select CPU_ARM926T
 512         select GENERIC_CLOCKEVENTS
 513         select GPIOLIB
 514         select MULTI_IRQ_HANDLER
 515         select SPARSE_IRQ
 516         select USE_OF
 517         help
 518           Support for the NXP LPC32XX family of processors
 519
 520 config ARCH_PXA
 521         bool "PXA2xx/PXA3xx-based"
 522         depends on MMU
 523         select ARCH_MTD_XIP
 524         select ARM_CPU_SUSPEND if PM
 525         select AUTO_ZRELADDR
 526         select COMMON_CLK
 527         select CLKDEV_LOOKUP
 528         select CLKSRC_PXA
 529         select CLKSRC_MMIO
 530         select TIMER_OF
 531         select CPU_XSCALE if !CPU_XSC3
 532         select GENERIC_CLOCKEVENTS
 533         select GPIO_PXA
 534         select GPIOLIB
 535         select HAVE_IDE
 536         select IRQ_DOMAIN
 537         select MULTI_IRQ_HANDLER
 538         select PLAT_PXA
 539         select SPARSE_IRQ
 540         help
 541           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 542
 543 config ARCH_RPC
 544         bool "RiscPC"
 545         depends on MMU
 546         select ARCH_ACORN
 547         select ARCH_MAY_HAVE_PC_FDC
 548         select ARCH_SPARSEMEM_ENABLE
 549         select ARCH_USES_GETTIMEOFFSET
 550         select CPU_SA110
 551         select FIQ
 552         select HAVE_IDE
 553         select HAVE_PATA_PLATFORM
 554         select ISA_DMA_API
 555         select NEED_MACH_IO_H
 556         select NEED_MACH_MEMORY_H
 557         select NO_IOPORT_MAP
 558         help
 559           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 560           CD-ROM interface, serial and parallel port, and the floppy drive.
 561
 562 config ARCH_SA1100
 563         bool "SA1100-based"
 564         select ARCH_MTD_XIP
 565         select ARCH_SPARSEMEM_ENABLE
 566         select CLKDEV_LOOKUP
 567         select CLKSRC_MMIO
 568         select CLKSRC_PXA
 569         select TIMER_OF if OF
 570         select CPU_FREQ
 571         select CPU_SA1100
 572         select GENERIC_CLOCKEVENTS
 573         select GPIOLIB
 574         select HAVE_IDE
 575         select IRQ_DOMAIN
 576         select ISA
 577         select MULTI_IRQ_HANDLER
 578         select NEED_MACH_MEMORY_H
 579         select SPARSE_IRQ
 580         help
 581           Support for StrongARM 11x0 based boards.
 582
 583 config ARCH_S3C24XX
 584         bool "Samsung S3C24XX SoCs"
 585         select ATAGS
 586         select CLKDEV_LOOKUP
 587         select CLKSRC_SAMSUNG_PWM
 588         select GENERIC_CLOCKEVENTS
 589         select GPIO_SAMSUNG
 590         select GPIOLIB
 591         select HAVE_S3C2410_I2C if I2C
 592         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 593         select HAVE_S3C_RTC if RTC_CLASS
 594         select MULTI_IRQ_HANDLER
 595         select NEED_MACH_IO_H
 596         select SAMSUNG_ATAGS
 597         select USE_OF
 598         help
 599           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 600           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 601           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 602           Samsung SMDK2410 development board (and derivatives).
 603
 604 config ARCH_DAVINCI
 605         bool "TI DaVinci"
 606         select ARCH_HAS_HOLES_MEMORYMODEL
 607         select CLKDEV_LOOKUP
 608         select CPU_ARM926T
 609         select GENERIC_ALLOCATOR
 610         select GENERIC_CLOCKEVENTS
 611         select GENERIC_IRQ_CHIP
 612         select GPIOLIB
 613         select HAVE_IDE
 614         select USE_OF
 615         select ZONE_DMA
 616         help
 617           Support for TI's DaVinci platform.
 618
 619 config ARCH_OMAP1
 620         bool "TI OMAP1"
 621         depends on MMU
 622         select ARCH_HAS_HOLES_MEMORYMODEL
 623         select ARCH_OMAP
 624         select CLKDEV_LOOKUP
 625         select CLKSRC_MMIO
 626         select GENERIC_CLOCKEVENTS
 627         select GENERIC_IRQ_CHIP
 628         select GPIOLIB
 629         select HAVE_IDE
 630         select IRQ_DOMAIN
 631         select MULTI_IRQ_HANDLER
 632         select NEED_MACH_IO_H if PCCARD
 633         select NEED_MACH_MEMORY_H
 634         select SPARSE_IRQ
 635         help
 636           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 637
 638 endchoice
 639
 640 menu "Multiple platform selection"
 641         depends on ARCH_MULTIPLATFORM
 642
 643 comment "CPU Core family selection"
 644
 645 config ARCH_MULTI_V4
 646         bool "ARMv4 based platforms (FA526)"
 647         depends on !ARCH_MULTI_V6_V7
 648         select ARCH_MULTI_V4_V5
 649         select CPU_FA526
 650
 651 config ARCH_MULTI_V4T
 652         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 653         depends on !ARCH_MULTI_V6_V7
 654         select ARCH_MULTI_V4_V5
 655         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 656                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 657                 CPU_ARM925T || CPU_ARM940T)
 658
 659 config ARCH_MULTI_V5
 660         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 661         depends on !ARCH_MULTI_V6_V7
 662         select ARCH_MULTI_V4_V5
 663         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 664                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 665                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 666
 667 config ARCH_MULTI_V4_V5
 668         bool
 669
 670 config ARCH_MULTI_V6
 671         bool "ARMv6 based platforms (ARM11)"
 672         select ARCH_MULTI_V6_V7
 673         select CPU_V6K
 674
 675 config ARCH_MULTI_V7
 676         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 677         default y
 678         select ARCH_MULTI_V6_V7
 679         select CPU_V7
 680         select HAVE_SMP
 681
 682 config ARCH_MULTI_V6_V7
 683         bool
 684         select MIGHT_HAVE_CACHE_L2X0
 685
 686 config ARCH_MULTI_CPU_AUTO
 687         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 688         select ARCH_MULTI_V5
 689
 690 endmenu
 691
 692 config ARCH_VIRT
 693         bool "Dummy Virtual Machine"
 694         depends on ARCH_MULTI_V7
 695         select ARM_AMBA
 696         select ARM_GIC
 697         select ARM_GIC_V2M if PCI
 698         select ARM_GIC_V3
 699         select ARM_GIC_V3_ITS if PCI
 700         select ARM_PSCI
 701         select HAVE_ARM_ARCH_TIMER
 702
 703 #
 704 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 705 # Kconfigs may be included either alphabetically (according to the
 706 # plat- suffix) or along side the corresponding mach-* source.
 707 #
 708 source "arch/arm/mach-actions/Kconfig"
 709
 710 source "arch/arm/mach-alpine/Kconfig"
 711
 712 source "arch/arm/mach-artpec/Kconfig"
 713
 714 source "arch/arm/mach-asm9260/Kconfig"
 715
 716 source "arch/arm/mach-aspeed/Kconfig"
 717
 718 source "arch/arm/mach-at91/Kconfig"
 719
 720 source "arch/arm/mach-axxia/Kconfig"
 721
 722 source "arch/arm/mach-bcm/Kconfig"
 723
 724 source "arch/arm/mach-berlin/Kconfig"
 725
 726 source "arch/arm/mach-clps711x/Kconfig"
 727
 728 source "arch/arm/mach-cns3xxx/Kconfig"
 729
 730 source "arch/arm/mach-davinci/Kconfig"
 731
 732 source "arch/arm/mach-digicolor/Kconfig"
 733
 734 source "arch/arm/mach-dove/Kconfig"
 735
 736 source "arch/arm/mach-ep93xx/Kconfig"
 737
 738 source "arch/arm/mach-exynos/Kconfig"
 739 source "arch/arm/plat-samsung/Kconfig"
 740
 741 source "arch/arm/mach-footbridge/Kconfig"
 742
 743 source "arch/arm/mach-gemini/Kconfig"
 744
 745 source "arch/arm/mach-highbank/Kconfig"
 746
 747 source "arch/arm/mach-hisi/Kconfig"
 748
 749 source "arch/arm/mach-imx/Kconfig"
 750
 751 source "arch/arm/mach-integrator/Kconfig"
 752
 753 source "arch/arm/mach-iop13xx/Kconfig"
 754
 755 source "arch/arm/mach-iop32x/Kconfig"
 756
 757 source "arch/arm/mach-iop33x/Kconfig"
 758
 759 source "arch/arm/mach-ixp4xx/Kconfig"
 760
 761 source "arch/arm/mach-keystone/Kconfig"
 762
 763 source "arch/arm/mach-ks8695/Kconfig"
 764
 765 source "arch/arm/mach-mediatek/Kconfig"
 766
 767 source "arch/arm/mach-meson/Kconfig"
 768
 769 source "arch/arm/mach-mmp/Kconfig"
 770
 771 source "arch/arm/mach-moxart/Kconfig"
 772
 773 source "arch/arm/mach-mv78xx0/Kconfig"
 774
 775 source "arch/arm/mach-mvebu/Kconfig"
 776
 777 source "arch/arm/mach-mxs/Kconfig"
 778
 779 source "arch/arm/mach-netx/Kconfig"
 780
 781 source "arch/arm/mach-nomadik/Kconfig"
 782
 783 source "arch/arm/mach-npcm/Kconfig"
 784
 785 source "arch/arm/mach-nspire/Kconfig"
 786
 787 source "arch/arm/plat-omap/Kconfig"
 788
 789 source "arch/arm/mach-omap1/Kconfig"
 790
 791 source "arch/arm/mach-omap2/Kconfig"
 792
 793 source "arch/arm/mach-orion5x/Kconfig"
 794
 795 source "arch/arm/mach-oxnas/Kconfig"
 796
 797 source "arch/arm/mach-picoxcell/Kconfig"
 798
 799 source "arch/arm/mach-prima2/Kconfig"
 800
 801 source "arch/arm/mach-pxa/Kconfig"
 802 source "arch/arm/plat-pxa/Kconfig"
 803
 804 source "arch/arm/mach-qcom/Kconfig"
 805
 806 source "arch/arm/mach-realview/Kconfig"
 807
 808 source "arch/arm/mach-rockchip/Kconfig"
 809
 810 source "arch/arm/mach-s3c24xx/Kconfig"
 811
 812 source "arch/arm/mach-s3c64xx/Kconfig"
 813
 814 source "arch/arm/mach-s5pv210/Kconfig"
 815
 816 source "arch/arm/mach-sa1100/Kconfig"
 817
 818 source "arch/arm/mach-shmobile/Kconfig"
 819
 820 source "arch/arm/mach-socfpga/Kconfig"
 821
 822 source "arch/arm/mach-spear/Kconfig"
 823
 824 source "arch/arm/mach-sti/Kconfig"
 825
 826 source "arch/arm/mach-stm32/Kconfig"
 827
 828 source "arch/arm/mach-sunxi/Kconfig"
 829
 830 source "arch/arm/mach-tango/Kconfig"
 831
 832 source "arch/arm/mach-tegra/Kconfig"
 833
 834 source "arch/arm/mach-u300/Kconfig"
 835
 836 source "arch/arm/mach-uniphier/Kconfig"
 837
 838 source "arch/arm/mach-ux500/Kconfig"
 839
 840 source "arch/arm/mach-versatile/Kconfig"
 841
 842 source "arch/arm/mach-vexpress/Kconfig"
 843 source "arch/arm/plat-versatile/Kconfig"
 844
 845 source "arch/arm/mach-vt8500/Kconfig"
 846
 847 source "arch/arm/mach-w90x900/Kconfig"
 848
 849 source "arch/arm/mach-zx/Kconfig"
 850
 851 source "arch/arm/mach-zynq/Kconfig"
 852
 853 # ARMv7-M architecture
 854 config ARCH_EFM32
 855         bool "Energy Micro efm32"
 856         depends on ARM_SINGLE_ARMV7M
 857         select GPIOLIB
 858         help
 859           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 860           processors.
 861
 862 config ARCH_LPC18XX
 863         bool "NXP LPC18xx/LPC43xx"
 864         depends on ARM_SINGLE_ARMV7M
 865         select ARCH_HAS_RESET_CONTROLLER
 866         select ARM_AMBA
 867         select CLKSRC_LPC32XX
 868         select PINCTRL
 869         help
 870           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 871           high performance microcontrollers.
 872
 873 config ARCH_MPS2
 874         bool "ARM MPS2 platform"
 875         depends on ARM_SINGLE_ARMV7M
 876         select ARM_AMBA
 877         select CLKSRC_MPS2
 878         help
 879           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 880           with a range of available cores like Cortex-M3/M4/M7.
 881
 882           Please, note that depends which Application Note is used memory map
 883           for the platform may vary, so adjustment of RAM base might be needed.
 884
 885 # Definitions to make life easier
 886 config ARCH_ACORN
 887         bool
 888
 889 config PLAT_IOP
 890         bool
 891         select GENERIC_CLOCKEVENTS
 892
 893 config PLAT_ORION
 894         bool
 895         select CLKSRC_MMIO
 896         select COMMON_CLK
 897         select GENERIC_IRQ_CHIP
 898         select IRQ_DOMAIN
 899
 900 config PLAT_ORION_LEGACY
 901         bool
 902         select PLAT_ORION
 903
 904 config PLAT_PXA
 905         bool
 906
 907 config PLAT_VERSATILE
 908         bool
 909
 910 source "arch/arm/firmware/Kconfig"
 911
 912 source arch/arm/mm/Kconfig
 913
 914 config IWMMXT
 915         bool "Enable iWMMXt support"
 916         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 917         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 918         help
 919           Enable support for iWMMXt context switching at run time if
 920           running on a CPU that supports it.
 921
 922 config MULTI_IRQ_HANDLER
 923         bool
 924         help
 925           Allow each machine to specify it's own IRQ handler at run time.
 926
 927 if !MMU
 928 source "arch/arm/Kconfig-nommu"
 929 endif
 930
 931 config PJ4B_ERRATA_4742
 932         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 933         depends on CPU_PJ4B && MACH_ARMADA_370
 934         default y
 935         help
 936           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 937           Event (WFE) IDLE states, a specific timing sensitivity exists between
 938           the retiring WFI/WFE instructions and the newly issued subsequent
 939           instructions.  This sensitivity can result in a CPU hang scenario.
 940           Workaround:
 941           The software must insert either a Data Synchronization Barrier (DSB)
 942           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 943           instruction
 944
 945 config ARM_ERRATA_326103
 946         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 947         depends on CPU_V6
 948         help
 949           Executing a SWP instruction to read-only memory does not set bit 11
 950           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 951           treat the access as a read, preventing a COW from occurring and
 952           causing the faulting task to livelock.
 953
 954 config ARM_ERRATA_411920
 955         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 956         depends on CPU_V6 || CPU_V6K
 957         help
 958           Invalidation of the Instruction Cache operation can
 959           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 960           It does not affect the MPCore. This option enables the ARM Ltd.
 961           recommended workaround.
 962
 963 config ARM_ERRATA_430973
 964         bool "ARM errata: Stale prediction on replaced interworking branch"
 965         depends on CPU_V7
 966         help
 967           This option enables the workaround for the 430973 Cortex-A8
 968           r1p* erratum. If a code sequence containing an ARM/Thumb
 969           interworking branch is replaced with another code sequence at the
 970           same virtual address, whether due to self-modifying code or virtual
 971           to physical address re-mapping, Cortex-A8 does not recover from the
 972           stale interworking branch prediction. This results in Cortex-A8
 973           executing the new code sequence in the incorrect ARM or Thumb state.
 974           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 975           and also flushes the branch target cache at every context switch.
 976           Note that setting specific bits in the ACTLR register may not be
 977           available in non-secure mode.
 978
 979 config ARM_ERRATA_458693
 980         bool "ARM errata: Processor deadlock when a false hazard is created"
 981         depends on CPU_V7
 982         depends on !ARCH_MULTIPLATFORM
 983         help
 984           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 985           erratum. For very specific sequences of memory operations, it is
 986           possible for a hazard condition intended for a cache line to instead
 987           be incorrectly associated with a different cache line. This false
 988           hazard might then cause a processor deadlock. The workaround enables
 989           the L1 caching of the NEON accesses and disables the PLD instruction
 990           in the ACTLR register. Note that setting specific bits in the ACTLR
 991           register may not be available in non-secure mode.
 992
 993 config ARM_ERRATA_460075
 994         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
 995         depends on CPU_V7
 996         depends on !ARCH_MULTIPLATFORM
 997         help
 998           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
 999           erratum. Any asynchronous access to the L2 cache may encounter a
1000           situation in which recent store transactions to the L2 cache are lost
1001           and overwritten with stale memory contents from external memory. The
1002           workaround disables the write-allocate mode for the L2 cache via the
1003           ACTLR register. Note that setting specific bits in the ACTLR register
1004           may not be available in non-secure mode.
1005
1006 config ARM_ERRATA_742230
1007         bool "ARM errata: DMB operation may be faulty"
1008         depends on CPU_V7 && SMP
1009         depends on !ARCH_MULTIPLATFORM
1010         help
1011           This option enables the workaround for the 742230 Cortex-A9
1012           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1013           between two write operations may not ensure the correct visibility
1014           ordering of the two writes. This workaround sets a specific bit in
1015           the diagnostic register of the Cortex-A9 which causes the DMB
1016           instruction to behave as a DSB, ensuring the correct behaviour of
1017           the two writes.
1018
1019 config ARM_ERRATA_742231
1020         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1021         depends on CPU_V7 && SMP
1022         depends on !ARCH_MULTIPLATFORM
1023         help
1024           This option enables the workaround for the 742231 Cortex-A9
1025           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1026           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1027           accessing some data located in the same cache line, may get corrupted
1028           data due to bad handling of the address hazard when the line gets
1029           replaced from one of the CPUs at the same time as another CPU is
1030           accessing it. This workaround sets specific bits in the diagnostic
1031           register of the Cortex-A9 which reduces the linefill issuing
1032           capabilities of the processor.
1033
1034 config ARM_ERRATA_643719
1035         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1036         depends on CPU_V7 && SMP
1037         default y
1038         help
1039           This option enables the workaround for the 643719 Cortex-A9 (prior to
1040           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1041           register returns zero when it should return one. The workaround
1042           corrects this value, ensuring cache maintenance operations which use
1043           it behave as intended and avoiding data corruption.
1044
1045 config ARM_ERRATA_720789
1046         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1047         depends on CPU_V7
1048         help
1049           This option enables the workaround for the 720789 Cortex-A9 (prior to
1050           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1051           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1052           As a consequence of this erratum, some TLB entries which should be
1053           invalidated are not, resulting in an incoherency in the system page
1054           tables. The workaround changes the TLB flushing routines to invalidate
1055           entries regardless of the ASID.
1056
1057 config ARM_ERRATA_743622
1058         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1059         depends on CPU_V7
1060         depends on !ARCH_MULTIPLATFORM
1061         help
1062           This option enables the workaround for the 743622 Cortex-A9
1063           (r2p*) erratum. Under very rare conditions, a faulty
1064           optimisation in the Cortex-A9 Store Buffer may lead to data
1065           corruption. This workaround sets a specific bit in the diagnostic
1066           register of the Cortex-A9 which disables the Store Buffer
1067           optimisation, preventing the defect from occurring. This has no
1068           visible impact on the overall performance or power consumption of the
1069           processor.
1070
1071 config ARM_ERRATA_751472
1072         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1073         depends on CPU_V7
1074         depends on !ARCH_MULTIPLATFORM
1075         help
1076           This option enables the workaround for the 751472 Cortex-A9 (prior
1077           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1078           completion of a following broadcasted operation if the second
1079           operation is received by a CPU before the ICIALLUIS has completed,
1080           potentially leading to corrupted entries in the cache or TLB.
1081
1082 config ARM_ERRATA_754322
1083         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1084         depends on CPU_V7
1085         help
1086           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1087           r3p*) erratum. A speculative memory access may cause a page table walk
1088           which starts prior to an ASID switch but completes afterwards. This
1089           can populate the micro-TLB with a stale entry which may be hit with
1090           the new ASID. This workaround places two dsb instructions in the mm
1091           switching code so that no page table walks can cross the ASID switch.
1092
1093 config ARM_ERRATA_754327
1094         bool "ARM errata: no automatic Store Buffer drain"
1095         depends on CPU_V7 && SMP
1096         help
1097           This option enables the workaround for the 754327 Cortex-A9 (prior to
1098           r2p0) erratum. The Store Buffer does not have any automatic draining
1099           mechanism and therefore a livelock may occur if an external agent
1100           continuously polls a memory location waiting to observe an update.
1101           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1102           written polling loops from denying visibility of updates to memory.
1103
1104 config ARM_ERRATA_364296
1105         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1106         depends on CPU_V6
1107         help
1108           This options enables the workaround for the 364296 ARM1136
1109           r0p2 erratum (possible cache data corruption with
1110           hit-under-miss enabled). It sets the undocumented bit 31 in
1111           the auxiliary control register and the FI bit in the control
1112           register, thus disabling hit-under-miss without putting the
1113           processor into full low interrupt latency mode. ARM11MPCore
1114           is not affected.
1115
1116 config ARM_ERRATA_764369
1117         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1118         depends on CPU_V7 && SMP
1119         help
1120           This option enables the workaround for erratum 764369
1121           affecting Cortex-A9 MPCore with two or more processors (all
1122           current revisions). Under certain timing circumstances, a data
1123           cache line maintenance operation by MVA targeting an Inner
1124           Shareable memory region may fail to proceed up to either the
1125           Point of Coherency or to the Point of Unification of the
1126           system. This workaround adds a DSB instruction before the
1127           relevant cache maintenance functions and sets a specific bit
1128           in the diagnostic control register of the SCU.
1129
1130 config ARM_ERRATA_775420
1131        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1132        depends on CPU_V7
1133        help
1134          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1135          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1136          operation aborts with MMU exception, it might cause the processor
1137          to deadlock. This workaround puts DSB before executing ISB if
1138          an abort may occur on cache maintenance.
1139
1140 config ARM_ERRATA_798181
1141         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1142         depends on CPU_V7 && SMP
1143         help
1144           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1145           adequately shooting down all use of the old entries. This
1146           option enables the Linux kernel workaround for this erratum
1147           which sends an IPI to the CPUs that are running the same ASID
1148           as the one being invalidated.
1149
1150 config ARM_ERRATA_773022
1151         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1152         depends on CPU_V7
1153         help
1154           This option enables the workaround for the 773022 Cortex-A15
1155           (up to r0p4) erratum. In certain rare sequences of code, the
1156           loop buffer may deliver incorrect instructions. This
1157           workaround disables the loop buffer to avoid the erratum.
1158
1159 config ARM_ERRATA_818325_852422
1160         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1161         depends on CPU_V7
1162         help
1163           This option enables the workaround for:
1164           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1165             instruction might deadlock.  Fixed in r0p1.
1166           - Cortex-A12 852422: Execution of a sequence of instructions might
1167             lead to either a data corruption or a CPU deadlock.  Not fixed in
1168             any Cortex-A12 cores yet.
1169           This workaround for all both errata involves setting bit[12] of the
1170           Feature Register. This bit disables an optimisation applied to a
1171           sequence of 2 instructions that use opposing condition codes.
1172
1173 config ARM_ERRATA_821420
1174         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1175         depends on CPU_V7
1176         help
1177           This option enables the workaround for the 821420 Cortex-A12
1178           (all revs) erratum. In very rare timing conditions, a sequence
1179           of VMOV to Core registers instructions, for which the second
1180           one is in the shadow of a branch or abort, can lead to a
1181           deadlock when the VMOV instructions are issued out-of-order.
1182
1183 config ARM_ERRATA_825619
1184         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1185         depends on CPU_V7
1186         help
1187           This option enables the workaround for the 825619 Cortex-A12
1188           (all revs) erratum. Within rare timing constraints, executing a
1189           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1190           and Device/Strongly-Ordered loads and stores might cause deadlock
1191
1192 config ARM_ERRATA_852421
1193         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1194         depends on CPU_V7
1195         help
1196           This option enables the workaround for the 852421 Cortex-A17
1197           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1198           execution of a DMB ST instruction might fail to properly order
1199           stores from GroupA and stores from GroupB.
1200
1201 config ARM_ERRATA_852423
1202         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1203         depends on CPU_V7
1204         help
1205           This option enables the workaround for:
1206           - Cortex-A17 852423: Execution of a sequence of instructions might
1207             lead to either a data corruption or a CPU deadlock.  Not fixed in
1208             any Cortex-A17 cores yet.
1209           This is identical to Cortex-A12 erratum 852422.  It is a separate
1210           config option from the A12 erratum due to the way errata are checked
1211           for and handled.
1212
1213 endmenu
1214
1215 source "arch/arm/common/Kconfig"
1216
1217 menu "Bus support"
1218
1219 config ISA
1220         bool
1221         help
1222           Find out whether you have ISA slots on your motherboard.  ISA is the
1223           name of a bus system, i.e. the way the CPU talks to the other stuff
1224           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1225           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1226           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1227
1228 # Select ISA DMA controller support
1229 config ISA_DMA
1230         bool
1231         select ISA_DMA_API
1232
1233 # Select ISA DMA interface
1234 config ISA_DMA_API
1235         bool
1236
1237 config PCI
1238         bool "PCI support" if MIGHT_HAVE_PCI
1239         help
1240           Find out whether you have a PCI motherboard. PCI is the name of a
1241           bus system, i.e. the way the CPU talks to the other stuff inside
1242           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1243           VESA. If you have PCI, say Y, otherwise N.
1244
1245 config PCI_DOMAINS
1246         bool
1247         depends on PCI
1248
1249 config PCI_DOMAINS_GENERIC
1250         def_bool PCI_DOMAINS
1251
1252 config PCI_NANOENGINE
1253         bool "BSE nanoEngine PCI support"
1254         depends on SA1100_NANOENGINE
1255         help
1256           Enable PCI on the BSE nanoEngine board.
1257
1258 config PCI_SYSCALL
1259         def_bool PCI
1260
1261 config PCI_HOST_ITE8152
1262         bool
1263         depends on PCI && MACH_ARMCORE
1264         default y
1265         select DMABOUNCE
1266
1267 source "drivers/pci/Kconfig"
1268
1269 source "drivers/pcmcia/Kconfig"
1270
1271 endmenu
1272
1273 menu "Kernel Features"
1274
1275 config HAVE_SMP
1276         bool
1277         help
1278           This option should be selected by machines which have an SMP-
1279           capable CPU.
1280
1281           The only effect of this option is to make the SMP-related
1282           options available to the user for configuration.
1283
1284 config SMP
1285         bool "Symmetric Multi-Processing"
1286         depends on CPU_V6K || CPU_V7
1287         depends on GENERIC_CLOCKEVENTS
1288         depends on HAVE_SMP
1289         depends on MMU || ARM_MPU
1290         select IRQ_WORK
1291         help
1292           This enables support for systems with more than one CPU. If you have
1293           a system with only one CPU, say N. If you have a system with more
1294           than one CPU, say Y.
1295
1296           If you say N here, the kernel will run on uni- and multiprocessor
1297           machines, but will use only one CPU of a multiprocessor machine. If
1298           you say Y here, the kernel will run on many, but not all,
1299           uniprocessor machines. On a uniprocessor machine, the kernel
1300           will run faster if you say N here.
1301
1302           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1303           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1304           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1305
1306           If you don't know what to do here, say N.
1307
1308 config SMP_ON_UP
1309         bool "Allow booting SMP kernel on uniprocessor systems"
1310         depends on SMP && !XIP_KERNEL && MMU
1311         default y
1312         help
1313           SMP kernels contain instructions which fail on non-SMP processors.
1314           Enabling this option allows the kernel to modify itself to make
1315           these instructions safe.  Disabling it allows about 1K of space
1316           savings.
1317
1318           If you don't know what to do here, say Y.
1319
1320 config ARM_CPU_TOPOLOGY
1321         bool "Support cpu topology definition"
1322         depends on SMP && CPU_V7
1323         default y
1324         help
1325           Support ARM cpu topology definition. The MPIDR register defines
1326           affinity between processors which is then used to describe the cpu
1327           topology of an ARM System.
1328
1329 config SCHED_MC
1330         bool "Multi-core scheduler support"
1331         depends on ARM_CPU_TOPOLOGY
1332         help
1333           Multi-core scheduler support improves the CPU scheduler's decision
1334           making when dealing with multi-core CPU chips at a cost of slightly
1335           increased overhead in some places. If unsure say N here.
1336
1337 config SCHED_SMT
1338         bool "SMT scheduler support"
1339         depends on ARM_CPU_TOPOLOGY
1340         help
1341           Improves the CPU scheduler's decision making when dealing with
1342           MultiThreading at a cost of slightly increased overhead in some
1343           places. If unsure say N here.
1344
1345 config HAVE_ARM_SCU
1346         bool
1347         help
1348           This option enables support for the ARM system coherency unit
1349
1350 config HAVE_ARM_ARCH_TIMER
1351         bool "Architected timer support"
1352         depends on CPU_V7
1353         select ARM_ARCH_TIMER
1354         select GENERIC_CLOCKEVENTS
1355         help
1356           This option enables support for the ARM architected timer
1357
1358 config HAVE_ARM_TWD
1359         bool
1360         select TIMER_OF if OF
1361         help
1362           This options enables support for the ARM timer and watchdog unit
1363
1364 config MCPM
1365         bool "Multi-Cluster Power Management"
1366         depends on CPU_V7 && SMP
1367         help
1368           This option provides the common power management infrastructure
1369           for (multi-)cluster based systems, such as big.LITTLE based
1370           systems.
1371
1372 config MCPM_QUAD_CLUSTER
1373         bool
1374         depends on MCPM
1375         help
1376           To avoid wasting resources unnecessarily, MCPM only supports up
1377           to 2 clusters by default.
1378           Platforms with 3 or 4 clusters that use MCPM must select this
1379           option to allow the additional clusters to be managed.
1380
1381 config BIG_LITTLE
1382         bool "big.LITTLE support (Experimental)"
1383         depends on CPU_V7 && SMP
1384         select MCPM
1385         help
1386           This option enables support selections for the big.LITTLE
1387           system architecture.
1388
1389 config BL_SWITCHER
1390         bool "big.LITTLE switcher support"
1391         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1392         select CPU_PM
1393         help
1394           The big.LITTLE "switcher" provides the core functionality to
1395           transparently handle transition between a cluster of A15's
1396           and a cluster of A7's in a big.LITTLE system.
1397
1398 config BL_SWITCHER_DUMMY_IF
1399         tristate "Simple big.LITTLE switcher user interface"
1400         depends on BL_SWITCHER && DEBUG_KERNEL
1401         help
1402           This is a simple and dummy char dev interface to control
1403           the big.LITTLE switcher core code.  It is meant for
1404           debugging purposes only.
1405
1406 choice
1407         prompt "Memory split"
1408         depends on MMU
1409         default VMSPLIT_3G
1410         help
1411           Select the desired split between kernel and user memory.
1412
1413           If you are not absolutely sure what you are doing, leave this
1414           option alone!
1415
1416         config VMSPLIT_3G
1417                 bool "3G/1G user/kernel split"
1418         config VMSPLIT_3G_OPT
1419                 depends on !ARM_LPAE
1420                 bool "3G/1G user/kernel split (for full 1G low memory)"
1421         config VMSPLIT_2G
1422                 bool "2G/2G user/kernel split"
1423         config VMSPLIT_1G
1424                 bool "1G/3G user/kernel split"
1425 endchoice
1426
1427 config PAGE_OFFSET
1428         hex
1429         default PHYS_OFFSET if !MMU
1430         default 0x40000000 if VMSPLIT_1G
1431         default 0x80000000 if VMSPLIT_2G
1432         default 0xB0000000 if VMSPLIT_3G_OPT
1433         default 0xC0000000
1434
1435 config NR_CPUS
1436         int "Maximum number of CPUs (2-32)"
1437         range 2 32
1438         depends on SMP
1439         default "4"
1440
1441 config HOTPLUG_CPU
1442         bool "Support for hot-pluggable CPUs"
1443         depends on SMP
1444         help
1445           Say Y here to experiment with turning CPUs off and on.  CPUs
1446           can be controlled through /sys/devices/system/cpu.
1447
1448 config ARM_PSCI
1449         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1450         depends on HAVE_ARM_SMCCC
1451         select ARM_PSCI_FW
1452         help
1453           Say Y here if you want Linux to communicate with system firmware
1454           implementing the PSCI specification for CPU-centric power
1455           management operations described in ARM document number ARM DEN
1456           0022A ("Power State Coordination Interface System Software on
1457           ARM processors").
1458
1459 # The GPIO number here must be sorted by descending number. In case of
1460 # a multiplatform kernel, we just want the highest value required by the
1461 # selected platforms.
1462 config ARCH_NR_GPIO
1463         int
1464         default 2048 if ARCH_SOCFPGA
1465         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1466                 ARCH_ZYNQ
1467         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1468                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1469         default 416 if ARCH_SUNXI
1470         default 392 if ARCH_U8500
1471         default 352 if ARCH_VT8500
1472         default 288 if ARCH_ROCKCHIP
1473         default 264 if MACH_H4700
1474         default 0
1475         help
1476           Maximum number of GPIOs in the system.
1477
1478           If unsure, leave the default value.
1479
1480 source kernel/Kconfig.preempt
1481
1482 config HZ_FIXED
1483         int
1484         default 200 if ARCH_EBSA110
1485         default 128 if SOC_AT91RM9200
1486         default 0
1487
1488 choice
1489         depends on HZ_FIXED = 0
1490         prompt "Timer frequency"
1491
1492 config HZ_100
1493         bool "100 Hz"
1494
1495 config HZ_200
1496         bool "200 Hz"
1497
1498 config HZ_250
1499         bool "250 Hz"
1500
1501 config HZ_300
1502         bool "300 Hz"
1503
1504 config HZ_500
1505         bool "500 Hz"
1506
1507 config HZ_1000
1508         bool "1000 Hz"
1509
1510 endchoice
1511
1512 config HZ
1513         int
1514         default HZ_FIXED if HZ_FIXED != 0
1515         default 100 if HZ_100
1516         default 200 if HZ_200
1517         default 250 if HZ_250
1518         default 300 if HZ_300
1519         default 500 if HZ_500
1520         default 1000
1521
1522 config SCHED_HRTICK
1523         def_bool HIGH_RES_TIMERS
1524
1525 config THUMB2_KERNEL
1526         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1527         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1528         default y if CPU_THUMBONLY
1529         select ARM_UNWIND
1530         help
1531           By enabling this option, the kernel will be compiled in
1532           Thumb-2 mode.
1533
1534           If unsure, say N.
1535
1536 config THUMB2_AVOID_R_ARM_THM_JUMP11
1537         bool "Work around buggy Thumb-2 short branch relocations in gas"
1538         depends on THUMB2_KERNEL && MODULES
1539         default y
1540         help
1541           Various binutils versions can resolve Thumb-2 branches to
1542           locally-defined, preemptible global symbols as short-range "b.n"
1543           branch instructions.
1544
1545           This is a problem, because there's no guarantee the final
1546           destination of the symbol, or any candidate locations for a
1547           trampoline, are within range of the branch.  For this reason, the
1548           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1549           relocation in modules at all, and it makes little sense to add
1550           support.
1551
1552           The symptom is that the kernel fails with an "unsupported
1553           relocation" error when loading some modules.
1554
1555           Until fixed tools are available, passing
1556           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1557           code which hits this problem, at the cost of a bit of extra runtime
1558           stack usage in some cases.
1559
1560           The problem is described in more detail at:
1561               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1562
1563           Only Thumb-2 kernels are affected.
1564
1565           Unless you are sure your tools don't have this problem, say Y.
1566
1567 config ARM_PATCH_IDIV
1568         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1569         depends on CPU_32v7 && !XIP_KERNEL
1570         default y
1571         help
1572           The ARM compiler inserts calls to __aeabi_idiv() and
1573           __aeabi_uidiv() when it needs to perform division on signed
1574           and unsigned integers. Some v7 CPUs have support for the sdiv
1575           and udiv instructions that can be used to implement those
1576           functions.
1577
1578           Enabling this option allows the kernel to modify itself to
1579           replace the first two instructions of these library functions
1580           with the sdiv or udiv plus "bx lr" instructions when the CPU
1581           it is running on supports them. Typically this will be faster
1582           and less power intensive than running the original library
1583           code to do integer division.
1584
1585 config AEABI
1586         bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1587         default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1588         help
1589           This option allows for the kernel to be compiled using the latest
1590           ARM ABI (aka EABI).  This is only useful if you are using a user
1591           space environment that is also compiled with EABI.
1592
1593           Since there are major incompatibilities between the legacy ABI and
1594           EABI, especially with regard to structure member alignment, this
1595           option also changes the kernel syscall calling convention to
1596           disambiguate both ABIs and allow for backward compatibility support
1597           (selected with CONFIG_OABI_COMPAT).
1598
1599           To use this you need GCC version 4.0.0 or later.
1600
1601 config OABI_COMPAT
1602         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1603         depends on AEABI && !THUMB2_KERNEL
1604         help
1605           This option preserves the old syscall interface along with the
1606           new (ARM EABI) one. It also provides a compatibility layer to
1607           intercept syscalls that have structure arguments which layout
1608           in memory differs between the legacy ABI and the new ARM EABI
1609           (only for non "thumb" binaries). This option adds a tiny
1610           overhead to all syscalls and produces a slightly larger kernel.
1611
1612           The seccomp filter system will not be available when this is
1613           selected, since there is no way yet to sensibly distinguish
1614           between calling conventions during filtering.
1615
1616           If you know you'll be using only pure EABI user space then you
1617           can say N here. If this option is not selected and you attempt
1618           to execute a legacy ABI binary then the result will be
1619           UNPREDICTABLE (in fact it can be predicted that it won't work
1620           at all). If in doubt say N.
1621
1622 config ARCH_HAS_HOLES_MEMORYMODEL
1623         bool
1624
1625 config ARCH_SPARSEMEM_ENABLE
1626         bool
1627
1628 config ARCH_SPARSEMEM_DEFAULT
1629         def_bool ARCH_SPARSEMEM_ENABLE
1630
1631 config ARCH_SELECT_MEMORY_MODEL
1632         def_bool ARCH_SPARSEMEM_ENABLE
1633
1634 config HAVE_ARCH_PFN_VALID
1635         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1636
1637 config HAVE_GENERIC_GUP
1638         def_bool y
1639         depends on ARM_LPAE
1640
1641 config HIGHMEM
1642         bool "High Memory Support"
1643         depends on MMU
1644         help
1645           The address space of ARM processors is only 4 Gigabytes large
1646           and it has to accommodate user address space, kernel address
1647           space as well as some memory mapped IO. That means that, if you
1648           have a large amount of physical memory and/or IO, not all of the
1649           memory can be "permanently mapped" by the kernel. The physical
1650           memory that is not permanently mapped is called "high memory".
1651
1652           Depending on the selected kernel/user memory split, minimum
1653           vmalloc space and actual amount of RAM, you may not need this
1654           option which should result in a slightly faster kernel.
1655
1656           If unsure, say n.
1657
1658 config HIGHPTE
1659         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1660         depends on HIGHMEM
1661         default y
1662         help
1663           The VM uses one page of physical memory for each page table.
1664           For systems with a lot of processes, this can use a lot of
1665           precious low memory, eventually leading to low memory being
1666           consumed by page tables.  Setting this option will allow
1667           user-space 2nd level page tables to reside in high memory.
1668
1669 config CPU_SW_DOMAIN_PAN
1670         bool "Enable use of CPU domains to implement privileged no-access"
1671         depends on MMU && !ARM_LPAE
1672         default y
1673         help
1674           Increase kernel security by ensuring that normal kernel accesses
1675           are unable to access userspace addresses.  This can help prevent
1676           use-after-free bugs becoming an exploitable privilege escalation
1677           by ensuring that magic values (such as LIST_POISON) will always
1678           fault when dereferenced.
1679
1680           CPUs with low-vector mappings use a best-efforts implementation.
1681           Their lower 1MB needs to remain accessible for the vectors, but
1682           the remainder of userspace will become appropriately inaccessible.
1683
1684 config HW_PERF_EVENTS
1685         def_bool y
1686         depends on ARM_PMU
1687
1688 config SYS_SUPPORTS_HUGETLBFS
1689        def_bool y
1690        depends on ARM_LPAE
1691
1692 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1693        def_bool y
1694        depends on ARM_LPAE
1695
1696 config ARCH_WANT_GENERAL_HUGETLB
1697         def_bool y
1698
1699 config ARM_MODULE_PLTS
1700         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1701         depends on MODULES
1702         default y
1703         help
1704           Allocate PLTs when loading modules so that jumps and calls whose
1705           targets are too far away for their relative offsets to be encoded
1706           in the instructions themselves can be bounced via veneers in the
1707           module's PLT. This allows modules to be allocated in the generic
1708           vmalloc area after the dedicated module memory area has been
1709           exhausted. The modules will use slightly more memory, but after
1710           rounding up to page size, the actual memory footprint is usually
1711           the same.
1712
1713           Disabling this is usually safe for small single-platform
1714           configurations. If unsure, say y.
1715
1716 source "mm/Kconfig"
1717
1718 config FORCE_MAX_ZONEORDER
1719         int "Maximum zone order"
1720         default "12" if SOC_AM33XX
1721         default "9" if SA1111 || ARCH_EFM32
1722         default "11"
1723         help
1724           The kernel memory allocator divides physically contiguous memory
1725           blocks into "zones", where each zone is a power of two number of
1726           pages.  This option selects the largest power of two that the kernel
1727           keeps in the memory allocator.  If you need to allocate very large
1728           blocks of physically contiguous memory, then you may need to
1729           increase this value.
1730
1731           This config option is actually maximum order plus one. For example,
1732           a value of 11 means that the largest free memory block is 2^10 pages.
1733
1734 config ALIGNMENT_TRAP
1735         bool
1736         depends on CPU_CP15_MMU
1737         default y if !ARCH_EBSA110
1738         select HAVE_PROC_CPU if PROC_FS
1739         help
1740           ARM processors cannot fetch/store information which is not
1741           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1742           address divisible by 4. On 32-bit ARM processors, these non-aligned
1743           fetch/store instructions will be emulated in software if you say
1744           here, which has a severe performance impact. This is necessary for
1745           correct operation of some network protocols. With an IP-only
1746           configuration it is safe to say N, otherwise say Y.
1747
1748 config UACCESS_WITH_MEMCPY
1749         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1750         depends on MMU
1751         default y if CPU_FEROCEON
1752         help
1753           Implement faster copy_to_user and clear_user methods for CPU
1754           cores where a 8-word STM instruction give significantly higher
1755           memory write throughput than a sequence of individual 32bit stores.
1756
1757           A possible side effect is a slight increase in scheduling latency
1758           between threads sharing the same address space if they invoke
1759           such copy operations with large buffers.
1760
1761           However, if the CPU data cache is using a write-allocate mode,
1762           this option is unlikely to provide any performance gain.
1763
1764 config SECCOMP
1765         bool
1766         prompt "Enable seccomp to safely compute untrusted bytecode"
1767         ---help---
1768           This kernel feature is useful for number crunching applications
1769           that may need to compute untrusted bytecode during their
1770           execution. By using pipes or other transports made available to
1771           the process as file descriptors supporting the read/write
1772           syscalls, it's possible to isolate those applications in
1773           their own address space using seccomp. Once seccomp is
1774           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1775           and the task is only allowed to execute a few safe syscalls
1776           defined by each seccomp mode.
1777
1778 config PARAVIRT
1779         bool "Enable paravirtualization code"
1780         help
1781           This changes the kernel so it can modify itself when it is run
1782           under a hypervisor, potentially improving performance significantly
1783           over full virtualization.
1784
1785 config PARAVIRT_TIME_ACCOUNTING
1786         bool "Paravirtual steal time accounting"
1787         select PARAVIRT
1788         default n
1789         help
1790           Select this option to enable fine granularity task steal time
1791           accounting. Time spent executing other tasks in parallel with
1792           the current vCPU is discounted from the vCPU power. To account for
1793           that, there can be a small performance impact.
1794
1795           If in doubt, say N here.
1796
1797 config XEN_DOM0
1798         def_bool y
1799         depends on XEN
1800
1801 config XEN
1802         bool "Xen guest support on ARM"
1803         depends on ARM && AEABI && OF
1804         depends on CPU_V7 && !CPU_V6
1805         depends on !GENERIC_ATOMIC64
1806         depends on MMU
1807         select ARCH_DMA_ADDR_T_64BIT
1808         select ARM_PSCI
1809         select SWIOTLB
1810         select SWIOTLB_XEN
1811         select PARAVIRT
1812         help
1813           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1814
1815 endmenu
1816
1817 menu "Boot options"
1818
1819 config USE_OF
1820         bool "Flattened Device Tree support"
1821         select IRQ_DOMAIN
1822         select OF
1823         help
1824           Include support for flattened device tree machine descriptions.
1825
1826 config ATAGS
1827         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1828         default y
1829         help
1830           This is the traditional way of passing data to the kernel at boot
1831           time. If you are solely relying on the flattened device tree (or
1832           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1833           to remove ATAGS support from your kernel binary.  If unsure,
1834           leave this to y.
1835
1836 config DEPRECATED_PARAM_STRUCT
1837         bool "Provide old way to pass kernel parameters"
1838         depends on ATAGS
1839         help
1840           This was deprecated in 2001 and announced to live on for 5 years.
1841           Some old boot loaders still use this way.
1842
1843 # Compressed boot loader in ROM.  Yes, we really want to ask about
1844 # TEXT and BSS so we preserve their values in the config files.
1845 config ZBOOT_ROM_TEXT
1846         hex "Compressed ROM boot loader base address"
1847         default "0"
1848         help
1849           The physical address at which the ROM-able zImage is to be
1850           placed in the target.  Platforms which normally make use of
1851           ROM-able zImage formats normally set this to a suitable
1852           value in their defconfig file.
1853
1854           If ZBOOT_ROM is not enabled, this has no effect.
1855
1856 config ZBOOT_ROM_BSS
1857         hex "Compressed ROM boot loader BSS address"
1858         default "0"
1859         help
1860           The base address of an area of read/write memory in the target
1861           for the ROM-able zImage which must be available while the
1862           decompressor is running. It must be large enough to hold the
1863           entire decompressed kernel plus an additional 128 KiB.
1864           Platforms which normally make use of ROM-able zImage formats
1865           normally set this to a suitable value in their defconfig file.
1866
1867           If ZBOOT_ROM is not enabled, this has no effect.
1868
1869 config ZBOOT_ROM
1870         bool "Compressed boot loader in ROM/flash"
1871         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1872         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1873         help
1874           Say Y here if you intend to execute your compressed kernel image
1875           (zImage) directly from ROM or flash.  If unsure, say N.
1876
1877 config ARM_APPENDED_DTB
1878         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1879         depends on OF
1880         help
1881           With this option, the boot code will look for a device tree binary
1882           (DTB) appended to zImage
1883           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1884
1885           This is meant as a backward compatibility convenience for those
1886           systems with a bootloader that can't be upgraded to accommodate
1887           the documented boot protocol using a device tree.
1888
1889           Beware that there is very little in terms of protection against
1890           this option being confused by leftover garbage in memory that might
1891           look like a DTB header after a reboot if no actual DTB is appended
1892           to zImage.  Do not leave this option active in a production kernel
1893           if you don't intend to always append a DTB.  Proper passing of the
1894           location into r2 of a bootloader provided DTB is always preferable
1895           to this option.
1896
1897 config ARM_ATAG_DTB_COMPAT
1898         bool "Supplement the appended DTB with traditional ATAG information"
1899         depends on ARM_APPENDED_DTB
1900         help
1901           Some old bootloaders can't be updated to a DTB capable one, yet
1902           they provide ATAGs with memory configuration, the ramdisk address,
1903           the kernel cmdline string, etc.  Such information is dynamically
1904           provided by the bootloader and can't always be stored in a static
1905           DTB.  To allow a device tree enabled kernel to be used with such
1906           bootloaders, this option allows zImage to extract the information
1907           from the ATAG list and store it at run time into the appended DTB.
1908
1909 choice
1910         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1911         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1912
1913 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1914         bool "Use bootloader kernel arguments if available"
1915         help
1916           Uses the command-line options passed by the boot loader instead of
1917           the device tree bootargs property. If the boot loader doesn't provide
1918           any, the device tree bootargs property will be used.
1919
1920 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1921         bool "Extend with bootloader kernel arguments"
1922         help
1923           The command-line arguments provided by the boot loader will be
1924           appended to the the device tree bootargs property.
1925
1926 endchoice
1927
1928 config CMDLINE
1929         string "Default kernel command string"
1930         default ""
1931         help
1932           On some architectures (EBSA110 and CATS), there is currently no way
1933           for the boot loader to pass arguments to the kernel. For these
1934           architectures, you should supply some command-line options at build
1935           time by entering them here. As a minimum, you should specify the
1936           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1937
1938 choice
1939         prompt "Kernel command line type" if CMDLINE != ""
1940         default CMDLINE_FROM_BOOTLOADER
1941         depends on ATAGS
1942
1943 config CMDLINE_FROM_BOOTLOADER
1944         bool "Use bootloader kernel arguments if available"
1945         help
1946           Uses the command-line options passed by the boot loader. If
1947           the boot loader doesn't provide any, the default kernel command
1948           string provided in CMDLINE will be used.
1949
1950 config CMDLINE_EXTEND
1951         bool "Extend bootloader kernel arguments"
1952         help
1953           The command-line arguments provided by the boot loader will be
1954           appended to the default kernel command string.
1955
1956 config CMDLINE_FORCE
1957         bool "Always use the default kernel command string"
1958         help
1959           Always use the default kernel command string, even if the boot
1960           loader passes other arguments to the kernel.
1961           This is useful if you cannot or don't want to change the
1962           command-line options your boot loader passes to the kernel.
1963 endchoice
1964
1965 config XIP_KERNEL
1966         bool "Kernel Execute-In-Place from ROM"
1967         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1968         help
1969           Execute-In-Place allows the kernel to run from non-volatile storage
1970           directly addressable by the CPU, such as NOR flash. This saves RAM
1971           space since the text section of the kernel is not loaded from flash
1972           to RAM.  Read-write sections, such as the data section and stack,
1973           are still copied to RAM.  The XIP kernel is not compressed since
1974           it has to run directly from flash, so it will take more space to
1975           store it.  The flash address used to link the kernel object files,
1976           and for storing it, is configuration dependent. Therefore, if you
1977           say Y here, you must know the proper physical address where to
1978           store the kernel image depending on your own flash memory usage.
1979
1980           Also note that the make target becomes "make xipImage" rather than
1981           "make zImage" or "make Image".  The final kernel binary to put in
1982           ROM memory will be arch/arm/boot/xipImage.
1983
1984           If unsure, say N.
1985
1986 config XIP_PHYS_ADDR
1987         hex "XIP Kernel Physical Location"
1988         depends on XIP_KERNEL
1989         default "0x00080000"
1990         help
1991           This is the physical address in your flash memory the kernel will
1992           be linked for and stored to.  This address is dependent on your
1993           own flash usage.
1994
1995 config XIP_DEFLATED_DATA
1996         bool "Store kernel .data section compressed in ROM"
1997         depends on XIP_KERNEL
1998         select ZLIB_INFLATE
1999         help
2000           Before the kernel is actually executed, its .data section has to be
2001           copied to RAM from ROM. This option allows for storing that data
2002           in compressed form and decompressed to RAM rather than merely being
2003           copied, saving some precious ROM space. A possible drawback is a
2004           slightly longer boot delay.
2005
2006 config KEXEC
2007         bool "Kexec system call (EXPERIMENTAL)"
2008         depends on (!SMP || PM_SLEEP_SMP)
2009         depends on !CPU_V7M
2010         select KEXEC_CORE
2011         help
2012           kexec is a system call that implements the ability to shutdown your
2013           current kernel, and to start another kernel.  It is like a reboot
2014           but it is independent of the system firmware.   And like a reboot
2015           you can start any kernel with it, not just Linux.
2016
2017           It is an ongoing process to be certain the hardware in a machine
2018           is properly shutdown, so do not be surprised if this code does not
2019           initially work for you.
2020
2021 config ATAGS_PROC
2022         bool "Export atags in procfs"
2023         depends on ATAGS && KEXEC
2024         default y
2025         help
2026           Should the atags used to boot the kernel be exported in an "atags"
2027           file in procfs. Useful with kexec.
2028
2029 config CRASH_DUMP
2030         bool "Build kdump crash kernel (EXPERIMENTAL)"
2031         help
2032           Generate crash dump after being started by kexec. This should
2033           be normally only set in special crash dump kernels which are
2034           loaded in the main kernel with kexec-tools into a specially
2035           reserved region and then later executed after a crash by
2036           kdump/kexec. The crash dump kernel must be compiled to a
2037           memory address not used by the main kernel
2038
2039           For more details see Documentation/kdump/kdump.txt
2040
2041 config AUTO_ZRELADDR
2042         bool "Auto calculation of the decompressed kernel image address"
2043         help
2044           ZRELADDR is the physical address where the decompressed kernel
2045           image will be placed. If AUTO_ZRELADDR is selected, the address
2046           will be determined at run-time by masking the current IP with
2047           0xf8000000. This assumes the zImage being placed in the first 128MB
2048           from start of memory.
2049
2050 config EFI_STUB
2051         bool
2052
2053 config EFI
2054         bool "UEFI runtime support"
2055         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2056         select UCS2_STRING
2057         select EFI_PARAMS_FROM_FDT
2058         select EFI_STUB
2059         select EFI_ARMSTUB
2060         select EFI_RUNTIME_WRAPPERS
2061         ---help---
2062           This option provides support for runtime services provided
2063           by UEFI firmware (such as non-volatile variables, realtime
2064           clock, and platform reset). A UEFI stub is also provided to
2065           allow the kernel to be booted as an EFI application. This
2066           is only useful for kernels that may run on systems that have
2067           UEFI firmware.
2068
2069 config DMI
2070         bool "Enable support for SMBIOS (DMI) tables"
2071         depends on EFI
2072         default y
2073         help
2074           This enables SMBIOS/DMI feature for systems.
2075
2076           This option is only useful on systems that have UEFI firmware.
2077           However, even with this option, the resultant kernel should
2078           continue to boot on existing non-UEFI platforms.
2079
2080           NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2081           i.e., the the practice of identifying the platform via DMI to
2082           decide whether certain workarounds for buggy hardware and/or
2083           firmware need to be enabled. This would require the DMI subsystem
2084           to be enabled much earlier than we do on ARM, which is non-trivial.
2085
2086 endmenu
2087
2088 menu "CPU Power Management"
2089
2090 source "drivers/cpufreq/Kconfig"
2091
2092 source "drivers/cpuidle/Kconfig"
2093
2094 endmenu
2095
2096 menu "Floating point emulation"
2097
2098 comment "At least one emulation must be selected"
2099
2100 config FPE_NWFPE
2101         bool "NWFPE math emulation"
2102         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2103         ---help---
2104           Say Y to include the NWFPE floating point emulator in the kernel.
2105           This is necessary to run most binaries. Linux does not currently
2106           support floating point hardware so you need to say Y here even if
2107           your machine has an FPA or floating point co-processor podule.
2108
2109           You may say N here if you are going to load the Acorn FPEmulator
2110           early in the bootup.
2111
2112 config FPE_NWFPE_XP
2113         bool "Support extended precision"
2114         depends on FPE_NWFPE
2115         help
2116           Say Y to include 80-bit support in the kernel floating-point
2117           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2118           Note that gcc does not generate 80-bit operations by default,
2119           so in most cases this option only enlarges the size of the
2120           floating point emulator without any good reason.
2121
2122           You almost surely want to say N here.
2123
2124 config FPE_FASTFPE
2125         bool "FastFPE math emulation (EXPERIMENTAL)"
2126         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2127         ---help---
2128           Say Y here to include the FAST floating point emulator in the kernel.
2129           This is an experimental much faster emulator which now also has full
2130           precision for the mantissa.  It does not support any exceptions.
2131           It is very simple, and approximately 3-6 times faster than NWFPE.
2132
2133           It should be sufficient for most programs.  It may be not suitable
2134           for scientific calculations, but you have to check this for yourself.
2135           If you do not feel you need a faster FP emulation you should better
2136           choose NWFPE.
2137
2138 config VFP
2139         bool "VFP-format floating point maths"
2140         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2141         help
2142           Say Y to include VFP support code in the kernel. This is needed
2143           if your hardware includes a VFP unit.
2144
2145           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2146           release notes and additional status information.
2147
2148           Say N if your target does not have VFP hardware.
2149
2150 config VFPv3
2151         bool
2152         depends on VFP
2153         default y if CPU_V7
2154
2155 config NEON
2156         bool "Advanced SIMD (NEON) Extension support"
2157         depends on VFPv3 && CPU_V7
2158         help
2159           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2160           Extension.
2161
2162 config KERNEL_MODE_NEON
2163         bool "Support for NEON in kernel mode"
2164         depends on NEON && AEABI
2165         help
2166           Say Y to include support for NEON in kernel mode.
2167
2168 endmenu
2169
2170 menu "Userspace binary formats"
2171
2172 source "fs/Kconfig.binfmt"
2173
2174 endmenu
2175
2176 menu "Power management options"
2177
2178 source "kernel/power/Kconfig"
2179
2180 config ARCH_SUSPEND_POSSIBLE
2181         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2182                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2183         def_bool y
2184
2185 config ARM_CPU_SUSPEND
2186         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2187         depends on ARCH_SUSPEND_POSSIBLE
2188
2189 config ARCH_HIBERNATION_POSSIBLE
2190         bool
2191         depends on MMU
2192         default y if ARCH_SUSPEND_POSSIBLE
2193
2194 endmenu
2195
2196 source "net/Kconfig"
2197
2198 source "drivers/Kconfig"
2199
2200 source "drivers/firmware/Kconfig"
2201
2202 source "fs/Kconfig"
2203
2204 source "arch/arm/Kconfig.debug"
2205
2206 source "security/Kconfig"
2207
2208 source "crypto/Kconfig"
2209 if CRYPTO
2210 source "arch/arm/crypto/Kconfig"
2211 endif
2212
2213 source "lib/Kconfig"
2214
2215 source "arch/arm/kvm/Kconfig"