arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_MIGHT_HAVE_PC_PARPORT
   9         select ARCH_USE_CMPXCHG_LOCKREF
  10         select ARCH_WANT_IPC_PARSE_VERSION
  11         select BUILDTIME_EXTABLE_SORT if MMU
  12         select CLONE_BACKWARDS
  13         select CPU_PM if (SUSPEND || CPU_IDLE)
  14         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
  15         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  16         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  17         select GENERIC_IDLE_POLL_SETUP
  18         select GENERIC_IRQ_PROBE
  19         select GENERIC_IRQ_SHOW
  20         select GENERIC_PCI_IOMAP
  21         select GENERIC_SCHED_CLOCK
  22         select GENERIC_SMP_IDLE_THREAD
  23         select GENERIC_STRNCPY_FROM_USER
  24         select GENERIC_STRNLEN_USER
  25         select HARDIRQS_SW_RESEND
  26         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  27         select HAVE_ARCH_KGDB
  28         select HAVE_ARCH_SECCOMP_FILTER
  29         select HAVE_ARCH_TRACEHOOK
  30         select HAVE_BPF_JIT
  31         select HAVE_CONTEXT_TRACKING
  32         select HAVE_C_RECORDMCOUNT
  33         select HAVE_DEBUG_KMEMLEAK
  34         select HAVE_DMA_API_DEBUG
  35         select HAVE_DMA_ATTRS
  36         select HAVE_DMA_CONTIGUOUS if MMU
  37         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  38         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  39         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  40         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  41         select HAVE_GENERIC_DMA_COHERENT
  42         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  43         select HAVE_IDE if PCI || ISA || PCMCIA
  44         select HAVE_IRQ_TIME_ACCOUNTING
  45         select HAVE_KERNEL_GZIP
  46         select HAVE_KERNEL_LZ4
  47         select HAVE_KERNEL_LZMA
  48         select HAVE_KERNEL_LZO
  49         select HAVE_KERNEL_XZ
  50         select HAVE_KPROBES if !XIP_KERNEL
  51         select HAVE_KRETPROBES if (HAVE_KPROBES)
  52         select HAVE_MEMBLOCK
  53         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  54         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  55         select HAVE_PERF_EVENTS
  56         select HAVE_PERF_REGS
  57         select HAVE_PERF_USER_STACK_DUMP
  58         select HAVE_REGS_AND_STACK_ACCESS_API
  59         select HAVE_SYSCALL_TRACEPOINTS
  60         select HAVE_UID16
  61         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  62         select IRQ_FORCED_THREADING
  63         select KTIME_SCALAR
  64         select MODULES_USE_ELF_REL
  65         select OLD_SIGACTION
  66         select OLD_SIGSUSPEND3
  67         select PERF_USE_VMALLOC
  68         select RTC_LIB
  69         select SYS_SUPPORTS_APM_EMULATION
  70         # Above selects are sorted alphabetically; please add new ones
  71         # according to that.  Thanks.
  72         help
  73           The ARM series is a line of low-power-consumption RISC chip designs
  74           licensed by ARM Ltd and targeted at embedded applications and
  75           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  76           manufactured, but legacy ARM-based PC hardware remains popular in
  77           Europe.  There is an ARM Linux project with a web page at
  78           <http://www.arm.linux.org.uk/>.
  79
  80 config ARM_HAS_SG_CHAIN
  81         bool
  82
  83 config NEED_SG_DMA_LENGTH
  84         bool
  85
  86 config ARM_DMA_USE_IOMMU
  87         bool
  88         select ARM_HAS_SG_CHAIN
  89         select NEED_SG_DMA_LENGTH
  90
  91 if ARM_DMA_USE_IOMMU
  92
  93 config ARM_DMA_IOMMU_ALIGNMENT
  94         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
  95         range 4 9
  96         default 8
  97         help
  98           DMA mapping framework by default aligns all buffers to the smallest
  99           PAGE_SIZE order which is greater than or equal to the requested buffer
 100           size. This works well for buffers up to a few hundreds kilobytes, but
 101           for larger buffers it just a waste of address space. Drivers which has
 102           relatively small addressing window (like 64Mib) might run out of
 103           virtual space with just a few allocations.
 104
 105           With this parameter you can specify the maximum PAGE_SIZE order for
 106           DMA IOMMU buffers. Larger buffers will be aligned only to this
 107           specified order. The order is expressed as a power of two multiplied
 108           by the PAGE_SIZE.
 109
 110 endif
 111
 112 config HAVE_PWM
 113         bool
 114
 115 config MIGHT_HAVE_PCI
 116         bool
 117
 118 config SYS_SUPPORTS_APM_EMULATION
 119         bool
 120
 121 config HAVE_TCM
 122         bool
 123         select GENERIC_ALLOCATOR
 124
 125 config HAVE_PROC_CPU
 126         bool
 127
 128 config NO_IOPORT
 129         bool
 130
 131 config EISA
 132         bool
 133         ---help---
 134           The Extended Industry Standard Architecture (EISA) bus was
 135           developed as an open alternative to the IBM MicroChannel bus.
 136
 137           The EISA bus provided some of the features of the IBM MicroChannel
 138           bus while maintaining backward compatibility with cards made for
 139           the older ISA bus.  The EISA bus saw limited use between 1988 and
 140           1995 when it was made obsolete by the PCI bus.
 141
 142           Say Y here if you are building a kernel for an EISA-based machine.
 143
 144           Otherwise, say N.
 145
 146 config SBUS
 147         bool
 148
 149 config STACKTRACE_SUPPORT
 150         bool
 151         default y
 152
 153 config HAVE_LATENCYTOP_SUPPORT
 154         bool
 155         depends on !SMP
 156         default y
 157
 158 config LOCKDEP_SUPPORT
 159         bool
 160         default y
 161
 162 config TRACE_IRQFLAGS_SUPPORT
 163         bool
 164         default y
 165
 166 config RWSEM_GENERIC_SPINLOCK
 167         bool
 168         default y
 169
 170 config RWSEM_XCHGADD_ALGORITHM
 171         bool
 172
 173 config ARCH_HAS_ILOG2_U32
 174         bool
 175
 176 config ARCH_HAS_ILOG2_U64
 177         bool
 178
 179 config ARCH_HAS_CPUFREQ
 180         bool
 181         help
 182           Internal node to signify that the ARCH has CPUFREQ support
 183           and that the relevant menu configurations are displayed for
 184           it.
 185
 186 config ARCH_HAS_BANDGAP
 187         bool
 188
 189 config GENERIC_HWEIGHT
 190         bool
 191         default y
 192
 193 config GENERIC_CALIBRATE_DELAY
 194         bool
 195         default y
 196
 197 config ARCH_MAY_HAVE_PC_FDC
 198         bool
 199
 200 config ZONE_DMA
 201         bool
 202
 203 config NEED_DMA_MAP_STATE
 204        def_bool y
 205
 206 config ARCH_HAS_DMA_SET_COHERENT_MASK
 207         bool
 208
 209 config GENERIC_ISA_DMA
 210         bool
 211
 212 config FIQ
 213         bool
 214
 215 config NEED_RET_TO_USER
 216         bool
 217
 218 config ARCH_MTD_XIP
 219         bool
 220
 221 config VECTORS_BASE
 222         hex
 223         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 224         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 225         default 0x00000000
 226         help
 227           The base address of exception vectors.  This must be two pages
 228           in size.
 229
 230 config ARM_PATCH_PHYS_VIRT
 231         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 232         default y
 233         depends on !XIP_KERNEL && MMU
 234         depends on !ARCH_REALVIEW || !SPARSEMEM
 235         help
 236           Patch phys-to-virt and virt-to-phys translation functions at
 237           boot and module load time according to the position of the
 238           kernel in system memory.
 239
 240           This can only be used with non-XIP MMU kernels where the base
 241           of physical memory is at a 16MB boundary.
 242
 243           Only disable this option if you know that you do not require
 244           this feature (eg, building a kernel for a single machine) and
 245           you need to shrink the kernel to the minimal size.
 246
 247 config NEED_MACH_GPIO_H
 248         bool
 249         help
 250           Select this when mach/gpio.h is required to provide special
 251           definitions for this platform. The need for mach/gpio.h should
 252           be avoided when possible.
 253
 254 config NEED_MACH_IO_H
 255         bool
 256         help
 257           Select this when mach/io.h is required to provide special
 258           definitions for this platform.  The need for mach/io.h should
 259           be avoided when possible.
 260
 261 config NEED_MACH_MEMORY_H
 262         bool
 263         help
 264           Select this when mach/memory.h is required to provide special
 265           definitions for this platform.  The need for mach/memory.h should
 266           be avoided when possible.
 267
 268 config PHYS_OFFSET
 269         hex "Physical address of main memory" if MMU
 270         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 271         default DRAM_BASE if !MMU
 272         help
 273           Please provide the physical address corresponding to the
 274           location of main memory in your system.
 275
 276 config GENERIC_BUG
 277         def_bool y
 278         depends on BUG
 279
 280 source "init/Kconfig"
 281
 282 source "kernel/Kconfig.freezer"
 283
 284 menu "System Type"
 285
 286 config MMU
 287         bool "MMU-based Paged Memory Management Support"
 288         default y
 289         help
 290           Select if you want MMU-based virtualised addressing space
 291           support by paged memory management. If unsure, say 'Y'.
 292
 293 #
 294 # The "ARM system type" choice list is ordered alphabetically by option
 295 # text.  Please add new entries in the option alphabetic order.
 296 #
 297 choice
 298         prompt "ARM system type"
 299         default ARCH_VERSATILE if !MMU
 300         default ARCH_MULTIPLATFORM if MMU
 301
 302 config ARCH_MULTIPLATFORM
 303         bool "Allow multiple platforms to be selected"
 304         depends on MMU
 305         select ARM_PATCH_PHYS_VIRT
 306         select AUTO_ZRELADDR
 307         select COMMON_CLK
 308         select MULTI_IRQ_HANDLER
 309         select SPARSE_IRQ
 310         select USE_OF
 311
 312 config ARCH_INTEGRATOR
 313         bool "ARM Ltd. Integrator family"
 314         select ARCH_HAS_CPUFREQ
 315         select ARM_AMBA
 316         select COMMON_CLK
 317         select COMMON_CLK_VERSATILE
 318         select GENERIC_CLOCKEVENTS
 319         select HAVE_TCM
 320         select ICST
 321         select MULTI_IRQ_HANDLER
 322         select NEED_MACH_MEMORY_H
 323         select PLAT_VERSATILE
 324         select SPARSE_IRQ
 325         select USE_OF
 326         select VERSATILE_FPGA_IRQ
 327         help
 328           Support for ARM's Integrator platform.
 329
 330 config ARCH_REALVIEW
 331         bool "ARM Ltd. RealView family"
 332         select ARCH_WANT_OPTIONAL_GPIOLIB
 333         select ARM_AMBA
 334         select ARM_TIMER_SP804
 335         select COMMON_CLK
 336         select COMMON_CLK_VERSATILE
 337         select GENERIC_CLOCKEVENTS
 338         select GPIO_PL061 if GPIOLIB
 339         select ICST
 340         select NEED_MACH_MEMORY_H
 341         select PLAT_VERSATILE
 342         select PLAT_VERSATILE_CLCD
 343         help
 344           This enables support for ARM Ltd RealView boards.
 345
 346 config ARCH_VERSATILE
 347         bool "ARM Ltd. Versatile family"
 348         select ARCH_WANT_OPTIONAL_GPIOLIB
 349         select ARM_AMBA
 350         select ARM_TIMER_SP804
 351         select ARM_VIC
 352         select CLKDEV_LOOKUP
 353         select GENERIC_CLOCKEVENTS
 354         select HAVE_MACH_CLKDEV
 355         select ICST
 356         select PLAT_VERSATILE
 357         select PLAT_VERSATILE_CLCD
 358         select PLAT_VERSATILE_CLOCK
 359         select VERSATILE_FPGA_IRQ
 360         help
 361           This enables support for ARM Ltd Versatile board.
 362
 363 config ARCH_AT91
 364         bool "Atmel AT91"
 365         select ARCH_REQUIRE_GPIOLIB
 366         select CLKDEV_LOOKUP
 367         select IRQ_DOMAIN
 368         select NEED_MACH_GPIO_H
 369         select NEED_MACH_IO_H if PCCARD
 370         select PINCTRL
 371         select PINCTRL_AT91 if USE_OF
 372         help
 373           This enables support for systems based on Atmel
 374           AT91RM9200 and AT91SAM9* processors.
 375
 376 config ARCH_CLPS711X
 377         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 378         select ARCH_REQUIRE_GPIOLIB
 379         select AUTO_ZRELADDR
 380         select CLKSRC_MMIO
 381         select COMMON_CLK
 382         select CPU_ARM720T
 383         select GENERIC_CLOCKEVENTS
 384         select MFD_SYSCON
 385         select MULTI_IRQ_HANDLER
 386         select SPARSE_IRQ
 387         help
 388           Support for Cirrus Logic 711x/721x/731x based boards.
 389
 390 config ARCH_GEMINI
 391         bool "Cortina Systems Gemini"
 392         select ARCH_REQUIRE_GPIOLIB
 393         select CLKSRC_MMIO
 394         select CPU_FA526
 395         select GENERIC_CLOCKEVENTS
 396         help
 397           Support for the Cortina Systems Gemini family SoCs
 398
 399 config ARCH_EBSA110
 400         bool "EBSA-110"
 401         select ARCH_USES_GETTIMEOFFSET
 402         select CPU_SA110
 403         select ISA
 404         select NEED_MACH_IO_H
 405         select NEED_MACH_MEMORY_H
 406         select NO_IOPORT
 407         help
 408           This is an evaluation board for the StrongARM processor available
 409           from Digital. It has limited hardware on-board, including an
 410           Ethernet interface, two PCMCIA sockets, two serial ports and a
 411           parallel port.
 412
 413 config ARCH_EP93XX
 414         bool "EP93xx-based"
 415         select ARCH_HAS_HOLES_MEMORYMODEL
 416         select ARCH_REQUIRE_GPIOLIB
 417         select ARCH_USES_GETTIMEOFFSET
 418         select ARM_AMBA
 419         select ARM_VIC
 420         select CLKDEV_LOOKUP
 421         select CPU_ARM920T
 422         select NEED_MACH_MEMORY_H
 423         help
 424           This enables support for the Cirrus EP93xx series of CPUs.
 425
 426 config ARCH_FOOTBRIDGE
 427         bool "FootBridge"
 428         select CPU_SA110
 429         select FOOTBRIDGE
 430         select GENERIC_CLOCKEVENTS
 431         select HAVE_IDE
 432         select NEED_MACH_IO_H if !MMU
 433         select NEED_MACH_MEMORY_H
 434         help
 435           Support for systems based on the DC21285 companion chip
 436           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 437
 438 config ARCH_NETX
 439         bool "Hilscher NetX based"
 440         select ARM_VIC
 441         select CLKSRC_MMIO
 442         select CPU_ARM926T
 443         select GENERIC_CLOCKEVENTS
 444         help
 445           This enables support for systems based on the Hilscher NetX Soc
 446
 447 config ARCH_IOP13XX
 448         bool "IOP13xx-based"
 449         depends on MMU
 450         select CPU_XSC3
 451         select NEED_MACH_MEMORY_H
 452         select NEED_RET_TO_USER
 453         select PCI
 454         select PLAT_IOP
 455         select VMSPLIT_1G
 456         help
 457           Support for Intel's IOP13XX (XScale) family of processors.
 458
 459 config ARCH_IOP32X
 460         bool "IOP32x-based"
 461         depends on MMU
 462         select ARCH_REQUIRE_GPIOLIB
 463         select CPU_XSCALE
 464         select GPIO_IOP
 465         select NEED_RET_TO_USER
 466         select PCI
 467         select PLAT_IOP
 468         help
 469           Support for Intel's 80219 and IOP32X (XScale) family of
 470           processors.
 471
 472 config ARCH_IOP33X
 473         bool "IOP33x-based"
 474         depends on MMU
 475         select ARCH_REQUIRE_GPIOLIB
 476         select CPU_XSCALE
 477         select GPIO_IOP
 478         select NEED_RET_TO_USER
 479         select PCI
 480         select PLAT_IOP
 481         help
 482           Support for Intel's IOP33X (XScale) family of processors.
 483
 484 config ARCH_IXP4XX
 485         bool "IXP4xx-based"
 486         depends on MMU
 487         select ARCH_HAS_DMA_SET_COHERENT_MASK
 488         select ARCH_SUPPORTS_BIG_ENDIAN
 489         select ARCH_REQUIRE_GPIOLIB
 490         select CLKSRC_MMIO
 491         select CPU_XSCALE
 492         select DMABOUNCE if PCI
 493         select GENERIC_CLOCKEVENTS
 494         select MIGHT_HAVE_PCI
 495         select NEED_MACH_IO_H
 496         select USB_EHCI_BIG_ENDIAN_DESC
 497         select USB_EHCI_BIG_ENDIAN_MMIO
 498         help
 499           Support for Intel's IXP4XX (XScale) family of processors.
 500
 501 config ARCH_DOVE
 502         bool "Marvell Dove"
 503         select ARCH_REQUIRE_GPIOLIB
 504         select CPU_PJ4
 505         select GENERIC_CLOCKEVENTS
 506         select MIGHT_HAVE_PCI
 507         select MVEBU_MBUS
 508         select PINCTRL
 509         select PINCTRL_DOVE
 510         select PLAT_ORION_LEGACY
 511         select USB_ARCH_HAS_EHCI
 512         help
 513           Support for the Marvell Dove SoC 88AP510
 514
 515 config ARCH_KIRKWOOD
 516         bool "Marvell Kirkwood"
 517         select ARCH_HAS_CPUFREQ
 518         select ARCH_REQUIRE_GPIOLIB
 519         select CPU_FEROCEON
 520         select GENERIC_CLOCKEVENTS
 521         select MVEBU_MBUS
 522         select PCI
 523         select PCI_QUIRKS
 524         select PINCTRL
 525         select PINCTRL_KIRKWOOD
 526         select PLAT_ORION_LEGACY
 527         help
 528           Support for the following Marvell Kirkwood series SoCs:
 529           88F6180, 88F6192 and 88F6281.
 530
 531 config ARCH_MV78XX0
 532         bool "Marvell MV78xx0"
 533         select ARCH_REQUIRE_GPIOLIB
 534         select CPU_FEROCEON
 535         select GENERIC_CLOCKEVENTS
 536         select MVEBU_MBUS
 537         select PCI
 538         select PLAT_ORION_LEGACY
 539         help
 540           Support for the following Marvell MV78xx0 series SoCs:
 541           MV781x0, MV782x0.
 542
 543 config ARCH_ORION5X
 544         bool "Marvell Orion"
 545         depends on MMU
 546         select ARCH_REQUIRE_GPIOLIB
 547         select CPU_FEROCEON
 548         select GENERIC_CLOCKEVENTS
 549         select MVEBU_MBUS
 550         select PCI
 551         select PLAT_ORION_LEGACY
 552         help
 553           Support for the following Marvell Orion 5x series SoCs:
 554           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 555           Orion-2 (5281), Orion-1-90 (6183).
 556
 557 config ARCH_MMP
 558         bool "Marvell PXA168/910/MMP2"
 559         depends on MMU
 560         select ARCH_REQUIRE_GPIOLIB
 561         select CLKDEV_LOOKUP
 562         select GENERIC_ALLOCATOR
 563         select GENERIC_CLOCKEVENTS
 564         select GPIO_PXA
 565         select IRQ_DOMAIN
 566         select MULTI_IRQ_HANDLER
 567         select PINCTRL
 568         select PLAT_PXA
 569         select SPARSE_IRQ
 570         help
 571           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 572
 573 config ARCH_KS8695
 574         bool "Micrel/Kendin KS8695"
 575         select ARCH_REQUIRE_GPIOLIB
 576         select CLKSRC_MMIO
 577         select CPU_ARM922T
 578         select GENERIC_CLOCKEVENTS
 579         select NEED_MACH_MEMORY_H
 580         help
 581           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 582           System-on-Chip devices.
 583
 584 config ARCH_W90X900
 585         bool "Nuvoton W90X900 CPU"
 586         select ARCH_REQUIRE_GPIOLIB
 587         select CLKDEV_LOOKUP
 588         select CLKSRC_MMIO
 589         select CPU_ARM926T
 590         select GENERIC_CLOCKEVENTS
 591         help
 592           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 593           At present, the w90x900 has been renamed nuc900, regarding
 594           the ARM series product line, you can login the following
 595           link address to know more.
 596
 597           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 598                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 599
 600 config ARCH_LPC32XX
 601         bool "NXP LPC32XX"
 602         select ARCH_REQUIRE_GPIOLIB
 603         select ARM_AMBA
 604         select CLKDEV_LOOKUP
 605         select CLKSRC_MMIO
 606         select CPU_ARM926T
 607         select GENERIC_CLOCKEVENTS
 608         select HAVE_IDE
 609         select HAVE_PWM
 610         select USB_ARCH_HAS_OHCI
 611         select USE_OF
 612         help
 613           Support for the NXP LPC32XX family of processors
 614
 615 config ARCH_PXA
 616         bool "PXA2xx/PXA3xx-based"
 617         depends on MMU
 618         select ARCH_HAS_CPUFREQ
 619         select ARCH_MTD_XIP
 620         select ARCH_REQUIRE_GPIOLIB
 621         select ARM_CPU_SUSPEND if PM
 622         select AUTO_ZRELADDR
 623         select CLKDEV_LOOKUP
 624         select CLKSRC_MMIO
 625         select GENERIC_CLOCKEVENTS
 626         select GPIO_PXA
 627         select HAVE_IDE
 628         select MULTI_IRQ_HANDLER
 629         select PLAT_PXA
 630         select SPARSE_IRQ
 631         help
 632           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 633
 634 config ARCH_MSM
 635         bool "Qualcomm MSM"
 636         select ARCH_REQUIRE_GPIOLIB
 637         select CLKSRC_OF if OF
 638         select COMMON_CLK
 639         select GENERIC_CLOCKEVENTS
 640         help
 641           Support for Qualcomm MSM/QSD based systems.  This runs on the
 642           apps processor of the MSM/QSD and depends on a shared memory
 643           interface to the modem processor which runs the baseband
 644           stack and controls some vital subsystems
 645           (clock and power control, etc).
 646
 647 config ARCH_SHMOBILE
 648         bool "Renesas SH-Mobile / R-Mobile"
 649         select ARM_PATCH_PHYS_VIRT
 650         select CLKDEV_LOOKUP
 651         select GENERIC_CLOCKEVENTS
 652         select HAVE_ARM_SCU if SMP
 653         select HAVE_ARM_TWD if SMP
 654         select HAVE_MACH_CLKDEV
 655         select HAVE_SMP
 656         select MIGHT_HAVE_CACHE_L2X0
 657         select MULTI_IRQ_HANDLER
 658         select NO_IOPORT
 659         select PINCTRL
 660         select PM_GENERIC_DOMAINS if PM
 661         select SPARSE_IRQ
 662         help
 663           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 664
 665 config ARCH_RPC
 666         bool "RiscPC"
 667         select ARCH_ACORN
 668         select ARCH_MAY_HAVE_PC_FDC
 669         select ARCH_SPARSEMEM_ENABLE
 670         select ARCH_USES_GETTIMEOFFSET
 671         select FIQ
 672         select HAVE_IDE
 673         select HAVE_PATA_PLATFORM
 674         select ISA_DMA_API
 675         select NEED_MACH_IO_H
 676         select NEED_MACH_MEMORY_H
 677         select NO_IOPORT
 678         select VIRT_TO_BUS
 679         help
 680           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 681           CD-ROM interface, serial and parallel port, and the floppy drive.
 682
 683 config ARCH_SA1100
 684         bool "SA1100-based"
 685         select ARCH_HAS_CPUFREQ
 686         select ARCH_MTD_XIP
 687         select ARCH_REQUIRE_GPIOLIB
 688         select ARCH_SPARSEMEM_ENABLE
 689         select CLKDEV_LOOKUP
 690         select CLKSRC_MMIO
 691         select CPU_FREQ
 692         select CPU_SA1100
 693         select GENERIC_CLOCKEVENTS
 694         select HAVE_IDE
 695         select ISA
 696         select NEED_MACH_MEMORY_H
 697         select SPARSE_IRQ
 698         help
 699           Support for StrongARM 11x0 based boards.
 700
 701 config ARCH_S3C24XX
 702         bool "Samsung S3C24XX SoCs"
 703         select ARCH_HAS_CPUFREQ
 704         select ARCH_REQUIRE_GPIOLIB
 705         select CLKDEV_LOOKUP
 706         select CLKSRC_SAMSUNG_PWM
 707         select GENERIC_CLOCKEVENTS
 708         select GPIO_SAMSUNG
 709         select HAVE_S3C2410_I2C if I2C
 710         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 711         select HAVE_S3C_RTC if RTC_CLASS
 712         select MULTI_IRQ_HANDLER
 713         select NEED_MACH_GPIO_H
 714         select NEED_MACH_IO_H
 715         select SAMSUNG_ATAGS
 716         help
 717           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 718           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 719           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 720           Samsung SMDK2410 development board (and derivatives).
 721
 722 config ARCH_S3C64XX
 723         bool "Samsung S3C64XX"
 724         select ARCH_HAS_CPUFREQ
 725         select ARCH_REQUIRE_GPIOLIB
 726         select ARM_VIC
 727         select CLKDEV_LOOKUP
 728         select CLKSRC_SAMSUNG_PWM
 729         select COMMON_CLK
 730         select CPU_V6
 731         select GENERIC_CLOCKEVENTS
 732         select GPIO_SAMSUNG
 733         select HAVE_S3C2410_I2C if I2C
 734         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 735         select HAVE_TCM
 736         select NEED_MACH_GPIO_H
 737         select NO_IOPORT
 738         select PLAT_SAMSUNG
 739         select PM_GENERIC_DOMAINS
 740         select S3C_DEV_NAND
 741         select S3C_GPIO_TRACK
 742         select SAMSUNG_ATAGS
 743         select SAMSUNG_GPIOLIB_4BIT
 744         select SAMSUNG_WAKEMASK
 745         select SAMSUNG_WDT_RESET
 746         select USB_ARCH_HAS_OHCI
 747         help
 748           Samsung S3C64XX series based systems
 749
 750 config ARCH_S5P64X0
 751         bool "Samsung S5P6440 S5P6450"
 752         select CLKDEV_LOOKUP
 753         select CLKSRC_SAMSUNG_PWM
 754         select CPU_V6
 755         select GENERIC_CLOCKEVENTS
 756         select GPIO_SAMSUNG
 757         select HAVE_S3C2410_I2C if I2C
 758         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 759         select HAVE_S3C_RTC if RTC_CLASS
 760         select NEED_MACH_GPIO_H
 761         select SAMSUNG_ATAGS
 762         select SAMSUNG_WDT_RESET
 763         help
 764           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 765           SMDK6450.
 766
 767 config ARCH_S5PC100
 768         bool "Samsung S5PC100"
 769         select ARCH_REQUIRE_GPIOLIB
 770         select CLKDEV_LOOKUP
 771         select CLKSRC_SAMSUNG_PWM
 772         select CPU_V7
 773         select GENERIC_CLOCKEVENTS
 774         select GPIO_SAMSUNG
 775         select HAVE_S3C2410_I2C if I2C
 776         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 777         select HAVE_S3C_RTC if RTC_CLASS
 778         select NEED_MACH_GPIO_H
 779         select SAMSUNG_ATAGS
 780         select SAMSUNG_WDT_RESET
 781         help
 782           Samsung S5PC100 series based systems
 783
 784 config ARCH_S5PV210
 785         bool "Samsung S5PV210/S5PC110"
 786         select ARCH_HAS_CPUFREQ
 787         select ARCH_HAS_HOLES_MEMORYMODEL
 788         select ARCH_SPARSEMEM_ENABLE
 789         select CLKDEV_LOOKUP
 790         select CLKSRC_SAMSUNG_PWM
 791         select CPU_V7
 792         select GENERIC_CLOCKEVENTS
 793         select GPIO_SAMSUNG
 794         select HAVE_S3C2410_I2C if I2C
 795         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 796         select HAVE_S3C_RTC if RTC_CLASS
 797         select NEED_MACH_GPIO_H
 798         select NEED_MACH_MEMORY_H
 799         select SAMSUNG_ATAGS
 800         help
 801           Samsung S5PV210/S5PC110 series based systems
 802
 803 config ARCH_EXYNOS
 804         bool "Samsung EXYNOS"
 805         select ARCH_HAS_CPUFREQ
 806         select ARCH_HAS_HOLES_MEMORYMODEL
 807         select ARCH_REQUIRE_GPIOLIB
 808         select ARCH_SPARSEMEM_ENABLE
 809         select ARM_GIC
 810         select COMMON_CLK
 811         select CPU_V7
 812         select GENERIC_CLOCKEVENTS
 813         select HAVE_S3C2410_I2C if I2C
 814         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 815         select HAVE_S3C_RTC if RTC_CLASS
 816         select NEED_MACH_MEMORY_H
 817         select SPARSE_IRQ
 818         select USE_OF
 819         help
 820           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 821
 822 config ARCH_DAVINCI
 823         bool "TI DaVinci"
 824         select ARCH_HAS_HOLES_MEMORYMODEL
 825         select ARCH_REQUIRE_GPIOLIB
 826         select CLKDEV_LOOKUP
 827         select GENERIC_ALLOCATOR
 828         select GENERIC_CLOCKEVENTS
 829         select GENERIC_IRQ_CHIP
 830         select HAVE_IDE
 831         select TI_PRIV_EDMA
 832         select USE_OF
 833         select ZONE_DMA
 834         help
 835           Support for TI's DaVinci platform.
 836
 837 config ARCH_OMAP1
 838         bool "TI OMAP1"
 839         depends on MMU
 840         select ARCH_HAS_CPUFREQ
 841         select ARCH_HAS_HOLES_MEMORYMODEL
 842         select ARCH_OMAP
 843         select ARCH_REQUIRE_GPIOLIB
 844         select CLKDEV_LOOKUP
 845         select CLKSRC_MMIO
 846         select GENERIC_CLOCKEVENTS
 847         select GENERIC_IRQ_CHIP
 848         select HAVE_IDE
 849         select IRQ_DOMAIN
 850         select NEED_MACH_IO_H if PCCARD
 851         select NEED_MACH_MEMORY_H
 852         help
 853           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 854
 855 endchoice
 856
 857 menu "Multiple platform selection"
 858         depends on ARCH_MULTIPLATFORM
 859
 860 comment "CPU Core family selection"
 861
 862 config ARCH_MULTI_V4T
 863         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 864         depends on !ARCH_MULTI_V6_V7
 865         select ARCH_MULTI_V4_V5
 866         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 867                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 868                 CPU_ARM925T || CPU_ARM940T)
 869
 870 config ARCH_MULTI_V5
 871         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 872         depends on !ARCH_MULTI_V6_V7
 873         select ARCH_MULTI_V4_V5
 874         select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
 875                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 876                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 877
 878 config ARCH_MULTI_V4_V5
 879         bool
 880
 881 config ARCH_MULTI_V6
 882         bool "ARMv6 based platforms (ARM11)"
 883         select ARCH_MULTI_V6_V7
 884         select CPU_V6
 885
 886 config ARCH_MULTI_V7
 887         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 888         default y
 889         select ARCH_MULTI_V6_V7
 890         select CPU_V7
 891
 892 config ARCH_MULTI_V6_V7
 893         bool
 894
 895 config ARCH_MULTI_CPU_AUTO
 896         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 897         select ARCH_MULTI_V5
 898
 899 endmenu
 900
 901 #
 902 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 903 # Kconfigs may be included either alphabetically (according to the
 904 # plat- suffix) or along side the corresponding mach-* source.
 905 #
 906 source "arch/arm/mach-mvebu/Kconfig"
 907
 908 source "arch/arm/mach-at91/Kconfig"
 909
 910 source "arch/arm/mach-bcm/Kconfig"
 911
 912 source "arch/arm/mach-bcm2835/Kconfig"
 913
 914 source "arch/arm/mach-clps711x/Kconfig"
 915
 916 source "arch/arm/mach-cns3xxx/Kconfig"
 917
 918 source "arch/arm/mach-davinci/Kconfig"
 919
 920 source "arch/arm/mach-dove/Kconfig"
 921
 922 source "arch/arm/mach-ep93xx/Kconfig"
 923
 924 source "arch/arm/mach-footbridge/Kconfig"
 925
 926 source "arch/arm/mach-gemini/Kconfig"
 927
 928 source "arch/arm/mach-highbank/Kconfig"
 929
 930 source "arch/arm/mach-integrator/Kconfig"
 931
 932 source "arch/arm/mach-iop32x/Kconfig"
 933
 934 source "arch/arm/mach-iop33x/Kconfig"
 935
 936 source "arch/arm/mach-iop13xx/Kconfig"
 937
 938 source "arch/arm/mach-ixp4xx/Kconfig"
 939
 940 source "arch/arm/mach-keystone/Kconfig"
 941
 942 source "arch/arm/mach-kirkwood/Kconfig"
 943
 944 source "arch/arm/mach-ks8695/Kconfig"
 945
 946 source "arch/arm/mach-msm/Kconfig"
 947
 948 source "arch/arm/mach-mv78xx0/Kconfig"
 949
 950 source "arch/arm/mach-imx/Kconfig"
 951
 952 source "arch/arm/mach-mxs/Kconfig"
 953
 954 source "arch/arm/mach-netx/Kconfig"
 955
 956 source "arch/arm/mach-nomadik/Kconfig"
 957
 958 source "arch/arm/mach-nspire/Kconfig"
 959
 960 source "arch/arm/plat-omap/Kconfig"
 961
 962 source "arch/arm/mach-omap1/Kconfig"
 963
 964 source "arch/arm/mach-omap2/Kconfig"
 965
 966 source "arch/arm/mach-orion5x/Kconfig"
 967
 968 source "arch/arm/mach-picoxcell/Kconfig"
 969
 970 source "arch/arm/mach-pxa/Kconfig"
 971 source "arch/arm/plat-pxa/Kconfig"
 972
 973 source "arch/arm/mach-mmp/Kconfig"
 974
 975 source "arch/arm/mach-realview/Kconfig"
 976
 977 source "arch/arm/mach-rockchip/Kconfig"
 978
 979 source "arch/arm/mach-sa1100/Kconfig"
 980
 981 source "arch/arm/plat-samsung/Kconfig"
 982
 983 source "arch/arm/mach-socfpga/Kconfig"
 984
 985 source "arch/arm/mach-spear/Kconfig"
 986
 987 source "arch/arm/mach-sti/Kconfig"
 988
 989 source "arch/arm/mach-s3c24xx/Kconfig"
 990
 991 source "arch/arm/mach-s3c64xx/Kconfig"
 992
 993 source "arch/arm/mach-s5p64x0/Kconfig"
 994
 995 source "arch/arm/mach-s5pc100/Kconfig"
 996
 997 source "arch/arm/mach-s5pv210/Kconfig"
 998
 999 source "arch/arm/mach-exynos/Kconfig"
1000
1001 source "arch/arm/mach-shmobile/Kconfig"
1002
1003 source "arch/arm/mach-sunxi/Kconfig"
1004
1005 source "arch/arm/mach-prima2/Kconfig"
1006
1007 source "arch/arm/mach-tegra/Kconfig"
1008
1009 source "arch/arm/mach-u300/Kconfig"
1010
1011 source "arch/arm/mach-ux500/Kconfig"
1012
1013 source "arch/arm/mach-versatile/Kconfig"
1014
1015 source "arch/arm/mach-vexpress/Kconfig"
1016 source "arch/arm/plat-versatile/Kconfig"
1017
1018 source "arch/arm/mach-virt/Kconfig"
1019
1020 source "arch/arm/mach-vt8500/Kconfig"
1021
1022 source "arch/arm/mach-w90x900/Kconfig"
1023
1024 source "arch/arm/mach-zynq/Kconfig"
1025
1026 # Definitions to make life easier
1027 config ARCH_ACORN
1028         bool
1029
1030 config PLAT_IOP
1031         bool
1032         select GENERIC_CLOCKEVENTS
1033
1034 config PLAT_ORION
1035         bool
1036         select CLKSRC_MMIO
1037         select COMMON_CLK
1038         select GENERIC_IRQ_CHIP
1039         select IRQ_DOMAIN
1040
1041 config PLAT_ORION_LEGACY
1042         bool
1043         select PLAT_ORION
1044
1045 config PLAT_PXA
1046         bool
1047
1048 config PLAT_VERSATILE
1049         bool
1050
1051 config ARM_TIMER_SP804
1052         bool
1053         select CLKSRC_MMIO
1054         select CLKSRC_OF if OF
1055
1056 source arch/arm/mm/Kconfig
1057
1058 config ARM_NR_BANKS
1059         int
1060         default 16 if ARCH_EP93XX
1061         default 8
1062
1063 config IWMMXT
1064         bool "Enable iWMMXt support" if !CPU_PJ4
1065         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1066         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1067         help
1068           Enable support for iWMMXt context switching at run time if
1069           running on a CPU that supports it.
1070
1071 config MULTI_IRQ_HANDLER
1072         bool
1073         help
1074           Allow each machine to specify it's own IRQ handler at run time.
1075
1076 if !MMU
1077 source "arch/arm/Kconfig-nommu"
1078 endif
1079
1080 config PJ4B_ERRATA_4742
1081         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1082         depends on CPU_PJ4B && MACH_ARMADA_370
1083         default y
1084         help
1085           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1086           Event (WFE) IDLE states, a specific timing sensitivity exists between
1087           the retiring WFI/WFE instructions and the newly issued subsequent
1088           instructions.  This sensitivity can result in a CPU hang scenario.
1089           Workaround:
1090           The software must insert either a Data Synchronization Barrier (DSB)
1091           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1092           instruction
1093
1094 config ARM_ERRATA_326103
1095         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1096         depends on CPU_V6
1097         help
1098           Executing a SWP instruction to read-only memory does not set bit 11
1099           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1100           treat the access as a read, preventing a COW from occurring and
1101           causing the faulting task to livelock.
1102
1103 config ARM_ERRATA_411920
1104         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1105         depends on CPU_V6 || CPU_V6K
1106         help
1107           Invalidation of the Instruction Cache operation can
1108           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1109           It does not affect the MPCore. This option enables the ARM Ltd.
1110           recommended workaround.
1111
1112 config ARM_ERRATA_430973
1113         bool "ARM errata: Stale prediction on replaced interworking branch"
1114         depends on CPU_V7
1115         help
1116           This option enables the workaround for the 430973 Cortex-A8
1117           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1118           interworking branch is replaced with another code sequence at the
1119           same virtual address, whether due to self-modifying code or virtual
1120           to physical address re-mapping, Cortex-A8 does not recover from the
1121           stale interworking branch prediction. This results in Cortex-A8
1122           executing the new code sequence in the incorrect ARM or Thumb state.
1123           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1124           and also flushes the branch target cache at every context switch.
1125           Note that setting specific bits in the ACTLR register may not be
1126           available in non-secure mode.
1127
1128 config ARM_ERRATA_458693
1129         bool "ARM errata: Processor deadlock when a false hazard is created"
1130         depends on CPU_V7
1131         depends on !ARCH_MULTIPLATFORM
1132         help
1133           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1134           erratum. For very specific sequences of memory operations, it is
1135           possible for a hazard condition intended for a cache line to instead
1136           be incorrectly associated with a different cache line. This false
1137           hazard might then cause a processor deadlock. The workaround enables
1138           the L1 caching of the NEON accesses and disables the PLD instruction
1139           in the ACTLR register. Note that setting specific bits in the ACTLR
1140           register may not be available in non-secure mode.
1141
1142 config ARM_ERRATA_460075
1143         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1144         depends on CPU_V7
1145         depends on !ARCH_MULTIPLATFORM
1146         help
1147           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1148           erratum. Any asynchronous access to the L2 cache may encounter a
1149           situation in which recent store transactions to the L2 cache are lost
1150           and overwritten with stale memory contents from external memory. The
1151           workaround disables the write-allocate mode for the L2 cache via the
1152           ACTLR register. Note that setting specific bits in the ACTLR register
1153           may not be available in non-secure mode.
1154
1155 config ARM_ERRATA_742230
1156         bool "ARM errata: DMB operation may be faulty"
1157         depends on CPU_V7 && SMP
1158         depends on !ARCH_MULTIPLATFORM
1159         help
1160           This option enables the workaround for the 742230 Cortex-A9
1161           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1162           between two write operations may not ensure the correct visibility
1163           ordering of the two writes. This workaround sets a specific bit in
1164           the diagnostic register of the Cortex-A9 which causes the DMB
1165           instruction to behave as a DSB, ensuring the correct behaviour of
1166           the two writes.
1167
1168 config ARM_ERRATA_742231
1169         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1170         depends on CPU_V7 && SMP
1171         depends on !ARCH_MULTIPLATFORM
1172         help
1173           This option enables the workaround for the 742231 Cortex-A9
1174           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1175           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1176           accessing some data located in the same cache line, may get corrupted
1177           data due to bad handling of the address hazard when the line gets
1178           replaced from one of the CPUs at the same time as another CPU is
1179           accessing it. This workaround sets specific bits in the diagnostic
1180           register of the Cortex-A9 which reduces the linefill issuing
1181           capabilities of the processor.
1182
1183 config PL310_ERRATA_588369
1184         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1185         depends on CACHE_L2X0
1186         help
1187            The PL310 L2 cache controller implements three types of Clean &
1188            Invalidate maintenance operations: by Physical Address
1189            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1190            They are architecturally defined to behave as the execution of a
1191            clean operation followed immediately by an invalidate operation,
1192            both performing to the same memory location. This functionality
1193            is not correctly implemented in PL310 as clean lines are not
1194            invalidated as a result of these operations.
1195
1196 config ARM_ERRATA_643719
1197         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1198         depends on CPU_V7 && SMP
1199         help
1200           This option enables the workaround for the 643719 Cortex-A9 (prior to
1201           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1202           register returns zero when it should return one. The workaround
1203           corrects this value, ensuring cache maintenance operations which use
1204           it behave as intended and avoiding data corruption.
1205
1206 config ARM_ERRATA_720789
1207         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1208         depends on CPU_V7
1209         help
1210           This option enables the workaround for the 720789 Cortex-A9 (prior to
1211           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1212           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1213           As a consequence of this erratum, some TLB entries which should be
1214           invalidated are not, resulting in an incoherency in the system page
1215           tables. The workaround changes the TLB flushing routines to invalidate
1216           entries regardless of the ASID.
1217
1218 config PL310_ERRATA_727915
1219         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1220         depends on CACHE_L2X0
1221         help
1222           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1223           operation (offset 0x7FC). This operation runs in background so that
1224           PL310 can handle normal accesses while it is in progress. Under very
1225           rare circumstances, due to this erratum, write data can be lost when
1226           PL310 treats a cacheable write transaction during a Clean &
1227           Invalidate by Way operation.
1228
1229 config ARM_ERRATA_743622
1230         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1231         depends on CPU_V7
1232         depends on !ARCH_MULTIPLATFORM
1233         help
1234           This option enables the workaround for the 743622 Cortex-A9
1235           (r2p*) erratum. Under very rare conditions, a faulty
1236           optimisation in the Cortex-A9 Store Buffer may lead to data
1237           corruption. This workaround sets a specific bit in the diagnostic
1238           register of the Cortex-A9 which disables the Store Buffer
1239           optimisation, preventing the defect from occurring. This has no
1240           visible impact on the overall performance or power consumption of the
1241           processor.
1242
1243 config ARM_ERRATA_751472
1244         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1245         depends on CPU_V7
1246         depends on !ARCH_MULTIPLATFORM
1247         help
1248           This option enables the workaround for the 751472 Cortex-A9 (prior
1249           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1250           completion of a following broadcasted operation if the second
1251           operation is received by a CPU before the ICIALLUIS has completed,
1252           potentially leading to corrupted entries in the cache or TLB.
1253
1254 config PL310_ERRATA_753970
1255         bool "PL310 errata: cache sync operation may be faulty"
1256         depends on CACHE_PL310
1257         help
1258           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1259
1260           Under some condition the effect of cache sync operation on
1261           the store buffer still remains when the operation completes.
1262           This means that the store buffer is always asked to drain and
1263           this prevents it from merging any further writes. The workaround
1264           is to replace the normal offset of cache sync operation (0x730)
1265           by another offset targeting an unmapped PL310 register 0x740.
1266           This has the same effect as the cache sync operation: store buffer
1267           drain and waiting for all buffers empty.
1268
1269 config ARM_ERRATA_754322
1270         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1271         depends on CPU_V7
1272         help
1273           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1274           r3p*) erratum. A speculative memory access may cause a page table walk
1275           which starts prior to an ASID switch but completes afterwards. This
1276           can populate the micro-TLB with a stale entry which may be hit with
1277           the new ASID. This workaround places two dsb instructions in the mm
1278           switching code so that no page table walks can cross the ASID switch.
1279
1280 config ARM_ERRATA_754327
1281         bool "ARM errata: no automatic Store Buffer drain"
1282         depends on CPU_V7 && SMP
1283         help
1284           This option enables the workaround for the 754327 Cortex-A9 (prior to
1285           r2p0) erratum. The Store Buffer does not have any automatic draining
1286           mechanism and therefore a livelock may occur if an external agent
1287           continuously polls a memory location waiting to observe an update.
1288           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1289           written polling loops from denying visibility of updates to memory.
1290
1291 config ARM_ERRATA_364296
1292         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1293         depends on CPU_V6
1294         help
1295           This options enables the workaround for the 364296 ARM1136
1296           r0p2 erratum (possible cache data corruption with
1297           hit-under-miss enabled). It sets the undocumented bit 31 in
1298           the auxiliary control register and the FI bit in the control
1299           register, thus disabling hit-under-miss without putting the
1300           processor into full low interrupt latency mode. ARM11MPCore
1301           is not affected.
1302
1303 config ARM_ERRATA_764369
1304         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1305         depends on CPU_V7 && SMP
1306         help
1307           This option enables the workaround for erratum 764369
1308           affecting Cortex-A9 MPCore with two or more processors (all
1309           current revisions). Under certain timing circumstances, a data
1310           cache line maintenance operation by MVA targeting an Inner
1311           Shareable memory region may fail to proceed up to either the
1312           Point of Coherency or to the Point of Unification of the
1313           system. This workaround adds a DSB instruction before the
1314           relevant cache maintenance functions and sets a specific bit
1315           in the diagnostic control register of the SCU.
1316
1317 config PL310_ERRATA_769419
1318         bool "PL310 errata: no automatic Store Buffer drain"
1319         depends on CACHE_L2X0
1320         help
1321           On revisions of the PL310 prior to r3p2, the Store Buffer does
1322           not automatically drain. This can cause normal, non-cacheable
1323           writes to be retained when the memory system is idle, leading
1324           to suboptimal I/O performance for drivers using coherent DMA.
1325           This option adds a write barrier to the cpu_idle loop so that,
1326           on systems with an outer cache, the store buffer is drained
1327           explicitly.
1328
1329 config ARM_ERRATA_775420
1330        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1331        depends on CPU_V7
1332        help
1333          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1334          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1335          operation aborts with MMU exception, it might cause the processor
1336          to deadlock. This workaround puts DSB before executing ISB if
1337          an abort may occur on cache maintenance.
1338
1339 config ARM_ERRATA_798181
1340         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1341         depends on CPU_V7 && SMP
1342         help
1343           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1344           adequately shooting down all use of the old entries. This
1345           option enables the Linux kernel workaround for this erratum
1346           which sends an IPI to the CPUs that are running the same ASID
1347           as the one being invalidated.
1348
1349 config ARM_ERRATA_773022
1350         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1351         depends on CPU_V7
1352         help
1353           This option enables the workaround for the 773022 Cortex-A15
1354           (up to r0p4) erratum. In certain rare sequences of code, the
1355           loop buffer may deliver incorrect instructions. This
1356           workaround disables the loop buffer to avoid the erratum.
1357
1358 endmenu
1359
1360 source "arch/arm/common/Kconfig"
1361
1362 menu "Bus support"
1363
1364 config ARM_AMBA
1365         bool
1366
1367 config ISA
1368         bool
1369         help
1370           Find out whether you have ISA slots on your motherboard.  ISA is the
1371           name of a bus system, i.e. the way the CPU talks to the other stuff
1372           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1373           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1374           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1375
1376 # Select ISA DMA controller support
1377 config ISA_DMA
1378         bool
1379         select ISA_DMA_API
1380
1381 # Select ISA DMA interface
1382 config ISA_DMA_API
1383         bool
1384
1385 config PCI
1386         bool "PCI support" if MIGHT_HAVE_PCI
1387         help
1388           Find out whether you have a PCI motherboard. PCI is the name of a
1389           bus system, i.e. the way the CPU talks to the other stuff inside
1390           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1391           VESA. If you have PCI, say Y, otherwise N.
1392
1393 config PCI_DOMAINS
1394         bool
1395         depends on PCI
1396
1397 config PCI_NANOENGINE
1398         bool "BSE nanoEngine PCI support"
1399         depends on SA1100_NANOENGINE
1400         help
1401           Enable PCI on the BSE nanoEngine board.
1402
1403 config PCI_SYSCALL
1404         def_bool PCI
1405
1406 config PCI_HOST_ITE8152
1407         bool
1408         depends on PCI && MACH_ARMCORE
1409         default y
1410         select DMABOUNCE
1411
1412 source "drivers/pci/Kconfig"
1413 source "drivers/pci/pcie/Kconfig"
1414
1415 source "drivers/pcmcia/Kconfig"
1416
1417 endmenu
1418
1419 menu "Kernel Features"
1420
1421 config HAVE_SMP
1422         bool
1423         help
1424           This option should be selected by machines which have an SMP-
1425           capable CPU.
1426
1427           The only effect of this option is to make the SMP-related
1428           options available to the user for configuration.
1429
1430 config SMP
1431         bool "Symmetric Multi-Processing"
1432         depends on CPU_V6K || CPU_V7
1433         depends on GENERIC_CLOCKEVENTS
1434         depends on HAVE_SMP
1435         depends on MMU || ARM_MPU
1436         help
1437           This enables support for systems with more than one CPU. If you have
1438           a system with only one CPU, like most personal computers, say N. If
1439           you have a system with more than one CPU, say Y.
1440
1441           If you say N here, the kernel will run on single and multiprocessor
1442           machines, but will use only one CPU of a multiprocessor machine. If
1443           you say Y here, the kernel will run on many, but not all, single
1444           processor machines. On a single processor machine, the kernel will
1445           run faster if you say N here.
1446
1447           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1448           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1449           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1450
1451           If you don't know what to do here, say N.
1452
1453 config SMP_ON_UP
1454         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1455         depends on SMP && !XIP_KERNEL && MMU
1456         default y
1457         help
1458           SMP kernels contain instructions which fail on non-SMP processors.
1459           Enabling this option allows the kernel to modify itself to make
1460           these instructions safe.  Disabling it allows about 1K of space
1461           savings.
1462
1463           If you don't know what to do here, say Y.
1464
1465 config ARM_CPU_TOPOLOGY
1466         bool "Support cpu topology definition"
1467         depends on SMP && CPU_V7
1468         default y
1469         help
1470           Support ARM cpu topology definition. The MPIDR register defines
1471           affinity between processors which is then used to describe the cpu
1472           topology of an ARM System.
1473
1474 config SCHED_MC
1475         bool "Multi-core scheduler support"
1476         depends on ARM_CPU_TOPOLOGY
1477         help
1478           Multi-core scheduler support improves the CPU scheduler's decision
1479           making when dealing with multi-core CPU chips at a cost of slightly
1480           increased overhead in some places. If unsure say N here.
1481
1482 config SCHED_SMT
1483         bool "SMT scheduler support"
1484         depends on ARM_CPU_TOPOLOGY
1485         help
1486           Improves the CPU scheduler's decision making when dealing with
1487           MultiThreading at a cost of slightly increased overhead in some
1488           places. If unsure say N here.
1489
1490 config HAVE_ARM_SCU
1491         bool
1492         help
1493           This option enables support for the ARM system coherency unit
1494
1495 config HAVE_ARM_ARCH_TIMER
1496         bool "Architected timer support"
1497         depends on CPU_V7
1498         select ARM_ARCH_TIMER
1499         help
1500           This option enables support for the ARM architected timer
1501
1502 config HAVE_ARM_TWD
1503         bool
1504         depends on SMP
1505         select CLKSRC_OF if OF
1506         help
1507           This options enables support for the ARM timer and watchdog unit
1508
1509 config MCPM
1510         bool "Multi-Cluster Power Management"
1511         depends on CPU_V7 && SMP
1512         help
1513           This option provides the common power management infrastructure
1514           for (multi-)cluster based systems, such as big.LITTLE based
1515           systems.
1516
1517 config BIG_LITTLE
1518         bool "big.LITTLE support (Experimental)"
1519         depends on CPU_V7 && SMP
1520         select MCPM
1521         help
1522           This option enables support selections for the big.LITTLE
1523           system architecture.
1524
1525 config BL_SWITCHER
1526         bool "big.LITTLE switcher support"
1527         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1528         select CPU_PM
1529         select ARM_CPU_SUSPEND
1530         help
1531           The big.LITTLE "switcher" provides the core functionality to
1532           transparently handle transition between a cluster of A15's
1533           and a cluster of A7's in a big.LITTLE system.
1534
1535 config BL_SWITCHER_DUMMY_IF
1536         tristate "Simple big.LITTLE switcher user interface"
1537         depends on BL_SWITCHER && DEBUG_KERNEL
1538         help
1539           This is a simple and dummy char dev interface to control
1540           the big.LITTLE switcher core code.  It is meant for
1541           debugging purposes only.
1542
1543 choice
1544         prompt "Memory split"
1545         default VMSPLIT_3G
1546         help
1547           Select the desired split between kernel and user memory.
1548
1549           If you are not absolutely sure what you are doing, leave this
1550           option alone!
1551
1552         config VMSPLIT_3G
1553                 bool "3G/1G user/kernel split"
1554         config VMSPLIT_2G
1555                 bool "2G/2G user/kernel split"
1556         config VMSPLIT_1G
1557                 bool "1G/3G user/kernel split"
1558 endchoice
1559
1560 config PAGE_OFFSET
1561         hex
1562         default 0x40000000 if VMSPLIT_1G
1563         default 0x80000000 if VMSPLIT_2G
1564         default 0xC0000000
1565
1566 config NR_CPUS
1567         int "Maximum number of CPUs (2-32)"
1568         range 2 32
1569         depends on SMP
1570         default "4"
1571
1572 config HOTPLUG_CPU
1573         bool "Support for hot-pluggable CPUs"
1574         depends on SMP
1575         help
1576           Say Y here to experiment with turning CPUs off and on.  CPUs
1577           can be controlled through /sys/devices/system/cpu.
1578
1579 config ARM_PSCI
1580         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1581         depends on CPU_V7
1582         help
1583           Say Y here if you want Linux to communicate with system firmware
1584           implementing the PSCI specification for CPU-centric power
1585           management operations described in ARM document number ARM DEN
1586           0022A ("Power State Coordination Interface System Software on
1587           ARM processors").
1588
1589 # The GPIO number here must be sorted by descending number. In case of
1590 # a multiplatform kernel, we just want the highest value required by the
1591 # selected platforms.
1592 config ARCH_NR_GPIO
1593         int
1594         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1595         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1596         default 392 if ARCH_U8500
1597         default 352 if ARCH_VT8500
1598         default 288 if ARCH_SUNXI
1599         default 264 if MACH_H4700
1600         default 0
1601         help
1602           Maximum number of GPIOs in the system.
1603
1604           If unsure, leave the default value.
1605
1606 source kernel/Kconfig.preempt
1607
1608 config HZ_FIXED
1609         int
1610         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1611                 ARCH_S5PV210 || ARCH_EXYNOS4
1612         default AT91_TIMER_HZ if ARCH_AT91
1613         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1614         default 0
1615
1616 choice
1617         depends on HZ_FIXED = 0
1618         prompt "Timer frequency"
1619
1620 config HZ_100
1621         bool "100 Hz"
1622
1623 config HZ_200
1624         bool "200 Hz"
1625
1626 config HZ_250
1627         bool "250 Hz"
1628
1629 config HZ_300
1630         bool "300 Hz"
1631
1632 config HZ_500
1633         bool "500 Hz"
1634
1635 config HZ_1000
1636         bool "1000 Hz"
1637
1638 endchoice
1639
1640 config HZ
1641         int
1642         default HZ_FIXED if HZ_FIXED != 0
1643         default 100 if HZ_100
1644         default 200 if HZ_200
1645         default 250 if HZ_250
1646         default 300 if HZ_300
1647         default 500 if HZ_500
1648         default 1000
1649
1650 config SCHED_HRTICK
1651         def_bool HIGH_RES_TIMERS
1652
1653 config SCHED_HRTICK
1654         def_bool HIGH_RES_TIMERS
1655
1656 config THUMB2_KERNEL
1657         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1658         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1659         default y if CPU_THUMBONLY
1660         select AEABI
1661         select ARM_ASM_UNIFIED
1662         select ARM_UNWIND
1663         help
1664           By enabling this option, the kernel will be compiled in
1665           Thumb-2 mode. A compiler/assembler that understand the unified
1666           ARM-Thumb syntax is needed.
1667
1668           If unsure, say N.
1669
1670 config THUMB2_AVOID_R_ARM_THM_JUMP11
1671         bool "Work around buggy Thumb-2 short branch relocations in gas"
1672         depends on THUMB2_KERNEL && MODULES
1673         default y
1674         help
1675           Various binutils versions can resolve Thumb-2 branches to
1676           locally-defined, preemptible global symbols as short-range "b.n"
1677           branch instructions.
1678
1679           This is a problem, because there's no guarantee the final
1680           destination of the symbol, or any candidate locations for a
1681           trampoline, are within range of the branch.  For this reason, the
1682           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1683           relocation in modules at all, and it makes little sense to add
1684           support.
1685
1686           The symptom is that the kernel fails with an "unsupported
1687           relocation" error when loading some modules.
1688
1689           Until fixed tools are available, passing
1690           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1691           code which hits this problem, at the cost of a bit of extra runtime
1692           stack usage in some cases.
1693
1694           The problem is described in more detail at:
1695               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1696
1697           Only Thumb-2 kernels are affected.
1698
1699           Unless you are sure your tools don't have this problem, say Y.
1700
1701 config ARM_ASM_UNIFIED
1702         bool
1703
1704 config AEABI
1705         bool "Use the ARM EABI to compile the kernel"
1706         help
1707           This option allows for the kernel to be compiled using the latest
1708           ARM ABI (aka EABI).  This is only useful if you are using a user
1709           space environment that is also compiled with EABI.
1710
1711           Since there are major incompatibilities between the legacy ABI and
1712           EABI, especially with regard to structure member alignment, this
1713           option also changes the kernel syscall calling convention to
1714           disambiguate both ABIs and allow for backward compatibility support
1715           (selected with CONFIG_OABI_COMPAT).
1716
1717           To use this you need GCC version 4.0.0 or later.
1718
1719 config OABI_COMPAT
1720         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1721         depends on AEABI && !THUMB2_KERNEL
1722         default y
1723         help
1724           This option preserves the old syscall interface along with the
1725           new (ARM EABI) one. It also provides a compatibility layer to
1726           intercept syscalls that have structure arguments which layout
1727           in memory differs between the legacy ABI and the new ARM EABI
1728           (only for non "thumb" binaries). This option adds a tiny
1729           overhead to all syscalls and produces a slightly larger kernel.
1730           If you know you'll be using only pure EABI user space then you
1731           can say N here. If this option is not selected and you attempt
1732           to execute a legacy ABI binary then the result will be
1733           UNPREDICTABLE (in fact it can be predicted that it won't work
1734           at all). If in doubt say Y.
1735
1736 config ARCH_HAS_HOLES_MEMORYMODEL
1737         bool
1738
1739 config ARCH_SPARSEMEM_ENABLE
1740         bool
1741
1742 config ARCH_SPARSEMEM_DEFAULT
1743         def_bool ARCH_SPARSEMEM_ENABLE
1744
1745 config ARCH_SELECT_MEMORY_MODEL
1746         def_bool ARCH_SPARSEMEM_ENABLE
1747
1748 config HAVE_ARCH_PFN_VALID
1749         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1750
1751 config HIGHMEM
1752         bool "High Memory Support"
1753         depends on MMU
1754         help
1755           The address space of ARM processors is only 4 Gigabytes large
1756           and it has to accommodate user address space, kernel address
1757           space as well as some memory mapped IO. That means that, if you
1758           have a large amount of physical memory and/or IO, not all of the
1759           memory can be "permanently mapped" by the kernel. The physical
1760           memory that is not permanently mapped is called "high memory".
1761
1762           Depending on the selected kernel/user memory split, minimum
1763           vmalloc space and actual amount of RAM, you may not need this
1764           option which should result in a slightly faster kernel.
1765
1766           If unsure, say n.
1767
1768 config HIGHPTE
1769         bool "Allocate 2nd-level pagetables from highmem"
1770         depends on HIGHMEM
1771
1772 config HW_PERF_EVENTS
1773         bool "Enable hardware performance counter support for perf events"
1774         depends on PERF_EVENTS
1775         default y
1776         help
1777           Enable hardware performance counter support for perf events. If
1778           disabled, perf events will use software events only.
1779
1780 config SYS_SUPPORTS_HUGETLBFS
1781        def_bool y
1782        depends on ARM_LPAE
1783
1784 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1785        def_bool y
1786        depends on ARM_LPAE
1787
1788 config ARCH_WANT_GENERAL_HUGETLB
1789         def_bool y
1790
1791 source "mm/Kconfig"
1792
1793 config FORCE_MAX_ZONEORDER
1794         int "Maximum zone order" if ARCH_SHMOBILE
1795         range 11 64 if ARCH_SHMOBILE
1796         default "12" if SOC_AM33XX
1797         default "9" if SA1111
1798         default "11"
1799         help
1800           The kernel memory allocator divides physically contiguous memory
1801           blocks into "zones", where each zone is a power of two number of
1802           pages.  This option selects the largest power of two that the kernel
1803           keeps in the memory allocator.  If you need to allocate very large
1804           blocks of physically contiguous memory, then you may need to
1805           increase this value.
1806
1807           This config option is actually maximum order plus one. For example,
1808           a value of 11 means that the largest free memory block is 2^10 pages.
1809
1810 config ALIGNMENT_TRAP
1811         bool
1812         depends on CPU_CP15_MMU
1813         default y if !ARCH_EBSA110
1814         select HAVE_PROC_CPU if PROC_FS
1815         help
1816           ARM processors cannot fetch/store information which is not
1817           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1818           address divisible by 4. On 32-bit ARM processors, these non-aligned
1819           fetch/store instructions will be emulated in software if you say
1820           here, which has a severe performance impact. This is necessary for
1821           correct operation of some network protocols. With an IP-only
1822           configuration it is safe to say N, otherwise say Y.
1823
1824 config UACCESS_WITH_MEMCPY
1825         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1826         depends on MMU
1827         default y if CPU_FEROCEON
1828         help
1829           Implement faster copy_to_user and clear_user methods for CPU
1830           cores where a 8-word STM instruction give significantly higher
1831           memory write throughput than a sequence of individual 32bit stores.
1832
1833           A possible side effect is a slight increase in scheduling latency
1834           between threads sharing the same address space if they invoke
1835           such copy operations with large buffers.
1836
1837           However, if the CPU data cache is using a write-allocate mode,
1838           this option is unlikely to provide any performance gain.
1839
1840 config SECCOMP
1841         bool
1842         prompt "Enable seccomp to safely compute untrusted bytecode"
1843         ---help---
1844           This kernel feature is useful for number crunching applications
1845           that may need to compute untrusted bytecode during their
1846           execution. By using pipes or other transports made available to
1847           the process as file descriptors supporting the read/write
1848           syscalls, it's possible to isolate those applications in
1849           their own address space using seccomp. Once seccomp is
1850           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1851           and the task is only allowed to execute a few safe syscalls
1852           defined by each seccomp mode.
1853
1854 config CC_STACKPROTECTOR
1855         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1856         help
1857           This option turns on the -fstack-protector GCC feature. This
1858           feature puts, at the beginning of functions, a canary value on
1859           the stack just before the return address, and validates
1860           the value just before actually returning.  Stack based buffer
1861           overflows (that need to overwrite this return address) now also
1862           overwrite the canary, which gets detected and the attack is then
1863           neutralized via a kernel panic.
1864           This feature requires gcc version 4.2 or above.
1865
1866 config SWIOTLB
1867         def_bool y
1868
1869 config IOMMU_HELPER
1870         def_bool SWIOTLB
1871
1872 config XEN_DOM0
1873         def_bool y
1874         depends on XEN
1875
1876 config XEN
1877         bool "Xen guest support on ARM (EXPERIMENTAL)"
1878         depends on ARM && AEABI && OF
1879         depends on CPU_V7 && !CPU_V6
1880         depends on !GENERIC_ATOMIC64
1881         select ARM_PSCI
1882         select SWIOTLB_XEN
1883         help
1884           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1885
1886 endmenu
1887
1888 menu "Boot options"
1889
1890 config USE_OF
1891         bool "Flattened Device Tree support"
1892         select IRQ_DOMAIN
1893         select OF
1894         select OF_EARLY_FLATTREE
1895         help
1896           Include support for flattened device tree machine descriptions.
1897
1898 config ATAGS
1899         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1900         default y
1901         help
1902           This is the traditional way of passing data to the kernel at boot
1903           time. If you are solely relying on the flattened device tree (or
1904           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1905           to remove ATAGS support from your kernel binary.  If unsure,
1906           leave this to y.
1907
1908 config DEPRECATED_PARAM_STRUCT
1909         bool "Provide old way to pass kernel parameters"
1910         depends on ATAGS
1911         help
1912           This was deprecated in 2001 and announced to live on for 5 years.
1913           Some old boot loaders still use this way.
1914
1915 # Compressed boot loader in ROM.  Yes, we really want to ask about
1916 # TEXT and BSS so we preserve their values in the config files.
1917 config ZBOOT_ROM_TEXT
1918         hex "Compressed ROM boot loader base address"
1919         default "0"
1920         help
1921           The physical address at which the ROM-able zImage is to be
1922           placed in the target.  Platforms which normally make use of
1923           ROM-able zImage formats normally set this to a suitable
1924           value in their defconfig file.
1925
1926           If ZBOOT_ROM is not enabled, this has no effect.
1927
1928 config ZBOOT_ROM_BSS
1929         hex "Compressed ROM boot loader BSS address"
1930         default "0"
1931         help
1932           The base address of an area of read/write memory in the target
1933           for the ROM-able zImage which must be available while the
1934           decompressor is running. It must be large enough to hold the
1935           entire decompressed kernel plus an additional 128 KiB.
1936           Platforms which normally make use of ROM-able zImage formats
1937           normally set this to a suitable value in their defconfig file.
1938
1939           If ZBOOT_ROM is not enabled, this has no effect.
1940
1941 config ZBOOT_ROM
1942         bool "Compressed boot loader in ROM/flash"
1943         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1944         help
1945           Say Y here if you intend to execute your compressed kernel image
1946           (zImage) directly from ROM or flash.  If unsure, say N.
1947
1948 choice
1949         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1950         depends on ZBOOT_ROM && ARCH_SH7372
1951         default ZBOOT_ROM_NONE
1952         help
1953           Include experimental SD/MMC loading code in the ROM-able zImage.
1954           With this enabled it is possible to write the ROM-able zImage
1955           kernel image to an MMC or SD card and boot the kernel straight
1956           from the reset vector. At reset the processor Mask ROM will load
1957           the first part of the ROM-able zImage which in turn loads the
1958           rest the kernel image to RAM.
1959
1960 config ZBOOT_ROM_NONE
1961         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1962         help
1963           Do not load image from SD or MMC
1964
1965 config ZBOOT_ROM_MMCIF
1966         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1967         help
1968           Load image from MMCIF hardware block.
1969
1970 config ZBOOT_ROM_SH_MOBILE_SDHI
1971         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1972         help
1973           Load image from SDHI hardware block
1974
1975 endchoice
1976
1977 config ARM_APPENDED_DTB
1978         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1979         depends on OF && !ZBOOT_ROM
1980         help
1981           With this option, the boot code will look for a device tree binary
1982           (DTB) appended to zImage
1983           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1984
1985           This is meant as a backward compatibility convenience for those
1986           systems with a bootloader that can't be upgraded to accommodate
1987           the documented boot protocol using a device tree.
1988
1989           Beware that there is very little in terms of protection against
1990           this option being confused by leftover garbage in memory that might
1991           look like a DTB header after a reboot if no actual DTB is appended
1992           to zImage.  Do not leave this option active in a production kernel
1993           if you don't intend to always append a DTB.  Proper passing of the
1994           location into r2 of a bootloader provided DTB is always preferable
1995           to this option.
1996
1997 config ARM_ATAG_DTB_COMPAT
1998         bool "Supplement the appended DTB with traditional ATAG information"
1999         depends on ARM_APPENDED_DTB
2000         help
2001           Some old bootloaders can't be updated to a DTB capable one, yet
2002           they provide ATAGs with memory configuration, the ramdisk address,
2003           the kernel cmdline string, etc.  Such information is dynamically
2004           provided by the bootloader and can't always be stored in a static
2005           DTB.  To allow a device tree enabled kernel to be used with such
2006           bootloaders, this option allows zImage to extract the information
2007           from the ATAG list and store it at run time into the appended DTB.
2008
2009 choice
2010         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2011         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2012
2013 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2014         bool "Use bootloader kernel arguments if available"
2015         help
2016           Uses the command-line options passed by the boot loader instead of
2017           the device tree bootargs property. If the boot loader doesn't provide
2018           any, the device tree bootargs property will be used.
2019
2020 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2021         bool "Extend with bootloader kernel arguments"
2022         help
2023           The command-line arguments provided by the boot loader will be
2024           appended to the the device tree bootargs property.
2025
2026 endchoice
2027
2028 config CMDLINE
2029         string "Default kernel command string"
2030         default ""
2031         help
2032           On some architectures (EBSA110 and CATS), there is currently no way
2033           for the boot loader to pass arguments to the kernel. For these
2034           architectures, you should supply some command-line options at build
2035           time by entering them here. As a minimum, you should specify the
2036           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2037
2038 choice
2039         prompt "Kernel command line type" if CMDLINE != ""
2040         default CMDLINE_FROM_BOOTLOADER
2041         depends on ATAGS
2042
2043 config CMDLINE_FROM_BOOTLOADER
2044         bool "Use bootloader kernel arguments if available"
2045         help
2046           Uses the command-line options passed by the boot loader. If
2047           the boot loader doesn't provide any, the default kernel command
2048           string provided in CMDLINE will be used.
2049
2050 config CMDLINE_EXTEND
2051         bool "Extend bootloader kernel arguments"
2052         help
2053           The command-line arguments provided by the boot loader will be
2054           appended to the default kernel command string.
2055
2056 config CMDLINE_FORCE
2057         bool "Always use the default kernel command string"
2058         help
2059           Always use the default kernel command string, even if the boot
2060           loader passes other arguments to the kernel.
2061           This is useful if you cannot or don't want to change the
2062           command-line options your boot loader passes to the kernel.
2063 endchoice
2064
2065 config XIP_KERNEL
2066         bool "Kernel Execute-In-Place from ROM"
2067         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2068         help
2069           Execute-In-Place allows the kernel to run from non-volatile storage
2070           directly addressable by the CPU, such as NOR flash. This saves RAM
2071           space since the text section of the kernel is not loaded from flash
2072           to RAM.  Read-write sections, such as the data section and stack,
2073           are still copied to RAM.  The XIP kernel is not compressed since
2074           it has to run directly from flash, so it will take more space to
2075           store it.  The flash address used to link the kernel object files,
2076           and for storing it, is configuration dependent. Therefore, if you
2077           say Y here, you must know the proper physical address where to
2078           store the kernel image depending on your own flash memory usage.
2079
2080           Also note that the make target becomes "make xipImage" rather than
2081           "make zImage" or "make Image".  The final kernel binary to put in
2082           ROM memory will be arch/arm/boot/xipImage.
2083
2084           If unsure, say N.
2085
2086 config XIP_PHYS_ADDR
2087         hex "XIP Kernel Physical Location"
2088         depends on XIP_KERNEL
2089         default "0x00080000"
2090         help
2091           This is the physical address in your flash memory the kernel will
2092           be linked for and stored to.  This address is dependent on your
2093           own flash usage.
2094
2095 config KEXEC
2096         bool "Kexec system call (EXPERIMENTAL)"
2097         depends on (!SMP || PM_SLEEP_SMP)
2098         help
2099           kexec is a system call that implements the ability to shutdown your
2100           current kernel, and to start another kernel.  It is like a reboot
2101           but it is independent of the system firmware.   And like a reboot
2102           you can start any kernel with it, not just Linux.
2103
2104           It is an ongoing process to be certain the hardware in a machine
2105           is properly shutdown, so do not be surprised if this code does not
2106           initially work for you.
2107
2108 config ATAGS_PROC
2109         bool "Export atags in procfs"
2110         depends on ATAGS && KEXEC
2111         default y
2112         help
2113           Should the atags used to boot the kernel be exported in an "atags"
2114           file in procfs. Useful with kexec.
2115
2116 config CRASH_DUMP
2117         bool "Build kdump crash kernel (EXPERIMENTAL)"
2118         help
2119           Generate crash dump after being started by kexec. This should
2120           be normally only set in special crash dump kernels which are
2121           loaded in the main kernel with kexec-tools into a specially
2122           reserved region and then later executed after a crash by
2123           kdump/kexec. The crash dump kernel must be compiled to a
2124           memory address not used by the main kernel
2125
2126           For more details see Documentation/kdump/kdump.txt
2127
2128 config AUTO_ZRELADDR
2129         bool "Auto calculation of the decompressed kernel image address"
2130         depends on !ZBOOT_ROM
2131         help
2132           ZRELADDR is the physical address where the decompressed kernel
2133           image will be placed. If AUTO_ZRELADDR is selected, the address
2134           will be determined at run-time by masking the current IP with
2135           0xf8000000. This assumes the zImage being placed in the first 128MB
2136           from start of memory.
2137
2138 endmenu
2139
2140 menu "CPU Power Management"
2141
2142 if ARCH_HAS_CPUFREQ
2143 source "drivers/cpufreq/Kconfig"
2144 endif
2145
2146 source "drivers/cpuidle/Kconfig"
2147
2148 endmenu
2149
2150 menu "Floating point emulation"
2151
2152 comment "At least one emulation must be selected"
2153
2154 config FPE_NWFPE
2155         bool "NWFPE math emulation"
2156         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2157         ---help---
2158           Say Y to include the NWFPE floating point emulator in the kernel.
2159           This is necessary to run most binaries. Linux does not currently
2160           support floating point hardware so you need to say Y here even if
2161           your machine has an FPA or floating point co-processor podule.
2162
2163           You may say N here if you are going to load the Acorn FPEmulator
2164           early in the bootup.
2165
2166 config FPE_NWFPE_XP
2167         bool "Support extended precision"
2168         depends on FPE_NWFPE
2169         help
2170           Say Y to include 80-bit support in the kernel floating-point
2171           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2172           Note that gcc does not generate 80-bit operations by default,
2173           so in most cases this option only enlarges the size of the
2174           floating point emulator without any good reason.
2175
2176           You almost surely want to say N here.
2177
2178 config FPE_FASTFPE
2179         bool "FastFPE math emulation (EXPERIMENTAL)"
2180         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2181         ---help---
2182           Say Y here to include the FAST floating point emulator in the kernel.
2183           This is an experimental much faster emulator which now also has full
2184           precision for the mantissa.  It does not support any exceptions.
2185           It is very simple, and approximately 3-6 times faster than NWFPE.
2186
2187           It should be sufficient for most programs.  It may be not suitable
2188           for scientific calculations, but you have to check this for yourself.
2189           If you do not feel you need a faster FP emulation you should better
2190           choose NWFPE.
2191
2192 config VFP
2193         bool "VFP-format floating point maths"
2194         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2195         help
2196           Say Y to include VFP support code in the kernel. This is needed
2197           if your hardware includes a VFP unit.
2198
2199           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2200           release notes and additional status information.
2201
2202           Say N if your target does not have VFP hardware.
2203
2204 config VFPv3
2205         bool
2206         depends on VFP
2207         default y if CPU_V7
2208
2209 config NEON
2210         bool "Advanced SIMD (NEON) Extension support"
2211         depends on VFPv3 && CPU_V7
2212         help
2213           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2214           Extension.
2215
2216 config KERNEL_MODE_NEON
2217         bool "Support for NEON in kernel mode"
2218         depends on NEON && AEABI
2219         help
2220           Say Y to include support for NEON in kernel mode.
2221
2222 endmenu
2223
2224 menu "Userspace binary formats"
2225
2226 source "fs/Kconfig.binfmt"
2227
2228 config ARTHUR
2229         tristate "RISC OS personality"
2230         depends on !AEABI
2231         help
2232           Say Y here to include the kernel code necessary if you want to run
2233           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2234           experimental; if this sounds frightening, say N and sleep in peace.
2235           You can also say M here to compile this support as a module (which
2236           will be called arthur).
2237
2238 endmenu
2239
2240 menu "Power management options"
2241
2242 source "kernel/power/Kconfig"
2243
2244 config ARCH_SUSPEND_POSSIBLE
2245         depends on !ARCH_S5PC100
2246         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2247                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2248         def_bool y
2249
2250 config ARM_CPU_SUSPEND
2251         def_bool PM_SLEEP
2252
2253 endmenu
2254
2255 source "net/Kconfig"
2256
2257 source "drivers/Kconfig"
2258
2259 source "fs/Kconfig"
2260
2261 source "arch/arm/Kconfig.debug"
2262
2263 source "security/Kconfig"
2264
2265 source "crypto/Kconfig"
2266
2267 source "lib/Kconfig"
2268
2269 source "arch/arm/kvm/Kconfig"