arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAVE_CUSTOM_GPIO_H
   5         select HAVE_AOUT
   6         select HAVE_DMA_API_DEBUG
   7         select HAVE_IDE if PCI || ISA || PCMCIA
   8         select HAVE_DMA_ATTRS
   9         select HAVE_DMA_CONTIGUOUS if MMU
  10         select HAVE_MEMBLOCK
  11         select RTC_LIB
  12         select SYS_SUPPORTS_APM_EMULATION
  13         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  15         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  16         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  17         select HAVE_ARCH_KGDB
  18         select HAVE_ARCH_TRACEHOOK
  19         select HAVE_SYSCALL_TRACEPOINTS
  20         select HAVE_KPROBES if !XIP_KERNEL
  21         select HAVE_KRETPROBES if (HAVE_KPROBES)
  22         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  23         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  24         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  25         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  26         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  27         select HAVE_GENERIC_DMA_COHERENT
  28         select HAVE_KERNEL_GZIP
  29         select HAVE_KERNEL_LZO
  30         select HAVE_KERNEL_LZMA
  31         select HAVE_KERNEL_XZ
  32         select HAVE_IRQ_WORK
  33         select HAVE_PERF_EVENTS
  34         select PERF_USE_VMALLOC
  35         select HAVE_REGS_AND_STACK_ACCESS_API
  36         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  37         select HAVE_C_RECORDMCOUNT
  38         select HAVE_GENERIC_HARDIRQS
  39         select HARDIRQS_SW_RESEND
  40         select GENERIC_IRQ_PROBE
  41         select GENERIC_IRQ_SHOW
  42         select ARCH_WANT_IPC_PARSE_VERSION
  43         select HARDIRQS_SW_RESEND
  44         select CPU_PM if (SUSPEND || CPU_IDLE)
  45         select GENERIC_PCI_IOMAP
  46         select HAVE_BPF_JIT
  47         select GENERIC_SMP_IDLE_THREAD
  48         select KTIME_SCALAR
  49         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  50         select GENERIC_STRNCPY_FROM_USER
  51         select GENERIC_STRNLEN_USER
  52         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
  53         help
  54           The ARM series is a line of low-power-consumption RISC chip designs
  55           licensed by ARM Ltd and targeted at embedded applications and
  56           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  57           manufactured, but legacy ARM-based PC hardware remains popular in
  58           Europe.  There is an ARM Linux project with a web page at
  59           <http://www.arm.linux.org.uk/>.
  60
  61 config ARM_HAS_SG_CHAIN
  62         bool
  63
  64 config NEED_SG_DMA_LENGTH
  65         bool
  66
  67 config ARM_DMA_USE_IOMMU
  68         select NEED_SG_DMA_LENGTH
  69         select ARM_HAS_SG_CHAIN
  70         bool
  71
  72 config HAVE_PWM
  73         bool
  74
  75 config MIGHT_HAVE_PCI
  76         bool
  77
  78 config SYS_SUPPORTS_APM_EMULATION
  79         bool
  80
  81 config GENERIC_GPIO
  82         bool
  83
  84 config HAVE_TCM
  85         bool
  86         select GENERIC_ALLOCATOR
  87
  88 config HAVE_PROC_CPU
  89         bool
  90
  91 config NO_IOPORT
  92         bool
  93
  94 config EISA
  95         bool
  96         ---help---
  97           The Extended Industry Standard Architecture (EISA) bus was
  98           developed as an open alternative to the IBM MicroChannel bus.
  99
 100           The EISA bus provided some of the features of the IBM MicroChannel
 101           bus while maintaining backward compatibility with cards made for
 102           the older ISA bus.  The EISA bus saw limited use between 1988 and
 103           1995 when it was made obsolete by the PCI bus.
 104
 105           Say Y here if you are building a kernel for an EISA-based machine.
 106
 107           Otherwise, say N.
 108
 109 config SBUS
 110         bool
 111
 112 config STACKTRACE_SUPPORT
 113         bool
 114         default y
 115
 116 config HAVE_LATENCYTOP_SUPPORT
 117         bool
 118         depends on !SMP
 119         default y
 120
 121 config LOCKDEP_SUPPORT
 122         bool
 123         default y
 124
 125 config TRACE_IRQFLAGS_SUPPORT
 126         bool
 127         default y
 128
 129 config RWSEM_GENERIC_SPINLOCK
 130         bool
 131         default y
 132
 133 config RWSEM_XCHGADD_ALGORITHM
 134         bool
 135
 136 config ARCH_HAS_ILOG2_U32
 137         bool
 138
 139 config ARCH_HAS_ILOG2_U64
 140         bool
 141
 142 config ARCH_HAS_CPUFREQ
 143         bool
 144         help
 145           Internal node to signify that the ARCH has CPUFREQ support
 146           and that the relevant menu configurations are displayed for
 147           it.
 148
 149 config GENERIC_HWEIGHT
 150         bool
 151         default y
 152
 153 config GENERIC_CALIBRATE_DELAY
 154         bool
 155         default y
 156
 157 config ARCH_MAY_HAVE_PC_FDC
 158         bool
 159
 160 config ZONE_DMA
 161         bool
 162
 163 config NEED_DMA_MAP_STATE
 164        def_bool y
 165
 166 config ARCH_HAS_DMA_SET_COHERENT_MASK
 167         bool
 168
 169 config GENERIC_ISA_DMA
 170         bool
 171
 172 config FIQ
 173         bool
 174
 175 config NEED_RET_TO_USER
 176         bool
 177
 178 config ARCH_MTD_XIP
 179         bool
 180
 181 config VECTORS_BASE
 182         hex
 183         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 184         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 185         default 0x00000000
 186         help
 187           The base address of exception vectors.
 188
 189 config ARM_PATCH_PHYS_VIRT
 190         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 191         default y
 192         depends on !XIP_KERNEL && MMU
 193         depends on !ARCH_REALVIEW || !SPARSEMEM
 194         help
 195           Patch phys-to-virt and virt-to-phys translation functions at
 196           boot and module load time according to the position of the
 197           kernel in system memory.
 198
 199           This can only be used with non-XIP MMU kernels where the base
 200           of physical memory is at a 16MB boundary.
 201
 202           Only disable this option if you know that you do not require
 203           this feature (eg, building a kernel for a single machine) and
 204           you need to shrink the kernel to the minimal size.
 205
 206 config NEED_MACH_GPIO_H
 207         bool
 208         help
 209           Select this when mach/gpio.h is required to provide special
 210           definitions for this platform. The need for mach/gpio.h should
 211           be avoided when possible.
 212
 213 config NEED_MACH_IO_H
 214         bool
 215         help
 216           Select this when mach/io.h is required to provide special
 217           definitions for this platform.  The need for mach/io.h should
 218           be avoided when possible.
 219
 220 config NEED_MACH_MEMORY_H
 221         bool
 222         help
 223           Select this when mach/memory.h is required to provide special
 224           definitions for this platform.  The need for mach/memory.h should
 225           be avoided when possible.
 226
 227 config PHYS_OFFSET
 228         hex "Physical address of main memory" if MMU
 229         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 230         default DRAM_BASE if !MMU
 231         help
 232           Please provide the physical address corresponding to the
 233           location of main memory in your system.
 234
 235 config GENERIC_BUG
 236         def_bool y
 237         depends on BUG
 238
 239 source "init/Kconfig"
 240
 241 source "kernel/Kconfig.freezer"
 242
 243 menu "System Type"
 244
 245 config MMU
 246         bool "MMU-based Paged Memory Management Support"
 247         default y
 248         help
 249           Select if you want MMU-based virtualised addressing space
 250           support by paged memory management. If unsure, say 'Y'.
 251
 252 #
 253 # The "ARM system type" choice list is ordered alphabetically by option
 254 # text.  Please add new entries in the option alphabetic order.
 255 #
 256 choice
 257         prompt "ARM system type"
 258         default ARCH_MULTIPLATFORM
 259
 260 config ARCH_MULTIPLATFORM
 261         bool "Allow multiple platforms to be selected"
 262         select ARM_PATCH_PHYS_VIRT
 263         select AUTO_ZRELADDR
 264         select COMMON_CLK
 265         select MULTI_IRQ_HANDLER
 266         select SPARSE_IRQ
 267         select USE_OF
 268         depends on MMU
 269
 270 config ARCH_INTEGRATOR
 271         bool "ARM Ltd. Integrator family"
 272         select ARM_AMBA
 273         select ARCH_HAS_CPUFREQ
 274         select COMMON_CLK
 275         select COMMON_CLK_VERSATILE
 276         select HAVE_TCM
 277         select ICST
 278         select GENERIC_CLOCKEVENTS
 279         select PLAT_VERSATILE
 280         select PLAT_VERSATILE_FPGA_IRQ
 281         select NEED_MACH_MEMORY_H
 282         select SPARSE_IRQ
 283         select MULTI_IRQ_HANDLER
 284         help
 285           Support for ARM's Integrator platform.
 286
 287 config ARCH_REALVIEW
 288         bool "ARM Ltd. RealView family"
 289         select ARM_AMBA
 290         select COMMON_CLK
 291         select COMMON_CLK_VERSATILE
 292         select ICST
 293         select GENERIC_CLOCKEVENTS
 294         select ARCH_WANT_OPTIONAL_GPIOLIB
 295         select PLAT_VERSATILE
 296         select PLAT_VERSATILE_CLCD
 297         select ARM_TIMER_SP804
 298         select GPIO_PL061 if GPIOLIB
 299         select NEED_MACH_MEMORY_H
 300         help
 301           This enables support for ARM Ltd RealView boards.
 302
 303 config ARCH_VERSATILE
 304         bool "ARM Ltd. Versatile family"
 305         select ARM_AMBA
 306         select ARM_VIC
 307         select CLKDEV_LOOKUP
 308         select HAVE_MACH_CLKDEV
 309         select ICST
 310         select GENERIC_CLOCKEVENTS
 311         select ARCH_WANT_OPTIONAL_GPIOLIB
 312         select PLAT_VERSATILE
 313         select PLAT_VERSATILE_CLOCK
 314         select PLAT_VERSATILE_CLCD
 315         select PLAT_VERSATILE_FPGA_IRQ
 316         select ARM_TIMER_SP804
 317         help
 318           This enables support for ARM Ltd Versatile board.
 319
 320 config ARCH_AT91
 321         bool "Atmel AT91"
 322         select ARCH_REQUIRE_GPIOLIB
 323         select HAVE_CLK
 324         select CLKDEV_LOOKUP
 325         select IRQ_DOMAIN
 326         select NEED_MACH_GPIO_H
 327         select NEED_MACH_IO_H if PCCARD
 328         help
 329           This enables support for systems based on Atmel
 330           AT91RM9200 and AT91SAM9* processors.
 331
 332 config ARCH_BCM2835
 333         bool "Broadcom BCM2835 family"
 334         select ARCH_WANT_OPTIONAL_GPIOLIB
 335         select ARM_AMBA
 336         select ARM_ERRATA_411920
 337         select ARM_TIMER_SP804
 338         select CLKDEV_LOOKUP
 339         select COMMON_CLK
 340         select CPU_V6
 341         select GENERIC_CLOCKEVENTS
 342         select MULTI_IRQ_HANDLER
 343         select SPARSE_IRQ
 344         select USE_OF
 345         help
 346           This enables support for the Broadcom BCM2835 SoC. This SoC is
 347           use in the Raspberry Pi, and Roku 2 devices.
 348
 349 config ARCH_CLPS711X
 350         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 351         select CPU_ARM720T
 352         select ARCH_USES_GETTIMEOFFSET
 353         select COMMON_CLK
 354         select CLKDEV_LOOKUP
 355         select NEED_MACH_MEMORY_H
 356         help
 357           Support for Cirrus Logic 711x/721x/731x based boards.
 358
 359 config ARCH_CNS3XXX
 360         bool "Cavium Networks CNS3XXX family"
 361         select CPU_V6K
 362         select GENERIC_CLOCKEVENTS
 363         select ARM_GIC
 364         select MIGHT_HAVE_CACHE_L2X0
 365         select MIGHT_HAVE_PCI
 366         select PCI_DOMAINS if PCI
 367         help
 368           Support for Cavium Networks CNS3XXX platform.
 369
 370 config ARCH_GEMINI
 371         bool "Cortina Systems Gemini"
 372         select CPU_FA526
 373         select ARCH_REQUIRE_GPIOLIB
 374         select ARCH_USES_GETTIMEOFFSET
 375         help
 376           Support for the Cortina Systems Gemini family SoCs
 377
 378 config ARCH_SIRF
 379         bool "CSR SiRF"
 380         select NO_IOPORT
 381         select ARCH_REQUIRE_GPIOLIB
 382         select GENERIC_CLOCKEVENTS
 383         select COMMON_CLK
 384         select GENERIC_IRQ_CHIP
 385         select MIGHT_HAVE_CACHE_L2X0
 386         select PINCTRL
 387         select PINCTRL_SIRF
 388         select USE_OF
 389         help
 390           Support for CSR SiRFprimaII/Marco/Polo platforms
 391
 392 config ARCH_EBSA110
 393         bool "EBSA-110"
 394         select CPU_SA110
 395         select ISA
 396         select NO_IOPORT
 397         select ARCH_USES_GETTIMEOFFSET
 398         select NEED_MACH_IO_H
 399         select NEED_MACH_MEMORY_H
 400         help
 401           This is an evaluation board for the StrongARM processor available
 402           from Digital. It has limited hardware on-board, including an
 403           Ethernet interface, two PCMCIA sockets, two serial ports and a
 404           parallel port.
 405
 406 config ARCH_EP93XX
 407         bool "EP93xx-based"
 408         select CPU_ARM920T
 409         select ARM_AMBA
 410         select ARM_VIC
 411         select CLKDEV_LOOKUP
 412         select ARCH_REQUIRE_GPIOLIB
 413         select ARCH_HAS_HOLES_MEMORYMODEL
 414         select ARCH_USES_GETTIMEOFFSET
 415         select NEED_MACH_MEMORY_H
 416         help
 417           This enables support for the Cirrus EP93xx series of CPUs.
 418
 419 config ARCH_FOOTBRIDGE
 420         bool "FootBridge"
 421         select CPU_SA110
 422         select FOOTBRIDGE
 423         select GENERIC_CLOCKEVENTS
 424         select HAVE_IDE
 425         select NEED_MACH_IO_H if !MMU
 426         select NEED_MACH_MEMORY_H
 427         help
 428           Support for systems based on the DC21285 companion chip
 429           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 430
 431 config ARCH_MXC
 432         bool "Freescale MXC/iMX-based"
 433         select GENERIC_CLOCKEVENTS
 434         select ARCH_REQUIRE_GPIOLIB
 435         select CLKDEV_LOOKUP
 436         select CLKSRC_MMIO
 437         select GENERIC_IRQ_CHIP
 438         select MULTI_IRQ_HANDLER
 439         select SPARSE_IRQ
 440         select USE_OF
 441         help
 442           Support for Freescale MXC/iMX-based family of processors
 443
 444 config ARCH_MXS
 445         bool "Freescale MXS-based"
 446         select GENERIC_CLOCKEVENTS
 447         select ARCH_REQUIRE_GPIOLIB
 448         select CLKDEV_LOOKUP
 449         select CLKSRC_MMIO
 450         select COMMON_CLK
 451         select HAVE_CLK_PREPARE
 452         select MULTI_IRQ_HANDLER
 453         select PINCTRL
 454         select SPARSE_IRQ
 455         select USE_OF
 456         help
 457           Support for Freescale MXS-based family of processors
 458
 459 config ARCH_NETX
 460         bool "Hilscher NetX based"
 461         select CLKSRC_MMIO
 462         select CPU_ARM926T
 463         select ARM_VIC
 464         select GENERIC_CLOCKEVENTS
 465         help
 466           This enables support for systems based on the Hilscher NetX Soc
 467
 468 config ARCH_H720X
 469         bool "Hynix HMS720x-based"
 470         select CPU_ARM720T
 471         select ISA_DMA_API
 472         select ARCH_USES_GETTIMEOFFSET
 473         help
 474           This enables support for systems based on the Hynix HMS720x
 475
 476 config ARCH_IOP13XX
 477         bool "IOP13xx-based"
 478         depends on MMU
 479         select CPU_XSC3
 480         select PLAT_IOP
 481         select PCI
 482         select ARCH_SUPPORTS_MSI
 483         select VMSPLIT_1G
 484         select NEED_MACH_MEMORY_H
 485         select NEED_RET_TO_USER
 486         help
 487           Support for Intel's IOP13XX (XScale) family of processors.
 488
 489 config ARCH_IOP32X
 490         bool "IOP32x-based"
 491         depends on MMU
 492         select CPU_XSCALE
 493         select NEED_MACH_GPIO_H
 494         select NEED_MACH_IO_H
 495         select NEED_RET_TO_USER
 496         select PLAT_IOP
 497         select PCI
 498         select ARCH_REQUIRE_GPIOLIB
 499         help
 500           Support for Intel's 80219 and IOP32X (XScale) family of
 501           processors.
 502
 503 config ARCH_IOP33X
 504         bool "IOP33x-based"
 505         depends on MMU
 506         select CPU_XSCALE
 507         select NEED_MACH_GPIO_H
 508         select NEED_MACH_IO_H
 509         select NEED_RET_TO_USER
 510         select PLAT_IOP
 511         select PCI
 512         select ARCH_REQUIRE_GPIOLIB
 513         help
 514           Support for Intel's IOP33X (XScale) family of processors.
 515
 516 config ARCH_IXP4XX
 517         bool "IXP4xx-based"
 518         depends on MMU
 519         select ARCH_HAS_DMA_SET_COHERENT_MASK
 520         select CLKSRC_MMIO
 521         select CPU_XSCALE
 522         select ARCH_REQUIRE_GPIOLIB
 523         select GENERIC_CLOCKEVENTS
 524         select MIGHT_HAVE_PCI
 525         select NEED_MACH_IO_H
 526         select DMABOUNCE if PCI
 527         help
 528           Support for Intel's IXP4XX (XScale) family of processors.
 529
 530 config ARCH_DOVE
 531         bool "Marvell Dove"
 532         select CPU_V7
 533         select ARCH_REQUIRE_GPIOLIB
 534         select GENERIC_CLOCKEVENTS
 535         select MIGHT_HAVE_PCI
 536         select PLAT_ORION_LEGACY
 537         select USB_ARCH_HAS_EHCI
 538         help
 539           Support for the Marvell Dove SoC 88AP510
 540
 541 config ARCH_KIRKWOOD
 542         bool "Marvell Kirkwood"
 543         select CPU_FEROCEON
 544         select PCI
 545         select ARCH_REQUIRE_GPIOLIB
 546         select GENERIC_CLOCKEVENTS
 547         select PLAT_ORION_LEGACY
 548         help
 549           Support for the following Marvell Kirkwood series SoCs:
 550           88F6180, 88F6192 and 88F6281.
 551
 552 config ARCH_LPC32XX
 553         bool "NXP LPC32XX"
 554         select CLKSRC_MMIO
 555         select CPU_ARM926T
 556         select ARCH_REQUIRE_GPIOLIB
 557         select HAVE_IDE
 558         select ARM_AMBA
 559         select USB_ARCH_HAS_OHCI
 560         select CLKDEV_LOOKUP
 561         select GENERIC_CLOCKEVENTS
 562         select USE_OF
 563         select HAVE_PWM
 564         help
 565           Support for the NXP LPC32XX family of processors
 566
 567 config ARCH_MV78XX0
 568         bool "Marvell MV78xx0"
 569         select CPU_FEROCEON
 570         select PCI
 571         select ARCH_REQUIRE_GPIOLIB
 572         select GENERIC_CLOCKEVENTS
 573         select PLAT_ORION_LEGACY
 574         help
 575           Support for the following Marvell MV78xx0 series SoCs:
 576           MV781x0, MV782x0.
 577
 578 config ARCH_ORION5X
 579         bool "Marvell Orion"
 580         depends on MMU
 581         select CPU_FEROCEON
 582         select PCI
 583         select ARCH_REQUIRE_GPIOLIB
 584         select GENERIC_CLOCKEVENTS
 585         select PLAT_ORION_LEGACY
 586         help
 587           Support for the following Marvell Orion 5x series SoCs:
 588           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 589           Orion-2 (5281), Orion-1-90 (6183).
 590
 591 config ARCH_MMP
 592         bool "Marvell PXA168/910/MMP2"
 593         depends on MMU
 594         select ARCH_REQUIRE_GPIOLIB
 595         select CLKDEV_LOOKUP
 596         select GENERIC_CLOCKEVENTS
 597         select GPIO_PXA
 598         select IRQ_DOMAIN
 599         select PLAT_PXA
 600         select SPARSE_IRQ
 601         select GENERIC_ALLOCATOR
 602         select NEED_MACH_GPIO_H
 603         help
 604           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 605
 606 config ARCH_KS8695
 607         bool "Micrel/Kendin KS8695"
 608         select CPU_ARM922T
 609         select ARCH_REQUIRE_GPIOLIB
 610         select NEED_MACH_MEMORY_H
 611         select CLKSRC_MMIO
 612         select GENERIC_CLOCKEVENTS
 613         help
 614           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 615           System-on-Chip devices.
 616
 617 config ARCH_W90X900
 618         bool "Nuvoton W90X900 CPU"
 619         select CPU_ARM926T
 620         select ARCH_REQUIRE_GPIOLIB
 621         select CLKDEV_LOOKUP
 622         select CLKSRC_MMIO
 623         select GENERIC_CLOCKEVENTS
 624         help
 625           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 626           At present, the w90x900 has been renamed nuc900, regarding
 627           the ARM series product line, you can login the following
 628           link address to know more.
 629
 630           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 631                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 632
 633 config ARCH_TEGRA
 634         bool "NVIDIA Tegra"
 635         select CLKDEV_LOOKUP
 636         select CLKSRC_MMIO
 637         select GENERIC_CLOCKEVENTS
 638         select GENERIC_GPIO
 639         select HAVE_CLK
 640         select HAVE_SMP
 641         select MIGHT_HAVE_CACHE_L2X0
 642         select ARCH_HAS_CPUFREQ
 643         select USE_OF
 644         select COMMON_CLK
 645         help
 646           This enables support for NVIDIA Tegra based systems (Tegra APX,
 647           Tegra 6xx and Tegra 2 series).
 648
 649 config ARCH_PXA
 650         bool "PXA2xx/PXA3xx-based"
 651         depends on MMU
 652         select ARCH_MTD_XIP
 653         select ARCH_HAS_CPUFREQ
 654         select CLKDEV_LOOKUP
 655         select CLKSRC_MMIO
 656         select ARCH_REQUIRE_GPIOLIB
 657         select GENERIC_CLOCKEVENTS
 658         select GPIO_PXA
 659         select PLAT_PXA
 660         select SPARSE_IRQ
 661         select AUTO_ZRELADDR
 662         select MULTI_IRQ_HANDLER
 663         select ARM_CPU_SUSPEND if PM
 664         select HAVE_IDE
 665         select NEED_MACH_GPIO_H
 666         help
 667           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 668
 669 config ARCH_MSM
 670         bool "Qualcomm MSM"
 671         select HAVE_CLK
 672         select GENERIC_CLOCKEVENTS
 673         select ARCH_REQUIRE_GPIOLIB
 674         select CLKDEV_LOOKUP
 675         help
 676           Support for Qualcomm MSM/QSD based systems.  This runs on the
 677           apps processor of the MSM/QSD and depends on a shared memory
 678           interface to the modem processor which runs the baseband
 679           stack and controls some vital subsystems
 680           (clock and power control, etc).
 681
 682 config ARCH_SHMOBILE
 683         bool "Renesas SH-Mobile / R-Mobile"
 684         select HAVE_CLK
 685         select CLKDEV_LOOKUP
 686         select HAVE_MACH_CLKDEV
 687         select HAVE_SMP
 688         select GENERIC_CLOCKEVENTS
 689         select MIGHT_HAVE_CACHE_L2X0
 690         select NO_IOPORT
 691         select SPARSE_IRQ
 692         select MULTI_IRQ_HANDLER
 693         select PM_GENERIC_DOMAINS if PM
 694         select NEED_MACH_MEMORY_H
 695         help
 696           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 697
 698 config ARCH_RPC
 699         bool "RiscPC"
 700         select ARCH_ACORN
 701         select FIQ
 702         select ARCH_MAY_HAVE_PC_FDC
 703         select HAVE_PATA_PLATFORM
 704         select ISA_DMA_API
 705         select NO_IOPORT
 706         select ARCH_SPARSEMEM_ENABLE
 707         select ARCH_USES_GETTIMEOFFSET
 708         select HAVE_IDE
 709         select NEED_MACH_IO_H
 710         select NEED_MACH_MEMORY_H
 711         help
 712           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 713           CD-ROM interface, serial and parallel port, and the floppy drive.
 714
 715 config ARCH_SA1100
 716         bool "SA1100-based"
 717         select CLKSRC_MMIO
 718         select CPU_SA1100
 719         select ISA
 720         select ARCH_SPARSEMEM_ENABLE
 721         select ARCH_MTD_XIP
 722         select ARCH_HAS_CPUFREQ
 723         select CPU_FREQ
 724         select GENERIC_CLOCKEVENTS
 725         select CLKDEV_LOOKUP
 726         select ARCH_REQUIRE_GPIOLIB
 727         select HAVE_IDE
 728         select NEED_MACH_GPIO_H
 729         select NEED_MACH_MEMORY_H
 730         select SPARSE_IRQ
 731         help
 732           Support for StrongARM 11x0 based boards.
 733
 734 config ARCH_S3C24XX
 735         bool "Samsung S3C24XX SoCs"
 736         select GENERIC_GPIO
 737         select ARCH_HAS_CPUFREQ
 738         select HAVE_CLK
 739         select CLKDEV_LOOKUP
 740         select ARCH_USES_GETTIMEOFFSET
 741         select HAVE_S3C2410_I2C if I2C
 742         select HAVE_S3C_RTC if RTC_CLASS
 743         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 744         select NEED_MACH_GPIO_H
 745         select NEED_MACH_IO_H
 746         help
 747           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 748           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 749           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 750           Samsung SMDK2410 development board (and derivatives).
 751
 752 config ARCH_S3C64XX
 753         bool "Samsung S3C64XX"
 754         select PLAT_SAMSUNG
 755         select CPU_V6
 756         select ARM_VIC
 757         select HAVE_CLK
 758         select HAVE_TCM
 759         select CLKDEV_LOOKUP
 760         select NO_IOPORT
 761         select ARCH_USES_GETTIMEOFFSET
 762         select ARCH_HAS_CPUFREQ
 763         select ARCH_REQUIRE_GPIOLIB
 764         select SAMSUNG_CLKSRC
 765         select SAMSUNG_IRQ_VIC_TIMER
 766         select S3C_GPIO_TRACK
 767         select S3C_DEV_NAND
 768         select USB_ARCH_HAS_OHCI
 769         select SAMSUNG_GPIOLIB_4BIT
 770         select HAVE_S3C2410_I2C if I2C
 771         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 772         select NEED_MACH_GPIO_H
 773         help
 774           Samsung S3C64XX series based systems
 775
 776 config ARCH_S5P64X0
 777         bool "Samsung S5P6440 S5P6450"
 778         select CPU_V6
 779         select GENERIC_GPIO
 780         select HAVE_CLK
 781         select CLKDEV_LOOKUP
 782         select CLKSRC_MMIO
 783         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 784         select GENERIC_CLOCKEVENTS
 785         select HAVE_S3C2410_I2C if I2C
 786         select HAVE_S3C_RTC if RTC_CLASS
 787         select NEED_MACH_GPIO_H
 788         help
 789           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 790           SMDK6450.
 791
 792 config ARCH_S5PC100
 793         bool "Samsung S5PC100"
 794         select GENERIC_GPIO
 795         select HAVE_CLK
 796         select CLKDEV_LOOKUP
 797         select CPU_V7
 798         select ARCH_USES_GETTIMEOFFSET
 799         select HAVE_S3C2410_I2C if I2C
 800         select HAVE_S3C_RTC if RTC_CLASS
 801         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 802         select NEED_MACH_GPIO_H
 803         help
 804           Samsung S5PC100 series based systems
 805
 806 config ARCH_S5PV210
 807         bool "Samsung S5PV210/S5PC110"
 808         select CPU_V7
 809         select ARCH_SPARSEMEM_ENABLE
 810         select ARCH_HAS_HOLES_MEMORYMODEL
 811         select GENERIC_GPIO
 812         select HAVE_CLK
 813         select CLKDEV_LOOKUP
 814         select CLKSRC_MMIO
 815         select ARCH_HAS_CPUFREQ
 816         select GENERIC_CLOCKEVENTS
 817         select HAVE_S3C2410_I2C if I2C
 818         select HAVE_S3C_RTC if RTC_CLASS
 819         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 820         select NEED_MACH_GPIO_H
 821         select NEED_MACH_MEMORY_H
 822         help
 823           Samsung S5PV210/S5PC110 series based systems
 824
 825 config ARCH_EXYNOS
 826         bool "SAMSUNG EXYNOS"
 827         select CPU_V7
 828         select ARCH_SPARSEMEM_ENABLE
 829         select ARCH_HAS_HOLES_MEMORYMODEL
 830         select GENERIC_GPIO
 831         select HAVE_CLK
 832         select CLKDEV_LOOKUP
 833         select ARCH_HAS_CPUFREQ
 834         select GENERIC_CLOCKEVENTS
 835         select HAVE_S3C_RTC if RTC_CLASS
 836         select HAVE_S3C2410_I2C if I2C
 837         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 838         select NEED_MACH_GPIO_H
 839         select NEED_MACH_MEMORY_H
 840         help
 841           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 842
 843 config ARCH_SHARK
 844         bool "Shark"
 845         select CPU_SA110
 846         select ISA
 847         select ISA_DMA
 848         select ZONE_DMA
 849         select PCI
 850         select ARCH_USES_GETTIMEOFFSET
 851         select NEED_MACH_MEMORY_H
 852         help
 853           Support for the StrongARM based Digital DNARD machine, also known
 854           as "Shark" (<http://www.shark-linux.de/shark.html>).
 855
 856 config ARCH_U300
 857         bool "ST-Ericsson U300 Series"
 858         depends on MMU
 859         select CLKSRC_MMIO
 860         select CPU_ARM926T
 861         select HAVE_TCM
 862         select ARM_AMBA
 863         select ARM_PATCH_PHYS_VIRT
 864         select ARM_VIC
 865         select GENERIC_CLOCKEVENTS
 866         select CLKDEV_LOOKUP
 867         select COMMON_CLK
 868         select GENERIC_GPIO
 869         select ARCH_REQUIRE_GPIOLIB
 870         select SPARSE_IRQ
 871         help
 872           Support for ST-Ericsson U300 series mobile platforms.
 873
 874 config ARCH_U8500
 875         bool "ST-Ericsson U8500 Series"
 876         depends on MMU
 877         select CPU_V7
 878         select ARM_AMBA
 879         select GENERIC_CLOCKEVENTS
 880         select CLKDEV_LOOKUP
 881         select ARCH_REQUIRE_GPIOLIB
 882         select ARCH_HAS_CPUFREQ
 883         select HAVE_SMP
 884         select MIGHT_HAVE_CACHE_L2X0
 885         help
 886           Support for ST-Ericsson's Ux500 architecture
 887
 888 config ARCH_NOMADIK
 889         bool "STMicroelectronics Nomadik"
 890         select ARM_AMBA
 891         select ARM_VIC
 892         select CPU_ARM926T
 893         select COMMON_CLK
 894         select GENERIC_CLOCKEVENTS
 895         select PINCTRL
 896         select PINCTRL_STN8815
 897         select MIGHT_HAVE_CACHE_L2X0
 898         select ARCH_REQUIRE_GPIOLIB
 899         help
 900           Support for the Nomadik platform by ST-Ericsson
 901
 902 config ARCH_DAVINCI
 903         bool "TI DaVinci"
 904         select GENERIC_CLOCKEVENTS
 905         select ARCH_REQUIRE_GPIOLIB
 906         select ZONE_DMA
 907         select HAVE_IDE
 908         select CLKDEV_LOOKUP
 909         select GENERIC_ALLOCATOR
 910         select GENERIC_IRQ_CHIP
 911         select ARCH_HAS_HOLES_MEMORYMODEL
 912         select NEED_MACH_GPIO_H
 913         help
 914           Support for TI's DaVinci platform.
 915
 916 config ARCH_OMAP
 917         bool "TI OMAP"
 918         depends on MMU
 919         select HAVE_CLK
 920         select ARCH_REQUIRE_GPIOLIB
 921         select ARCH_HAS_CPUFREQ
 922         select CLKSRC_MMIO
 923         select GENERIC_CLOCKEVENTS
 924         select ARCH_HAS_HOLES_MEMORYMODEL
 925         select NEED_MACH_GPIO_H
 926         help
 927           Support for TI's OMAP platform (OMAP1/2/3/4).
 928
 929 config PLAT_SPEAR
 930         bool "ST SPEAr"
 931         select ARM_AMBA
 932         select ARCH_REQUIRE_GPIOLIB
 933         select CLKDEV_LOOKUP
 934         select COMMON_CLK
 935         select CLKSRC_MMIO
 936         select GENERIC_CLOCKEVENTS
 937         select HAVE_CLK
 938         help
 939           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 940
 941 config ARCH_VT8500
 942         bool "VIA/WonderMedia 85xx"
 943         select CPU_ARM926T
 944         select GENERIC_GPIO
 945         select ARCH_HAS_CPUFREQ
 946         select GENERIC_CLOCKEVENTS
 947         select ARCH_REQUIRE_GPIOLIB
 948         select USE_OF
 949         select COMMON_CLK
 950         select HAVE_CLK
 951         select CLKDEV_LOOKUP
 952         help
 953           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 954
 955 config ARCH_ZYNQ
 956         bool "Xilinx Zynq ARM Cortex A9 Platform"
 957         select CPU_V7
 958         select GENERIC_CLOCKEVENTS
 959         select CLKDEV_LOOKUP
 960         select ARM_GIC
 961         select ARM_AMBA
 962         select ICST
 963         select MIGHT_HAVE_CACHE_L2X0
 964         select USE_OF
 965         help
 966           Support for Xilinx Zynq ARM Cortex A9 Platform
 967 endchoice
 968
 969 menu "Multiple platform selection"
 970         depends on ARCH_MULTIPLATFORM
 971
 972 comment "CPU Core family selection"
 973
 974 config ARCH_MULTI_V4
 975         bool "ARMv4 based platforms (FA526, StrongARM)"
 976         select ARCH_MULTI_V4_V5
 977         depends on !ARCH_MULTI_V6_V7
 978
 979 config ARCH_MULTI_V4T
 980         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 981         select ARCH_MULTI_V4_V5
 982         depends on !ARCH_MULTI_V6_V7
 983
 984 config ARCH_MULTI_V5
 985         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 986         select ARCH_MULTI_V4_V5
 987         depends on !ARCH_MULTI_V6_V7
 988
 989 config ARCH_MULTI_V4_V5
 990         bool
 991
 992 config ARCH_MULTI_V6
 993         bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
 994         select CPU_V6
 995         select ARCH_MULTI_V6_V7
 996
 997 config ARCH_MULTI_V7
 998         bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
 999         select CPU_V7
1000         select ARCH_VEXPRESS
1001         default y
1002         select ARCH_MULTI_V6_V7
1003
1004 config ARCH_MULTI_V6_V7
1005         bool
1006
1007 config ARCH_MULTI_CPU_AUTO
1008         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1009         select ARCH_MULTI_V5
1010
1011 endmenu
1012
1013 #
1014 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1015 # Kconfigs may be included either alphabetically (according to the
1016 # plat- suffix) or along side the corresponding mach-* source.
1017 #
1018 source "arch/arm/mach-mvebu/Kconfig"
1019
1020 source "arch/arm/mach-at91/Kconfig"
1021
1022 source "arch/arm/mach-clps711x/Kconfig"
1023
1024 source "arch/arm/mach-cns3xxx/Kconfig"
1025
1026 source "arch/arm/mach-davinci/Kconfig"
1027
1028 source "arch/arm/mach-dove/Kconfig"
1029
1030 source "arch/arm/mach-ep93xx/Kconfig"
1031
1032 source "arch/arm/mach-footbridge/Kconfig"
1033
1034 source "arch/arm/mach-gemini/Kconfig"
1035
1036 source "arch/arm/mach-h720x/Kconfig"
1037
1038 source "arch/arm/mach-highbank/Kconfig"
1039
1040 source "arch/arm/mach-integrator/Kconfig"
1041
1042 source "arch/arm/mach-iop32x/Kconfig"
1043
1044 source "arch/arm/mach-iop33x/Kconfig"
1045
1046 source "arch/arm/mach-iop13xx/Kconfig"
1047
1048 source "arch/arm/mach-ixp4xx/Kconfig"
1049
1050 source "arch/arm/mach-kirkwood/Kconfig"
1051
1052 source "arch/arm/mach-ks8695/Kconfig"
1053
1054 source "arch/arm/mach-msm/Kconfig"
1055
1056 source "arch/arm/mach-mv78xx0/Kconfig"
1057
1058 source "arch/arm/plat-mxc/Kconfig"
1059
1060 source "arch/arm/mach-mxs/Kconfig"
1061
1062 source "arch/arm/mach-netx/Kconfig"
1063
1064 source "arch/arm/mach-nomadik/Kconfig"
1065 source "arch/arm/plat-nomadik/Kconfig"
1066
1067 source "arch/arm/plat-omap/Kconfig"
1068
1069 source "arch/arm/mach-omap1/Kconfig"
1070
1071 source "arch/arm/mach-omap2/Kconfig"
1072
1073 source "arch/arm/mach-orion5x/Kconfig"
1074
1075 source "arch/arm/mach-picoxcell/Kconfig"
1076
1077 source "arch/arm/mach-pxa/Kconfig"
1078 source "arch/arm/plat-pxa/Kconfig"
1079
1080 source "arch/arm/mach-mmp/Kconfig"
1081
1082 source "arch/arm/mach-realview/Kconfig"
1083
1084 source "arch/arm/mach-sa1100/Kconfig"
1085
1086 source "arch/arm/plat-samsung/Kconfig"
1087 source "arch/arm/plat-s3c24xx/Kconfig"
1088
1089 source "arch/arm/mach-socfpga/Kconfig"
1090
1091 source "arch/arm/plat-spear/Kconfig"
1092
1093 source "arch/arm/mach-s3c24xx/Kconfig"
1094 if ARCH_S3C24XX
1095 source "arch/arm/mach-s3c2412/Kconfig"
1096 source "arch/arm/mach-s3c2440/Kconfig"
1097 endif
1098
1099 if ARCH_S3C64XX
1100 source "arch/arm/mach-s3c64xx/Kconfig"
1101 endif
1102
1103 source "arch/arm/mach-s5p64x0/Kconfig"
1104
1105 source "arch/arm/mach-s5pc100/Kconfig"
1106
1107 source "arch/arm/mach-s5pv210/Kconfig"
1108
1109 source "arch/arm/mach-exynos/Kconfig"
1110
1111 source "arch/arm/mach-shmobile/Kconfig"
1112
1113 source "arch/arm/mach-prima2/Kconfig"
1114
1115 source "arch/arm/mach-tegra/Kconfig"
1116
1117 source "arch/arm/mach-u300/Kconfig"
1118
1119 source "arch/arm/mach-ux500/Kconfig"
1120
1121 source "arch/arm/mach-versatile/Kconfig"
1122
1123 source "arch/arm/mach-vexpress/Kconfig"
1124 source "arch/arm/plat-versatile/Kconfig"
1125
1126 source "arch/arm/mach-w90x900/Kconfig"
1127
1128 # Definitions to make life easier
1129 config ARCH_ACORN
1130         bool
1131
1132 config PLAT_IOP
1133         bool
1134         select GENERIC_CLOCKEVENTS
1135
1136 config PLAT_ORION
1137         bool
1138         select CLKSRC_MMIO
1139         select GENERIC_IRQ_CHIP
1140         select IRQ_DOMAIN
1141         select COMMON_CLK
1142
1143 config PLAT_ORION_LEGACY
1144         bool
1145         select PLAT_ORION
1146
1147 config PLAT_PXA
1148         bool
1149
1150 config PLAT_VERSATILE
1151         bool
1152
1153 config ARM_TIMER_SP804
1154         bool
1155         select CLKSRC_MMIO
1156         select HAVE_SCHED_CLOCK
1157
1158 source arch/arm/mm/Kconfig
1159
1160 config ARM_NR_BANKS
1161         int
1162         default 16 if ARCH_EP93XX
1163         default 8
1164
1165 config IWMMXT
1166         bool "Enable iWMMXt support"
1167         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1168         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1169         help
1170           Enable support for iWMMXt context switching at run time if
1171           running on a CPU that supports it.
1172
1173 config XSCALE_PMU
1174         bool
1175         depends on CPU_XSCALE
1176         default y
1177
1178 config MULTI_IRQ_HANDLER
1179         bool
1180         help
1181           Allow each machine to specify it's own IRQ handler at run time.
1182
1183 if !MMU
1184 source "arch/arm/Kconfig-nommu"
1185 endif
1186
1187 config ARM_ERRATA_326103
1188         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1189         depends on CPU_V6
1190         help
1191           Executing a SWP instruction to read-only memory does not set bit 11
1192           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1193           treat the access as a read, preventing a COW from occurring and
1194           causing the faulting task to livelock.
1195
1196 config ARM_ERRATA_411920
1197         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1198         depends on CPU_V6 || CPU_V6K
1199         help
1200           Invalidation of the Instruction Cache operation can
1201           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1202           It does not affect the MPCore. This option enables the ARM Ltd.
1203           recommended workaround.
1204
1205 config ARM_ERRATA_430973
1206         bool "ARM errata: Stale prediction on replaced interworking branch"
1207         depends on CPU_V7
1208         help
1209           This option enables the workaround for the 430973 Cortex-A8
1210           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1211           interworking branch is replaced with another code sequence at the
1212           same virtual address, whether due to self-modifying code or virtual
1213           to physical address re-mapping, Cortex-A8 does not recover from the
1214           stale interworking branch prediction. This results in Cortex-A8
1215           executing the new code sequence in the incorrect ARM or Thumb state.
1216           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1217           and also flushes the branch target cache at every context switch.
1218           Note that setting specific bits in the ACTLR register may not be
1219           available in non-secure mode.
1220
1221 config ARM_ERRATA_458693
1222         bool "ARM errata: Processor deadlock when a false hazard is created"
1223         depends on CPU_V7
1224         help
1225           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1226           erratum. For very specific sequences of memory operations, it is
1227           possible for a hazard condition intended for a cache line to instead
1228           be incorrectly associated with a different cache line. This false
1229           hazard might then cause a processor deadlock. The workaround enables
1230           the L1 caching of the NEON accesses and disables the PLD instruction
1231           in the ACTLR register. Note that setting specific bits in the ACTLR
1232           register may not be available in non-secure mode.
1233
1234 config ARM_ERRATA_460075
1235         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1236         depends on CPU_V7
1237         help
1238           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1239           erratum. Any asynchronous access to the L2 cache may encounter a
1240           situation in which recent store transactions to the L2 cache are lost
1241           and overwritten with stale memory contents from external memory. The
1242           workaround disables the write-allocate mode for the L2 cache via the
1243           ACTLR register. Note that setting specific bits in the ACTLR register
1244           may not be available in non-secure mode.
1245
1246 config ARM_ERRATA_742230
1247         bool "ARM errata: DMB operation may be faulty"
1248         depends on CPU_V7 && SMP
1249         help
1250           This option enables the workaround for the 742230 Cortex-A9
1251           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1252           between two write operations may not ensure the correct visibility
1253           ordering of the two writes. This workaround sets a specific bit in
1254           the diagnostic register of the Cortex-A9 which causes the DMB
1255           instruction to behave as a DSB, ensuring the correct behaviour of
1256           the two writes.
1257
1258 config ARM_ERRATA_742231
1259         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1260         depends on CPU_V7 && SMP
1261         help
1262           This option enables the workaround for the 742231 Cortex-A9
1263           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1264           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1265           accessing some data located in the same cache line, may get corrupted
1266           data due to bad handling of the address hazard when the line gets
1267           replaced from one of the CPUs at the same time as another CPU is
1268           accessing it. This workaround sets specific bits in the diagnostic
1269           register of the Cortex-A9 which reduces the linefill issuing
1270           capabilities of the processor.
1271
1272 config PL310_ERRATA_588369
1273         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1274         depends on CACHE_L2X0
1275         help
1276            The PL310 L2 cache controller implements three types of Clean &
1277            Invalidate maintenance operations: by Physical Address
1278            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1279            They are architecturally defined to behave as the execution of a
1280            clean operation followed immediately by an invalidate operation,
1281            both performing to the same memory location. This functionality
1282            is not correctly implemented in PL310 as clean lines are not
1283            invalidated as a result of these operations.
1284
1285 config ARM_ERRATA_720789
1286         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1287         depends on CPU_V7
1288         help
1289           This option enables the workaround for the 720789 Cortex-A9 (prior to
1290           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1291           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1292           As a consequence of this erratum, some TLB entries which should be
1293           invalidated are not, resulting in an incoherency in the system page
1294           tables. The workaround changes the TLB flushing routines to invalidate
1295           entries regardless of the ASID.
1296
1297 config PL310_ERRATA_727915
1298         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1299         depends on CACHE_L2X0
1300         help
1301           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1302           operation (offset 0x7FC). This operation runs in background so that
1303           PL310 can handle normal accesses while it is in progress. Under very
1304           rare circumstances, due to this erratum, write data can be lost when
1305           PL310 treats a cacheable write transaction during a Clean &
1306           Invalidate by Way operation.
1307
1308 config ARM_ERRATA_743622
1309         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1310         depends on CPU_V7
1311         help
1312           This option enables the workaround for the 743622 Cortex-A9
1313           (r2p*) erratum. Under very rare conditions, a faulty
1314           optimisation in the Cortex-A9 Store Buffer may lead to data
1315           corruption. This workaround sets a specific bit in the diagnostic
1316           register of the Cortex-A9 which disables the Store Buffer
1317           optimisation, preventing the defect from occurring. This has no
1318           visible impact on the overall performance or power consumption of the
1319           processor.
1320
1321 config ARM_ERRATA_751472
1322         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1323         depends on CPU_V7
1324         help
1325           This option enables the workaround for the 751472 Cortex-A9 (prior
1326           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1327           completion of a following broadcasted operation if the second
1328           operation is received by a CPU before the ICIALLUIS has completed,
1329           potentially leading to corrupted entries in the cache or TLB.
1330
1331 config PL310_ERRATA_753970
1332         bool "PL310 errata: cache sync operation may be faulty"
1333         depends on CACHE_PL310
1334         help
1335           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1336
1337           Under some condition the effect of cache sync operation on
1338           the store buffer still remains when the operation completes.
1339           This means that the store buffer is always asked to drain and
1340           this prevents it from merging any further writes. The workaround
1341           is to replace the normal offset of cache sync operation (0x730)
1342           by another offset targeting an unmapped PL310 register 0x740.
1343           This has the same effect as the cache sync operation: store buffer
1344           drain and waiting for all buffers empty.
1345
1346 config ARM_ERRATA_754322
1347         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1348         depends on CPU_V7
1349         help
1350           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1351           r3p*) erratum. A speculative memory access may cause a page table walk
1352           which starts prior to an ASID switch but completes afterwards. This
1353           can populate the micro-TLB with a stale entry which may be hit with
1354           the new ASID. This workaround places two dsb instructions in the mm
1355           switching code so that no page table walks can cross the ASID switch.
1356
1357 config ARM_ERRATA_754327
1358         bool "ARM errata: no automatic Store Buffer drain"
1359         depends on CPU_V7 && SMP
1360         help
1361           This option enables the workaround for the 754327 Cortex-A9 (prior to
1362           r2p0) erratum. The Store Buffer does not have any automatic draining
1363           mechanism and therefore a livelock may occur if an external agent
1364           continuously polls a memory location waiting to observe an update.
1365           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1366           written polling loops from denying visibility of updates to memory.
1367
1368 config ARM_ERRATA_364296
1369         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1370         depends on CPU_V6 && !SMP
1371         help
1372           This options enables the workaround for the 364296 ARM1136
1373           r0p2 erratum (possible cache data corruption with
1374           hit-under-miss enabled). It sets the undocumented bit 31 in
1375           the auxiliary control register and the FI bit in the control
1376           register, thus disabling hit-under-miss without putting the
1377           processor into full low interrupt latency mode. ARM11MPCore
1378           is not affected.
1379
1380 config ARM_ERRATA_764369
1381         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1382         depends on CPU_V7 && SMP
1383         help
1384           This option enables the workaround for erratum 764369
1385           affecting Cortex-A9 MPCore with two or more processors (all
1386           current revisions). Under certain timing circumstances, a data
1387           cache line maintenance operation by MVA targeting an Inner
1388           Shareable memory region may fail to proceed up to either the
1389           Point of Coherency or to the Point of Unification of the
1390           system. This workaround adds a DSB instruction before the
1391           relevant cache maintenance functions and sets a specific bit
1392           in the diagnostic control register of the SCU.
1393
1394 config PL310_ERRATA_769419
1395         bool "PL310 errata: no automatic Store Buffer drain"
1396         depends on CACHE_L2X0
1397         help
1398           On revisions of the PL310 prior to r3p2, the Store Buffer does
1399           not automatically drain. This can cause normal, non-cacheable
1400           writes to be retained when the memory system is idle, leading
1401           to suboptimal I/O performance for drivers using coherent DMA.
1402           This option adds a write barrier to the cpu_idle loop so that,
1403           on systems with an outer cache, the store buffer is drained
1404           explicitly.
1405
1406 config ARM_ERRATA_775420
1407        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1408        depends on CPU_V7
1409        help
1410          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1411          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1412          operation aborts with MMU exception, it might cause the processor
1413          to deadlock. This workaround puts DSB before executing ISB if
1414          an abort may occur on cache maintenance.
1415
1416 endmenu
1417
1418 source "arch/arm/common/Kconfig"
1419
1420 menu "Bus support"
1421
1422 config ARM_AMBA
1423         bool
1424
1425 config ISA
1426         bool
1427         help
1428           Find out whether you have ISA slots on your motherboard.  ISA is the
1429           name of a bus system, i.e. the way the CPU talks to the other stuff
1430           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1431           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1432           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1433
1434 # Select ISA DMA controller support
1435 config ISA_DMA
1436         bool
1437         select ISA_DMA_API
1438
1439 # Select ISA DMA interface
1440 config ISA_DMA_API
1441         bool
1442
1443 config PCI
1444         bool "PCI support" if MIGHT_HAVE_PCI
1445         help
1446           Find out whether you have a PCI motherboard. PCI is the name of a
1447           bus system, i.e. the way the CPU talks to the other stuff inside
1448           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1449           VESA. If you have PCI, say Y, otherwise N.
1450
1451 config PCI_DOMAINS
1452         bool
1453         depends on PCI
1454
1455 config PCI_NANOENGINE
1456         bool "BSE nanoEngine PCI support"
1457         depends on SA1100_NANOENGINE
1458         help
1459           Enable PCI on the BSE nanoEngine board.
1460
1461 config PCI_SYSCALL
1462         def_bool PCI
1463
1464 # Select the host bridge type
1465 config PCI_HOST_VIA82C505
1466         bool
1467         depends on PCI && ARCH_SHARK
1468         default y
1469
1470 config PCI_HOST_ITE8152
1471         bool
1472         depends on PCI && MACH_ARMCORE
1473         default y
1474         select DMABOUNCE
1475
1476 source "drivers/pci/Kconfig"
1477
1478 source "drivers/pcmcia/Kconfig"
1479
1480 endmenu
1481
1482 menu "Kernel Features"
1483
1484 config HAVE_SMP
1485         bool
1486         help
1487           This option should be selected by machines which have an SMP-
1488           capable CPU.
1489
1490           The only effect of this option is to make the SMP-related
1491           options available to the user for configuration.
1492
1493 config SMP
1494         bool "Symmetric Multi-Processing"
1495         depends on CPU_V6K || CPU_V7
1496         depends on GENERIC_CLOCKEVENTS
1497         depends on HAVE_SMP
1498         depends on MMU
1499         select USE_GENERIC_SMP_HELPERS
1500         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1501         help
1502           This enables support for systems with more than one CPU. If you have
1503           a system with only one CPU, like most personal computers, say N. If
1504           you have a system with more than one CPU, say Y.
1505
1506           If you say N here, the kernel will run on single and multiprocessor
1507           machines, but will use only one CPU of a multiprocessor machine. If
1508           you say Y here, the kernel will run on many, but not all, single
1509           processor machines. On a single processor machine, the kernel will
1510           run faster if you say N here.
1511
1512           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1513           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1514           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1515
1516           If you don't know what to do here, say N.
1517
1518 config SMP_ON_UP
1519         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1520         depends on EXPERIMENTAL
1521         depends on SMP && !XIP_KERNEL
1522         default y
1523         help
1524           SMP kernels contain instructions which fail on non-SMP processors.
1525           Enabling this option allows the kernel to modify itself to make
1526           these instructions safe.  Disabling it allows about 1K of space
1527           savings.
1528
1529           If you don't know what to do here, say Y.
1530
1531 config ARM_CPU_TOPOLOGY
1532         bool "Support cpu topology definition"
1533         depends on SMP && CPU_V7
1534         default y
1535         help
1536           Support ARM cpu topology definition. The MPIDR register defines
1537           affinity between processors which is then used to describe the cpu
1538           topology of an ARM System.
1539
1540 config SCHED_MC
1541         bool "Multi-core scheduler support"
1542         depends on ARM_CPU_TOPOLOGY
1543         help
1544           Multi-core scheduler support improves the CPU scheduler's decision
1545           making when dealing with multi-core CPU chips at a cost of slightly
1546           increased overhead in some places. If unsure say N here.
1547
1548 config SCHED_SMT
1549         bool "SMT scheduler support"
1550         depends on ARM_CPU_TOPOLOGY
1551         help
1552           Improves the CPU scheduler's decision making when dealing with
1553           MultiThreading at a cost of slightly increased overhead in some
1554           places. If unsure say N here.
1555
1556 config HAVE_ARM_SCU
1557         bool
1558         help
1559           This option enables support for the ARM system coherency unit
1560
1561 config ARM_ARCH_TIMER
1562         bool "Architected timer support"
1563         depends on CPU_V7
1564         help
1565           This option enables support for the ARM architected timer
1566
1567 config HAVE_ARM_TWD
1568         bool
1569         depends on SMP
1570         help
1571           This options enables support for the ARM timer and watchdog unit
1572
1573 choice
1574         prompt "Memory split"
1575         default VMSPLIT_3G
1576         help
1577           Select the desired split between kernel and user memory.
1578
1579           If you are not absolutely sure what you are doing, leave this
1580           option alone!
1581
1582         config VMSPLIT_3G
1583                 bool "3G/1G user/kernel split"
1584         config VMSPLIT_2G
1585                 bool "2G/2G user/kernel split"
1586         config VMSPLIT_1G
1587                 bool "1G/3G user/kernel split"
1588 endchoice
1589
1590 config PAGE_OFFSET
1591         hex
1592         default 0x40000000 if VMSPLIT_1G
1593         default 0x80000000 if VMSPLIT_2G
1594         default 0xC0000000
1595
1596 config NR_CPUS
1597         int "Maximum number of CPUs (2-32)"
1598         range 2 32
1599         depends on SMP
1600         default "4"
1601
1602 config HOTPLUG_CPU
1603         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1604         depends on SMP && HOTPLUG && EXPERIMENTAL
1605         help
1606           Say Y here to experiment with turning CPUs off and on.  CPUs
1607           can be controlled through /sys/devices/system/cpu.
1608
1609 config LOCAL_TIMERS
1610         bool "Use local timer interrupts"
1611         depends on SMP
1612         default y
1613         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1614         help
1615           Enable support for local timers on SMP platforms, rather then the
1616           legacy IPI broadcast method.  Local timers allows the system
1617           accounting to be spread across the timer interval, preventing a
1618           "thundering herd" at every timer tick.
1619
1620 config ARCH_NR_GPIO
1621         int
1622         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1623         default 355 if ARCH_U8500
1624         default 264 if MACH_H4700
1625         default 512 if SOC_OMAP5
1626         default 288 if ARCH_VT8500
1627         default 0
1628         help
1629           Maximum number of GPIOs in the system.
1630
1631           If unsure, leave the default value.
1632
1633 source kernel/Kconfig.preempt
1634
1635 config HZ
1636         int
1637         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1638                 ARCH_S5PV210 || ARCH_EXYNOS4
1639         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1640         default AT91_TIMER_HZ if ARCH_AT91
1641         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1642         default 100
1643
1644 config THUMB2_KERNEL
1645         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1646         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1647         select AEABI
1648         select ARM_ASM_UNIFIED
1649         select ARM_UNWIND
1650         help
1651           By enabling this option, the kernel will be compiled in
1652           Thumb-2 mode. A compiler/assembler that understand the unified
1653           ARM-Thumb syntax is needed.
1654
1655           If unsure, say N.
1656
1657 config THUMB2_AVOID_R_ARM_THM_JUMP11
1658         bool "Work around buggy Thumb-2 short branch relocations in gas"
1659         depends on THUMB2_KERNEL && MODULES
1660         default y
1661         help
1662           Various binutils versions can resolve Thumb-2 branches to
1663           locally-defined, preemptible global symbols as short-range "b.n"
1664           branch instructions.
1665
1666           This is a problem, because there's no guarantee the final
1667           destination of the symbol, or any candidate locations for a
1668           trampoline, are within range of the branch.  For this reason, the
1669           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1670           relocation in modules at all, and it makes little sense to add
1671           support.
1672
1673           The symptom is that the kernel fails with an "unsupported
1674           relocation" error when loading some modules.
1675
1676           Until fixed tools are available, passing
1677           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1678           code which hits this problem, at the cost of a bit of extra runtime
1679           stack usage in some cases.
1680
1681           The problem is described in more detail at:
1682               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1683
1684           Only Thumb-2 kernels are affected.
1685
1686           Unless you are sure your tools don't have this problem, say Y.
1687
1688 config ARM_ASM_UNIFIED
1689         bool
1690
1691 config AEABI
1692         bool "Use the ARM EABI to compile the kernel"
1693         help
1694           This option allows for the kernel to be compiled using the latest
1695           ARM ABI (aka EABI).  This is only useful if you are using a user
1696           space environment that is also compiled with EABI.
1697
1698           Since there are major incompatibilities between the legacy ABI and
1699           EABI, especially with regard to structure member alignment, this
1700           option also changes the kernel syscall calling convention to
1701           disambiguate both ABIs and allow for backward compatibility support
1702           (selected with CONFIG_OABI_COMPAT).
1703
1704           To use this you need GCC version 4.0.0 or later.
1705
1706 config OABI_COMPAT
1707         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1708         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1709         default y
1710         help
1711           This option preserves the old syscall interface along with the
1712           new (ARM EABI) one. It also provides a compatibility layer to
1713           intercept syscalls that have structure arguments which layout
1714           in memory differs between the legacy ABI and the new ARM EABI
1715           (only for non "thumb" binaries). This option adds a tiny
1716           overhead to all syscalls and produces a slightly larger kernel.
1717           If you know you'll be using only pure EABI user space then you
1718           can say N here. If this option is not selected and you attempt
1719           to execute a legacy ABI binary then the result will be
1720           UNPREDICTABLE (in fact it can be predicted that it won't work
1721           at all). If in doubt say Y.
1722
1723 config ARCH_HAS_HOLES_MEMORYMODEL
1724         bool
1725
1726 config ARCH_SPARSEMEM_ENABLE
1727         bool
1728
1729 config ARCH_SPARSEMEM_DEFAULT
1730         def_bool ARCH_SPARSEMEM_ENABLE
1731
1732 config ARCH_SELECT_MEMORY_MODEL
1733         def_bool ARCH_SPARSEMEM_ENABLE
1734
1735 config HAVE_ARCH_PFN_VALID
1736         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1737
1738 config HIGHMEM
1739         bool "High Memory Support"
1740         depends on MMU
1741         help
1742           The address space of ARM processors is only 4 Gigabytes large
1743           and it has to accommodate user address space, kernel address
1744           space as well as some memory mapped IO. That means that, if you
1745           have a large amount of physical memory and/or IO, not all of the
1746           memory can be "permanently mapped" by the kernel. The physical
1747           memory that is not permanently mapped is called "high memory".
1748
1749           Depending on the selected kernel/user memory split, minimum
1750           vmalloc space and actual amount of RAM, you may not need this
1751           option which should result in a slightly faster kernel.
1752
1753           If unsure, say n.
1754
1755 config HIGHPTE
1756         bool "Allocate 2nd-level pagetables from highmem"
1757         depends on HIGHMEM
1758
1759 config HW_PERF_EVENTS
1760         bool "Enable hardware performance counter support for perf events"
1761         depends on PERF_EVENTS
1762         default y
1763         help
1764           Enable hardware performance counter support for perf events. If
1765           disabled, perf events will use software events only.
1766
1767 source "mm/Kconfig"
1768
1769 config FORCE_MAX_ZONEORDER
1770         int "Maximum zone order" if ARCH_SHMOBILE
1771         range 11 64 if ARCH_SHMOBILE
1772         default "9" if SA1111
1773         default "11"
1774         help
1775           The kernel memory allocator divides physically contiguous memory
1776           blocks into "zones", where each zone is a power of two number of
1777           pages.  This option selects the largest power of two that the kernel
1778           keeps in the memory allocator.  If you need to allocate very large
1779           blocks of physically contiguous memory, then you may need to
1780           increase this value.
1781
1782           This config option is actually maximum order plus one. For example,
1783           a value of 11 means that the largest free memory block is 2^10 pages.
1784
1785 config ALIGNMENT_TRAP
1786         bool
1787         depends on CPU_CP15_MMU
1788         default y if !ARCH_EBSA110
1789         select HAVE_PROC_CPU if PROC_FS
1790         help
1791           ARM processors cannot fetch/store information which is not
1792           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1793           address divisible by 4. On 32-bit ARM processors, these non-aligned
1794           fetch/store instructions will be emulated in software if you say
1795           here, which has a severe performance impact. This is necessary for
1796           correct operation of some network protocols. With an IP-only
1797           configuration it is safe to say N, otherwise say Y.
1798
1799 config UACCESS_WITH_MEMCPY
1800         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1801         depends on MMU
1802         default y if CPU_FEROCEON
1803         help
1804           Implement faster copy_to_user and clear_user methods for CPU
1805           cores where a 8-word STM instruction give significantly higher
1806           memory write throughput than a sequence of individual 32bit stores.
1807
1808           A possible side effect is a slight increase in scheduling latency
1809           between threads sharing the same address space if they invoke
1810           such copy operations with large buffers.
1811
1812           However, if the CPU data cache is using a write-allocate mode,
1813           this option is unlikely to provide any performance gain.
1814
1815 config SECCOMP
1816         bool
1817         prompt "Enable seccomp to safely compute untrusted bytecode"
1818         ---help---
1819           This kernel feature is useful for number crunching applications
1820           that may need to compute untrusted bytecode during their
1821           execution. By using pipes or other transports made available to
1822           the process as file descriptors supporting the read/write
1823           syscalls, it's possible to isolate those applications in
1824           their own address space using seccomp. Once seccomp is
1825           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1826           and the task is only allowed to execute a few safe syscalls
1827           defined by each seccomp mode.
1828
1829 config CC_STACKPROTECTOR
1830         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1831         depends on EXPERIMENTAL
1832         help
1833           This option turns on the -fstack-protector GCC feature. This
1834           feature puts, at the beginning of functions, a canary value on
1835           the stack just before the return address, and validates
1836           the value just before actually returning.  Stack based buffer
1837           overflows (that need to overwrite this return address) now also
1838           overwrite the canary, which gets detected and the attack is then
1839           neutralized via a kernel panic.
1840           This feature requires gcc version 4.2 or above.
1841
1842 config XEN_DOM0
1843         def_bool y
1844         depends on XEN
1845
1846 config XEN
1847         bool "Xen guest support on ARM (EXPERIMENTAL)"
1848         depends on EXPERIMENTAL && ARM && OF
1849         help
1850           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1851
1852 endmenu
1853
1854 menu "Boot options"
1855
1856 config USE_OF
1857         bool "Flattened Device Tree support"
1858         select OF
1859         select OF_EARLY_FLATTREE
1860         select IRQ_DOMAIN
1861         help
1862           Include support for flattened device tree machine descriptions.
1863
1864 config ATAGS
1865         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1866         default y
1867         help
1868           This is the traditional way of passing data to the kernel at boot
1869           time. If you are solely relying on the flattened device tree (or
1870           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1871           to remove ATAGS support from your kernel binary.  If unsure,
1872           leave this to y.
1873
1874 config DEPRECATED_PARAM_STRUCT
1875         bool "Provide old way to pass kernel parameters"
1876         depends on ATAGS
1877         help
1878           This was deprecated in 2001 and announced to live on for 5 years.
1879           Some old boot loaders still use this way.
1880
1881 # Compressed boot loader in ROM.  Yes, we really want to ask about
1882 # TEXT and BSS so we preserve their values in the config files.
1883 config ZBOOT_ROM_TEXT
1884         hex "Compressed ROM boot loader base address"
1885         default "0"
1886         help
1887           The physical address at which the ROM-able zImage is to be
1888           placed in the target.  Platforms which normally make use of
1889           ROM-able zImage formats normally set this to a suitable
1890           value in their defconfig file.
1891
1892           If ZBOOT_ROM is not enabled, this has no effect.
1893
1894 config ZBOOT_ROM_BSS
1895         hex "Compressed ROM boot loader BSS address"
1896         default "0"
1897         help
1898           The base address of an area of read/write memory in the target
1899           for the ROM-able zImage which must be available while the
1900           decompressor is running. It must be large enough to hold the
1901           entire decompressed kernel plus an additional 128 KiB.
1902           Platforms which normally make use of ROM-able zImage formats
1903           normally set this to a suitable value in their defconfig file.
1904
1905           If ZBOOT_ROM is not enabled, this has no effect.
1906
1907 config ZBOOT_ROM
1908         bool "Compressed boot loader in ROM/flash"
1909         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1910         help
1911           Say Y here if you intend to execute your compressed kernel image
1912           (zImage) directly from ROM or flash.  If unsure, say N.
1913
1914 choice
1915         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1916         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1917         default ZBOOT_ROM_NONE
1918         help
1919           Include experimental SD/MMC loading code in the ROM-able zImage.
1920           With this enabled it is possible to write the ROM-able zImage
1921           kernel image to an MMC or SD card and boot the kernel straight
1922           from the reset vector. At reset the processor Mask ROM will load
1923           the first part of the ROM-able zImage which in turn loads the
1924           rest the kernel image to RAM.
1925
1926 config ZBOOT_ROM_NONE
1927         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1928         help
1929           Do not load image from SD or MMC
1930
1931 config ZBOOT_ROM_MMCIF
1932         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1933         help
1934           Load image from MMCIF hardware block.
1935
1936 config ZBOOT_ROM_SH_MOBILE_SDHI
1937         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1938         help
1939           Load image from SDHI hardware block
1940
1941 endchoice
1942
1943 config ARM_APPENDED_DTB
1944         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1945         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1946         help
1947           With this option, the boot code will look for a device tree binary
1948           (DTB) appended to zImage
1949           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1950
1951           This is meant as a backward compatibility convenience for those
1952           systems with a bootloader that can't be upgraded to accommodate
1953           the documented boot protocol using a device tree.
1954
1955           Beware that there is very little in terms of protection against
1956           this option being confused by leftover garbage in memory that might
1957           look like a DTB header after a reboot if no actual DTB is appended
1958           to zImage.  Do not leave this option active in a production kernel
1959           if you don't intend to always append a DTB.  Proper passing of the
1960           location into r2 of a bootloader provided DTB is always preferable
1961           to this option.
1962
1963 config ARM_ATAG_DTB_COMPAT
1964         bool "Supplement the appended DTB with traditional ATAG information"
1965         depends on ARM_APPENDED_DTB
1966         help
1967           Some old bootloaders can't be updated to a DTB capable one, yet
1968           they provide ATAGs with memory configuration, the ramdisk address,
1969           the kernel cmdline string, etc.  Such information is dynamically
1970           provided by the bootloader and can't always be stored in a static
1971           DTB.  To allow a device tree enabled kernel to be used with such
1972           bootloaders, this option allows zImage to extract the information
1973           from the ATAG list and store it at run time into the appended DTB.
1974
1975 choice
1976         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1977         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1978
1979 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1980         bool "Use bootloader kernel arguments if available"
1981         help
1982           Uses the command-line options passed by the boot loader instead of
1983           the device tree bootargs property. If the boot loader doesn't provide
1984           any, the device tree bootargs property will be used.
1985
1986 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1987         bool "Extend with bootloader kernel arguments"
1988         help
1989           The command-line arguments provided by the boot loader will be
1990           appended to the the device tree bootargs property.
1991
1992 endchoice
1993
1994 config CMDLINE
1995         string "Default kernel command string"
1996         default ""
1997         help
1998           On some architectures (EBSA110 and CATS), there is currently no way
1999           for the boot loader to pass arguments to the kernel. For these
2000           architectures, you should supply some command-line options at build
2001           time by entering them here. As a minimum, you should specify the
2002           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2003
2004 choice
2005         prompt "Kernel command line type" if CMDLINE != ""
2006         default CMDLINE_FROM_BOOTLOADER
2007         depends on ATAGS
2008
2009 config CMDLINE_FROM_BOOTLOADER
2010         bool "Use bootloader kernel arguments if available"
2011         help
2012           Uses the command-line options passed by the boot loader. If
2013           the boot loader doesn't provide any, the default kernel command
2014           string provided in CMDLINE will be used.
2015
2016 config CMDLINE_EXTEND
2017         bool "Extend bootloader kernel arguments"
2018         help
2019           The command-line arguments provided by the boot loader will be
2020           appended to the default kernel command string.
2021
2022 config CMDLINE_FORCE
2023         bool "Always use the default kernel command string"
2024         help
2025           Always use the default kernel command string, even if the boot
2026           loader passes other arguments to the kernel.
2027           This is useful if you cannot or don't want to change the
2028           command-line options your boot loader passes to the kernel.
2029 endchoice
2030
2031 config XIP_KERNEL
2032         bool "Kernel Execute-In-Place from ROM"
2033         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2034         help
2035           Execute-In-Place allows the kernel to run from non-volatile storage
2036           directly addressable by the CPU, such as NOR flash. This saves RAM
2037           space since the text section of the kernel is not loaded from flash
2038           to RAM.  Read-write sections, such as the data section and stack,
2039           are still copied to RAM.  The XIP kernel is not compressed since
2040           it has to run directly from flash, so it will take more space to
2041           store it.  The flash address used to link the kernel object files,
2042           and for storing it, is configuration dependent. Therefore, if you
2043           say Y here, you must know the proper physical address where to
2044           store the kernel image depending on your own flash memory usage.
2045
2046           Also note that the make target becomes "make xipImage" rather than
2047           "make zImage" or "make Image".  The final kernel binary to put in
2048           ROM memory will be arch/arm/boot/xipImage.
2049
2050           If unsure, say N.
2051
2052 config XIP_PHYS_ADDR
2053         hex "XIP Kernel Physical Location"
2054         depends on XIP_KERNEL
2055         default "0x00080000"
2056         help
2057           This is the physical address in your flash memory the kernel will
2058           be linked for and stored to.  This address is dependent on your
2059           own flash usage.
2060
2061 config KEXEC
2062         bool "Kexec system call (EXPERIMENTAL)"
2063         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2064         help
2065           kexec is a system call that implements the ability to shutdown your
2066           current kernel, and to start another kernel.  It is like a reboot
2067           but it is independent of the system firmware.   And like a reboot
2068           you can start any kernel with it, not just Linux.
2069
2070           It is an ongoing process to be certain the hardware in a machine
2071           is properly shutdown, so do not be surprised if this code does not
2072           initially work for you.  It may help to enable device hotplugging
2073           support.
2074
2075 config ATAGS_PROC
2076         bool "Export atags in procfs"
2077         depends on ATAGS && KEXEC
2078         default y
2079         help
2080           Should the atags used to boot the kernel be exported in an "atags"
2081           file in procfs. Useful with kexec.
2082
2083 config CRASH_DUMP
2084         bool "Build kdump crash kernel (EXPERIMENTAL)"
2085         depends on EXPERIMENTAL
2086         help
2087           Generate crash dump after being started by kexec. This should
2088           be normally only set in special crash dump kernels which are
2089           loaded in the main kernel with kexec-tools into a specially
2090           reserved region and then later executed after a crash by
2091           kdump/kexec. The crash dump kernel must be compiled to a
2092           memory address not used by the main kernel
2093
2094           For more details see Documentation/kdump/kdump.txt
2095
2096 config AUTO_ZRELADDR
2097         bool "Auto calculation of the decompressed kernel image address"
2098         depends on !ZBOOT_ROM && !ARCH_U300
2099         help
2100           ZRELADDR is the physical address where the decompressed kernel
2101           image will be placed. If AUTO_ZRELADDR is selected, the address
2102           will be determined at run-time by masking the current IP with
2103           0xf8000000. This assumes the zImage being placed in the first 128MB
2104           from start of memory.
2105
2106 endmenu
2107
2108 menu "CPU Power Management"
2109
2110 if ARCH_HAS_CPUFREQ
2111
2112 source "drivers/cpufreq/Kconfig"
2113
2114 config CPU_FREQ_IMX
2115         tristate "CPUfreq driver for i.MX CPUs"
2116         depends on ARCH_MXC && CPU_FREQ
2117         select CPU_FREQ_TABLE
2118         help
2119           This enables the CPUfreq driver for i.MX CPUs.
2120
2121 config CPU_FREQ_SA1100
2122         bool
2123
2124 config CPU_FREQ_SA1110
2125         bool
2126
2127 config CPU_FREQ_INTEGRATOR
2128         tristate "CPUfreq driver for ARM Integrator CPUs"
2129         depends on ARCH_INTEGRATOR && CPU_FREQ
2130         default y
2131         help
2132           This enables the CPUfreq driver for ARM Integrator CPUs.
2133
2134           For details, take a look at <file:Documentation/cpu-freq>.
2135
2136           If in doubt, say Y.
2137
2138 config CPU_FREQ_PXA
2139         bool
2140         depends on CPU_FREQ && ARCH_PXA && PXA25x
2141         default y
2142         select CPU_FREQ_TABLE
2143         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2144
2145 config CPU_FREQ_S3C
2146         bool
2147         help
2148           Internal configuration node for common cpufreq on Samsung SoC
2149
2150 config CPU_FREQ_S3C24XX
2151         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2152         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2153         select CPU_FREQ_S3C
2154         help
2155           This enables the CPUfreq driver for the Samsung S3C24XX family
2156           of CPUs.
2157
2158           For details, take a look at <file:Documentation/cpu-freq>.
2159
2160           If in doubt, say N.
2161
2162 config CPU_FREQ_S3C24XX_PLL
2163         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2164         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2165         help
2166           Compile in support for changing the PLL frequency from the
2167           S3C24XX series CPUfreq driver. The PLL takes time to settle
2168           after a frequency change, so by default it is not enabled.
2169
2170           This also means that the PLL tables for the selected CPU(s) will
2171           be built which may increase the size of the kernel image.
2172
2173 config CPU_FREQ_S3C24XX_DEBUG
2174         bool "Debug CPUfreq Samsung driver core"
2175         depends on CPU_FREQ_S3C24XX
2176         help
2177           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2178
2179 config CPU_FREQ_S3C24XX_IODEBUG
2180         bool "Debug CPUfreq Samsung driver IO timing"
2181         depends on CPU_FREQ_S3C24XX
2182         help
2183           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2184
2185 config CPU_FREQ_S3C24XX_DEBUGFS
2186         bool "Export debugfs for CPUFreq"
2187         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2188         help
2189           Export status information via debugfs.
2190
2191 endif
2192
2193 source "drivers/cpuidle/Kconfig"
2194
2195 endmenu
2196
2197 menu "Floating point emulation"
2198
2199 comment "At least one emulation must be selected"
2200
2201 config FPE_NWFPE
2202         bool "NWFPE math emulation"
2203         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2204         ---help---
2205           Say Y to include the NWFPE floating point emulator in the kernel.
2206           This is necessary to run most binaries. Linux does not currently
2207           support floating point hardware so you need to say Y here even if
2208           your machine has an FPA or floating point co-processor podule.
2209
2210           You may say N here if you are going to load the Acorn FPEmulator
2211           early in the bootup.
2212
2213 config FPE_NWFPE_XP
2214         bool "Support extended precision"
2215         depends on FPE_NWFPE
2216         help
2217           Say Y to include 80-bit support in the kernel floating-point
2218           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2219           Note that gcc does not generate 80-bit operations by default,
2220           so in most cases this option only enlarges the size of the
2221           floating point emulator without any good reason.
2222
2223           You almost surely want to say N here.
2224
2225 config FPE_FASTFPE
2226         bool "FastFPE math emulation (EXPERIMENTAL)"
2227         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2228         ---help---
2229           Say Y here to include the FAST floating point emulator in the kernel.
2230           This is an experimental much faster emulator which now also has full
2231           precision for the mantissa.  It does not support any exceptions.
2232           It is very simple, and approximately 3-6 times faster than NWFPE.
2233
2234           It should be sufficient for most programs.  It may be not suitable
2235           for scientific calculations, but you have to check this for yourself.
2236           If you do not feel you need a faster FP emulation you should better
2237           choose NWFPE.
2238
2239 config VFP
2240         bool "VFP-format floating point maths"
2241         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2242         help
2243           Say Y to include VFP support code in the kernel. This is needed
2244           if your hardware includes a VFP unit.
2245
2246           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2247           release notes and additional status information.
2248
2249           Say N if your target does not have VFP hardware.
2250
2251 config VFPv3
2252         bool
2253         depends on VFP
2254         default y if CPU_V7
2255
2256 config NEON
2257         bool "Advanced SIMD (NEON) Extension support"
2258         depends on VFPv3 && CPU_V7
2259         help
2260           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2261           Extension.
2262
2263 endmenu
2264
2265 menu "Userspace binary formats"
2266
2267 source "fs/Kconfig.binfmt"
2268
2269 config ARTHUR
2270         tristate "RISC OS personality"
2271         depends on !AEABI
2272         help
2273           Say Y here to include the kernel code necessary if you want to run
2274           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2275           experimental; if this sounds frightening, say N and sleep in peace.
2276           You can also say M here to compile this support as a module (which
2277           will be called arthur).
2278
2279 endmenu
2280
2281 menu "Power management options"
2282
2283 source "kernel/power/Kconfig"
2284
2285 config ARCH_SUSPEND_POSSIBLE
2286         depends on !ARCH_S5PC100
2287         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2288                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2289         def_bool y
2290
2291 config ARM_CPU_SUSPEND
2292         def_bool PM_SLEEP
2293
2294 endmenu
2295
2296 source "net/Kconfig"
2297
2298 source "drivers/Kconfig"
2299
2300 source "fs/Kconfig"
2301
2302 source "arch/arm/Kconfig.debug"
2303
2304 source "security/Kconfig"
2305
2306 source "crypto/Kconfig"
2307
2308 source "lib/Kconfig"