arch/arm/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0
   2 config ARM
   3         bool
   4         default y
   5         select ARCH_CLOCKSOURCE_DATA
   6         select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
   7         select ARCH_HAS_DEBUG_VIRTUAL if MMU
   8         select ARCH_HAS_DEVMEM_IS_ALLOWED
   9         select ARCH_HAS_ELF_RANDOMIZE
  10         select ARCH_HAS_FORTIFY_SOURCE
  11         select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
  12         select ARCH_HAS_SET_MEMORY
  13         select ARCH_HAS_PHYS_TO_DMA
  14         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  15         select ARCH_HAS_STRICT_MODULE_RWX if MMU
  16         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  17         select ARCH_HAVE_CUSTOM_GPIO_H
  18         select ARCH_HAS_GCOV_PROFILE_ALL
  19         select ARCH_MIGHT_HAVE_PC_PARPORT
  20         select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  21         select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  22         select ARCH_SUPPORTS_ATOMIC_RMW
  23         select ARCH_USE_BUILTIN_BSWAP
  24         select ARCH_USE_CMPXCHG_LOCKREF
  25         select ARCH_WANT_IPC_PARSE_VERSION
  26         select BUILDTIME_EXTABLE_SORT if MMU
  27         select CLONE_BACKWARDS
  28         select CPU_PM if (SUSPEND || CPU_IDLE)
  29         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  30         select DMA_DIRECT_OPS if !MMU
  31         select EDAC_SUPPORT
  32         select EDAC_ATOMIC_SCRUB
  33         select GENERIC_ALLOCATOR
  34         select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  35         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  36         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  37         select GENERIC_CPU_AUTOPROBE
  38         select GENERIC_EARLY_IOREMAP
  39         select GENERIC_IDLE_POLL_SETUP
  40         select GENERIC_IRQ_PROBE
  41         select GENERIC_IRQ_SHOW
  42         select GENERIC_IRQ_SHOW_LEVEL
  43         select GENERIC_PCI_IOMAP
  44         select GENERIC_SCHED_CLOCK
  45         select GENERIC_SMP_IDLE_THREAD
  46         select GENERIC_STRNCPY_FROM_USER
  47         select GENERIC_STRNLEN_USER
  48         select HANDLE_DOMAIN_IRQ
  49         select HARDIRQS_SW_RESEND
  50         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  51         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  52         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  53         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  54         select HAVE_ARCH_MMAP_RND_BITS if MMU
  55         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  56         select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  57         select HAVE_ARCH_TRACEHOOK
  58         select HAVE_ARM_SMCCC if CPU_V7
  59         select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  60         select HAVE_CC_STACKPROTECTOR
  61         select HAVE_CONTEXT_TRACKING
  62         select HAVE_C_RECORDMCOUNT
  63         select HAVE_DEBUG_KMEMLEAK
  64         select HAVE_DMA_CONTIGUOUS if MMU
  65         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  66         select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  67         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  68         select HAVE_EXIT_THREAD
  69         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  70         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  71         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  72         select HAVE_GCC_PLUGINS
  73         select HAVE_GENERIC_DMA_COHERENT
  74         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  75         select HAVE_IDE if PCI || ISA || PCMCIA
  76         select HAVE_IRQ_TIME_ACCOUNTING
  77         select HAVE_KERNEL_GZIP
  78         select HAVE_KERNEL_LZ4
  79         select HAVE_KERNEL_LZMA
  80         select HAVE_KERNEL_LZO
  81         select HAVE_KERNEL_XZ
  82         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  83         select HAVE_KRETPROBES if (HAVE_KPROBES)
  84         select HAVE_MEMBLOCK
  85         select HAVE_MOD_ARCH_SPECIFIC
  86         select HAVE_NMI
  87         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  88         select HAVE_OPTPROBES if !THUMB2_KERNEL
  89         select HAVE_PERF_EVENTS
  90         select HAVE_PERF_REGS
  91         select HAVE_PERF_USER_STACK_DUMP
  92         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  93         select HAVE_REGS_AND_STACK_ACCESS_API
  94         select HAVE_RSEQ
  95         select HAVE_SYSCALL_TRACEPOINTS
  96         select HAVE_UID16
  97         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  98         select IRQ_FORCED_THREADING
  99         select MODULES_USE_ELF_REL
 100         select NEED_DMA_MAP_STATE
 101         select NO_BOOTMEM
 102         select OF_EARLY_FLATTREE if OF
 103         select OF_RESERVED_MEM if OF
 104         select OLD_SIGACTION
 105         select OLD_SIGSUSPEND3
 106         select PERF_USE_VMALLOC
 107         select REFCOUNT_FULL
 108         select RTC_LIB
 109         select SYS_SUPPORTS_APM_EMULATION
 110         # Above selects are sorted alphabetically; please add new ones
 111         # according to that.  Thanks.
 112         help
 113           The ARM series is a line of low-power-consumption RISC chip designs
 114           licensed by ARM Ltd and targeted at embedded applications and
 115           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 116           manufactured, but legacy ARM-based PC hardware remains popular in
 117           Europe.  There is an ARM Linux project with a web page at
 118           <http://www.arm.linux.org.uk/>.
 119
 120 config ARM_HAS_SG_CHAIN
 121         select ARCH_HAS_SG_CHAIN
 122         bool
 123
 124 config ARM_DMA_USE_IOMMU
 125         bool
 126         select ARM_HAS_SG_CHAIN
 127         select NEED_SG_DMA_LENGTH
 128
 129 if ARM_DMA_USE_IOMMU
 130
 131 config ARM_DMA_IOMMU_ALIGNMENT
 132         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 133         range 4 9
 134         default 8
 135         help
 136           DMA mapping framework by default aligns all buffers to the smallest
 137           PAGE_SIZE order which is greater than or equal to the requested buffer
 138           size. This works well for buffers up to a few hundreds kilobytes, but
 139           for larger buffers it just a waste of address space. Drivers which has
 140           relatively small addressing window (like 64Mib) might run out of
 141           virtual space with just a few allocations.
 142
 143           With this parameter you can specify the maximum PAGE_SIZE order for
 144           DMA IOMMU buffers. Larger buffers will be aligned only to this
 145           specified order. The order is expressed as a power of two multiplied
 146           by the PAGE_SIZE.
 147
 148 endif
 149
 150 config MIGHT_HAVE_PCI
 151         bool
 152
 153 config SYS_SUPPORTS_APM_EMULATION
 154         bool
 155
 156 config HAVE_TCM
 157         bool
 158         select GENERIC_ALLOCATOR
 159
 160 config HAVE_PROC_CPU
 161         bool
 162
 163 config NO_IOPORT_MAP
 164         bool
 165
 166 config EISA
 167         bool
 168         ---help---
 169           The Extended Industry Standard Architecture (EISA) bus was
 170           developed as an open alternative to the IBM MicroChannel bus.
 171
 172           The EISA bus provided some of the features of the IBM MicroChannel
 173           bus while maintaining backward compatibility with cards made for
 174           the older ISA bus.  The EISA bus saw limited use between 1988 and
 175           1995 when it was made obsolete by the PCI bus.
 176
 177           Say Y here if you are building a kernel for an EISA-based machine.
 178
 179           Otherwise, say N.
 180
 181 config SBUS
 182         bool
 183
 184 config STACKTRACE_SUPPORT
 185         bool
 186         default y
 187
 188 config LOCKDEP_SUPPORT
 189         bool
 190         default y
 191
 192 config TRACE_IRQFLAGS_SUPPORT
 193         bool
 194         default !CPU_V7M
 195
 196 config RWSEM_XCHGADD_ALGORITHM
 197         bool
 198         default y
 199
 200 config ARCH_HAS_ILOG2_U32
 201         bool
 202
 203 config ARCH_HAS_ILOG2_U64
 204         bool
 205
 206 config ARCH_HAS_BANDGAP
 207         bool
 208
 209 config FIX_EARLYCON_MEM
 210         def_bool y if MMU
 211
 212 config GENERIC_HWEIGHT
 213         bool
 214         default y
 215
 216 config GENERIC_CALIBRATE_DELAY
 217         bool
 218         default y
 219
 220 config ARCH_MAY_HAVE_PC_FDC
 221         bool
 222
 223 config ZONE_DMA
 224         bool
 225
 226 config ARCH_SUPPORTS_UPROBES
 227         def_bool y
 228
 229 config ARCH_HAS_DMA_SET_COHERENT_MASK
 230         bool
 231
 232 config GENERIC_ISA_DMA
 233         bool
 234
 235 config FIQ
 236         bool
 237
 238 config NEED_RET_TO_USER
 239         bool
 240
 241 config ARCH_MTD_XIP
 242         bool
 243
 244 config ARM_PATCH_PHYS_VIRT
 245         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 246         default y
 247         depends on !XIP_KERNEL && MMU
 248         help
 249           Patch phys-to-virt and virt-to-phys translation functions at
 250           boot and module load time according to the position of the
 251           kernel in system memory.
 252
 253           This can only be used with non-XIP MMU kernels where the base
 254           of physical memory is at a 16MB boundary.
 255
 256           Only disable this option if you know that you do not require
 257           this feature (eg, building a kernel for a single machine) and
 258           you need to shrink the kernel to the minimal size.
 259
 260 config NEED_MACH_IO_H
 261         bool
 262         help
 263           Select this when mach/io.h is required to provide special
 264           definitions for this platform.  The need for mach/io.h should
 265           be avoided when possible.
 266
 267 config NEED_MACH_MEMORY_H
 268         bool
 269         help
 270           Select this when mach/memory.h is required to provide special
 271           definitions for this platform.  The need for mach/memory.h should
 272           be avoided when possible.
 273
 274 config PHYS_OFFSET
 275         hex "Physical address of main memory" if MMU
 276         depends on !ARM_PATCH_PHYS_VIRT
 277         default DRAM_BASE if !MMU
 278         default 0x00000000 if ARCH_EBSA110 || \
 279                         ARCH_FOOTBRIDGE || \
 280                         ARCH_INTEGRATOR || \
 281                         ARCH_IOP13XX || \
 282                         ARCH_KS8695 || \
 283                         ARCH_REALVIEW
 284         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 285         default 0x20000000 if ARCH_S5PV210
 286         default 0xc0000000 if ARCH_SA1100
 287         help
 288           Please provide the physical address corresponding to the
 289           location of main memory in your system.
 290
 291 config GENERIC_BUG
 292         def_bool y
 293         depends on BUG
 294
 295 config PGTABLE_LEVELS
 296         int
 297         default 3 if ARM_LPAE
 298         default 2
 299
 300 source "init/Kconfig"
 301
 302 source "kernel/Kconfig.freezer"
 303
 304 menu "System Type"
 305
 306 config MMU
 307         bool "MMU-based Paged Memory Management Support"
 308         default y
 309         help
 310           Select if you want MMU-based virtualised addressing space
 311           support by paged memory management. If unsure, say 'Y'.
 312
 313 config ARCH_MMAP_RND_BITS_MIN
 314         default 8
 315
 316 config ARCH_MMAP_RND_BITS_MAX
 317         default 14 if PAGE_OFFSET=0x40000000
 318         default 15 if PAGE_OFFSET=0x80000000
 319         default 16
 320
 321 #
 322 # The "ARM system type" choice list is ordered alphabetically by option
 323 # text.  Please add new entries in the option alphabetic order.
 324 #
 325 choice
 326         prompt "ARM system type"
 327         default ARM_SINGLE_ARMV7M if !MMU
 328         default ARCH_MULTIPLATFORM if MMU
 329
 330 config ARCH_MULTIPLATFORM
 331         bool "Allow multiple platforms to be selected"
 332         depends on MMU
 333         select ARM_HAS_SG_CHAIN
 334         select ARM_PATCH_PHYS_VIRT
 335         select AUTO_ZRELADDR
 336         select TIMER_OF
 337         select COMMON_CLK
 338         select GENERIC_CLOCKEVENTS
 339         select MIGHT_HAVE_PCI
 340         select MULTI_IRQ_HANDLER
 341         select PCI_DOMAINS if PCI
 342         select SPARSE_IRQ
 343         select USE_OF
 344
 345 config ARM_SINGLE_ARMV7M
 346         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 347         depends on !MMU
 348         select ARM_NVIC
 349         select AUTO_ZRELADDR
 350         select TIMER_OF
 351         select COMMON_CLK
 352         select CPU_V7M
 353         select GENERIC_CLOCKEVENTS
 354         select NO_IOPORT_MAP
 355         select SPARSE_IRQ
 356         select USE_OF
 357
 358 config ARCH_EBSA110
 359         bool "EBSA-110"
 360         select ARCH_USES_GETTIMEOFFSET
 361         select CPU_SA110
 362         select ISA
 363         select NEED_MACH_IO_H
 364         select NEED_MACH_MEMORY_H
 365         select NO_IOPORT_MAP
 366         help
 367           This is an evaluation board for the StrongARM processor available
 368           from Digital. It has limited hardware on-board, including an
 369           Ethernet interface, two PCMCIA sockets, two serial ports and a
 370           parallel port.
 371
 372 config ARCH_EP93XX
 373         bool "EP93xx-based"
 374         select ARCH_SPARSEMEM_ENABLE
 375         select ARM_AMBA
 376         imply ARM_PATCH_PHYS_VIRT
 377         select ARM_VIC
 378         select AUTO_ZRELADDR
 379         select CLKDEV_LOOKUP
 380         select CLKSRC_MMIO
 381         select CPU_ARM920T
 382         select GENERIC_CLOCKEVENTS
 383         select GPIOLIB
 384         help
 385           This enables support for the Cirrus EP93xx series of CPUs.
 386
 387 config ARCH_FOOTBRIDGE
 388         bool "FootBridge"
 389         select CPU_SA110
 390         select FOOTBRIDGE
 391         select GENERIC_CLOCKEVENTS
 392         select HAVE_IDE
 393         select NEED_MACH_IO_H if !MMU
 394         select NEED_MACH_MEMORY_H
 395         help
 396           Support for systems based on the DC21285 companion chip
 397           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 398
 399 config ARCH_NETX
 400         bool "Hilscher NetX based"
 401         select ARM_VIC
 402         select CLKSRC_MMIO
 403         select CPU_ARM926T
 404         select GENERIC_CLOCKEVENTS
 405         help
 406           This enables support for systems based on the Hilscher NetX Soc
 407
 408 config ARCH_IOP13XX
 409         bool "IOP13xx-based"
 410         depends on MMU
 411         select CPU_XSC3
 412         select NEED_MACH_MEMORY_H
 413         select NEED_RET_TO_USER
 414         select PCI
 415         select PLAT_IOP
 416         select VMSPLIT_1G
 417         select SPARSE_IRQ
 418         help
 419           Support for Intel's IOP13XX (XScale) family of processors.
 420
 421 config ARCH_IOP32X
 422         bool "IOP32x-based"
 423         depends on MMU
 424         select CPU_XSCALE
 425         select GPIO_IOP
 426         select GPIOLIB
 427         select NEED_RET_TO_USER
 428         select PCI
 429         select PLAT_IOP
 430         help
 431           Support for Intel's 80219 and IOP32X (XScale) family of
 432           processors.
 433
 434 config ARCH_IOP33X
 435         bool "IOP33x-based"
 436         depends on MMU
 437         select CPU_XSCALE
 438         select GPIO_IOP
 439         select GPIOLIB
 440         select NEED_RET_TO_USER
 441         select PCI
 442         select PLAT_IOP
 443         help
 444           Support for Intel's IOP33X (XScale) family of processors.
 445
 446 config ARCH_IXP4XX
 447         bool "IXP4xx-based"
 448         depends on MMU
 449         select ARCH_HAS_DMA_SET_COHERENT_MASK
 450         select ARCH_SUPPORTS_BIG_ENDIAN
 451         select CLKSRC_MMIO
 452         select CPU_XSCALE
 453         select DMABOUNCE if PCI
 454         select GENERIC_CLOCKEVENTS
 455         select GPIOLIB
 456         select MIGHT_HAVE_PCI
 457         select NEED_MACH_IO_H
 458         select USB_EHCI_BIG_ENDIAN_DESC
 459         select USB_EHCI_BIG_ENDIAN_MMIO
 460         help
 461           Support for Intel's IXP4XX (XScale) family of processors.
 462
 463 config ARCH_DOVE
 464         bool "Marvell Dove"
 465         select CPU_PJ4
 466         select GENERIC_CLOCKEVENTS
 467         select GPIOLIB
 468         select MIGHT_HAVE_PCI
 469         select MULTI_IRQ_HANDLER
 470         select MVEBU_MBUS
 471         select PINCTRL
 472         select PINCTRL_DOVE
 473         select PLAT_ORION_LEGACY
 474         select SPARSE_IRQ
 475         select PM_GENERIC_DOMAINS if PM
 476         help
 477           Support for the Marvell Dove SoC 88AP510
 478
 479 config ARCH_KS8695
 480         bool "Micrel/Kendin KS8695"
 481         select CLKSRC_MMIO
 482         select CPU_ARM922T
 483         select GENERIC_CLOCKEVENTS
 484         select GPIOLIB
 485         select NEED_MACH_MEMORY_H
 486         help
 487           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 488           System-on-Chip devices.
 489
 490 config ARCH_W90X900
 491         bool "Nuvoton W90X900 CPU"
 492         select CLKDEV_LOOKUP
 493         select CLKSRC_MMIO
 494         select CPU_ARM926T
 495         select GENERIC_CLOCKEVENTS
 496         select GPIOLIB
 497         help
 498           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 499           At present, the w90x900 has been renamed nuc900, regarding
 500           the ARM series product line, you can login the following
 501           link address to know more.
 502
 503           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 504                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 505
 506 config ARCH_LPC32XX
 507         bool "NXP LPC32XX"
 508         select ARM_AMBA
 509         select CLKDEV_LOOKUP
 510         select CLKSRC_LPC32XX
 511         select COMMON_CLK
 512         select CPU_ARM926T
 513         select GENERIC_CLOCKEVENTS
 514         select GPIOLIB
 515         select MULTI_IRQ_HANDLER
 516         select SPARSE_IRQ
 517         select USE_OF
 518         help
 519           Support for the NXP LPC32XX family of processors
 520
 521 config ARCH_PXA
 522         bool "PXA2xx/PXA3xx-based"
 523         depends on MMU
 524         select ARCH_MTD_XIP
 525         select ARM_CPU_SUSPEND if PM
 526         select AUTO_ZRELADDR
 527         select COMMON_CLK
 528         select CLKDEV_LOOKUP
 529         select CLKSRC_PXA
 530         select CLKSRC_MMIO
 531         select TIMER_OF
 532         select CPU_XSCALE if !CPU_XSC3
 533         select GENERIC_CLOCKEVENTS
 534         select GPIO_PXA
 535         select GPIOLIB
 536         select HAVE_IDE
 537         select IRQ_DOMAIN
 538         select MULTI_IRQ_HANDLER
 539         select PLAT_PXA
 540         select SPARSE_IRQ
 541         help
 542           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 543
 544 config ARCH_RPC
 545         bool "RiscPC"
 546         depends on MMU
 547         select ARCH_ACORN
 548         select ARCH_MAY_HAVE_PC_FDC
 549         select ARCH_SPARSEMEM_ENABLE
 550         select ARCH_USES_GETTIMEOFFSET
 551         select CPU_SA110
 552         select FIQ
 553         select HAVE_IDE
 554         select HAVE_PATA_PLATFORM
 555         select ISA_DMA_API
 556         select NEED_MACH_IO_H
 557         select NEED_MACH_MEMORY_H
 558         select NO_IOPORT_MAP
 559         help
 560           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 561           CD-ROM interface, serial and parallel port, and the floppy drive.
 562
 563 config ARCH_SA1100
 564         bool "SA1100-based"
 565         select ARCH_MTD_XIP
 566         select ARCH_SPARSEMEM_ENABLE
 567         select CLKDEV_LOOKUP
 568         select CLKSRC_MMIO
 569         select CLKSRC_PXA
 570         select TIMER_OF if OF
 571         select CPU_FREQ
 572         select CPU_SA1100
 573         select GENERIC_CLOCKEVENTS
 574         select GPIOLIB
 575         select HAVE_IDE
 576         select IRQ_DOMAIN
 577         select ISA
 578         select MULTI_IRQ_HANDLER
 579         select NEED_MACH_MEMORY_H
 580         select SPARSE_IRQ
 581         help
 582           Support for StrongARM 11x0 based boards.
 583
 584 config ARCH_S3C24XX
 585         bool "Samsung S3C24XX SoCs"
 586         select ATAGS
 587         select CLKDEV_LOOKUP
 588         select CLKSRC_SAMSUNG_PWM
 589         select GENERIC_CLOCKEVENTS
 590         select GPIO_SAMSUNG
 591         select GPIOLIB
 592         select HAVE_S3C2410_I2C if I2C
 593         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 594         select HAVE_S3C_RTC if RTC_CLASS
 595         select MULTI_IRQ_HANDLER
 596         select NEED_MACH_IO_H
 597         select SAMSUNG_ATAGS
 598         select USE_OF
 599         help
 600           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 601           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 602           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 603           Samsung SMDK2410 development board (and derivatives).
 604
 605 config ARCH_DAVINCI
 606         bool "TI DaVinci"
 607         select ARCH_HAS_HOLES_MEMORYMODEL
 608         select CLKDEV_LOOKUP
 609         select CPU_ARM926T
 610         select GENERIC_ALLOCATOR
 611         select GENERIC_CLOCKEVENTS
 612         select GENERIC_IRQ_CHIP
 613         select GPIOLIB
 614         select HAVE_IDE
 615         select USE_OF
 616         select ZONE_DMA
 617         help
 618           Support for TI's DaVinci platform.
 619
 620 config ARCH_OMAP1
 621         bool "TI OMAP1"
 622         depends on MMU
 623         select ARCH_HAS_HOLES_MEMORYMODEL
 624         select ARCH_OMAP
 625         select CLKDEV_LOOKUP
 626         select CLKSRC_MMIO
 627         select GENERIC_CLOCKEVENTS
 628         select GENERIC_IRQ_CHIP
 629         select GPIOLIB
 630         select HAVE_IDE
 631         select IRQ_DOMAIN
 632         select MULTI_IRQ_HANDLER
 633         select NEED_MACH_IO_H if PCCARD
 634         select NEED_MACH_MEMORY_H
 635         select SPARSE_IRQ
 636         help
 637           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 638
 639 endchoice
 640
 641 menu "Multiple platform selection"
 642         depends on ARCH_MULTIPLATFORM
 643
 644 comment "CPU Core family selection"
 645
 646 config ARCH_MULTI_V4
 647         bool "ARMv4 based platforms (FA526)"
 648         depends on !ARCH_MULTI_V6_V7
 649         select ARCH_MULTI_V4_V5
 650         select CPU_FA526
 651
 652 config ARCH_MULTI_V4T
 653         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 654         depends on !ARCH_MULTI_V6_V7
 655         select ARCH_MULTI_V4_V5
 656         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 657                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 658                 CPU_ARM925T || CPU_ARM940T)
 659
 660 config ARCH_MULTI_V5
 661         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 662         depends on !ARCH_MULTI_V6_V7
 663         select ARCH_MULTI_V4_V5
 664         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 665                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 666                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 667
 668 config ARCH_MULTI_V4_V5
 669         bool
 670
 671 config ARCH_MULTI_V6
 672         bool "ARMv6 based platforms (ARM11)"
 673         select ARCH_MULTI_V6_V7
 674         select CPU_V6K
 675
 676 config ARCH_MULTI_V7
 677         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 678         default y
 679         select ARCH_MULTI_V6_V7
 680         select CPU_V7
 681         select HAVE_SMP
 682
 683 config ARCH_MULTI_V6_V7
 684         bool
 685         select MIGHT_HAVE_CACHE_L2X0
 686
 687 config ARCH_MULTI_CPU_AUTO
 688         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 689         select ARCH_MULTI_V5
 690
 691 endmenu
 692
 693 config ARCH_VIRT
 694         bool "Dummy Virtual Machine"
 695         depends on ARCH_MULTI_V7
 696         select ARM_AMBA
 697         select ARM_GIC
 698         select ARM_GIC_V2M if PCI
 699         select ARM_GIC_V3
 700         select ARM_GIC_V3_ITS if PCI
 701         select ARM_PSCI
 702         select HAVE_ARM_ARCH_TIMER
 703
 704 #
 705 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 706 # Kconfigs may be included either alphabetically (according to the
 707 # plat- suffix) or along side the corresponding mach-* source.
 708 #
 709 source "arch/arm/mach-actions/Kconfig"
 710
 711 source "arch/arm/mach-alpine/Kconfig"
 712
 713 source "arch/arm/mach-artpec/Kconfig"
 714
 715 source "arch/arm/mach-asm9260/Kconfig"
 716
 717 source "arch/arm/mach-aspeed/Kconfig"
 718
 719 source "arch/arm/mach-at91/Kconfig"
 720
 721 source "arch/arm/mach-axxia/Kconfig"
 722
 723 source "arch/arm/mach-bcm/Kconfig"
 724
 725 source "arch/arm/mach-berlin/Kconfig"
 726
 727 source "arch/arm/mach-clps711x/Kconfig"
 728
 729 source "arch/arm/mach-cns3xxx/Kconfig"
 730
 731 source "arch/arm/mach-davinci/Kconfig"
 732
 733 source "arch/arm/mach-digicolor/Kconfig"
 734
 735 source "arch/arm/mach-dove/Kconfig"
 736
 737 source "arch/arm/mach-ep93xx/Kconfig"
 738
 739 source "arch/arm/mach-exynos/Kconfig"
 740 source "arch/arm/plat-samsung/Kconfig"
 741
 742 source "arch/arm/mach-footbridge/Kconfig"
 743
 744 source "arch/arm/mach-gemini/Kconfig"
 745
 746 source "arch/arm/mach-highbank/Kconfig"
 747
 748 source "arch/arm/mach-hisi/Kconfig"
 749
 750 source "arch/arm/mach-imx/Kconfig"
 751
 752 source "arch/arm/mach-integrator/Kconfig"
 753
 754 source "arch/arm/mach-iop13xx/Kconfig"
 755
 756 source "arch/arm/mach-iop32x/Kconfig"
 757
 758 source "arch/arm/mach-iop33x/Kconfig"
 759
 760 source "arch/arm/mach-ixp4xx/Kconfig"
 761
 762 source "arch/arm/mach-keystone/Kconfig"
 763
 764 source "arch/arm/mach-ks8695/Kconfig"
 765
 766 source "arch/arm/mach-mediatek/Kconfig"
 767
 768 source "arch/arm/mach-meson/Kconfig"
 769
 770 source "arch/arm/mach-mmp/Kconfig"
 771
 772 source "arch/arm/mach-moxart/Kconfig"
 773
 774 source "arch/arm/mach-mv78xx0/Kconfig"
 775
 776 source "arch/arm/mach-mvebu/Kconfig"
 777
 778 source "arch/arm/mach-mxs/Kconfig"
 779
 780 source "arch/arm/mach-netx/Kconfig"
 781
 782 source "arch/arm/mach-nomadik/Kconfig"
 783
 784 source "arch/arm/mach-npcm/Kconfig"
 785
 786 source "arch/arm/mach-nspire/Kconfig"
 787
 788 source "arch/arm/plat-omap/Kconfig"
 789
 790 source "arch/arm/mach-omap1/Kconfig"
 791
 792 source "arch/arm/mach-omap2/Kconfig"
 793
 794 source "arch/arm/mach-orion5x/Kconfig"
 795
 796 source "arch/arm/mach-oxnas/Kconfig"
 797
 798 source "arch/arm/mach-picoxcell/Kconfig"
 799
 800 source "arch/arm/mach-prima2/Kconfig"
 801
 802 source "arch/arm/mach-pxa/Kconfig"
 803 source "arch/arm/plat-pxa/Kconfig"
 804
 805 source "arch/arm/mach-qcom/Kconfig"
 806
 807 source "arch/arm/mach-realview/Kconfig"
 808
 809 source "arch/arm/mach-rockchip/Kconfig"
 810
 811 source "arch/arm/mach-s3c24xx/Kconfig"
 812
 813 source "arch/arm/mach-s3c64xx/Kconfig"
 814
 815 source "arch/arm/mach-s5pv210/Kconfig"
 816
 817 source "arch/arm/mach-sa1100/Kconfig"
 818
 819 source "arch/arm/mach-shmobile/Kconfig"
 820
 821 source "arch/arm/mach-socfpga/Kconfig"
 822
 823 source "arch/arm/mach-spear/Kconfig"
 824
 825 source "arch/arm/mach-sti/Kconfig"
 826
 827 source "arch/arm/mach-stm32/Kconfig"
 828
 829 source "arch/arm/mach-sunxi/Kconfig"
 830
 831 source "arch/arm/mach-tango/Kconfig"
 832
 833 source "arch/arm/mach-tegra/Kconfig"
 834
 835 source "arch/arm/mach-u300/Kconfig"
 836
 837 source "arch/arm/mach-uniphier/Kconfig"
 838
 839 source "arch/arm/mach-ux500/Kconfig"
 840
 841 source "arch/arm/mach-versatile/Kconfig"
 842
 843 source "arch/arm/mach-vexpress/Kconfig"
 844 source "arch/arm/plat-versatile/Kconfig"
 845
 846 source "arch/arm/mach-vt8500/Kconfig"
 847
 848 source "arch/arm/mach-w90x900/Kconfig"
 849
 850 source "arch/arm/mach-zx/Kconfig"
 851
 852 source "arch/arm/mach-zynq/Kconfig"
 853
 854 # ARMv7-M architecture
 855 config ARCH_EFM32
 856         bool "Energy Micro efm32"
 857         depends on ARM_SINGLE_ARMV7M
 858         select GPIOLIB
 859         help
 860           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 861           processors.
 862
 863 config ARCH_LPC18XX
 864         bool "NXP LPC18xx/LPC43xx"
 865         depends on ARM_SINGLE_ARMV7M
 866         select ARCH_HAS_RESET_CONTROLLER
 867         select ARM_AMBA
 868         select CLKSRC_LPC32XX
 869         select PINCTRL
 870         help
 871           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 872           high performance microcontrollers.
 873
 874 config ARCH_MPS2
 875         bool "ARM MPS2 platform"
 876         depends on ARM_SINGLE_ARMV7M
 877         select ARM_AMBA
 878         select CLKSRC_MPS2
 879         help
 880           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 881           with a range of available cores like Cortex-M3/M4/M7.
 882
 883           Please, note that depends which Application Note is used memory map
 884           for the platform may vary, so adjustment of RAM base might be needed.
 885
 886 # Definitions to make life easier
 887 config ARCH_ACORN
 888         bool
 889
 890 config PLAT_IOP
 891         bool
 892         select GENERIC_CLOCKEVENTS
 893
 894 config PLAT_ORION
 895         bool
 896         select CLKSRC_MMIO
 897         select COMMON_CLK
 898         select GENERIC_IRQ_CHIP
 899         select IRQ_DOMAIN
 900
 901 config PLAT_ORION_LEGACY
 902         bool
 903         select PLAT_ORION
 904
 905 config PLAT_PXA
 906         bool
 907
 908 config PLAT_VERSATILE
 909         bool
 910
 911 source "arch/arm/firmware/Kconfig"
 912
 913 source arch/arm/mm/Kconfig
 914
 915 config IWMMXT
 916         bool "Enable iWMMXt support"
 917         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 918         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 919         help
 920           Enable support for iWMMXt context switching at run time if
 921           running on a CPU that supports it.
 922
 923 config MULTI_IRQ_HANDLER
 924         bool
 925         help
 926           Allow each machine to specify it's own IRQ handler at run time.
 927
 928 if !MMU
 929 source "arch/arm/Kconfig-nommu"
 930 endif
 931
 932 config PJ4B_ERRATA_4742
 933         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 934         depends on CPU_PJ4B && MACH_ARMADA_370
 935         default y
 936         help
 937           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 938           Event (WFE) IDLE states, a specific timing sensitivity exists between
 939           the retiring WFI/WFE instructions and the newly issued subsequent
 940           instructions.  This sensitivity can result in a CPU hang scenario.
 941           Workaround:
 942           The software must insert either a Data Synchronization Barrier (DSB)
 943           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 944           instruction
 945
 946 config ARM_ERRATA_326103
 947         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 948         depends on CPU_V6
 949         help
 950           Executing a SWP instruction to read-only memory does not set bit 11
 951           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 952           treat the access as a read, preventing a COW from occurring and
 953           causing the faulting task to livelock.
 954
 955 config ARM_ERRATA_411920
 956         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 957         depends on CPU_V6 || CPU_V6K
 958         help
 959           Invalidation of the Instruction Cache operation can
 960           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 961           It does not affect the MPCore. This option enables the ARM Ltd.
 962           recommended workaround.
 963
 964 config ARM_ERRATA_430973
 965         bool "ARM errata: Stale prediction on replaced interworking branch"
 966         depends on CPU_V7
 967         help
 968           This option enables the workaround for the 430973 Cortex-A8
 969           r1p* erratum. If a code sequence containing an ARM/Thumb
 970           interworking branch is replaced with another code sequence at the
 971           same virtual address, whether due to self-modifying code or virtual
 972           to physical address re-mapping, Cortex-A8 does not recover from the
 973           stale interworking branch prediction. This results in Cortex-A8
 974           executing the new code sequence in the incorrect ARM or Thumb state.
 975           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 976           and also flushes the branch target cache at every context switch.
 977           Note that setting specific bits in the ACTLR register may not be
 978           available in non-secure mode.
 979
 980 config ARM_ERRATA_458693
 981         bool "ARM errata: Processor deadlock when a false hazard is created"
 982         depends on CPU_V7
 983         depends on !ARCH_MULTIPLATFORM
 984         help
 985           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 986           erratum. For very specific sequences of memory operations, it is
 987           possible for a hazard condition intended for a cache line to instead
 988           be incorrectly associated with a different cache line. This false
 989           hazard might then cause a processor deadlock. The workaround enables
 990           the L1 caching of the NEON accesses and disables the PLD instruction
 991           in the ACTLR register. Note that setting specific bits in the ACTLR
 992           register may not be available in non-secure mode.
 993
 994 config ARM_ERRATA_460075
 995         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
 996         depends on CPU_V7
 997         depends on !ARCH_MULTIPLATFORM
 998         help
 999           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1000           erratum. Any asynchronous access to the L2 cache may encounter a
1001           situation in which recent store transactions to the L2 cache are lost
1002           and overwritten with stale memory contents from external memory. The
1003           workaround disables the write-allocate mode for the L2 cache via the
1004           ACTLR register. Note that setting specific bits in the ACTLR register
1005           may not be available in non-secure mode.
1006
1007 config ARM_ERRATA_742230
1008         bool "ARM errata: DMB operation may be faulty"
1009         depends on CPU_V7 && SMP
1010         depends on !ARCH_MULTIPLATFORM
1011         help
1012           This option enables the workaround for the 742230 Cortex-A9
1013           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1014           between two write operations may not ensure the correct visibility
1015           ordering of the two writes. This workaround sets a specific bit in
1016           the diagnostic register of the Cortex-A9 which causes the DMB
1017           instruction to behave as a DSB, ensuring the correct behaviour of
1018           the two writes.
1019
1020 config ARM_ERRATA_742231
1021         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1022         depends on CPU_V7 && SMP
1023         depends on !ARCH_MULTIPLATFORM
1024         help
1025           This option enables the workaround for the 742231 Cortex-A9
1026           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1027           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1028           accessing some data located in the same cache line, may get corrupted
1029           data due to bad handling of the address hazard when the line gets
1030           replaced from one of the CPUs at the same time as another CPU is
1031           accessing it. This workaround sets specific bits in the diagnostic
1032           register of the Cortex-A9 which reduces the linefill issuing
1033           capabilities of the processor.
1034
1035 config ARM_ERRATA_643719
1036         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1037         depends on CPU_V7 && SMP
1038         default y
1039         help
1040           This option enables the workaround for the 643719 Cortex-A9 (prior to
1041           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1042           register returns zero when it should return one. The workaround
1043           corrects this value, ensuring cache maintenance operations which use
1044           it behave as intended and avoiding data corruption.
1045
1046 config ARM_ERRATA_720789
1047         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1048         depends on CPU_V7
1049         help
1050           This option enables the workaround for the 720789 Cortex-A9 (prior to
1051           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1052           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1053           As a consequence of this erratum, some TLB entries which should be
1054           invalidated are not, resulting in an incoherency in the system page
1055           tables. The workaround changes the TLB flushing routines to invalidate
1056           entries regardless of the ASID.
1057
1058 config ARM_ERRATA_743622
1059         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1060         depends on CPU_V7
1061         depends on !ARCH_MULTIPLATFORM
1062         help
1063           This option enables the workaround for the 743622 Cortex-A9
1064           (r2p*) erratum. Under very rare conditions, a faulty
1065           optimisation in the Cortex-A9 Store Buffer may lead to data
1066           corruption. This workaround sets a specific bit in the diagnostic
1067           register of the Cortex-A9 which disables the Store Buffer
1068           optimisation, preventing the defect from occurring. This has no
1069           visible impact on the overall performance or power consumption of the
1070           processor.
1071
1072 config ARM_ERRATA_751472
1073         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1074         depends on CPU_V7
1075         depends on !ARCH_MULTIPLATFORM
1076         help
1077           This option enables the workaround for the 751472 Cortex-A9 (prior
1078           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1079           completion of a following broadcasted operation if the second
1080           operation is received by a CPU before the ICIALLUIS has completed,
1081           potentially leading to corrupted entries in the cache or TLB.
1082
1083 config ARM_ERRATA_754322
1084         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1085         depends on CPU_V7
1086         help
1087           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1088           r3p*) erratum. A speculative memory access may cause a page table walk
1089           which starts prior to an ASID switch but completes afterwards. This
1090           can populate the micro-TLB with a stale entry which may be hit with
1091           the new ASID. This workaround places two dsb instructions in the mm
1092           switching code so that no page table walks can cross the ASID switch.
1093
1094 config ARM_ERRATA_754327
1095         bool "ARM errata: no automatic Store Buffer drain"
1096         depends on CPU_V7 && SMP
1097         help
1098           This option enables the workaround for the 754327 Cortex-A9 (prior to
1099           r2p0) erratum. The Store Buffer does not have any automatic draining
1100           mechanism and therefore a livelock may occur if an external agent
1101           continuously polls a memory location waiting to observe an update.
1102           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1103           written polling loops from denying visibility of updates to memory.
1104
1105 config ARM_ERRATA_364296
1106         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1107         depends on CPU_V6
1108         help
1109           This options enables the workaround for the 364296 ARM1136
1110           r0p2 erratum (possible cache data corruption with
1111           hit-under-miss enabled). It sets the undocumented bit 31 in
1112           the auxiliary control register and the FI bit in the control
1113           register, thus disabling hit-under-miss without putting the
1114           processor into full low interrupt latency mode. ARM11MPCore
1115           is not affected.
1116
1117 config ARM_ERRATA_764369
1118         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1119         depends on CPU_V7 && SMP
1120         help
1121           This option enables the workaround for erratum 764369
1122           affecting Cortex-A9 MPCore with two or more processors (all
1123           current revisions). Under certain timing circumstances, a data
1124           cache line maintenance operation by MVA targeting an Inner
1125           Shareable memory region may fail to proceed up to either the
1126           Point of Coherency or to the Point of Unification of the
1127           system. This workaround adds a DSB instruction before the
1128           relevant cache maintenance functions and sets a specific bit
1129           in the diagnostic control register of the SCU.
1130
1131 config ARM_ERRATA_775420
1132        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1133        depends on CPU_V7
1134        help
1135          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1136          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1137          operation aborts with MMU exception, it might cause the processor
1138          to deadlock. This workaround puts DSB before executing ISB if
1139          an abort may occur on cache maintenance.
1140
1141 config ARM_ERRATA_798181
1142         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1143         depends on CPU_V7 && SMP
1144         help
1145           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1146           adequately shooting down all use of the old entries. This
1147           option enables the Linux kernel workaround for this erratum
1148           which sends an IPI to the CPUs that are running the same ASID
1149           as the one being invalidated.
1150
1151 config ARM_ERRATA_773022
1152         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1153         depends on CPU_V7
1154         help
1155           This option enables the workaround for the 773022 Cortex-A15
1156           (up to r0p4) erratum. In certain rare sequences of code, the
1157           loop buffer may deliver incorrect instructions. This
1158           workaround disables the loop buffer to avoid the erratum.
1159
1160 config ARM_ERRATA_818325_852422
1161         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1162         depends on CPU_V7
1163         help
1164           This option enables the workaround for:
1165           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1166             instruction might deadlock.  Fixed in r0p1.
1167           - Cortex-A12 852422: Execution of a sequence of instructions might
1168             lead to either a data corruption or a CPU deadlock.  Not fixed in
1169             any Cortex-A12 cores yet.
1170           This workaround for all both errata involves setting bit[12] of the
1171           Feature Register. This bit disables an optimisation applied to a
1172           sequence of 2 instructions that use opposing condition codes.
1173
1174 config ARM_ERRATA_821420
1175         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1176         depends on CPU_V7
1177         help
1178           This option enables the workaround for the 821420 Cortex-A12
1179           (all revs) erratum. In very rare timing conditions, a sequence
1180           of VMOV to Core registers instructions, for which the second
1181           one is in the shadow of a branch or abort, can lead to a
1182           deadlock when the VMOV instructions are issued out-of-order.
1183
1184 config ARM_ERRATA_825619
1185         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1186         depends on CPU_V7
1187         help
1188           This option enables the workaround for the 825619 Cortex-A12
1189           (all revs) erratum. Within rare timing constraints, executing a
1190           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1191           and Device/Strongly-Ordered loads and stores might cause deadlock
1192
1193 config ARM_ERRATA_852421
1194         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1195         depends on CPU_V7
1196         help
1197           This option enables the workaround for the 852421 Cortex-A17
1198           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1199           execution of a DMB ST instruction might fail to properly order
1200           stores from GroupA and stores from GroupB.
1201
1202 config ARM_ERRATA_852423
1203         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1204         depends on CPU_V7
1205         help
1206           This option enables the workaround for:
1207           - Cortex-A17 852423: Execution of a sequence of instructions might
1208             lead to either a data corruption or a CPU deadlock.  Not fixed in
1209             any Cortex-A17 cores yet.
1210           This is identical to Cortex-A12 erratum 852422.  It is a separate
1211           config option from the A12 erratum due to the way errata are checked
1212           for and handled.
1213
1214 endmenu
1215
1216 source "arch/arm/common/Kconfig"
1217
1218 menu "Bus support"
1219
1220 config ISA
1221         bool
1222         help
1223           Find out whether you have ISA slots on your motherboard.  ISA is the
1224           name of a bus system, i.e. the way the CPU talks to the other stuff
1225           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1226           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1227           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1228
1229 # Select ISA DMA controller support
1230 config ISA_DMA
1231         bool
1232         select ISA_DMA_API
1233
1234 # Select ISA DMA interface
1235 config ISA_DMA_API
1236         bool
1237
1238 config PCI
1239         bool "PCI support" if MIGHT_HAVE_PCI
1240         help
1241           Find out whether you have a PCI motherboard. PCI is the name of a
1242           bus system, i.e. the way the CPU talks to the other stuff inside
1243           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1244           VESA. If you have PCI, say Y, otherwise N.
1245
1246 config PCI_DOMAINS
1247         bool
1248         depends on PCI
1249
1250 config PCI_DOMAINS_GENERIC
1251         def_bool PCI_DOMAINS
1252
1253 config PCI_NANOENGINE
1254         bool "BSE nanoEngine PCI support"
1255         depends on SA1100_NANOENGINE
1256         help
1257           Enable PCI on the BSE nanoEngine board.
1258
1259 config PCI_SYSCALL
1260         def_bool PCI
1261
1262 config PCI_HOST_ITE8152
1263         bool
1264         depends on PCI && MACH_ARMCORE
1265         default y
1266         select DMABOUNCE
1267
1268 source "drivers/pci/Kconfig"
1269
1270 source "drivers/pcmcia/Kconfig"
1271
1272 endmenu
1273
1274 menu "Kernel Features"
1275
1276 config HAVE_SMP
1277         bool
1278         help
1279           This option should be selected by machines which have an SMP-
1280           capable CPU.
1281
1282           The only effect of this option is to make the SMP-related
1283           options available to the user for configuration.
1284
1285 config SMP
1286         bool "Symmetric Multi-Processing"
1287         depends on CPU_V6K || CPU_V7
1288         depends on GENERIC_CLOCKEVENTS
1289         depends on HAVE_SMP
1290         depends on MMU || ARM_MPU
1291         select IRQ_WORK
1292         help
1293           This enables support for systems with more than one CPU. If you have
1294           a system with only one CPU, say N. If you have a system with more
1295           than one CPU, say Y.
1296
1297           If you say N here, the kernel will run on uni- and multiprocessor
1298           machines, but will use only one CPU of a multiprocessor machine. If
1299           you say Y here, the kernel will run on many, but not all,
1300           uniprocessor machines. On a uniprocessor machine, the kernel
1301           will run faster if you say N here.
1302
1303           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1304           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1305           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1306
1307           If you don't know what to do here, say N.
1308
1309 config SMP_ON_UP
1310         bool "Allow booting SMP kernel on uniprocessor systems"
1311         depends on SMP && !XIP_KERNEL && MMU
1312         default y
1313         help
1314           SMP kernels contain instructions which fail on non-SMP processors.
1315           Enabling this option allows the kernel to modify itself to make
1316           these instructions safe.  Disabling it allows about 1K of space
1317           savings.
1318
1319           If you don't know what to do here, say Y.
1320
1321 config ARM_CPU_TOPOLOGY
1322         bool "Support cpu topology definition"
1323         depends on SMP && CPU_V7
1324         default y
1325         help
1326           Support ARM cpu topology definition. The MPIDR register defines
1327           affinity between processors which is then used to describe the cpu
1328           topology of an ARM System.
1329
1330 config SCHED_MC
1331         bool "Multi-core scheduler support"
1332         depends on ARM_CPU_TOPOLOGY
1333         help
1334           Multi-core scheduler support improves the CPU scheduler's decision
1335           making when dealing with multi-core CPU chips at a cost of slightly
1336           increased overhead in some places. If unsure say N here.
1337
1338 config SCHED_SMT
1339         bool "SMT scheduler support"
1340         depends on ARM_CPU_TOPOLOGY
1341         help
1342           Improves the CPU scheduler's decision making when dealing with
1343           MultiThreading at a cost of slightly increased overhead in some
1344           places. If unsure say N here.
1345
1346 config HAVE_ARM_SCU
1347         bool
1348         help
1349           This option enables support for the ARM system coherency unit
1350
1351 config HAVE_ARM_ARCH_TIMER
1352         bool "Architected timer support"
1353         depends on CPU_V7
1354         select ARM_ARCH_TIMER
1355         select GENERIC_CLOCKEVENTS
1356         help
1357           This option enables support for the ARM architected timer
1358
1359 config HAVE_ARM_TWD
1360         bool
1361         select TIMER_OF if OF
1362         help
1363           This options enables support for the ARM timer and watchdog unit
1364
1365 config MCPM
1366         bool "Multi-Cluster Power Management"
1367         depends on CPU_V7 && SMP
1368         help
1369           This option provides the common power management infrastructure
1370           for (multi-)cluster based systems, such as big.LITTLE based
1371           systems.
1372
1373 config MCPM_QUAD_CLUSTER
1374         bool
1375         depends on MCPM
1376         help
1377           To avoid wasting resources unnecessarily, MCPM only supports up
1378           to 2 clusters by default.
1379           Platforms with 3 or 4 clusters that use MCPM must select this
1380           option to allow the additional clusters to be managed.
1381
1382 config BIG_LITTLE
1383         bool "big.LITTLE support (Experimental)"
1384         depends on CPU_V7 && SMP
1385         select MCPM
1386         help
1387           This option enables support selections for the big.LITTLE
1388           system architecture.
1389
1390 config BL_SWITCHER
1391         bool "big.LITTLE switcher support"
1392         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1393         select CPU_PM
1394         help
1395           The big.LITTLE "switcher" provides the core functionality to
1396           transparently handle transition between a cluster of A15's
1397           and a cluster of A7's in a big.LITTLE system.
1398
1399 config BL_SWITCHER_DUMMY_IF
1400         tristate "Simple big.LITTLE switcher user interface"
1401         depends on BL_SWITCHER && DEBUG_KERNEL
1402         help
1403           This is a simple and dummy char dev interface to control
1404           the big.LITTLE switcher core code.  It is meant for
1405           debugging purposes only.
1406
1407 choice
1408         prompt "Memory split"
1409         depends on MMU
1410         default VMSPLIT_3G
1411         help
1412           Select the desired split between kernel and user memory.
1413
1414           If you are not absolutely sure what you are doing, leave this
1415           option alone!
1416
1417         config VMSPLIT_3G
1418                 bool "3G/1G user/kernel split"
1419         config VMSPLIT_3G_OPT
1420                 depends on !ARM_LPAE
1421                 bool "3G/1G user/kernel split (for full 1G low memory)"
1422         config VMSPLIT_2G
1423                 bool "2G/2G user/kernel split"
1424         config VMSPLIT_1G
1425                 bool "1G/3G user/kernel split"
1426 endchoice
1427
1428 config PAGE_OFFSET
1429         hex
1430         default PHYS_OFFSET if !MMU
1431         default 0x40000000 if VMSPLIT_1G
1432         default 0x80000000 if VMSPLIT_2G
1433         default 0xB0000000 if VMSPLIT_3G_OPT
1434         default 0xC0000000
1435
1436 config NR_CPUS
1437         int "Maximum number of CPUs (2-32)"
1438         range 2 32
1439         depends on SMP
1440         default "4"
1441
1442 config HOTPLUG_CPU
1443         bool "Support for hot-pluggable CPUs"
1444         depends on SMP
1445         help
1446           Say Y here to experiment with turning CPUs off and on.  CPUs
1447           can be controlled through /sys/devices/system/cpu.
1448
1449 config ARM_PSCI
1450         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1451         depends on HAVE_ARM_SMCCC
1452         select ARM_PSCI_FW
1453         help
1454           Say Y here if you want Linux to communicate with system firmware
1455           implementing the PSCI specification for CPU-centric power
1456           management operations described in ARM document number ARM DEN
1457           0022A ("Power State Coordination Interface System Software on
1458           ARM processors").
1459
1460 # The GPIO number here must be sorted by descending number. In case of
1461 # a multiplatform kernel, we just want the highest value required by the
1462 # selected platforms.
1463 config ARCH_NR_GPIO
1464         int
1465         default 2048 if ARCH_SOCFPGA
1466         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1467                 ARCH_ZYNQ
1468         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1469                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1470         default 416 if ARCH_SUNXI
1471         default 392 if ARCH_U8500
1472         default 352 if ARCH_VT8500
1473         default 288 if ARCH_ROCKCHIP
1474         default 264 if MACH_H4700
1475         default 0
1476         help
1477           Maximum number of GPIOs in the system.
1478
1479           If unsure, leave the default value.
1480
1481 source kernel/Kconfig.preempt
1482
1483 config HZ_FIXED
1484         int
1485         default 200 if ARCH_EBSA110
1486         default 128 if SOC_AT91RM9200
1487         default 0
1488
1489 choice
1490         depends on HZ_FIXED = 0
1491         prompt "Timer frequency"
1492
1493 config HZ_100
1494         bool "100 Hz"
1495
1496 config HZ_200
1497         bool "200 Hz"
1498
1499 config HZ_250
1500         bool "250 Hz"
1501
1502 config HZ_300
1503         bool "300 Hz"
1504
1505 config HZ_500
1506         bool "500 Hz"
1507
1508 config HZ_1000
1509         bool "1000 Hz"
1510
1511 endchoice
1512
1513 config HZ
1514         int
1515         default HZ_FIXED if HZ_FIXED != 0
1516         default 100 if HZ_100
1517         default 200 if HZ_200
1518         default 250 if HZ_250
1519         default 300 if HZ_300
1520         default 500 if HZ_500
1521         default 1000
1522
1523 config SCHED_HRTICK
1524         def_bool HIGH_RES_TIMERS
1525
1526 config THUMB2_KERNEL
1527         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1528         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1529         default y if CPU_THUMBONLY
1530         select ARM_UNWIND
1531         help
1532           By enabling this option, the kernel will be compiled in
1533           Thumb-2 mode.
1534
1535           If unsure, say N.
1536
1537 config THUMB2_AVOID_R_ARM_THM_JUMP11
1538         bool "Work around buggy Thumb-2 short branch relocations in gas"
1539         depends on THUMB2_KERNEL && MODULES
1540         default y
1541         help
1542           Various binutils versions can resolve Thumb-2 branches to
1543           locally-defined, preemptible global symbols as short-range "b.n"
1544           branch instructions.
1545
1546           This is a problem, because there's no guarantee the final
1547           destination of the symbol, or any candidate locations for a
1548           trampoline, are within range of the branch.  For this reason, the
1549           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1550           relocation in modules at all, and it makes little sense to add
1551           support.
1552
1553           The symptom is that the kernel fails with an "unsupported
1554           relocation" error when loading some modules.
1555
1556           Until fixed tools are available, passing
1557           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1558           code which hits this problem, at the cost of a bit of extra runtime
1559           stack usage in some cases.
1560
1561           The problem is described in more detail at:
1562               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1563
1564           Only Thumb-2 kernels are affected.
1565
1566           Unless you are sure your tools don't have this problem, say Y.
1567
1568 config ARM_PATCH_IDIV
1569         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1570         depends on CPU_32v7 && !XIP_KERNEL
1571         default y
1572         help
1573           The ARM compiler inserts calls to __aeabi_idiv() and
1574           __aeabi_uidiv() when it needs to perform division on signed
1575           and unsigned integers. Some v7 CPUs have support for the sdiv
1576           and udiv instructions that can be used to implement those
1577           functions.
1578
1579           Enabling this option allows the kernel to modify itself to
1580           replace the first two instructions of these library functions
1581           with the sdiv or udiv plus "bx lr" instructions when the CPU
1582           it is running on supports them. Typically this will be faster
1583           and less power intensive than running the original library
1584           code to do integer division.
1585
1586 config AEABI
1587         bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1588         default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1589         help
1590           This option allows for the kernel to be compiled using the latest
1591           ARM ABI (aka EABI).  This is only useful if you are using a user
1592           space environment that is also compiled with EABI.
1593
1594           Since there are major incompatibilities between the legacy ABI and
1595           EABI, especially with regard to structure member alignment, this
1596           option also changes the kernel syscall calling convention to
1597           disambiguate both ABIs and allow for backward compatibility support
1598           (selected with CONFIG_OABI_COMPAT).
1599
1600           To use this you need GCC version 4.0.0 or later.
1601
1602 config OABI_COMPAT
1603         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1604         depends on AEABI && !THUMB2_KERNEL
1605         help
1606           This option preserves the old syscall interface along with the
1607           new (ARM EABI) one. It also provides a compatibility layer to
1608           intercept syscalls that have structure arguments which layout
1609           in memory differs between the legacy ABI and the new ARM EABI
1610           (only for non "thumb" binaries). This option adds a tiny
1611           overhead to all syscalls and produces a slightly larger kernel.
1612
1613           The seccomp filter system will not be available when this is
1614           selected, since there is no way yet to sensibly distinguish
1615           between calling conventions during filtering.
1616
1617           If you know you'll be using only pure EABI user space then you
1618           can say N here. If this option is not selected and you attempt
1619           to execute a legacy ABI binary then the result will be
1620           UNPREDICTABLE (in fact it can be predicted that it won't work
1621           at all). If in doubt say N.
1622
1623 config ARCH_HAS_HOLES_MEMORYMODEL
1624         bool
1625
1626 config ARCH_SPARSEMEM_ENABLE
1627         bool
1628
1629 config ARCH_SPARSEMEM_DEFAULT
1630         def_bool ARCH_SPARSEMEM_ENABLE
1631
1632 config ARCH_SELECT_MEMORY_MODEL
1633         def_bool ARCH_SPARSEMEM_ENABLE
1634
1635 config HAVE_ARCH_PFN_VALID
1636         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1637
1638 config HAVE_GENERIC_GUP
1639         def_bool y
1640         depends on ARM_LPAE
1641
1642 config HIGHMEM
1643         bool "High Memory Support"
1644         depends on MMU
1645         help
1646           The address space of ARM processors is only 4 Gigabytes large
1647           and it has to accommodate user address space, kernel address
1648           space as well as some memory mapped IO. That means that, if you
1649           have a large amount of physical memory and/or IO, not all of the
1650           memory can be "permanently mapped" by the kernel. The physical
1651           memory that is not permanently mapped is called "high memory".
1652
1653           Depending on the selected kernel/user memory split, minimum
1654           vmalloc space and actual amount of RAM, you may not need this
1655           option which should result in a slightly faster kernel.
1656
1657           If unsure, say n.
1658
1659 config HIGHPTE
1660         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1661         depends on HIGHMEM
1662         default y
1663         help
1664           The VM uses one page of physical memory for each page table.
1665           For systems with a lot of processes, this can use a lot of
1666           precious low memory, eventually leading to low memory being
1667           consumed by page tables.  Setting this option will allow
1668           user-space 2nd level page tables to reside in high memory.
1669
1670 config CPU_SW_DOMAIN_PAN
1671         bool "Enable use of CPU domains to implement privileged no-access"
1672         depends on MMU && !ARM_LPAE
1673         default y
1674         help
1675           Increase kernel security by ensuring that normal kernel accesses
1676           are unable to access userspace addresses.  This can help prevent
1677           use-after-free bugs becoming an exploitable privilege escalation
1678           by ensuring that magic values (such as LIST_POISON) will always
1679           fault when dereferenced.
1680
1681           CPUs with low-vector mappings use a best-efforts implementation.
1682           Their lower 1MB needs to remain accessible for the vectors, but
1683           the remainder of userspace will become appropriately inaccessible.
1684
1685 config HW_PERF_EVENTS
1686         def_bool y
1687         depends on ARM_PMU
1688
1689 config SYS_SUPPORTS_HUGETLBFS
1690        def_bool y
1691        depends on ARM_LPAE
1692
1693 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1694        def_bool y
1695        depends on ARM_LPAE
1696
1697 config ARCH_WANT_GENERAL_HUGETLB
1698         def_bool y
1699
1700 config ARM_MODULE_PLTS
1701         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1702         depends on MODULES
1703         default y
1704         help
1705           Allocate PLTs when loading modules so that jumps and calls whose
1706           targets are too far away for their relative offsets to be encoded
1707           in the instructions themselves can be bounced via veneers in the
1708           module's PLT. This allows modules to be allocated in the generic
1709           vmalloc area after the dedicated module memory area has been
1710           exhausted. The modules will use slightly more memory, but after
1711           rounding up to page size, the actual memory footprint is usually
1712           the same.
1713
1714           Disabling this is usually safe for small single-platform
1715           configurations. If unsure, say y.
1716
1717 source "mm/Kconfig"
1718
1719 config FORCE_MAX_ZONEORDER
1720         int "Maximum zone order"
1721         default "12" if SOC_AM33XX
1722         default "9" if SA1111 || ARCH_EFM32
1723         default "11"
1724         help
1725           The kernel memory allocator divides physically contiguous memory
1726           blocks into "zones", where each zone is a power of two number of
1727           pages.  This option selects the largest power of two that the kernel
1728           keeps in the memory allocator.  If you need to allocate very large
1729           blocks of physically contiguous memory, then you may need to
1730           increase this value.
1731
1732           This config option is actually maximum order plus one. For example,
1733           a value of 11 means that the largest free memory block is 2^10 pages.
1734
1735 config ALIGNMENT_TRAP
1736         bool
1737         depends on CPU_CP15_MMU
1738         default y if !ARCH_EBSA110
1739         select HAVE_PROC_CPU if PROC_FS
1740         help
1741           ARM processors cannot fetch/store information which is not
1742           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1743           address divisible by 4. On 32-bit ARM processors, these non-aligned
1744           fetch/store instructions will be emulated in software if you say
1745           here, which has a severe performance impact. This is necessary for
1746           correct operation of some network protocols. With an IP-only
1747           configuration it is safe to say N, otherwise say Y.
1748
1749 config UACCESS_WITH_MEMCPY
1750         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1751         depends on MMU
1752         default y if CPU_FEROCEON
1753         help
1754           Implement faster copy_to_user and clear_user methods for CPU
1755           cores where a 8-word STM instruction give significantly higher
1756           memory write throughput than a sequence of individual 32bit stores.
1757
1758           A possible side effect is a slight increase in scheduling latency
1759           between threads sharing the same address space if they invoke
1760           such copy operations with large buffers.
1761
1762           However, if the CPU data cache is using a write-allocate mode,
1763           this option is unlikely to provide any performance gain.
1764
1765 config SECCOMP
1766         bool
1767         prompt "Enable seccomp to safely compute untrusted bytecode"
1768         ---help---
1769           This kernel feature is useful for number crunching applications
1770           that may need to compute untrusted bytecode during their
1771           execution. By using pipes or other transports made available to
1772           the process as file descriptors supporting the read/write
1773           syscalls, it's possible to isolate those applications in
1774           their own address space using seccomp. Once seccomp is
1775           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1776           and the task is only allowed to execute a few safe syscalls
1777           defined by each seccomp mode.
1778
1779 config PARAVIRT
1780         bool "Enable paravirtualization code"
1781         help
1782           This changes the kernel so it can modify itself when it is run
1783           under a hypervisor, potentially improving performance significantly
1784           over full virtualization.
1785
1786 config PARAVIRT_TIME_ACCOUNTING
1787         bool "Paravirtual steal time accounting"
1788         select PARAVIRT
1789         default n
1790         help
1791           Select this option to enable fine granularity task steal time
1792           accounting. Time spent executing other tasks in parallel with
1793           the current vCPU is discounted from the vCPU power. To account for
1794           that, there can be a small performance impact.
1795
1796           If in doubt, say N here.
1797
1798 config XEN_DOM0
1799         def_bool y
1800         depends on XEN
1801
1802 config XEN
1803         bool "Xen guest support on ARM"
1804         depends on ARM && AEABI && OF
1805         depends on CPU_V7 && !CPU_V6
1806         depends on !GENERIC_ATOMIC64
1807         depends on MMU
1808         select ARCH_DMA_ADDR_T_64BIT
1809         select ARM_PSCI
1810         select SWIOTLB
1811         select SWIOTLB_XEN
1812         select PARAVIRT
1813         help
1814           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1815
1816 endmenu
1817
1818 menu "Boot options"
1819
1820 config USE_OF
1821         bool "Flattened Device Tree support"
1822         select IRQ_DOMAIN
1823         select OF
1824         help
1825           Include support for flattened device tree machine descriptions.
1826
1827 config ATAGS
1828         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1829         default y
1830         help
1831           This is the traditional way of passing data to the kernel at boot
1832           time. If you are solely relying on the flattened device tree (or
1833           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1834           to remove ATAGS support from your kernel binary.  If unsure,
1835           leave this to y.
1836
1837 config DEPRECATED_PARAM_STRUCT
1838         bool "Provide old way to pass kernel parameters"
1839         depends on ATAGS
1840         help
1841           This was deprecated in 2001 and announced to live on for 5 years.
1842           Some old boot loaders still use this way.
1843
1844 # Compressed boot loader in ROM.  Yes, we really want to ask about
1845 # TEXT and BSS so we preserve their values in the config files.
1846 config ZBOOT_ROM_TEXT
1847         hex "Compressed ROM boot loader base address"
1848         default "0"
1849         help
1850           The physical address at which the ROM-able zImage is to be
1851           placed in the target.  Platforms which normally make use of
1852           ROM-able zImage formats normally set this to a suitable
1853           value in their defconfig file.
1854
1855           If ZBOOT_ROM is not enabled, this has no effect.
1856
1857 config ZBOOT_ROM_BSS
1858         hex "Compressed ROM boot loader BSS address"
1859         default "0"
1860         help
1861           The base address of an area of read/write memory in the target
1862           for the ROM-able zImage which must be available while the
1863           decompressor is running. It must be large enough to hold the
1864           entire decompressed kernel plus an additional 128 KiB.
1865           Platforms which normally make use of ROM-able zImage formats
1866           normally set this to a suitable value in their defconfig file.
1867
1868           If ZBOOT_ROM is not enabled, this has no effect.
1869
1870 config ZBOOT_ROM
1871         bool "Compressed boot loader in ROM/flash"
1872         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1873         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1874         help
1875           Say Y here if you intend to execute your compressed kernel image
1876           (zImage) directly from ROM or flash.  If unsure, say N.
1877
1878 config ARM_APPENDED_DTB
1879         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1880         depends on OF
1881         help
1882           With this option, the boot code will look for a device tree binary
1883           (DTB) appended to zImage
1884           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1885
1886           This is meant as a backward compatibility convenience for those
1887           systems with a bootloader that can't be upgraded to accommodate
1888           the documented boot protocol using a device tree.
1889
1890           Beware that there is very little in terms of protection against
1891           this option being confused by leftover garbage in memory that might
1892           look like a DTB header after a reboot if no actual DTB is appended
1893           to zImage.  Do not leave this option active in a production kernel
1894           if you don't intend to always append a DTB.  Proper passing of the
1895           location into r2 of a bootloader provided DTB is always preferable
1896           to this option.
1897
1898 config ARM_ATAG_DTB_COMPAT
1899         bool "Supplement the appended DTB with traditional ATAG information"
1900         depends on ARM_APPENDED_DTB
1901         help
1902           Some old bootloaders can't be updated to a DTB capable one, yet
1903           they provide ATAGs with memory configuration, the ramdisk address,
1904           the kernel cmdline string, etc.  Such information is dynamically
1905           provided by the bootloader and can't always be stored in a static
1906           DTB.  To allow a device tree enabled kernel to be used with such
1907           bootloaders, this option allows zImage to extract the information
1908           from the ATAG list and store it at run time into the appended DTB.
1909
1910 choice
1911         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1912         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1913
1914 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1915         bool "Use bootloader kernel arguments if available"
1916         help
1917           Uses the command-line options passed by the boot loader instead of
1918           the device tree bootargs property. If the boot loader doesn't provide
1919           any, the device tree bootargs property will be used.
1920
1921 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1922         bool "Extend with bootloader kernel arguments"
1923         help
1924           The command-line arguments provided by the boot loader will be
1925           appended to the the device tree bootargs property.
1926
1927 endchoice
1928
1929 config CMDLINE
1930         string "Default kernel command string"
1931         default ""
1932         help
1933           On some architectures (EBSA110 and CATS), there is currently no way
1934           for the boot loader to pass arguments to the kernel. For these
1935           architectures, you should supply some command-line options at build
1936           time by entering them here. As a minimum, you should specify the
1937           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1938
1939 choice
1940         prompt "Kernel command line type" if CMDLINE != ""
1941         default CMDLINE_FROM_BOOTLOADER
1942         depends on ATAGS
1943
1944 config CMDLINE_FROM_BOOTLOADER
1945         bool "Use bootloader kernel arguments if available"
1946         help
1947           Uses the command-line options passed by the boot loader. If
1948           the boot loader doesn't provide any, the default kernel command
1949           string provided in CMDLINE will be used.
1950
1951 config CMDLINE_EXTEND
1952         bool "Extend bootloader kernel arguments"
1953         help
1954           The command-line arguments provided by the boot loader will be
1955           appended to the default kernel command string.
1956
1957 config CMDLINE_FORCE
1958         bool "Always use the default kernel command string"
1959         help
1960           Always use the default kernel command string, even if the boot
1961           loader passes other arguments to the kernel.
1962           This is useful if you cannot or don't want to change the
1963           command-line options your boot loader passes to the kernel.
1964 endchoice
1965
1966 config XIP_KERNEL
1967         bool "Kernel Execute-In-Place from ROM"
1968         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1969         help
1970           Execute-In-Place allows the kernel to run from non-volatile storage
1971           directly addressable by the CPU, such as NOR flash. This saves RAM
1972           space since the text section of the kernel is not loaded from flash
1973           to RAM.  Read-write sections, such as the data section and stack,
1974           are still copied to RAM.  The XIP kernel is not compressed since
1975           it has to run directly from flash, so it will take more space to
1976           store it.  The flash address used to link the kernel object files,
1977           and for storing it, is configuration dependent. Therefore, if you
1978           say Y here, you must know the proper physical address where to
1979           store the kernel image depending on your own flash memory usage.
1980
1981           Also note that the make target becomes "make xipImage" rather than
1982           "make zImage" or "make Image".  The final kernel binary to put in
1983           ROM memory will be arch/arm/boot/xipImage.
1984
1985           If unsure, say N.
1986
1987 config XIP_PHYS_ADDR
1988         hex "XIP Kernel Physical Location"
1989         depends on XIP_KERNEL
1990         default "0x00080000"
1991         help
1992           This is the physical address in your flash memory the kernel will
1993           be linked for and stored to.  This address is dependent on your
1994           own flash usage.
1995
1996 config XIP_DEFLATED_DATA
1997         bool "Store kernel .data section compressed in ROM"
1998         depends on XIP_KERNEL
1999         select ZLIB_INFLATE
2000         help
2001           Before the kernel is actually executed, its .data section has to be
2002           copied to RAM from ROM. This option allows for storing that data
2003           in compressed form and decompressed to RAM rather than merely being
2004           copied, saving some precious ROM space. A possible drawback is a
2005           slightly longer boot delay.
2006
2007 config KEXEC
2008         bool "Kexec system call (EXPERIMENTAL)"
2009         depends on (!SMP || PM_SLEEP_SMP)
2010         depends on !CPU_V7M
2011         select KEXEC_CORE
2012         help
2013           kexec is a system call that implements the ability to shutdown your
2014           current kernel, and to start another kernel.  It is like a reboot
2015           but it is independent of the system firmware.   And like a reboot
2016           you can start any kernel with it, not just Linux.
2017
2018           It is an ongoing process to be certain the hardware in a machine
2019           is properly shutdown, so do not be surprised if this code does not
2020           initially work for you.
2021
2022 config ATAGS_PROC
2023         bool "Export atags in procfs"
2024         depends on ATAGS && KEXEC
2025         default y
2026         help
2027           Should the atags used to boot the kernel be exported in an "atags"
2028           file in procfs. Useful with kexec.
2029
2030 config CRASH_DUMP
2031         bool "Build kdump crash kernel (EXPERIMENTAL)"
2032         help
2033           Generate crash dump after being started by kexec. This should
2034           be normally only set in special crash dump kernels which are
2035           loaded in the main kernel with kexec-tools into a specially
2036           reserved region and then later executed after a crash by
2037           kdump/kexec. The crash dump kernel must be compiled to a
2038           memory address not used by the main kernel
2039
2040           For more details see Documentation/kdump/kdump.txt
2041
2042 config AUTO_ZRELADDR
2043         bool "Auto calculation of the decompressed kernel image address"
2044         help
2045           ZRELADDR is the physical address where the decompressed kernel
2046           image will be placed. If AUTO_ZRELADDR is selected, the address
2047           will be determined at run-time by masking the current IP with
2048           0xf8000000. This assumes the zImage being placed in the first 128MB
2049           from start of memory.
2050
2051 config EFI_STUB
2052         bool
2053
2054 config EFI
2055         bool "UEFI runtime support"
2056         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2057         select UCS2_STRING
2058         select EFI_PARAMS_FROM_FDT
2059         select EFI_STUB
2060         select EFI_ARMSTUB
2061         select EFI_RUNTIME_WRAPPERS
2062         ---help---
2063           This option provides support for runtime services provided
2064           by UEFI firmware (such as non-volatile variables, realtime
2065           clock, and platform reset). A UEFI stub is also provided to
2066           allow the kernel to be booted as an EFI application. This
2067           is only useful for kernels that may run on systems that have
2068           UEFI firmware.
2069
2070 config DMI
2071         bool "Enable support for SMBIOS (DMI) tables"
2072         depends on EFI
2073         default y
2074         help
2075           This enables SMBIOS/DMI feature for systems.
2076
2077           This option is only useful on systems that have UEFI firmware.
2078           However, even with this option, the resultant kernel should
2079           continue to boot on existing non-UEFI platforms.
2080
2081           NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2082           i.e., the the practice of identifying the platform via DMI to
2083           decide whether certain workarounds for buggy hardware and/or
2084           firmware need to be enabled. This would require the DMI subsystem
2085           to be enabled much earlier than we do on ARM, which is non-trivial.
2086
2087 endmenu
2088
2089 menu "CPU Power Management"
2090
2091 source "drivers/cpufreq/Kconfig"
2092
2093 source "drivers/cpuidle/Kconfig"
2094
2095 endmenu
2096
2097 menu "Floating point emulation"
2098
2099 comment "At least one emulation must be selected"
2100
2101 config FPE_NWFPE
2102         bool "NWFPE math emulation"
2103         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2104         ---help---
2105           Say Y to include the NWFPE floating point emulator in the kernel.
2106           This is necessary to run most binaries. Linux does not currently
2107           support floating point hardware so you need to say Y here even if
2108           your machine has an FPA or floating point co-processor podule.
2109
2110           You may say N here if you are going to load the Acorn FPEmulator
2111           early in the bootup.
2112
2113 config FPE_NWFPE_XP
2114         bool "Support extended precision"
2115         depends on FPE_NWFPE
2116         help
2117           Say Y to include 80-bit support in the kernel floating-point
2118           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2119           Note that gcc does not generate 80-bit operations by default,
2120           so in most cases this option only enlarges the size of the
2121           floating point emulator without any good reason.
2122
2123           You almost surely want to say N here.
2124
2125 config FPE_FASTFPE
2126         bool "FastFPE math emulation (EXPERIMENTAL)"
2127         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2128         ---help---
2129           Say Y here to include the FAST floating point emulator in the kernel.
2130           This is an experimental much faster emulator which now also has full
2131           precision for the mantissa.  It does not support any exceptions.
2132           It is very simple, and approximately 3-6 times faster than NWFPE.
2133
2134           It should be sufficient for most programs.  It may be not suitable
2135           for scientific calculations, but you have to check this for yourself.
2136           If you do not feel you need a faster FP emulation you should better
2137           choose NWFPE.
2138
2139 config VFP
2140         bool "VFP-format floating point maths"
2141         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2142         help
2143           Say Y to include VFP support code in the kernel. This is needed
2144           if your hardware includes a VFP unit.
2145
2146           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2147           release notes and additional status information.
2148
2149           Say N if your target does not have VFP hardware.
2150
2151 config VFPv3
2152         bool
2153         depends on VFP
2154         default y if CPU_V7
2155
2156 config NEON
2157         bool "Advanced SIMD (NEON) Extension support"
2158         depends on VFPv3 && CPU_V7
2159         help
2160           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2161           Extension.
2162
2163 config KERNEL_MODE_NEON
2164         bool "Support for NEON in kernel mode"
2165         depends on NEON && AEABI
2166         help
2167           Say Y to include support for NEON in kernel mode.
2168
2169 endmenu
2170
2171 menu "Userspace binary formats"
2172
2173 source "fs/Kconfig.binfmt"
2174
2175 endmenu
2176
2177 menu "Power management options"
2178
2179 source "kernel/power/Kconfig"
2180
2181 config ARCH_SUSPEND_POSSIBLE
2182         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2183                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2184         def_bool y
2185
2186 config ARM_CPU_SUSPEND
2187         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2188         depends on ARCH_SUSPEND_POSSIBLE
2189
2190 config ARCH_HIBERNATION_POSSIBLE
2191         bool
2192         depends on MMU
2193         default y if ARCH_SUSPEND_POSSIBLE
2194
2195 endmenu
2196
2197 source "net/Kconfig"
2198
2199 source "drivers/Kconfig"
2200
2201 source "drivers/firmware/Kconfig"
2202
2203 source "fs/Kconfig"
2204
2205 source "arch/arm/Kconfig.debug"
2206
2207 source "security/Kconfig"
2208
2209 source "crypto/Kconfig"
2210 if CRYPTO
2211 source "arch/arm/crypto/Kconfig"
2212 endif
2213
2214 source "lib/Kconfig"
2215
2216 source "arch/arm/kvm/Kconfig"