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1 /*
2 * linux/arch/arm/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
13
14 .arch armv7-a
15 /*
16 * Debugging stuff
17 *
18 * Note that these macros must not contain any code which is not
19 * 100% relocatable. Any attempt to do so will result in a crash.
20 * Please select one of the following when turning on debugging.
21 */
22 #ifdef DEBUG
23
24 #if defined(CONFIG_DEBUG_ICEDCC)
25
26 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
27 .macro loadsp, rb, tmp
28 .endm
29 .macro writeb, ch, rb
30 mcr p14, 0, \ch, c0, c5, 0
31 .endm
32 #elif defined(CONFIG_CPU_XSCALE)
33 .macro loadsp, rb, tmp
34 .endm
35 .macro writeb, ch, rb
36 mcr p14, 0, \ch, c8, c0, 0
37 .endm
38 #else
39 .macro loadsp, rb, tmp
40 .endm
41 .macro writeb, ch, rb
42 mcr p14, 0, \ch, c1, c0, 0
43 .endm
44 #endif
45
46 #else
47
48 #include CONFIG_DEBUG_LL_INCLUDE
49
50 .macro writeb, ch, rb
51 senduart \ch, \rb
52 .endm
53
54 #if defined(CONFIG_ARCH_SA1100)
55 .macro loadsp, rb, tmp
56 mov \rb, #0x80000000 @ physical base address
57 #ifdef CONFIG_DEBUG_LL_SER3
58 add \rb, \rb, #0x00050000 @ Ser3
59 #else
60 add \rb, \rb, #0x00010000 @ Ser1
61 #endif
62 .endm
63 #else
64 .macro loadsp, rb, tmp
65 addruart \rb, \tmp
66 .endm
67 #endif
68 #endif
69 #endif
70
71 .macro kputc,val
72 mov r0, \val
73 bl putc
74 .endm
75
76 .macro kphex,val,len
77 mov r0, \val
78 mov r1, #\len
79 bl phex
80 .endm
81
82 .macro debug_reloc_start
83 #ifdef DEBUG
84 kputc #'\n'
85 kphex r6, 8 /* processor id */
86 kputc #':'
87 kphex r7, 8 /* architecture id */
88 #ifdef CONFIG_CPU_CP15
89 kputc #':'
90 mrc p15, 0, r0, c1, c0
91 kphex r0, 8 /* control reg */
92 #endif
93 kputc #'\n'
94 kphex r5, 8 /* decompressed kernel start */
95 kputc #'-'
96 kphex r9, 8 /* decompressed kernel end */
97 kputc #'>'
98 kphex r4, 8 /* kernel execution address */
99 kputc #'\n'
100 #endif
101 .endm
102
103 .macro debug_reloc_end
104 #ifdef DEBUG
105 kphex r5, 8 /* end of kernel */
106 kputc #'\n'
107 mov r0, r4
108 bl memdump /* dump 256 bytes at start of kernel */
109 #endif
110 .endm
111
112 .section ".start", #alloc, #execinstr
113 /*
114 * sort out different calling conventions
115 */
116 .align
117 .arm @ Always enter in ARM state
118 start:
119 .type start,#function
120 .rept 7
121 mov r0, r0
122 .endr
123 ARM( mov r0, r0 )
124 ARM( b 1f )
125 THUMB( adr r12, BSYM(1f) )
126 THUMB( bx r12 )
127
128 .word _magic_sig @ Magic numbers to help the loader
129 .word _magic_start @ absolute load/run zImage address
130 .word _magic_end @ zImage end address
131 .word 0x04030201 @ endianness flag
132
133 THUMB( .thumb )
134 1:
135 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
136 mrs r9, cpsr
137 #ifdef CONFIG_ARM_VIRT_EXT
138 bl __hyp_stub_install @ get into SVC mode, reversibly
139 #endif
140 mov r7, r1 @ save architecture ID
141 mov r8, r2 @ save atags pointer
142
143 /*
144 * Booting from Angel - need to enter SVC mode and disable
145 * FIQs/IRQs (numeric definitions from angel arm.h source).
146 * We only do this if we were in user mode on entry.
147 */
148 mrs r2, cpsr @ get current mode
149 tst r2, #3 @ not user?
150 bne not_angel
151 mov r0, #0x17 @ angel_SWIreason_EnterSVC
152 ARM( swi 0x123456 ) @ angel_SWI_ARM
153 THUMB( svc 0xab ) @ angel_SWI_THUMB
154 not_angel:
155 safe_svcmode_maskall r0
156 msr spsr_cxsf, r9 @ Save the CPU boot mode in
157 @ SPSR
158 /*
159 * Note that some cache flushing and other stuff may
160 * be needed here - is there an Angel SWI call for this?
161 */
162
163 /*
164 * some architecture specific code can be inserted
165 * by the linker here, but it should preserve r7, r8, and r9.
166 */
167
168 .text
169
170 #ifdef CONFIG_AUTO_ZRELADDR
171 @ determine final kernel image address
172 mov r4, pc
173 and r4, r4, #0xf8000000
174 add r4, r4, #TEXT_OFFSET
175 #else
176 ldr r4, =zreladdr
177 #endif
178
179 /*
180 * Set up a page table only if it won't overwrite ourself.
181 * That means r4 < pc && r4 - 16k page directory > &_end.
182 * Given that r4 > &_end is most unfrequent, we add a rough
183 * additional 1MB of room for a possible appended DTB.
184 */
185 mov r0, pc
186 cmp r0, r4
187 ldrcc r0, LC0+32
188 addcc r0, r0, pc
189 cmpcc r4, r0
190 orrcc r4, r4, #1 @ remember we skipped cache_on
191 blcs cache_on
192
193 restart: adr r0, LC0
194 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
195 ldr sp, [r0, #28]
196
197 /*
198 * We might be running at a different address. We need
199 * to fix up various pointers.
200 */
201 sub r0, r0, r1 @ calculate the delta offset
202 add r6, r6, r0 @ _edata
203 add r10, r10, r0 @ inflated kernel size location
204
205 /*
206 * The kernel build system appends the size of the
207 * decompressed kernel at the end of the compressed data
208 * in little-endian form.
209 */
210 ldrb r9, [r10, #0]
211 ldrb lr, [r10, #1]
212 orr r9, r9, lr, lsl #8
213 ldrb lr, [r10, #2]
214 ldrb r10, [r10, #3]
215 orr r9, r9, lr, lsl #16
216 orr r9, r9, r10, lsl #24
217
218 #ifndef CONFIG_ZBOOT_ROM
219 /* malloc space is above the relocated stack (64k max) */
220 add sp, sp, r0
221 add r10, sp, #0x10000
222 #else
223 /*
224 * With ZBOOT_ROM the bss/stack is non relocatable,
225 * but someone could still run this code from RAM,
226 * in which case our reference is _edata.
227 */
228 mov r10, r6
229 #endif
230
231 mov r5, #0 @ init dtb size to 0
232 #ifdef CONFIG_ARM_APPENDED_DTB
233 /*
234 * r0 = delta
235 * r2 = BSS start
236 * r3 = BSS end
237 * r4 = final kernel address (possibly with LSB set)
238 * r5 = appended dtb size (still unknown)
239 * r6 = _edata
240 * r7 = architecture ID
241 * r8 = atags/device tree pointer
242 * r9 = size of decompressed image
243 * r10 = end of this image, including bss/stack/malloc space if non XIP
244 * r11 = GOT start
245 * r12 = GOT end
246 * sp = stack pointer
247 *
248 * if there are device trees (dtb) appended to zImage, advance r10 so that the
249 * dtb data will get relocated along with the kernel if necessary.
250 */
251
252 ldr lr, [r6, #0]
253 #ifndef __ARMEB__
254 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
255 #else
256 ldr r1, =0xd00dfeed
257 #endif
258 cmp lr, r1
259 bne dtb_check_done @ not found
260
261 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
262 /*
263 * OK... Let's do some funky business here.
264 * If we do have a DTB appended to zImage, and we do have
265 * an ATAG list around, we want the later to be translated
266 * and folded into the former here. To be on the safe side,
267 * let's temporarily move the stack away into the malloc
268 * area. No GOT fixup has occurred yet, but none of the
269 * code we're about to call uses any global variable.
270 */
271 add sp, sp, #0x10000
272 stmfd sp!, {r0-r3, ip, lr}
273 mov r0, r8
274 mov r1, r6
275 sub r2, sp, r6
276 bl atags_to_fdt
277
278 /*
279 * If returned value is 1, there is no ATAG at the location
280 * pointed by r8. Try the typical 0x100 offset from start
281 * of RAM and hope for the best.
282 */
283 cmp r0, #1
284 sub r0, r4, #TEXT_OFFSET
285 bic r0, r0, #1
286 add r0, r0, #0x100
287 mov r1, r6
288 sub r2, sp, r6
289 bleq atags_to_fdt
290
291 ldmfd sp!, {r0-r3, ip, lr}
292 sub sp, sp, #0x10000
293 #endif
294
295 mov r8, r6 @ use the appended device tree
296
297 /*
298 * Make sure that the DTB doesn't end up in the final
299 * kernel's .bss area. To do so, we adjust the decompressed
300 * kernel size to compensate if that .bss size is larger
301 * than the relocated code.
302 */
303 ldr r5, =_kernel_bss_size
304 adr r1, wont_overwrite
305 sub r1, r6, r1
306 subs r1, r5, r1
307 addhi r9, r9, r1
308
309 /* Get the dtb's size */
310 ldr r5, [r6, #4]
311 #ifndef __ARMEB__
312 /* convert r5 (dtb size) to little endian */
313 eor r1, r5, r5, ror #16
314 bic r1, r1, #0x00ff0000
315 mov r5, r5, ror #8
316 eor r5, r5, r1, lsr #8
317 #endif
318
319 /* preserve 64-bit alignment */
320 add r5, r5, #7
321 bic r5, r5, #7
322
323 /* relocate some pointers past the appended dtb */
324 add r6, r6, r5
325 add r10, r10, r5
326 add sp, sp, r5
327 dtb_check_done:
328 #endif
329
330 /*
331 * Check to see if we will overwrite ourselves.
332 * r4 = final kernel address (possibly with LSB set)
333 * r9 = size of decompressed image
334 * r10 = end of this image, including bss/stack/malloc space if non XIP
335 * We basically want:
336 * r4 - 16k page directory >= r10 -> OK
337 * r4 + image length <= address of wont_overwrite -> OK
338 * Note: the possible LSB in r4 is harmless here.
339 */
340 add r10, r10, #16384
341 cmp r4, r10
342 bhs wont_overwrite
343 add r10, r4, r9
344 adr r9, wont_overwrite
345 cmp r10, r9
346 bls wont_overwrite
347
348 /*
349 * Relocate ourselves past the end of the decompressed kernel.
350 * r6 = _edata
351 * r10 = end of the decompressed kernel
352 * Because we always copy ahead, we need to do it from the end and go
353 * backward in case the source and destination overlap.
354 */
355 /*
356 * Bump to the next 256-byte boundary with the size of
357 * the relocation code added. This avoids overwriting
358 * ourself when the offset is small.
359 */
360 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
361 bic r10, r10, #255
362
363 /* Get start of code we want to copy and align it down. */
364 adr r5, restart
365 bic r5, r5, #31
366
367 /* Relocate the hyp vector base if necessary */
368 #ifdef CONFIG_ARM_VIRT_EXT
369 mrs r0, spsr
370 and r0, r0, #MODE_MASK
371 cmp r0, #HYP_MODE
372 bne 1f
373
374 bl __hyp_get_vectors
375 sub r0, r0, r5
376 add r0, r0, r10
377 bl __hyp_set_vectors
378 1:
379 #endif
380
381 sub r9, r6, r5 @ size to copy
382 add r9, r9, #31 @ rounded up to a multiple
383 bic r9, r9, #31 @ ... of 32 bytes
384 add r6, r9, r5
385 add r9, r9, r10
386
387 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
388 cmp r6, r5
389 stmdb r9!, {r0 - r3, r10 - r12, lr}
390 bhi 1b
391
392 /* Preserve offset to relocated code. */
393 sub r6, r9, r6
394
395 #ifndef CONFIG_ZBOOT_ROM
396 /* cache_clean_flush may use the stack, so relocate it */
397 add sp, sp, r6
398 #endif
399
400 tst r4, #1
401 bleq cache_clean_flush
402
403 adr r0, BSYM(restart)
404 add r0, r0, r6
405 mov pc, r0
406
407 wont_overwrite:
408 /*
409 * If delta is zero, we are running at the address we were linked at.
410 * r0 = delta
411 * r2 = BSS start
412 * r3 = BSS end
413 * r4 = kernel execution address (possibly with LSB set)
414 * r5 = appended dtb size (0 if not present)
415 * r7 = architecture ID
416 * r8 = atags pointer
417 * r11 = GOT start
418 * r12 = GOT end
419 * sp = stack pointer
420 */
421 orrs r1, r0, r5
422 beq not_relocated
423
424 add r11, r11, r0
425 add r12, r12, r0
426
427 #ifndef CONFIG_ZBOOT_ROM
428 /*
429 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
430 * we need to fix up pointers into the BSS region.
431 * Note that the stack pointer has already been fixed up.
432 */
433 add r2, r2, r0
434 add r3, r3, r0
435
436 /*
437 * Relocate all entries in the GOT table.
438 * Bump bss entries to _edata + dtb size
439 */
440 1: ldr r1, [r11, #0] @ relocate entries in the GOT
441 add r1, r1, r0 @ This fixes up C references
442 cmp r1, r2 @ if entry >= bss_start &&
443 cmphs r3, r1 @ bss_end > entry
444 addhi r1, r1, r5 @ entry += dtb size
445 str r1, [r11], #4 @ next entry
446 cmp r11, r12
447 blo 1b
448
449 /* bump our bss pointers too */
450 add r2, r2, r5
451 add r3, r3, r5
452
453 #else
454
455 /*
456 * Relocate entries in the GOT table. We only relocate
457 * the entries that are outside the (relocated) BSS region.
458 */
459 1: ldr r1, [r11, #0] @ relocate entries in the GOT
460 cmp r1, r2 @ entry < bss_start ||
461 cmphs r3, r1 @ _end < entry
462 addlo r1, r1, r0 @ table. This fixes up the
463 str r1, [r11], #4 @ C references.
464 cmp r11, r12
465 blo 1b
466 #endif
467
468 not_relocated: mov r0, #0
469 1: str r0, [r2], #4 @ clear bss
470 str r0, [r2], #4
471 str r0, [r2], #4
472 str r0, [r2], #4
473 cmp r2, r3
474 blo 1b
475
476 /*
477 * Did we skip the cache setup earlier?
478 * That is indicated by the LSB in r4.
479 * Do it now if so.
480 */
481 tst r4, #1
482 bic r4, r4, #1
483 blne cache_on
484
485 /*
486 * The C runtime environment should now be setup sufficiently.
487 * Set up some pointers, and start decompressing.
488 * r4 = kernel execution address
489 * r7 = architecture ID
490 * r8 = atags pointer
491 */
492 mov r0, r4
493 mov r1, sp @ malloc space above stack
494 add r2, sp, #0x10000 @ 64k max
495 mov r3, r7
496 bl decompress_kernel
497 bl cache_clean_flush
498 bl cache_off
499 mov r1, r7 @ restore architecture number
500 mov r2, r8 @ restore atags pointer
501
502 #ifdef CONFIG_ARM_VIRT_EXT
503 mrs r0, spsr @ Get saved CPU boot mode
504 and r0, r0, #MODE_MASK
505 cmp r0, #HYP_MODE @ if not booted in HYP mode...
506 bne __enter_kernel @ boot kernel directly
507
508 adr r12, .L__hyp_reentry_vectors_offset
509 ldr r0, [r12]
510 add r0, r0, r12
511
512 bl __hyp_set_vectors
513 __HVC(0) @ otherwise bounce to hyp mode
514
515 b . @ should never be reached
516
517 .align 2
518 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
519 #else
520 b __enter_kernel
521 #endif
522
523 .align 2
524 .type LC0, #object
525 LC0: .word LC0 @ r1
526 .word __bss_start @ r2
527 .word _end @ r3
528 .word _edata @ r6
529 .word input_data_end - 4 @ r10 (inflated size location)
530 .word _got_start @ r11
531 .word _got_end @ ip
532 .word .L_user_stack_end @ sp
533 .word _end - restart + 16384 + 1024*1024
534 .size LC0, . - LC0
535
536 #ifdef CONFIG_ARCH_RPC
537 .globl params
538 params: ldr r0, =0x10000100 @ params_phys for RPC
539 mov pc, lr
540 .ltorg
541 .align
542 #endif
543
544 /*
545 * Turn on the cache. We need to setup some page tables so that we
546 * can have both the I and D caches on.
547 *
548 * We place the page tables 16k down from the kernel execution address,
549 * and we hope that nothing else is using it. If we're using it, we
550 * will go pop!
551 *
552 * On entry,
553 * r4 = kernel execution address
554 * r7 = architecture number
555 * r8 = atags pointer
556 * On exit,
557 * r0, r1, r2, r3, r9, r10, r12 corrupted
558 * This routine must preserve:
559 * r4, r7, r8
560 */
561 .align 5
562 cache_on: mov r3, #8 @ cache_on function
563 b call_cache_fn
564
565 /*
566 * Initialize the highest priority protection region, PR7
567 * to cover all 32bit address and cacheable and bufferable.
568 */
569 __armv4_mpu_cache_on:
570 mov r0, #0x3f @ 4G, the whole
571 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
572 mcr p15, 0, r0, c6, c7, 1
573
574 mov r0, #0x80 @ PR7
575 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
576 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
577 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
578
579 mov r0, #0xc000
580 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
581 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
582
583 mov r0, #0
584 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
585 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
586 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
587 mrc p15, 0, r0, c1, c0, 0 @ read control reg
588 @ ...I .... ..D. WC.M
589 orr r0, r0, #0x002d @ .... .... ..1. 11.1
590 orr r0, r0, #0x1000 @ ...1 .... .... ....
591
592 mcr p15, 0, r0, c1, c0, 0 @ write control reg
593
594 mov r0, #0
595 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
596 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
597 mov pc, lr
598
599 __armv3_mpu_cache_on:
600 mov r0, #0x3f @ 4G, the whole
601 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
602
603 mov r0, #0x80 @ PR7
604 mcr p15, 0, r0, c2, c0, 0 @ cache on
605 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
606
607 mov r0, #0xc000
608 mcr p15, 0, r0, c5, c0, 0 @ access permission
609
610 mov r0, #0
611 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
612 /*
613 * ?? ARMv3 MMU does not allow reading the control register,
614 * does this really work on ARMv3 MPU?
615 */
616 mrc p15, 0, r0, c1, c0, 0 @ read control reg
617 @ .... .... .... WC.M
618 orr r0, r0, #0x000d @ .... .... .... 11.1
619 /* ?? this overwrites the value constructed above? */
620 mov r0, #0
621 mcr p15, 0, r0, c1, c0, 0 @ write control reg
622
623 /* ?? invalidate for the second time? */
624 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
625 mov pc, lr
626
627 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
628 #define CB_BITS 0x08
629 #else
630 #define CB_BITS 0x0c
631 #endif
632
633 __setup_mmu: sub r3, r4, #16384 @ Page directory size
634 bic r3, r3, #0xff @ Align the pointer
635 bic r3, r3, #0x3f00
636 /*
637 * Initialise the page tables, turning on the cacheable and bufferable
638 * bits for the RAM area only.
639 */
640 mov r0, r3
641 mov r9, r0, lsr #18
642 mov r9, r9, lsl #18 @ start of RAM
643 add r10, r9, #0x10000000 @ a reasonable RAM size
644 mov r1, #0x12 @ XN|U + section mapping
645 orr r1, r1, #3 << 10 @ AP=11
646 add r2, r3, #16384
647 1: cmp r1, r9 @ if virt > start of RAM
648 cmphs r10, r1 @ && end of RAM > virt
649 bic r1, r1, #0x1c @ clear XN|U + C + B
650 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
651 orrhs r1, r1, r6 @ set RAM section settings
652 str r1, [r0], #4 @ 1:1 mapping
653 add r1, r1, #1048576
654 teq r0, r2
655 bne 1b
656 /*
657 * If ever we are running from Flash, then we surely want the cache
658 * to be enabled also for our execution instance... We map 2MB of it
659 * so there is no map overlap problem for up to 1 MB compressed kernel.
660 * If the execution is in RAM then we would only be duplicating the above.
661 */
662 orr r1, r6, #0x04 @ ensure B is set for this
663 orr r1, r1, #3 << 10
664 mov r2, pc
665 mov r2, r2, lsr #20
666 orr r1, r1, r2, lsl #20
667 add r0, r3, r2, lsl #2
668 str r1, [r0], #4
669 add r1, r1, #1048576
670 str r1, [r0]
671 mov pc, lr
672 ENDPROC(__setup_mmu)
673
674 @ Enable unaligned access on v6, to allow better code generation
675 @ for the decompressor C code:
676 __armv6_mmu_cache_on:
677 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
678 bic r0, r0, #2 @ A (no unaligned access fault)
679 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
680 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
681 b __armv4_mmu_cache_on
682
683 __arm926ejs_mmu_cache_on:
684 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
685 mov r0, #4 @ put dcache in WT mode
686 mcr p15, 7, r0, c15, c0, 0
687 #endif
688
689 __armv4_mmu_cache_on:
690 mov r12, lr
691 #ifdef CONFIG_MMU
692 mov r6, #CB_BITS | 0x12 @ U
693 bl __setup_mmu
694 mov r0, #0
695 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
696 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
697 mrc p15, 0, r0, c1, c0, 0 @ read control reg
698 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
699 orr r0, r0, #0x0030
700 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
701 bl __common_mmu_cache_on
702 mov r0, #0
703 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
704 #endif
705 mov pc, r12
706
707 __armv7_mmu_cache_on:
708 mov r12, lr
709 #ifdef CONFIG_MMU
710 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
711 tst r11, #0xf @ VMSA
712 movne r6, #CB_BITS | 0x02 @ !XN
713 blne __setup_mmu
714 mov r0, #0
715 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
716 tst r11, #0xf @ VMSA
717 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
718 #endif
719 mrc p15, 0, r0, c1, c0, 0 @ read control reg
720 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
721 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
722 orr r0, r0, #0x003c @ write buffer
723 bic r0, r0, #2 @ A (no unaligned access fault)
724 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
725 @ (needed for ARM1176)
726 #ifdef CONFIG_MMU
727 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
728 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
729 orrne r0, r0, #1 @ MMU enabled
730 movne r1, #0xfffffffd @ domain 0 = client
731 bic r6, r6, #1 << 31 @ 32-bit translation system
732 bic r6, r6, #3 << 0 @ use only ttbr0
733 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
734 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
735 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
736 #endif
737 mcr p15, 0, r0, c7, c5, 4 @ ISB
738 mcr p15, 0, r0, c1, c0, 0 @ load control register
739 mrc p15, 0, r0, c1, c0, 0 @ and read it back
740 mov r0, #0
741 mcr p15, 0, r0, c7, c5, 4 @ ISB
742 mov pc, r12
743
744 __fa526_cache_on:
745 mov r12, lr
746 mov r6, #CB_BITS | 0x12 @ U
747 bl __setup_mmu
748 mov r0, #0
749 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
750 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
751 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
752 mrc p15, 0, r0, c1, c0, 0 @ read control reg
753 orr r0, r0, #0x1000 @ I-cache enable
754 bl __common_mmu_cache_on
755 mov r0, #0
756 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
757 mov pc, r12
758
759 __common_mmu_cache_on:
760 #ifndef CONFIG_THUMB2_KERNEL
761 #ifndef DEBUG
762 orr r0, r0, #0x000d @ Write buffer, mmu
763 #endif
764 mov r1, #-1
765 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
766 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
767 b 1f
768 .align 5 @ cache line aligned
769 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
770 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
771 sub pc, lr, r0, lsr #32 @ properly flush pipeline
772 #endif
773
774 #define PROC_ENTRY_SIZE (4*5)
775
776 /*
777 * Here follow the relocatable cache support functions for the
778 * various processors. This is a generic hook for locating an
779 * entry and jumping to an instruction at the specified offset
780 * from the start of the block. Please note this is all position
781 * independent code.
782 *
783 * r1 = corrupted
784 * r2 = corrupted
785 * r3 = block offset
786 * r9 = corrupted
787 * r12 = corrupted
788 */
789
790 call_cache_fn: adr r12, proc_types
791 #ifdef CONFIG_CPU_CP15
792 mrc p15, 0, r9, c0, c0 @ get processor ID
793 #else
794 ldr r9, =CONFIG_PROCESSOR_ID
795 #endif
796 1: ldr r1, [r12, #0] @ get value
797 ldr r2, [r12, #4] @ get mask
798 eor r1, r1, r9 @ (real ^ match)
799 tst r1, r2 @ & mask
800 ARM( addeq pc, r12, r3 ) @ call cache function
801 THUMB( addeq r12, r3 )
802 THUMB( moveq pc, r12 ) @ call cache function
803 add r12, r12, #PROC_ENTRY_SIZE
804 b 1b
805
806 /*
807 * Table for cache operations. This is basically:
808 * - CPU ID match
809 * - CPU ID mask
810 * - 'cache on' method instruction
811 * - 'cache off' method instruction
812 * - 'cache flush' method instruction
813 *
814 * We match an entry using: ((real_id ^ match) & mask) == 0
815 *
816 * Writethrough caches generally only need 'on' and 'off'
817 * methods. Writeback caches _must_ have the flush method
818 * defined.
819 */
820 .align 2
821 .type proc_types,#object
822 proc_types:
823 .word 0x41000000 @ old ARM ID
824 .word 0xff00f000
825 mov pc, lr
826 THUMB( nop )
827 mov pc, lr
828 THUMB( nop )
829 mov pc, lr
830 THUMB( nop )
831
832 .word 0x41007000 @ ARM7/710
833 .word 0xfff8fe00
834 mov pc, lr
835 THUMB( nop )
836 mov pc, lr
837 THUMB( nop )
838 mov pc, lr
839 THUMB( nop )
840
841 .word 0x41807200 @ ARM720T (writethrough)
842 .word 0xffffff00
843 W(b) __armv4_mmu_cache_on
844 W(b) __armv4_mmu_cache_off
845 mov pc, lr
846 THUMB( nop )
847
848 .word 0x41007400 @ ARM74x
849 .word 0xff00ff00
850 W(b) __armv3_mpu_cache_on
851 W(b) __armv3_mpu_cache_off
852 W(b) __armv3_mpu_cache_flush
853
854 .word 0x41009400 @ ARM94x
855 .word 0xff00ff00
856 W(b) __armv4_mpu_cache_on
857 W(b) __armv4_mpu_cache_off
858 W(b) __armv4_mpu_cache_flush
859
860 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
861 .word 0xff0ffff0
862 W(b) __arm926ejs_mmu_cache_on
863 W(b) __armv4_mmu_cache_off
864 W(b) __armv5tej_mmu_cache_flush
865
866 .word 0x00007000 @ ARM7 IDs
867 .word 0x0000f000
868 mov pc, lr
869 THUMB( nop )
870 mov pc, lr
871 THUMB( nop )
872 mov pc, lr
873 THUMB( nop )
874
875 @ Everything from here on will be the new ID system.
876
877 .word 0x4401a100 @ sa110 / sa1100
878 .word 0xffffffe0
879 W(b) __armv4_mmu_cache_on
880 W(b) __armv4_mmu_cache_off
881 W(b) __armv4_mmu_cache_flush
882
883 .word 0x6901b110 @ sa1110
884 .word 0xfffffff0
885 W(b) __armv4_mmu_cache_on
886 W(b) __armv4_mmu_cache_off
887 W(b) __armv4_mmu_cache_flush
888
889 .word 0x56056900
890 .word 0xffffff00 @ PXA9xx
891 W(b) __armv4_mmu_cache_on
892 W(b) __armv4_mmu_cache_off
893 W(b) __armv4_mmu_cache_flush
894
895 .word 0x56158000 @ PXA168
896 .word 0xfffff000
897 W(b) __armv4_mmu_cache_on
898 W(b) __armv4_mmu_cache_off
899 W(b) __armv5tej_mmu_cache_flush
900
901 .word 0x56050000 @ Feroceon
902 .word 0xff0f0000
903 W(b) __armv4_mmu_cache_on
904 W(b) __armv4_mmu_cache_off
905 W(b) __armv5tej_mmu_cache_flush
906
907 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
908 /* this conflicts with the standard ARMv5TE entry */
909 .long 0x41009260 @ Old Feroceon
910 .long 0xff00fff0
911 b __armv4_mmu_cache_on
912 b __armv4_mmu_cache_off
913 b __armv5tej_mmu_cache_flush
914 #endif
915
916 .word 0x66015261 @ FA526
917 .word 0xff01fff1
918 W(b) __fa526_cache_on
919 W(b) __armv4_mmu_cache_off
920 W(b) __fa526_cache_flush
921
922 @ These match on the architecture ID
923
924 .word 0x00020000 @ ARMv4T
925 .word 0x000f0000
926 W(b) __armv4_mmu_cache_on
927 W(b) __armv4_mmu_cache_off
928 W(b) __armv4_mmu_cache_flush
929
930 .word 0x00050000 @ ARMv5TE
931 .word 0x000f0000
932 W(b) __armv4_mmu_cache_on
933 W(b) __armv4_mmu_cache_off
934 W(b) __armv4_mmu_cache_flush
935
936 .word 0x00060000 @ ARMv5TEJ
937 .word 0x000f0000
938 W(b) __armv4_mmu_cache_on
939 W(b) __armv4_mmu_cache_off
940 W(b) __armv5tej_mmu_cache_flush
941
942 .word 0x0007b000 @ ARMv6
943 .word 0x000ff000
944 W(b) __armv6_mmu_cache_on
945 W(b) __armv4_mmu_cache_off
946 W(b) __armv6_mmu_cache_flush
947
948 .word 0x000f0000 @ new CPU Id
949 .word 0x000f0000
950 W(b) __armv7_mmu_cache_on
951 W(b) __armv7_mmu_cache_off
952 W(b) __armv7_mmu_cache_flush
953
954 .word 0 @ unrecognised type
955 .word 0
956 mov pc, lr
957 THUMB( nop )
958 mov pc, lr
959 THUMB( nop )
960 mov pc, lr
961 THUMB( nop )
962
963 .size proc_types, . - proc_types
964
965 /*
966 * If you get a "non-constant expression in ".if" statement"
967 * error from the assembler on this line, check that you have
968 * not accidentally written a "b" instruction where you should
969 * have written W(b).
970 */
971 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
972 .error "The size of one or more proc_types entries is wrong."
973 .endif
974
975 /*
976 * Turn off the Cache and MMU. ARMv3 does not support
977 * reading the control register, but ARMv4 does.
978 *
979 * On exit,
980 * r0, r1, r2, r3, r9, r12 corrupted
981 * This routine must preserve:
982 * r4, r7, r8
983 */
984 .align 5
985 cache_off: mov r3, #12 @ cache_off function
986 b call_cache_fn
987
988 __armv4_mpu_cache_off:
989 mrc p15, 0, r0, c1, c0
990 bic r0, r0, #0x000d
991 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
992 mov r0, #0
993 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
994 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
995 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
996 mov pc, lr
997
998 __armv3_mpu_cache_off:
999 mrc p15, 0, r0, c1, c0
1000 bic r0, r0, #0x000d
1001 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1002 mov r0, #0
1003 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1004 mov pc, lr
1005
1006 __armv4_mmu_cache_off:
1007 #ifdef CONFIG_MMU
1008 mrc p15, 0, r0, c1, c0
1009 bic r0, r0, #0x000d
1010 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1011 mov r0, #0
1012 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1013 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1014 #endif
1015 mov pc, lr
1016
1017 __armv7_mmu_cache_off:
1018 mrc p15, 0, r0, c1, c0
1019 #ifdef CONFIG_MMU
1020 bic r0, r0, #0x000d
1021 #else
1022 bic r0, r0, #0x000c
1023 #endif
1024 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1025 mov r12, lr
1026 bl __armv7_mmu_cache_flush
1027 mov r0, #0
1028 #ifdef CONFIG_MMU
1029 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1030 #endif
1031 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1032 mcr p15, 0, r0, c7, c10, 4 @ DSB
1033 mcr p15, 0, r0, c7, c5, 4 @ ISB
1034 mov pc, r12
1035
1036 /*
1037 * Clean and flush the cache to maintain consistency.
1038 *
1039 * On exit,
1040 * r1, r2, r3, r9, r10, r11, r12 corrupted
1041 * This routine must preserve:
1042 * r4, r6, r7, r8
1043 */
1044 .align 5
1045 cache_clean_flush:
1046 mov r3, #16
1047 b call_cache_fn
1048
1049 __armv4_mpu_cache_flush:
1050 mov r2, #1
1051 mov r3, #0
1052 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1053 mov r1, #7 << 5 @ 8 segments
1054 1: orr r3, r1, #63 << 26 @ 64 entries
1055 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1056 subs r3, r3, #1 << 26
1057 bcs 2b @ entries 63 to 0
1058 subs r1, r1, #1 << 5
1059 bcs 1b @ segments 7 to 0
1060
1061 teq r2, #0
1062 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1063 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1064 mov pc, lr
1065
1066 __fa526_cache_flush:
1067 mov r1, #0
1068 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1069 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1070 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1071 mov pc, lr
1072
1073 __armv6_mmu_cache_flush:
1074 mov r1, #0
1075 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1076 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1077 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1078 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1079 mov pc, lr
1080
1081 __armv7_mmu_cache_flush:
1082 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1083 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1084 mov r10, #0
1085 beq hierarchical
1086 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1087 b iflush
1088 hierarchical:
1089 mcr p15, 0, r10, c7, c10, 5 @ DMB
1090 stmfd sp!, {r0-r7, r9-r11}
1091 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1092 ands r3, r0, #0x7000000 @ extract loc from clidr
1093 mov r3, r3, lsr #23 @ left align loc bit field
1094 beq finished @ if loc is 0, then no need to clean
1095 mov r10, #0 @ start clean at cache level 0
1096 loop1:
1097 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1098 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1099 and r1, r1, #7 @ mask of the bits for current cache only
1100 cmp r1, #2 @ see what cache we have at this level
1101 blt skip @ skip if no cache, or just i-cache
1102 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1103 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1104 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1105 and r2, r1, #7 @ extract the length of the cache lines
1106 add r2, r2, #4 @ add 4 (line length offset)
1107 ldr r4, =0x3ff
1108 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1109 clz r5, r4 @ find bit position of way size increment
1110 ldr r7, =0x7fff
1111 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1112 loop2:
1113 mov r9, r4 @ create working copy of max way size
1114 loop3:
1115 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1116 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1117 THUMB( lsl r6, r9, r5 )
1118 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1119 THUMB( lsl r6, r7, r2 )
1120 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1121 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1122 subs r9, r9, #1 @ decrement the way
1123 bge loop3
1124 subs r7, r7, #1 @ decrement the index
1125 bge loop2
1126 skip:
1127 add r10, r10, #2 @ increment cache number
1128 cmp r3, r10
1129 bgt loop1
1130 finished:
1131 ldmfd sp!, {r0-r7, r9-r11}
1132 mov r10, #0 @ swith back to cache level 0
1133 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1134 iflush:
1135 mcr p15, 0, r10, c7, c10, 4 @ DSB
1136 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1137 mcr p15, 0, r10, c7, c10, 4 @ DSB
1138 mcr p15, 0, r10, c7, c5, 4 @ ISB
1139 mov pc, lr
1140
1141 __armv5tej_mmu_cache_flush:
1142 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1143 bne 1b
1144 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1145 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1146 mov pc, lr
1147
1148 __armv4_mmu_cache_flush:
1149 mov r2, #64*1024 @ default: 32K dcache size (*2)
1150 mov r11, #32 @ default: 32 byte line size
1151 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1152 teq r3, r9 @ cache ID register present?
1153 beq no_cache_id
1154 mov r1, r3, lsr #18
1155 and r1, r1, #7
1156 mov r2, #1024
1157 mov r2, r2, lsl r1 @ base dcache size *2
1158 tst r3, #1 << 14 @ test M bit
1159 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1160 mov r3, r3, lsr #12
1161 and r3, r3, #3
1162 mov r11, #8
1163 mov r11, r11, lsl r3 @ cache line size in bytes
1164 no_cache_id:
1165 mov r1, pc
1166 bic r1, r1, #63 @ align to longest cache line
1167 add r2, r1, r2
1168 1:
1169 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1170 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1171 THUMB( add r1, r1, r11 )
1172 teq r1, r2
1173 bne 1b
1174
1175 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1176 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1177 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1178 mov pc, lr
1179
1180 __armv3_mmu_cache_flush:
1181 __armv3_mpu_cache_flush:
1182 mov r1, #0
1183 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1184 mov pc, lr
1185
1186 /*
1187 * Various debugging routines for printing hex characters and
1188 * memory, which again must be relocatable.
1189 */
1190 #ifdef DEBUG
1191 .align 2
1192 .type phexbuf,#object
1193 phexbuf: .space 12
1194 .size phexbuf, . - phexbuf
1195
1196 @ phex corrupts {r0, r1, r2, r3}
1197 phex: adr r3, phexbuf
1198 mov r2, #0
1199 strb r2, [r3, r1]
1200 1: subs r1, r1, #1
1201 movmi r0, r3
1202 bmi puts
1203 and r2, r0, #15
1204 mov r0, r0, lsr #4
1205 cmp r2, #10
1206 addge r2, r2, #7
1207 add r2, r2, #'0'
1208 strb r2, [r3, r1]
1209 b 1b
1210
1211 @ puts corrupts {r0, r1, r2, r3}
1212 puts: loadsp r3, r1
1213 1: ldrb r2, [r0], #1
1214 teq r2, #0
1215 moveq pc, lr
1216 2: writeb r2, r3
1217 mov r1, #0x00020000
1218 3: subs r1, r1, #1
1219 bne 3b
1220 teq r2, #'\n'
1221 moveq r2, #'\r'
1222 beq 2b
1223 teq r0, #0
1224 bne 1b
1225 mov pc, lr
1226 @ putc corrupts {r0, r1, r2, r3}
1227 putc:
1228 mov r2, r0
1229 mov r0, #0
1230 loadsp r3, r1
1231 b 2b
1232
1233 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1234 memdump: mov r12, r0
1235 mov r10, lr
1236 mov r11, #0
1237 2: mov r0, r11, lsl #2
1238 add r0, r0, r12
1239 mov r1, #8
1240 bl phex
1241 mov r0, #':'
1242 bl putc
1243 1: mov r0, #' '
1244 bl putc
1245 ldr r0, [r12, r11, lsl #2]
1246 mov r1, #8
1247 bl phex
1248 and r0, r11, #7
1249 teq r0, #3
1250 moveq r0, #' '
1251 bleq putc
1252 and r0, r11, #7
1253 add r11, r11, #1
1254 teq r0, #7
1255 bne 1b
1256 mov r0, #'\n'
1257 bl putc
1258 cmp r11, #64
1259 blt 2b
1260 mov pc, r10
1261 #endif
1262
1263 .ltorg
1264
1265 #ifdef CONFIG_ARM_VIRT_EXT
1266 .align 5
1267 __hyp_reentry_vectors:
1268 W(b) . @ reset
1269 W(b) . @ undef
1270 W(b) . @ svc
1271 W(b) . @ pabort
1272 W(b) . @ dabort
1273 W(b) __enter_kernel @ hyp
1274 W(b) . @ irq
1275 W(b) . @ fiq
1276 #endif /* CONFIG_ARM_VIRT_EXT */
1277
1278 __enter_kernel:
1279 mov r0, #0 @ must be 0
1280 ARM( mov pc, r4 ) @ call kernel
1281 THUMB( bx r4 ) @ entry point is always ARM
1282
1283 reloc_code_end:
1284
1285 .align
1286 .section ".stack", "aw", %nobits
1287 .L_user_stack: .space 4096
1288 .L_user_stack_end:
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