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1 /*
2 * linux/arch/arm/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/linkage.h>
12
13 /*
14 * Debugging stuff
15 *
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
19 */
20 #ifdef DEBUG
21
22 #if defined(CONFIG_DEBUG_ICEDCC)
23
24 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
25 .macro loadsp, rb, tmp
26 .endm
27 .macro writeb, ch, rb
28 mcr p14, 0, \ch, c0, c5, 0
29 .endm
30 #elif defined(CONFIG_CPU_XSCALE)
31 .macro loadsp, rb, tmp
32 .endm
33 .macro writeb, ch, rb
34 mcr p14, 0, \ch, c8, c0, 0
35 .endm
36 #else
37 .macro loadsp, rb, tmp
38 .endm
39 .macro writeb, ch, rb
40 mcr p14, 0, \ch, c1, c0, 0
41 .endm
42 #endif
43
44 #else
45
46 #include <mach/debug-macro.S>
47
48 .macro writeb, ch, rb
49 senduart \ch, \rb
50 .endm
51
52 #if defined(CONFIG_ARCH_SA1100)
53 .macro loadsp, rb, tmp
54 mov \rb, #0x80000000 @ physical base address
55 #ifdef CONFIG_DEBUG_LL_SER3
56 add \rb, \rb, #0x00050000 @ Ser3
57 #else
58 add \rb, \rb, #0x00010000 @ Ser1
59 #endif
60 .endm
61 #elif defined(CONFIG_ARCH_S3C2410)
62 .macro loadsp, rb, tmp
63 mov \rb, #0x50000000
64 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
65 .endm
66 #else
67 .macro loadsp, rb, tmp
68 addruart \rb, \tmp
69 .endm
70 #endif
71 #endif
72 #endif
73
74 .macro kputc,val
75 mov r0, \val
76 bl putc
77 .endm
78
79 .macro kphex,val,len
80 mov r0, \val
81 mov r1, #\len
82 bl phex
83 .endm
84
85 .macro debug_reloc_start
86 #ifdef DEBUG
87 kputc #'\n'
88 kphex r6, 8 /* processor id */
89 kputc #':'
90 kphex r7, 8 /* architecture id */
91 #ifdef CONFIG_CPU_CP15
92 kputc #':'
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
95 #endif
96 kputc #'\n'
97 kphex r5, 8 /* decompressed kernel start */
98 kputc #'-'
99 kphex r9, 8 /* decompressed kernel end */
100 kputc #'>'
101 kphex r4, 8 /* kernel execution address */
102 kputc #'\n'
103 #endif
104 .endm
105
106 .macro debug_reloc_end
107 #ifdef DEBUG
108 kphex r5, 8 /* end of kernel */
109 kputc #'\n'
110 mov r0, r4
111 bl memdump /* dump 256 bytes at start of kernel */
112 #endif
113 .endm
114
115 .section ".start", #alloc, #execinstr
116 /*
117 * sort out different calling conventions
118 */
119 .align
120 .arm @ Always enter in ARM state
121 start:
122 .type start,#function
123 .rept 7
124 mov r0, r0
125 .endr
126 ARM( mov r0, r0 )
127 ARM( b 1f )
128 THUMB( adr r12, BSYM(1f) )
129 THUMB( bx r12 )
130
131 .word 0x016f2818 @ Magic numbers to help the loader
132 .word start @ absolute load/run zImage address
133 .word _edata @ zImage end address
134 THUMB( .thumb )
135 1: mov r7, r1 @ save architecture ID
136 mov r8, r2 @ save atags pointer
137
138 #ifndef __ARM_ARCH_2__
139 /*
140 * Booting from Angel - need to enter SVC mode and disable
141 * FIQs/IRQs (numeric definitions from angel arm.h source).
142 * We only do this if we were in user mode on entry.
143 */
144 mrs r2, cpsr @ get current mode
145 tst r2, #3 @ not user?
146 bne not_angel
147 mov r0, #0x17 @ angel_SWIreason_EnterSVC
148 ARM( swi 0x123456 ) @ angel_SWI_ARM
149 THUMB( svc 0xab ) @ angel_SWI_THUMB
150 not_angel:
151 mrs r2, cpsr @ turn off interrupts to
152 orr r2, r2, #0xc0 @ prevent angel from running
153 msr cpsr_c, r2
154 #else
155 teqp pc, #0x0c000003 @ turn off interrupts
156 #endif
157
158 /*
159 * Note that some cache flushing and other stuff may
160 * be needed here - is there an Angel SWI call for this?
161 */
162
163 /*
164 * some architecture specific code can be inserted
165 * by the linker here, but it should preserve r7, r8, and r9.
166 */
167
168 .text
169
170 #ifdef CONFIG_AUTO_ZRELADDR
171 @ determine final kernel image address
172 mov r4, pc
173 and r4, r4, #0xf8000000
174 add r4, r4, #TEXT_OFFSET
175 #else
176 ldr r4, =zreladdr
177 #endif
178
179 bl cache_on
180
181 restart: adr r0, LC0
182 ldmia r0, {r1, r2, r3, r6, r9, r11, r12}
183 ldr sp, [r0, #28]
184
185 /*
186 * We might be running at a different address. We need
187 * to fix up various pointers.
188 */
189 sub r0, r0, r1 @ calculate the delta offset
190 add r6, r6, r0 @ _edata
191
192 #ifndef CONFIG_ZBOOT_ROM
193 /* malloc space is above the relocated stack (64k max) */
194 add sp, sp, r0
195 add r10, sp, #0x10000
196 #else
197 /*
198 * With ZBOOT_ROM the bss/stack is non relocatable,
199 * but someone could still run this code from RAM,
200 * in which case our reference is _edata.
201 */
202 mov r10, r6
203 #endif
204
205 /*
206 * Check to see if we will overwrite ourselves.
207 * r4 = final kernel address
208 * r9 = size of decompressed image
209 * r10 = end of this image, including bss/stack/malloc space if non XIP
210 * We basically want:
211 * r4 - 16k page directory >= r10 -> OK
212 * r4 + image length <= current position (pc) -> OK
213 */
214 add r10, r10, #16384
215 cmp r4, r10
216 bhs wont_overwrite
217 add r10, r4, r9
218 ARM( cmp r10, pc )
219 THUMB( mov lr, pc )
220 THUMB( cmp r10, lr )
221 bls wont_overwrite
222
223 /*
224 * Relocate ourselves past the end of the decompressed kernel.
225 * r6 = _edata
226 * r10 = end of the decompressed kernel
227 * Because we always copy ahead, we need to do it from the end and go
228 * backward in case the source and destination overlap.
229 */
230 /*
231 * Bump to the next 256-byte boundary with the size of
232 * the relocation code added. This avoids overwriting
233 * ourself when the offset is small.
234 */
235 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
236 bic r10, r10, #255
237
238 /* Get start of code we want to copy and align it down. */
239 adr r5, restart
240 bic r5, r5, #31
241
242 sub r9, r6, r5 @ size to copy
243 add r9, r9, #31 @ rounded up to a multiple
244 bic r9, r9, #31 @ ... of 32 bytes
245 add r6, r9, r5
246 add r9, r9, r10
247
248 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
249 cmp r6, r5
250 stmdb r9!, {r0 - r3, r10 - r12, lr}
251 bhi 1b
252
253 /* Preserve offset to relocated code. */
254 sub r6, r9, r6
255
256 #ifndef CONFIG_ZBOOT_ROM
257 /* cache_clean_flush may use the stack, so relocate it */
258 add sp, sp, r6
259 #endif
260
261 bl cache_clean_flush
262
263 adr r0, BSYM(restart)
264 add r0, r0, r6
265 mov pc, r0
266
267 wont_overwrite:
268 /*
269 * If delta is zero, we are running at the address we were linked at.
270 * r0 = delta
271 * r2 = BSS start
272 * r3 = BSS end
273 * r4 = kernel execution address
274 * r7 = architecture ID
275 * r8 = atags pointer
276 * r11 = GOT start
277 * r12 = GOT end
278 * sp = stack pointer
279 */
280 teq r0, #0
281 beq not_relocated
282 add r11, r11, r0
283 add r12, r12, r0
284
285 #ifndef CONFIG_ZBOOT_ROM
286 /*
287 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
288 * we need to fix up pointers into the BSS region.
289 * Note that the stack pointer has already been fixed up.
290 */
291 add r2, r2, r0
292 add r3, r3, r0
293
294 /*
295 * Relocate all entries in the GOT table.
296 */
297 1: ldr r1, [r11, #0] @ relocate entries in the GOT
298 add r1, r1, r0 @ table. This fixes up the
299 str r1, [r11], #4 @ C references.
300 cmp r11, r12
301 blo 1b
302 #else
303
304 /*
305 * Relocate entries in the GOT table. We only relocate
306 * the entries that are outside the (relocated) BSS region.
307 */
308 1: ldr r1, [r11, #0] @ relocate entries in the GOT
309 cmp r1, r2 @ entry < bss_start ||
310 cmphs r3, r1 @ _end < entry
311 addlo r1, r1, r0 @ table. This fixes up the
312 str r1, [r11], #4 @ C references.
313 cmp r11, r12
314 blo 1b
315 #endif
316
317 not_relocated: mov r0, #0
318 1: str r0, [r2], #4 @ clear bss
319 str r0, [r2], #4
320 str r0, [r2], #4
321 str r0, [r2], #4
322 cmp r2, r3
323 blo 1b
324
325 /*
326 * The C runtime environment should now be setup sufficiently.
327 * Set up some pointers, and start decompressing.
328 * r4 = kernel execution address
329 * r7 = architecture ID
330 * r8 = atags pointer
331 */
332 mov r0, r4
333 mov r1, sp @ malloc space above stack
334 add r2, sp, #0x10000 @ 64k max
335 mov r3, r7
336 bl decompress_kernel
337 bl cache_clean_flush
338 bl cache_off
339 mov r0, #0 @ must be zero
340 mov r1, r7 @ restore architecture number
341 mov r2, r8 @ restore atags pointer
342 mov pc, r4 @ call kernel
343
344 .align 2
345 .type LC0, #object
346 LC0: .word LC0 @ r1
347 .word __bss_start @ r2
348 .word _end @ r3
349 .word _edata @ r6
350 .word _image_size @ r9
351 .word _got_start @ r11
352 .word _got_end @ ip
353 .word user_stack_end @ sp
354 .size LC0, . - LC0
355
356 #ifdef CONFIG_ARCH_RPC
357 .globl params
358 params: ldr r0, =0x10000100 @ params_phys for RPC
359 mov pc, lr
360 .ltorg
361 .align
362 #endif
363
364 /*
365 * Turn on the cache. We need to setup some page tables so that we
366 * can have both the I and D caches on.
367 *
368 * We place the page tables 16k down from the kernel execution address,
369 * and we hope that nothing else is using it. If we're using it, we
370 * will go pop!
371 *
372 * On entry,
373 * r4 = kernel execution address
374 * r7 = architecture number
375 * r8 = atags pointer
376 * On exit,
377 * r0, r1, r2, r3, r9, r10, r12 corrupted
378 * This routine must preserve:
379 * r4, r7, r8
380 */
381 .align 5
382 cache_on: mov r3, #8 @ cache_on function
383 b call_cache_fn
384
385 /*
386 * Initialize the highest priority protection region, PR7
387 * to cover all 32bit address and cacheable and bufferable.
388 */
389 __armv4_mpu_cache_on:
390 mov r0, #0x3f @ 4G, the whole
391 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
392 mcr p15, 0, r0, c6, c7, 1
393
394 mov r0, #0x80 @ PR7
395 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
396 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
397 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
398
399 mov r0, #0xc000
400 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
401 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
402
403 mov r0, #0
404 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
405 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
406 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
407 mrc p15, 0, r0, c1, c0, 0 @ read control reg
408 @ ...I .... ..D. WC.M
409 orr r0, r0, #0x002d @ .... .... ..1. 11.1
410 orr r0, r0, #0x1000 @ ...1 .... .... ....
411
412 mcr p15, 0, r0, c1, c0, 0 @ write control reg
413
414 mov r0, #0
415 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
416 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
417 mov pc, lr
418
419 __armv3_mpu_cache_on:
420 mov r0, #0x3f @ 4G, the whole
421 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
422
423 mov r0, #0x80 @ PR7
424 mcr p15, 0, r0, c2, c0, 0 @ cache on
425 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
426
427 mov r0, #0xc000
428 mcr p15, 0, r0, c5, c0, 0 @ access permission
429
430 mov r0, #0
431 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
432 /*
433 * ?? ARMv3 MMU does not allow reading the control register,
434 * does this really work on ARMv3 MPU?
435 */
436 mrc p15, 0, r0, c1, c0, 0 @ read control reg
437 @ .... .... .... WC.M
438 orr r0, r0, #0x000d @ .... .... .... 11.1
439 /* ?? this overwrites the value constructed above? */
440 mov r0, #0
441 mcr p15, 0, r0, c1, c0, 0 @ write control reg
442
443 /* ?? invalidate for the second time? */
444 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
445 mov pc, lr
446
447 __setup_mmu: sub r3, r4, #16384 @ Page directory size
448 bic r3, r3, #0xff @ Align the pointer
449 bic r3, r3, #0x3f00
450 /*
451 * Initialise the page tables, turning on the cacheable and bufferable
452 * bits for the RAM area only.
453 */
454 mov r0, r3
455 mov r9, r0, lsr #18
456 mov r9, r9, lsl #18 @ start of RAM
457 add r10, r9, #0x10000000 @ a reasonable RAM size
458 mov r1, #0x12
459 orr r1, r1, #3 << 10
460 add r2, r3, #16384
461 1: cmp r1, r9 @ if virt > start of RAM
462 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
463 orrhs r1, r1, #0x08 @ set cacheable
464 #else
465 orrhs r1, r1, #0x0c @ set cacheable, bufferable
466 #endif
467 cmp r1, r10 @ if virt > end of RAM
468 bichs r1, r1, #0x0c @ clear cacheable, bufferable
469 str r1, [r0], #4 @ 1:1 mapping
470 add r1, r1, #1048576
471 teq r0, r2
472 bne 1b
473 /*
474 * If ever we are running from Flash, then we surely want the cache
475 * to be enabled also for our execution instance... We map 2MB of it
476 * so there is no map overlap problem for up to 1 MB compressed kernel.
477 * If the execution is in RAM then we would only be duplicating the above.
478 */
479 mov r1, #0x1e
480 orr r1, r1, #3 << 10
481 mov r2, pc
482 mov r2, r2, lsr #20
483 orr r1, r1, r2, lsl #20
484 add r0, r3, r2, lsl #2
485 str r1, [r0], #4
486 add r1, r1, #1048576
487 str r1, [r0]
488 mov pc, lr
489 ENDPROC(__setup_mmu)
490
491 __arm926ejs_mmu_cache_on:
492 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
493 mov r0, #4 @ put dcache in WT mode
494 mcr p15, 7, r0, c15, c0, 0
495 #endif
496
497 __armv4_mmu_cache_on:
498 mov r12, lr
499 #ifdef CONFIG_MMU
500 bl __setup_mmu
501 mov r0, #0
502 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
503 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
504 mrc p15, 0, r0, c1, c0, 0 @ read control reg
505 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
506 orr r0, r0, #0x0030
507 #ifdef CONFIG_CPU_ENDIAN_BE8
508 orr r0, r0, #1 << 25 @ big-endian page tables
509 #endif
510 bl __common_mmu_cache_on
511 mov r0, #0
512 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
513 #endif
514 mov pc, r12
515
516 __armv7_mmu_cache_on:
517 mov r12, lr
518 #ifdef CONFIG_MMU
519 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
520 tst r11, #0xf @ VMSA
521 blne __setup_mmu
522 mov r0, #0
523 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
524 tst r11, #0xf @ VMSA
525 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
526 #endif
527 mrc p15, 0, r0, c1, c0, 0 @ read control reg
528 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
529 orr r0, r0, #0x003c @ write buffer
530 #ifdef CONFIG_MMU
531 #ifdef CONFIG_CPU_ENDIAN_BE8
532 orr r0, r0, #1 << 25 @ big-endian page tables
533 #endif
534 orrne r0, r0, #1 @ MMU enabled
535 movne r1, #-1
536 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
537 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
538 #endif
539 mcr p15, 0, r0, c1, c0, 0 @ load control register
540 mrc p15, 0, r0, c1, c0, 0 @ and read it back
541 mov r0, #0
542 mcr p15, 0, r0, c7, c5, 4 @ ISB
543 mov pc, r12
544
545 __fa526_cache_on:
546 mov r12, lr
547 bl __setup_mmu
548 mov r0, #0
549 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
550 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
551 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
552 mrc p15, 0, r0, c1, c0, 0 @ read control reg
553 orr r0, r0, #0x1000 @ I-cache enable
554 bl __common_mmu_cache_on
555 mov r0, #0
556 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
557 mov pc, r12
558
559 __arm6_mmu_cache_on:
560 mov r12, lr
561 bl __setup_mmu
562 mov r0, #0
563 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
564 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
565 mov r0, #0x30
566 bl __common_mmu_cache_on
567 mov r0, #0
568 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
569 mov pc, r12
570
571 __common_mmu_cache_on:
572 #ifndef CONFIG_THUMB2_KERNEL
573 #ifndef DEBUG
574 orr r0, r0, #0x000d @ Write buffer, mmu
575 #endif
576 mov r1, #-1
577 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
578 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
579 b 1f
580 .align 5 @ cache line aligned
581 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
582 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
583 sub pc, lr, r0, lsr #32 @ properly flush pipeline
584 #endif
585
586 /*
587 * Here follow the relocatable cache support functions for the
588 * various processors. This is a generic hook for locating an
589 * entry and jumping to an instruction at the specified offset
590 * from the start of the block. Please note this is all position
591 * independent code.
592 *
593 * r1 = corrupted
594 * r2 = corrupted
595 * r3 = block offset
596 * r9 = corrupted
597 * r12 = corrupted
598 */
599
600 call_cache_fn: adr r12, proc_types
601 #ifdef CONFIG_CPU_CP15
602 mrc p15, 0, r9, c0, c0 @ get processor ID
603 #else
604 ldr r9, =CONFIG_PROCESSOR_ID
605 #endif
606 1: ldr r1, [r12, #0] @ get value
607 ldr r2, [r12, #4] @ get mask
608 eor r1, r1, r9 @ (real ^ match)
609 tst r1, r2 @ & mask
610 ARM( addeq pc, r12, r3 ) @ call cache function
611 THUMB( addeq r12, r3 )
612 THUMB( moveq pc, r12 ) @ call cache function
613 add r12, r12, #4*5
614 b 1b
615
616 /*
617 * Table for cache operations. This is basically:
618 * - CPU ID match
619 * - CPU ID mask
620 * - 'cache on' method instruction
621 * - 'cache off' method instruction
622 * - 'cache flush' method instruction
623 *
624 * We match an entry using: ((real_id ^ match) & mask) == 0
625 *
626 * Writethrough caches generally only need 'on' and 'off'
627 * methods. Writeback caches _must_ have the flush method
628 * defined.
629 */
630 .align 2
631 .type proc_types,#object
632 proc_types:
633 .word 0x41560600 @ ARM6/610
634 .word 0xffffffe0
635 W(b) __arm6_mmu_cache_off @ works, but slow
636 W(b) __arm6_mmu_cache_off
637 mov pc, lr
638 THUMB( nop )
639 @ b __arm6_mmu_cache_on @ untested
640 @ b __arm6_mmu_cache_off
641 @ b __armv3_mmu_cache_flush
642
643 .word 0x00000000 @ old ARM ID
644 .word 0x0000f000
645 mov pc, lr
646 THUMB( nop )
647 mov pc, lr
648 THUMB( nop )
649 mov pc, lr
650 THUMB( nop )
651
652 .word 0x41007000 @ ARM7/710
653 .word 0xfff8fe00
654 W(b) __arm7_mmu_cache_off
655 W(b) __arm7_mmu_cache_off
656 mov pc, lr
657 THUMB( nop )
658
659 .word 0x41807200 @ ARM720T (writethrough)
660 .word 0xffffff00
661 W(b) __armv4_mmu_cache_on
662 W(b) __armv4_mmu_cache_off
663 mov pc, lr
664 THUMB( nop )
665
666 .word 0x41007400 @ ARM74x
667 .word 0xff00ff00
668 W(b) __armv3_mpu_cache_on
669 W(b) __armv3_mpu_cache_off
670 W(b) __armv3_mpu_cache_flush
671
672 .word 0x41009400 @ ARM94x
673 .word 0xff00ff00
674 W(b) __armv4_mpu_cache_on
675 W(b) __armv4_mpu_cache_off
676 W(b) __armv4_mpu_cache_flush
677
678 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
679 .word 0xff0ffff0
680 b __arm926ejs_mmu_cache_on
681 b __armv4_mmu_cache_off
682 b __armv5tej_mmu_cache_flush
683
684 .word 0x00007000 @ ARM7 IDs
685 .word 0x0000f000
686 mov pc, lr
687 THUMB( nop )
688 mov pc, lr
689 THUMB( nop )
690 mov pc, lr
691 THUMB( nop )
692
693 @ Everything from here on will be the new ID system.
694
695 .word 0x4401a100 @ sa110 / sa1100
696 .word 0xffffffe0
697 W(b) __armv4_mmu_cache_on
698 W(b) __armv4_mmu_cache_off
699 W(b) __armv4_mmu_cache_flush
700
701 .word 0x6901b110 @ sa1110
702 .word 0xfffffff0
703 W(b) __armv4_mmu_cache_on
704 W(b) __armv4_mmu_cache_off
705 W(b) __armv4_mmu_cache_flush
706
707 .word 0x56056900
708 .word 0xffffff00 @ PXA9xx
709 W(b) __armv4_mmu_cache_on
710 W(b) __armv4_mmu_cache_off
711 W(b) __armv4_mmu_cache_flush
712
713 .word 0x56158000 @ PXA168
714 .word 0xfffff000
715 W(b) __armv4_mmu_cache_on
716 W(b) __armv4_mmu_cache_off
717 W(b) __armv5tej_mmu_cache_flush
718
719 .word 0x56050000 @ Feroceon
720 .word 0xff0f0000
721 W(b) __armv4_mmu_cache_on
722 W(b) __armv4_mmu_cache_off
723 W(b) __armv5tej_mmu_cache_flush
724
725 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
726 /* this conflicts with the standard ARMv5TE entry */
727 .long 0x41009260 @ Old Feroceon
728 .long 0xff00fff0
729 b __armv4_mmu_cache_on
730 b __armv4_mmu_cache_off
731 b __armv5tej_mmu_cache_flush
732 #endif
733
734 .word 0x66015261 @ FA526
735 .word 0xff01fff1
736 W(b) __fa526_cache_on
737 W(b) __armv4_mmu_cache_off
738 W(b) __fa526_cache_flush
739
740 @ These match on the architecture ID
741
742 .word 0x00020000 @ ARMv4T
743 .word 0x000f0000
744 W(b) __armv4_mmu_cache_on
745 W(b) __armv4_mmu_cache_off
746 W(b) __armv4_mmu_cache_flush
747
748 .word 0x00050000 @ ARMv5TE
749 .word 0x000f0000
750 W(b) __armv4_mmu_cache_on
751 W(b) __armv4_mmu_cache_off
752 W(b) __armv4_mmu_cache_flush
753
754 .word 0x00060000 @ ARMv5TEJ
755 .word 0x000f0000
756 W(b) __armv4_mmu_cache_on
757 W(b) __armv4_mmu_cache_off
758 W(b) __armv5tej_mmu_cache_flush
759
760 .word 0x0007b000 @ ARMv6
761 .word 0x000ff000
762 W(b) __armv4_mmu_cache_on
763 W(b) __armv4_mmu_cache_off
764 W(b) __armv6_mmu_cache_flush
765
766 .word 0x560f5810 @ Marvell PJ4 ARMv6
767 .word 0xff0ffff0
768 W(b) __armv4_mmu_cache_on
769 W(b) __armv4_mmu_cache_off
770 W(b) __armv6_mmu_cache_flush
771
772 .word 0x000f0000 @ new CPU Id
773 .word 0x000f0000
774 W(b) __armv7_mmu_cache_on
775 W(b) __armv7_mmu_cache_off
776 W(b) __armv7_mmu_cache_flush
777
778 .word 0 @ unrecognised type
779 .word 0
780 mov pc, lr
781 THUMB( nop )
782 mov pc, lr
783 THUMB( nop )
784 mov pc, lr
785 THUMB( nop )
786
787 .size proc_types, . - proc_types
788
789 /*
790 * Turn off the Cache and MMU. ARMv3 does not support
791 * reading the control register, but ARMv4 does.
792 *
793 * On exit,
794 * r0, r1, r2, r3, r9, r12 corrupted
795 * This routine must preserve:
796 * r4, r7, r8
797 */
798 .align 5
799 cache_off: mov r3, #12 @ cache_off function
800 b call_cache_fn
801
802 __armv4_mpu_cache_off:
803 mrc p15, 0, r0, c1, c0
804 bic r0, r0, #0x000d
805 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
806 mov r0, #0
807 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
808 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
809 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
810 mov pc, lr
811
812 __armv3_mpu_cache_off:
813 mrc p15, 0, r0, c1, c0
814 bic r0, r0, #0x000d
815 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
816 mov r0, #0
817 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
818 mov pc, lr
819
820 __armv4_mmu_cache_off:
821 #ifdef CONFIG_MMU
822 mrc p15, 0, r0, c1, c0
823 bic r0, r0, #0x000d
824 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
825 mov r0, #0
826 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
827 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
828 #endif
829 mov pc, lr
830
831 __armv7_mmu_cache_off:
832 mrc p15, 0, r0, c1, c0
833 #ifdef CONFIG_MMU
834 bic r0, r0, #0x000d
835 #else
836 bic r0, r0, #0x000c
837 #endif
838 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
839 mov r12, lr
840 bl __armv7_mmu_cache_flush
841 mov r0, #0
842 #ifdef CONFIG_MMU
843 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
844 #endif
845 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
846 mcr p15, 0, r0, c7, c10, 4 @ DSB
847 mcr p15, 0, r0, c7, c5, 4 @ ISB
848 mov pc, r12
849
850 __arm6_mmu_cache_off:
851 mov r0, #0x00000030 @ ARM6 control reg.
852 b __armv3_mmu_cache_off
853
854 __arm7_mmu_cache_off:
855 mov r0, #0x00000070 @ ARM7 control reg.
856 b __armv3_mmu_cache_off
857
858 __armv3_mmu_cache_off:
859 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
860 mov r0, #0
861 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
862 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
863 mov pc, lr
864
865 /*
866 * Clean and flush the cache to maintain consistency.
867 *
868 * On exit,
869 * r1, r2, r3, r9, r10, r11, r12 corrupted
870 * This routine must preserve:
871 * r4, r6, r7, r8
872 */
873 .align 5
874 cache_clean_flush:
875 mov r3, #16
876 b call_cache_fn
877
878 __armv4_mpu_cache_flush:
879 mov r2, #1
880 mov r3, #0
881 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
882 mov r1, #7 << 5 @ 8 segments
883 1: orr r3, r1, #63 << 26 @ 64 entries
884 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
885 subs r3, r3, #1 << 26
886 bcs 2b @ entries 63 to 0
887 subs r1, r1, #1 << 5
888 bcs 1b @ segments 7 to 0
889
890 teq r2, #0
891 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
892 mcr p15, 0, ip, c7, c10, 4 @ drain WB
893 mov pc, lr
894
895 __fa526_cache_flush:
896 mov r1, #0
897 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
898 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
899 mcr p15, 0, r1, c7, c10, 4 @ drain WB
900 mov pc, lr
901
902 __armv6_mmu_cache_flush:
903 mov r1, #0
904 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
905 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
906 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
907 mcr p15, 0, r1, c7, c10, 4 @ drain WB
908 mov pc, lr
909
910 __armv7_mmu_cache_flush:
911 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
912 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
913 mov r10, #0
914 beq hierarchical
915 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
916 b iflush
917 hierarchical:
918 mcr p15, 0, r10, c7, c10, 5 @ DMB
919 stmfd sp!, {r0-r7, r9-r11}
920 mrc p15, 1, r0, c0, c0, 1 @ read clidr
921 ands r3, r0, #0x7000000 @ extract loc from clidr
922 mov r3, r3, lsr #23 @ left align loc bit field
923 beq finished @ if loc is 0, then no need to clean
924 mov r10, #0 @ start clean at cache level 0
925 loop1:
926 add r2, r10, r10, lsr #1 @ work out 3x current cache level
927 mov r1, r0, lsr r2 @ extract cache type bits from clidr
928 and r1, r1, #7 @ mask of the bits for current cache only
929 cmp r1, #2 @ see what cache we have at this level
930 blt skip @ skip if no cache, or just i-cache
931 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
932 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
933 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
934 and r2, r1, #7 @ extract the length of the cache lines
935 add r2, r2, #4 @ add 4 (line length offset)
936 ldr r4, =0x3ff
937 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
938 clz r5, r4 @ find bit position of way size increment
939 ldr r7, =0x7fff
940 ands r7, r7, r1, lsr #13 @ extract max number of the index size
941 loop2:
942 mov r9, r4 @ create working copy of max way size
943 loop3:
944 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
945 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
946 THUMB( lsl r6, r9, r5 )
947 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
948 THUMB( lsl r6, r7, r2 )
949 THUMB( orr r11, r11, r6 ) @ factor index number into r11
950 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
951 subs r9, r9, #1 @ decrement the way
952 bge loop3
953 subs r7, r7, #1 @ decrement the index
954 bge loop2
955 skip:
956 add r10, r10, #2 @ increment cache number
957 cmp r3, r10
958 bgt loop1
959 finished:
960 ldmfd sp!, {r0-r7, r9-r11}
961 mov r10, #0 @ swith back to cache level 0
962 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
963 iflush:
964 mcr p15, 0, r10, c7, c10, 4 @ DSB
965 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
966 mcr p15, 0, r10, c7, c10, 4 @ DSB
967 mcr p15, 0, r10, c7, c5, 4 @ ISB
968 mov pc, lr
969
970 __armv5tej_mmu_cache_flush:
971 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
972 bne 1b
973 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
974 mcr p15, 0, r0, c7, c10, 4 @ drain WB
975 mov pc, lr
976
977 __armv4_mmu_cache_flush:
978 mov r2, #64*1024 @ default: 32K dcache size (*2)
979 mov r11, #32 @ default: 32 byte line size
980 mrc p15, 0, r3, c0, c0, 1 @ read cache type
981 teq r3, r9 @ cache ID register present?
982 beq no_cache_id
983 mov r1, r3, lsr #18
984 and r1, r1, #7
985 mov r2, #1024
986 mov r2, r2, lsl r1 @ base dcache size *2
987 tst r3, #1 << 14 @ test M bit
988 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
989 mov r3, r3, lsr #12
990 and r3, r3, #3
991 mov r11, #8
992 mov r11, r11, lsl r3 @ cache line size in bytes
993 no_cache_id:
994 mov r1, pc
995 bic r1, r1, #63 @ align to longest cache line
996 add r2, r1, r2
997 1:
998 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
999 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1000 THUMB( add r1, r1, r11 )
1001 teq r1, r2
1002 bne 1b
1003
1004 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1005 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1006 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1007 mov pc, lr
1008
1009 __armv3_mmu_cache_flush:
1010 __armv3_mpu_cache_flush:
1011 mov r1, #0
1012 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1013 mov pc, lr
1014
1015 /*
1016 * Various debugging routines for printing hex characters and
1017 * memory, which again must be relocatable.
1018 */
1019 #ifdef DEBUG
1020 .align 2
1021 .type phexbuf,#object
1022 phexbuf: .space 12
1023 .size phexbuf, . - phexbuf
1024
1025 @ phex corrupts {r0, r1, r2, r3}
1026 phex: adr r3, phexbuf
1027 mov r2, #0
1028 strb r2, [r3, r1]
1029 1: subs r1, r1, #1
1030 movmi r0, r3
1031 bmi puts
1032 and r2, r0, #15
1033 mov r0, r0, lsr #4
1034 cmp r2, #10
1035 addge r2, r2, #7
1036 add r2, r2, #'0'
1037 strb r2, [r3, r1]
1038 b 1b
1039
1040 @ puts corrupts {r0, r1, r2, r3}
1041 puts: loadsp r3, r1
1042 1: ldrb r2, [r0], #1
1043 teq r2, #0
1044 moveq pc, lr
1045 2: writeb r2, r3
1046 mov r1, #0x00020000
1047 3: subs r1, r1, #1
1048 bne 3b
1049 teq r2, #'\n'
1050 moveq r2, #'\r'
1051 beq 2b
1052 teq r0, #0
1053 bne 1b
1054 mov pc, lr
1055 @ putc corrupts {r0, r1, r2, r3}
1056 putc:
1057 mov r2, r0
1058 mov r0, #0
1059 loadsp r3, r1
1060 b 2b
1061
1062 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1063 memdump: mov r12, r0
1064 mov r10, lr
1065 mov r11, #0
1066 2: mov r0, r11, lsl #2
1067 add r0, r0, r12
1068 mov r1, #8
1069 bl phex
1070 mov r0, #':'
1071 bl putc
1072 1: mov r0, #' '
1073 bl putc
1074 ldr r0, [r12, r11, lsl #2]
1075 mov r1, #8
1076 bl phex
1077 and r0, r11, #7
1078 teq r0, #3
1079 moveq r0, #' '
1080 bleq putc
1081 and r0, r11, #7
1082 add r11, r11, #1
1083 teq r0, #7
1084 bne 1b
1085 mov r0, #'\n'
1086 bl putc
1087 cmp r11, #64
1088 blt 2b
1089 mov pc, r10
1090 #endif
1091
1092 .ltorg
1093 reloc_code_end:
1094
1095 .align
1096 .section ".stack", "aw", %nobits
1097 user_stack: .space 4096
1098 user_stack_end:
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