arch/arm/boot/dts/am335x-baltos-ir3220.dts

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * VScom OnRISC
  11  * http://www.vscom.de
  12  */
  13
  14 /dts-v1/;
  15
  16 #include "am335x-baltos.dtsi"
  17 #include "am335x-baltos-leds.dtsi"
  18
  19 / {
  20         model = "OnRISC Baltos iR 3220";
  21 };
  22
  23 &am33xx_pinmux {
  24         tca6416_pins: pinmux_tca6416_pins {
  25                 pinctrl-single,pins = <
  26                         AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
  27                 >;
  28         };
  29
  30         uart1_pins: pinmux_uart1_pins {
  31                 pinctrl-single,pins = <
  32                         AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
  33                         AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
  34                         AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
  35                         AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  36                         AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
  37                         AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
  38                         AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
  39                         AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
  40                 >;
  41         };
  42
  43         uart2_pins: pinmux_uart2_pins {
  44                 pinctrl-single,pins = <
  45                         AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
  46                         AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
  47                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
  48                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
  49                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
  50                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
  51                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
  52                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
  53
  54                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
  55                 >;
  56         };
  57 };
  58
  59 &uart1 {
  60         pinctrl-names = "default";
  61         pinctrl-0 = <&uart1_pins>;
  62         dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
  63         dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
  64         dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
  65         rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
  66
  67         status = "okay";
  68 };
  69
  70 &uart2 {
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&uart2_pins>;
  73         dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  74         dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  75         dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  76         rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  77
  78         status = "okay";
  79 };
  80
  81 &i2c1 {
  82         tca6416: gpio@20 {
  83                 compatible = "ti,tca6416";
  84                 reg = <0x20>;
  85                 gpio-controller;
  86                 #gpio-cells = <2>;
  87                 interrupt-parent = <&gpio0>;
  88                 interrupts = <20 IRQ_TYPE_EDGE_RISING>;
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&tca6416_pins>;
  91         };
  92 };
  93
  94 &usb0_phy {
  95         status = "okay";
  96 };
  97
  98 &usb0 {
  99         status = "okay";
 100         dr_mode = "host";
 101 };
 102
 103 &cpsw_emac0 {
 104         phy-mode = "rmii";
 105         dual_emac_res_vlan = <1>;
 106         fixed-link {
 107                 speed = <100>;
 108                 full-duplex;
 109         };
 110 };
 111
 112 &cpsw_emac1 {
 113         phy-mode = "rgmii-txid";
 114         dual_emac_res_vlan = <2>;
 115         phy-handle = <&phy1>;
 116 };