arch/arm/boot/dts/am3874-iceboard.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device tree for Winterland IceBoard
   4  *
   5  * http://mcgillcosmology.com
   6  * http://threespeedlogic.com
   7  *
   8  * This is an ARM + FPGA instrumentation board used at telescopes in
   9  * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO
  10  * observatory in British Columbia (CHIME).
  11  *
  12  * Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com>
  13  */
  14
  15 /dts-v1/;
  16
  17 #include "dm814x.dtsi"
  18 #include <dt-bindings/interrupt-controller/irq.h>
  19
  20 / {
  21         model = "Winterland IceBoard";
  22         compatible = "ti,dm8148", "ti,dm814";
  23
  24         chosen {
  25                 stdout-path = "serial1:115200n8";
  26                 bootargs = "earlycon";
  27         };
  28
  29         memory@80000000 {
  30                 device_type = "memory";
  31                 reg = <0x80000000 0x40000000>;  /* 1 GB */
  32         };
  33
  34         vmmcsd_fixed: fixedregulator0 {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "vmmcsd_fixed";
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39                 regulator-always-on;
  40         };
  41 };
  42
  43 /* The MAC provides internal delay for the transmit path ONLY, which is enabled
  44  * provided no -id/-txid/-rxid suffix is provided to "phy-mode".
  45  *
  46  * The receive path is delayed at the PHY. The recommended register settings
  47  * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
  48  * conversion code in the kernel lies: the PHY's registers are 120 ps per tap,
  49  * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to
  50  * obtain the correct register settings.
  51  */
  52 &mac { dual_emac = <1>; };
  53 &cpsw_emac0 {
  54         phy-handle = <&ethphy0>;
  55         phy-mode = "rgmii";
  56         dual_emac_res_vlan = <1>;
  57 };
  58 &cpsw_emac1 {
  59         phy-handle = <&ethphy1>;
  60         phy-mode = "rgmii";
  61         dual_emac_res_vlan = <2>;
  62 };
  63
  64 &davinci_mdio {
  65         ethphy0: ethernet-phy@0 {
  66                 reg = <0x2>;
  67
  68                 rxc-skew-ps = <3000>;
  69                 rxdv-skew-ps = <0>;
  70
  71                 rxd3-skew-ps = <0>;
  72                 rxd2-skew-ps = <0>;
  73                 rxd1-skew-ps = <0>;
  74                 rxd0-skew-ps = <0>;
  75
  76                 phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
  77         };
  78
  79         ethphy1: ethernet-phy@1 {
  80                 reg = <0x1>;
  81
  82                 rxc-skew-ps = <3000>;
  83                 rxdv-skew-ps = <0>;
  84
  85                 rxd3-skew-ps = <0>;
  86                 rxd2-skew-ps = <0>;
  87                 rxd1-skew-ps = <0>;
  88                 rxd0-skew-ps = <0>;
  89
  90                 phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  91         };
  92 };
  93
  94 &mmc1 { status = "disabled"; };
  95 &mmc2 {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&mmc2_pins>;
  98         vmmc-supply = <&vmmcsd_fixed>;
  99         bus-width = <4>;
 100 };
 101 &mmc3 { status = "disabled"; };
 102
 103 &i2c1 {
 104         /* Most I2C activity happens through this port, with the sole exception
 105          * of the backplane. Since there are multiply assigned addresses, the
 106          * "i2c-mux-idle-disconnect" is important.
 107          */
 108
 109         pca9548@70 {
 110                 compatible = "nxp,pca9548";
 111                 reg = <0x70>;
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114
 115                 i2c@0 {
 116                         /* FMC A */
 117                         #address-cells = <1>;
 118                         #size-cells = <0>;
 119                         reg = <0>;
 120                         i2c-mux-idle-disconnect;
 121                 };
 122
 123                 i2c@1 {
 124                         /* FMC B */
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127                         reg = <1>;
 128                         i2c-mux-idle-disconnect;
 129                 };
 130
 131                 i2c@2 {
 132                         /* QSFP A */
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         reg = <2>;
 136                         i2c-mux-idle-disconnect;
 137                 };
 138
 139                 i2c@3 {
 140                         /* QSFP B */
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         reg = <3>;
 144                         i2c-mux-idle-disconnect;
 145                 };
 146
 147                 i2c@4 {
 148                         /* SFP */
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         reg = <4>;
 152                         i2c-mux-idle-disconnect;
 153                 };
 154
 155                 i2c@5 {
 156                         #address-cells = <1>;
 157                         #size-cells = <0>;
 158                         reg = <5>;
 159                         i2c-mux-idle-disconnect;
 160
 161                         ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
 162                         ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
 163                         ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; };
 164
 165                         ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; };
 166                         ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; };
 167                         ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; };
 168
 169                         ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; };
 170                         ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; };
 171                         ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; };
 172                         ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; };
 173                         ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; };
 174                         ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; };
 175                         ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; };
 176                         ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; };
 177                         ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; };
 178                 };
 179
 180                 i2c@6 {
 181                         /* Backplane */
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         reg = <6>;
 185                         i2c-mux-idle-disconnect;
 186                 };
 187
 188                 i2c@7 {
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         reg = <7>;
 192                         i2c-mux-idle-disconnect;
 193
 194                         u41: pca9575@20 {
 195                                 compatible = "nxp,pca9575";
 196                                 reg = <0x20>;
 197                                 gpio-controller;
 198                                 #gpio-cells = <2>;
 199
 200                                 gpio-line-names =
 201                                         "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C",
 202                                         "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS",
 203                                         "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C",
 204                                         "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL";
 205                                 reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
 206                         };
 207
 208                         u42: pca9575@21 {
 209                                 compatible = "nxp,pca9575";
 210                                 reg = <0x21>;
 211                                 gpio-controller;
 212                                 #gpio-cells = <2>;
 213                                 gpio-line-names =
 214                                         "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL",
 215                                         "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL",
 216                                         "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1",
 217                                         "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR";
 218                                 reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
 219                         };
 220
 221                         u48: pca9575@22 {
 222                                 compatible = "nxp,pca9575";
 223                                 reg=<0x22>;
 224                                 gpio-controller;
 225                                 #gpio-cells = <2>;
 226
 227                                 sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>,
 228                                         <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>;
 229                                 led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>,
 230                                         <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>;
 231
 232                                 gpio-line-names =
 233                                         "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4",
 234                                         "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8",
 235                                         "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5",
 236                                         "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1";
 237                                 reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
 238                         };
 239
 240                         u59: pca9575@23 {
 241                                 compatible = "nxp,pca9575";
 242                                 reg=<0x23>;
 243                                 gpio-controller;
 244                                 #gpio-cells = <2>;
 245                                 gpio-line-names =
 246                                         "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12",
 247                                         "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault",
 248                                         "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3",
 249                                         "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17";
 250                                 reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
 251                         };
 252
 253                         tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; };
 254                         tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; };
 255                         tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; };
 256                         tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; };
 257
 258                         /* EEPROM bank and serial number are treated as separate devices */
 259                         at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; };
 260                         at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; };
 261                 };
 262         };
 263 };
 264
 265 &i2c2 {
 266         pca9548@71 {
 267                 compatible = "nxp,pca9548";
 268                 reg = <0x71>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271
 272                 i2c@6 {
 273                         /* Backplane */
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         reg = <6>;
 277                         multi-master;
 278
 279                         /* All backplanes should have this -- it's how we know they're there. */
 280                         at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; };
 281                         at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; };
 282
 283                         /* 16 slot backplane */
 284                         tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; };
 285                         tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; };
 286                         ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; };
 287                         amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; };
 288
 289                         /* Single slot backplane */
 290                 };
 291         };
 292 };
 293
 294 &pincntl {
 295         mmc2_pins: pinmux_mmc2_pins {
 296                 pinctrl-single,pins = <
 297                         DM814X_IOPAD(0x0800, PIN_INPUT | 0x1)   /* SD1_CLK */
 298                         DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1)    /* SD1_CMD */
 299                         DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1)    /* SD1_DAT[0] */
 300                         DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1)    /* SD1_DAT[1] */
 301                         DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1)    /* SD1_DAT[2] */
 302                         DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1)    /* SD1_DAT[3] */
 303                         DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40)   /* SD1_POW */
 304                         DM814X_IOPAD(0x0928, PIN_INPUT | 0x40)  /* SD1_SDWP */
 305                         DM814X_IOPAD(0x093C, PIN_INPUT | 0x2)   /* SD1_SDCD */
 306                         >;
 307         };
 308
 309         usb0_pins: pinmux_usb0_pins {
 310                 pinctrl-single,pins = <
 311                         DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1)  /* USB0_DRVVBUS */
 312                         >;
 313         };
 314
 315         usb1_pins: pinmux_usb1_pins {
 316                 pinctrl-single,pins = <
 317                         DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */
 318                         >;
 319         };
 320
 321         gpio1_pins: pinmux_gpio1_pins {
 322                 pinctrl-single,pins = <
 323                         DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */
 324                         DM814X_IOPAD(0x0820, PIN_INPUT | 0x80)  /* INIT_B */
 325                         DM814X_IOPAD(0x0824, PIN_INPUT | 0x80)  /* DONE */
 326
 327                         DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */
 328                         DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */
 329                         DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */
 330                         DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */
 331                         DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */
 332
 333                         DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */
 334                         DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */
 335                         DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */
 336                         DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */
 337                         DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */
 338
 339                         DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */
 340                         DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */
 341                         DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */
 342                         DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */
 343                         >;
 344         };
 345
 346         gpio2_pins: pinmux_gpio2_pins {
 347                 pinctrl-single,pins = <
 348                         DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */
 349                         DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */
 350                         DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */
 351                         DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */
 352
 353                         //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */
 354                         //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */
 355                         DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */
 356                 >;
 357         };
 358
 359         gpio4_pins: pinmux_gpio4_pins {
 360                 pinctrl-single,pins = <
 361                         /* The PLL doesn't react well to the SPI controller reset, so
 362                          * we force the CS lines to pull up as GPIOs until we're ready.
 363                          * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3
 364                          */
 365                         DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */
 366                         DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */
 367                         DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */
 368                         DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */
 369                         DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */
 370                         DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */
 371                 >;
 372         };
 373
 374         spi2_pins: pinmux_spi2_pins {
 375                 pinctrl-single,pins = <
 376                         DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */
 377                         DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */
 378                 >;
 379         };
 380
 381         spi4_pins: pinmux_spi4_pins {
 382                 pinctrl-single,pins = <
 383                         DM814X_IOPAD(0x0a7c, 0x20)
 384                         DM814X_IOPAD(0x0b74, 0x20)
 385                         DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20)
 386                         DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20)
 387                         DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20)
 388                 >;
 389         };
 390 };
 391
 392 &gpio1 {
 393         pinctrl-names = "default";
 394         pinctrl-0 = <&gpio1_pins>;
 395         gpio-line-names =
 396                 "", "PROGRAM_B", "INIT_B", "DONE",                      /* 0-3 */
 397                 "", "", "", "",                                         /* 4-7 */
 398                 "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI",         /* 8-11 */
 399                 "", "", "", "FMCA_TRST",                                /* 12-15 */
 400                 "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI",         /* 16-19 */
 401                 "FMCB_TRST", "", "", "",                                /* 20-23 */
 402                 "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI",         /* 24-27 */
 403                 "", "", "", "";                                         /* 28-31 */
 404 };
 405
 406 &gpio2 {
 407         pinctrl-names = "default";
 408         pinctrl-0 = <&gpio2_pins>;
 409         gpio-line-names =
 410                 "PHYA_IRQ_N", "PHYA_RESET_N", "", "",                   /* 0-3 */
 411                 "", "", "", "PHYB_IRQ_N",                               /* 4-7 */
 412                 "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", "";              /* 8-11 */
 413 };
 414
 415 &gpio3 {
 416         pinctrl-names = "default";
 417         /*pinctrl-0 = <&gpio3_pins>;*/
 418         gpio-line-names =
 419                 "", "", "ARMClkSel0", "",                               /* 0-3 */
 420                 "EnFPGARef", "", "", "ARMClkSel1";                      /* 4-7 */
 421 };
 422
 423 &gpio4 {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&gpio4_pins>;
 426         gpio-line-names =
 427                 "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3",
 428                 "BP_ARM_GPIO4", "BP_ARM_GPIO5";
 429 };
 430
 431 &usb0 {
 432         pinctrl-names = "default";
 433         pinctrl-0 = <&usb0_pins>;
 434         dr_mode = "host";
 435 };
 436
 437 &usb1 {
 438         pinctrl-names = "default";
 439         pinctrl-0 = <&usb1_pins>;
 440         dr_mode = "host";
 441 };
 442
 443 &mcspi1 {
 444         s25fl256@0 {
 445                 #address-cells = <1>;
 446                 #size-cells = <1>;
 447                 compatible = "jedec,spi-nor";
 448                 reg = <0>;
 449                 spi-max-frequency = <40000000>;
 450
 451                 fsbl@0 {
 452                         /* 256 kB */
 453                         label = "U-Boot-min";
 454                         reg = <0 0x40000>;
 455                 };
 456                 ssbl@1 {
 457                         /* 512 kB */
 458                         label = "U-Boot";
 459                         reg = <0x40000 0x80000>;
 460                 };
 461                 bootenv@2 {
 462                         /* 256 kB */
 463                         label = "U-Boot Env";
 464                         reg = <0xc0000 0x40000>;
 465                 };
 466                 kernel@3 {
 467                         /* 4 MB */
 468                         label = "Kernel";
 469                         reg = <0x100000 0x400000>;
 470                 };
 471                 ipmi@4 {
 472                         label = "IPMI FRU";
 473                         reg = <0x500000 0x40000>;
 474                 };
 475                 fs@5 {
 476                         label = "File System";
 477                         reg = <0x540000 0x1ac0000>;
 478                 };
 479         };
 480 };
 481
 482 &mcspi3 {
 483         /* DMA event numbers stolen from MCASP */
 484         dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17
 485                 &edma_xbar 10 0 18 &edma_xbar 11 0 19>;
 486         dma-names = "tx0", "rx0", "tx1", "rx1";
 487 };
 488
 489 &mcspi4 {
 490         pinctrl-names = "default";
 491         pinctrl-0 = <&spi4_pins>;
 492
 493         /* DMA event numbers stolen from MCASP, MCBSP */
 494         dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>;
 495         dma-names = "tx0", "rx0";
 496 };