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Merge tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / am4372.dtsi
1 /*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13
14 #include "skeleton.dtsi"
15
16 / {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
19
20
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 serial0 = &uart0;
26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 cpu: cpu@0 {
34 compatible = "arm,cortex-a9";
35 device_type = "cpu";
36 reg = <0>;
37
38 clocks = <&dpll_mpu_ck>;
39 clock-names = "cpu";
40
41 clock-latency = <300000>; /* From omap-cpufreq driver */
42 };
43 };
44
45 gic: interrupt-controller@48241000 {
46 compatible = "arm,cortex-a9-gic";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0x48241000 0x1000>,
50 <0x48240100 0x0100>;
51 interrupt-parent = <&gic>;
52 };
53
54 wakeupgen: interrupt-controller@48281000 {
55 compatible = "ti,omap4-wugen-mpu";
56 interrupt-controller;
57 #interrupt-cells = <3>;
58 reg = <0x48281000 0x1000>;
59 interrupt-parent = <&gic>;
60 };
61
62 l2-cache-controller@48242000 {
63 compatible = "arm,pl310-cache";
64 reg = <0x48242000 0x1000>;
65 cache-unified;
66 cache-level = <2>;
67 };
68
69 am43xx_control_module: control_module@4a002000 {
70 compatible = "syscon";
71 reg = <0x44e10000 0x7f4>;
72 };
73
74 am43xx_pinmux: pinmux@44e10800 {
75 compatible = "ti,am437-padconf", "pinctrl-single";
76 reg = <0x44e10800 0x31c>;
77 #address-cells = <1>;
78 #size-cells = <0>;
79 #interrupt-cells = <1>;
80 interrupt-controller;
81 pinctrl-single,register-width = <32>;
82 pinctrl-single,function-mask = <0xffffffff>;
83 };
84
85 ocp {
86 compatible = "ti,am4372-l3-noc", "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
90 ti,hwmods = "l3_main";
91 reg = <0x44000000 0x400000
92 0x44800000 0x400000>;
93 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
95
96 prcm: prcm@44df0000 {
97 compatible = "ti,am4-prcm";
98 reg = <0x44df0000 0x11000>;
99
100 prcm_clocks: clocks {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 };
104
105 prcm_clockdomains: clockdomains {
106 };
107 };
108
109 scrm: scrm@44e10000 {
110 compatible = "ti,am4-scrm";
111 reg = <0x44e10000 0x2000>;
112
113 scrm_clocks: clocks {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 };
117
118 scrm_clockdomains: clockdomains {
119 };
120 };
121
122 edma: edma@49000000 {
123 compatible = "ti,edma3";
124 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
125 reg = <0x49000000 0x10000>,
126 <0x44e10f90 0x10>;
127 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
130 #dma-cells = <1>;
131 };
132
133 uart0: serial@44e09000 {
134 compatible = "ti,am4372-uart","ti,omap2-uart";
135 reg = <0x44e09000 0x2000>;
136 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
137 ti,hwmods = "uart1";
138 };
139
140 uart1: serial@48022000 {
141 compatible = "ti,am4372-uart","ti,omap2-uart";
142 reg = <0x48022000 0x2000>;
143 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
144 ti,hwmods = "uart2";
145 status = "disabled";
146 };
147
148 uart2: serial@48024000 {
149 compatible = "ti,am4372-uart","ti,omap2-uart";
150 reg = <0x48024000 0x2000>;
151 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
152 ti,hwmods = "uart3";
153 status = "disabled";
154 };
155
156 uart3: serial@481a6000 {
157 compatible = "ti,am4372-uart","ti,omap2-uart";
158 reg = <0x481a6000 0x2000>;
159 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
160 ti,hwmods = "uart4";
161 status = "disabled";
162 };
163
164 uart4: serial@481a8000 {
165 compatible = "ti,am4372-uart","ti,omap2-uart";
166 reg = <0x481a8000 0x2000>;
167 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
168 ti,hwmods = "uart5";
169 status = "disabled";
170 };
171
172 uart5: serial@481aa000 {
173 compatible = "ti,am4372-uart","ti,omap2-uart";
174 reg = <0x481aa000 0x2000>;
175 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
176 ti,hwmods = "uart6";
177 status = "disabled";
178 };
179
180 mailbox: mailbox@480C8000 {
181 compatible = "ti,omap4-mailbox";
182 reg = <0x480C8000 0x200>;
183 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
184 ti,hwmods = "mailbox";
185 #mbox-cells = <1>;
186 ti,mbox-num-users = <4>;
187 ti,mbox-num-fifos = <8>;
188 mbox_wkupm3: wkup_m3 {
189 ti,mbox-tx = <0 0 0>;
190 ti,mbox-rx = <0 0 3>;
191 };
192 };
193
194 timer1: timer@44e31000 {
195 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
196 reg = <0x44e31000 0x400>;
197 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
198 ti,timer-alwon;
199 ti,hwmods = "timer1";
200 };
201
202 timer2: timer@48040000 {
203 compatible = "ti,am4372-timer","ti,am335x-timer";
204 reg = <0x48040000 0x400>;
205 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
206 ti,hwmods = "timer2";
207 };
208
209 timer3: timer@48042000 {
210 compatible = "ti,am4372-timer","ti,am335x-timer";
211 reg = <0x48042000 0x400>;
212 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
213 ti,hwmods = "timer3";
214 status = "disabled";
215 };
216
217 timer4: timer@48044000 {
218 compatible = "ti,am4372-timer","ti,am335x-timer";
219 reg = <0x48044000 0x400>;
220 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
221 ti,timer-pwm;
222 ti,hwmods = "timer4";
223 status = "disabled";
224 };
225
226 timer5: timer@48046000 {
227 compatible = "ti,am4372-timer","ti,am335x-timer";
228 reg = <0x48046000 0x400>;
229 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
230 ti,timer-pwm;
231 ti,hwmods = "timer5";
232 status = "disabled";
233 };
234
235 timer6: timer@48048000 {
236 compatible = "ti,am4372-timer","ti,am335x-timer";
237 reg = <0x48048000 0x400>;
238 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
239 ti,timer-pwm;
240 ti,hwmods = "timer6";
241 status = "disabled";
242 };
243
244 timer7: timer@4804a000 {
245 compatible = "ti,am4372-timer","ti,am335x-timer";
246 reg = <0x4804a000 0x400>;
247 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
248 ti,timer-pwm;
249 ti,hwmods = "timer7";
250 status = "disabled";
251 };
252
253 timer8: timer@481c1000 {
254 compatible = "ti,am4372-timer","ti,am335x-timer";
255 reg = <0x481c1000 0x400>;
256 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
257 ti,hwmods = "timer8";
258 status = "disabled";
259 };
260
261 timer9: timer@4833d000 {
262 compatible = "ti,am4372-timer","ti,am335x-timer";
263 reg = <0x4833d000 0x400>;
264 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
265 ti,hwmods = "timer9";
266 status = "disabled";
267 };
268
269 timer10: timer@4833f000 {
270 compatible = "ti,am4372-timer","ti,am335x-timer";
271 reg = <0x4833f000 0x400>;
272 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
273 ti,hwmods = "timer10";
274 status = "disabled";
275 };
276
277 timer11: timer@48341000 {
278 compatible = "ti,am4372-timer","ti,am335x-timer";
279 reg = <0x48341000 0x400>;
280 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
281 ti,hwmods = "timer11";
282 status = "disabled";
283 };
284
285 counter32k: counter@44e86000 {
286 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
287 reg = <0x44e86000 0x40>;
288 ti,hwmods = "counter_32k";
289 };
290
291 rtc: rtc@44e3e000 {
292 compatible = "ti,am4372-rtc","ti,da830-rtc";
293 reg = <0x44e3e000 0x1000>;
294 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
296 ti,hwmods = "rtc";
297 status = "disabled";
298 };
299
300 wdt: wdt@44e35000 {
301 compatible = "ti,am4372-wdt","ti,omap3-wdt";
302 reg = <0x44e35000 0x1000>;
303 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
304 ti,hwmods = "wd_timer2";
305 };
306
307 gpio0: gpio@44e07000 {
308 compatible = "ti,am4372-gpio","ti,omap4-gpio";
309 reg = <0x44e07000 0x1000>;
310 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
311 gpio-controller;
312 #gpio-cells = <2>;
313 interrupt-controller;
314 #interrupt-cells = <2>;
315 ti,hwmods = "gpio1";
316 status = "disabled";
317 };
318
319 gpio1: gpio@4804c000 {
320 compatible = "ti,am4372-gpio","ti,omap4-gpio";
321 reg = <0x4804c000 0x1000>;
322 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 ti,hwmods = "gpio2";
328 status = "disabled";
329 };
330
331 gpio2: gpio@481ac000 {
332 compatible = "ti,am4372-gpio","ti,omap4-gpio";
333 reg = <0x481ac000 0x1000>;
334 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
335 gpio-controller;
336 #gpio-cells = <2>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339 ti,hwmods = "gpio3";
340 status = "disabled";
341 };
342
343 gpio3: gpio@481ae000 {
344 compatible = "ti,am4372-gpio","ti,omap4-gpio";
345 reg = <0x481ae000 0x1000>;
346 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 ti,hwmods = "gpio4";
352 status = "disabled";
353 };
354
355 gpio4: gpio@48320000 {
356 compatible = "ti,am4372-gpio","ti,omap4-gpio";
357 reg = <0x48320000 0x1000>;
358 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
359 gpio-controller;
360 #gpio-cells = <2>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 ti,hwmods = "gpio5";
364 status = "disabled";
365 };
366
367 gpio5: gpio@48322000 {
368 compatible = "ti,am4372-gpio","ti,omap4-gpio";
369 reg = <0x48322000 0x1000>;
370 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 ti,hwmods = "gpio6";
376 status = "disabled";
377 };
378
379 hwspinlock: spinlock@480ca000 {
380 compatible = "ti,omap4-hwspinlock";
381 reg = <0x480ca000 0x1000>;
382 ti,hwmods = "spinlock";
383 #hwlock-cells = <1>;
384 };
385
386 i2c0: i2c@44e0b000 {
387 compatible = "ti,am4372-i2c","ti,omap4-i2c";
388 reg = <0x44e0b000 0x1000>;
389 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
390 ti,hwmods = "i2c1";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 status = "disabled";
394 };
395
396 i2c1: i2c@4802a000 {
397 compatible = "ti,am4372-i2c","ti,omap4-i2c";
398 reg = <0x4802a000 0x1000>;
399 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
400 ti,hwmods = "i2c2";
401 #address-cells = <1>;
402 #size-cells = <0>;
403 status = "disabled";
404 };
405
406 i2c2: i2c@4819c000 {
407 compatible = "ti,am4372-i2c","ti,omap4-i2c";
408 reg = <0x4819c000 0x1000>;
409 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
410 ti,hwmods = "i2c3";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 status = "disabled";
414 };
415
416 spi0: spi@48030000 {
417 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
418 reg = <0x48030000 0x400>;
419 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
420 ti,hwmods = "spi0";
421 #address-cells = <1>;
422 #size-cells = <0>;
423 status = "disabled";
424 };
425
426 mmc1: mmc@48060000 {
427 compatible = "ti,omap4-hsmmc";
428 reg = <0x48060000 0x1000>;
429 ti,hwmods = "mmc1";
430 ti,dual-volt;
431 ti,needs-special-reset;
432 dmas = <&edma 24
433 &edma 25>;
434 dma-names = "tx", "rx";
435 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
436 status = "disabled";
437 };
438
439 mmc2: mmc@481d8000 {
440 compatible = "ti,omap4-hsmmc";
441 reg = <0x481d8000 0x1000>;
442 ti,hwmods = "mmc2";
443 ti,needs-special-reset;
444 dmas = <&edma 2
445 &edma 3>;
446 dma-names = "tx", "rx";
447 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
448 status = "disabled";
449 };
450
451 mmc3: mmc@47810000 {
452 compatible = "ti,omap4-hsmmc";
453 reg = <0x47810000 0x1000>;
454 ti,hwmods = "mmc3";
455 ti,needs-special-reset;
456 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
457 status = "disabled";
458 };
459
460 spi1: spi@481a0000 {
461 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
462 reg = <0x481a0000 0x400>;
463 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
464 ti,hwmods = "spi1";
465 #address-cells = <1>;
466 #size-cells = <0>;
467 status = "disabled";
468 };
469
470 spi2: spi@481a2000 {
471 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
472 reg = <0x481a2000 0x400>;
473 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
474 ti,hwmods = "spi2";
475 #address-cells = <1>;
476 #size-cells = <0>;
477 status = "disabled";
478 };
479
480 spi3: spi@481a4000 {
481 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
482 reg = <0x481a4000 0x400>;
483 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
484 ti,hwmods = "spi3";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 status = "disabled";
488 };
489
490 spi4: spi@48345000 {
491 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
492 reg = <0x48345000 0x400>;
493 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
494 ti,hwmods = "spi4";
495 #address-cells = <1>;
496 #size-cells = <0>;
497 status = "disabled";
498 };
499
500 mac: ethernet@4a100000 {
501 compatible = "ti,am4372-cpsw","ti,cpsw";
502 reg = <0x4a100000 0x800
503 0x4a101200 0x100>;
504 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
505 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
506 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
507 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
509 #size-cells = <1>;
510 ti,hwmods = "cpgmac0";
511 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
512 clock-names = "fck", "cpts";
513 status = "disabled";
514 cpdma_channels = <8>;
515 ale_entries = <1024>;
516 bd_ram_size = <0x2000>;
517 no_bd_ram = <0>;
518 rx_descs = <64>;
519 mac_control = <0x20>;
520 slaves = <2>;
521 active_slave = <0>;
522 cpts_clock_mult = <0x80000000>;
523 cpts_clock_shift = <29>;
524 ranges;
525
526 davinci_mdio: mdio@4a101000 {
527 compatible = "ti,am4372-mdio","ti,davinci_mdio";
528 reg = <0x4a101000 0x100>;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 ti,hwmods = "davinci_mdio";
532 bus_freq = <1000000>;
533 status = "disabled";
534 };
535
536 cpsw_emac0: slave@4a100200 {
537 /* Filled in by U-Boot */
538 mac-address = [ 00 00 00 00 00 00 ];
539 };
540
541 cpsw_emac1: slave@4a100300 {
542 /* Filled in by U-Boot */
543 mac-address = [ 00 00 00 00 00 00 ];
544 };
545
546 phy_sel: cpsw-phy-sel@44e10650 {
547 compatible = "ti,am43xx-cpsw-phy-sel";
548 reg= <0x44e10650 0x4>;
549 reg-names = "gmii-sel";
550 };
551 };
552
553 epwmss0: epwmss@48300000 {
554 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
555 reg = <0x48300000 0x10>;
556 #address-cells = <1>;
557 #size-cells = <1>;
558 ranges;
559 ti,hwmods = "epwmss0";
560 status = "disabled";
561
562 ecap0: ecap@48300100 {
563 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
564 #pwm-cells = <3>;
565 reg = <0x48300100 0x80>;
566 ti,hwmods = "ecap0";
567 status = "disabled";
568 };
569
570 ehrpwm0: ehrpwm@48300200 {
571 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
572 #pwm-cells = <3>;
573 reg = <0x48300200 0x80>;
574 ti,hwmods = "ehrpwm0";
575 status = "disabled";
576 };
577 };
578
579 epwmss1: epwmss@48302000 {
580 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
581 reg = <0x48302000 0x10>;
582 #address-cells = <1>;
583 #size-cells = <1>;
584 ranges;
585 ti,hwmods = "epwmss1";
586 status = "disabled";
587
588 ecap1: ecap@48302100 {
589 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
590 #pwm-cells = <3>;
591 reg = <0x48302100 0x80>;
592 ti,hwmods = "ecap1";
593 status = "disabled";
594 };
595
596 ehrpwm1: ehrpwm@48302200 {
597 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
598 #pwm-cells = <3>;
599 reg = <0x48302200 0x80>;
600 ti,hwmods = "ehrpwm1";
601 status = "disabled";
602 };
603 };
604
605 epwmss2: epwmss@48304000 {
606 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
607 reg = <0x48304000 0x10>;
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges;
611 ti,hwmods = "epwmss2";
612 status = "disabled";
613
614 ecap2: ecap@48304100 {
615 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
616 #pwm-cells = <3>;
617 reg = <0x48304100 0x80>;
618 ti,hwmods = "ecap2";
619 status = "disabled";
620 };
621
622 ehrpwm2: ehrpwm@48304200 {
623 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
624 #pwm-cells = <3>;
625 reg = <0x48304200 0x80>;
626 ti,hwmods = "ehrpwm2";
627 status = "disabled";
628 };
629 };
630
631 epwmss3: epwmss@48306000 {
632 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
633 reg = <0x48306000 0x10>;
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges;
637 ti,hwmods = "epwmss3";
638 status = "disabled";
639
640 ehrpwm3: ehrpwm@48306200 {
641 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
642 #pwm-cells = <3>;
643 reg = <0x48306200 0x80>;
644 ti,hwmods = "ehrpwm3";
645 status = "disabled";
646 };
647 };
648
649 epwmss4: epwmss@48308000 {
650 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
651 reg = <0x48308000 0x10>;
652 #address-cells = <1>;
653 #size-cells = <1>;
654 ranges;
655 ti,hwmods = "epwmss4";
656 status = "disabled";
657
658 ehrpwm4: ehrpwm@48308200 {
659 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
660 #pwm-cells = <3>;
661 reg = <0x48308200 0x80>;
662 ti,hwmods = "ehrpwm4";
663 status = "disabled";
664 };
665 };
666
667 epwmss5: epwmss@4830a000 {
668 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
669 reg = <0x4830a000 0x10>;
670 #address-cells = <1>;
671 #size-cells = <1>;
672 ranges;
673 ti,hwmods = "epwmss5";
674 status = "disabled";
675
676 ehrpwm5: ehrpwm@4830a200 {
677 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
678 #pwm-cells = <3>;
679 reg = <0x4830a200 0x80>;
680 ti,hwmods = "ehrpwm5";
681 status = "disabled";
682 };
683 };
684
685 tscadc: tscadc@44e0d000 {
686 compatible = "ti,am3359-tscadc";
687 reg = <0x44e0d000 0x1000>;
688 ti,hwmods = "adc_tsc";
689 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&adc_tsc_fck>;
691 clock-names = "fck";
692 status = "disabled";
693
694 tsc {
695 compatible = "ti,am3359-tsc";
696 };
697
698 adc {
699 #io-channel-cells = <1>;
700 compatible = "ti,am3359-adc";
701 };
702
703 };
704
705 sham: sham@53100000 {
706 compatible = "ti,omap5-sham";
707 ti,hwmods = "sham";
708 reg = <0x53100000 0x300>;
709 dmas = <&edma 36>;
710 dma-names = "rx";
711 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
712 };
713
714 aes: aes@53501000 {
715 compatible = "ti,omap4-aes";
716 ti,hwmods = "aes";
717 reg = <0x53501000 0xa0>;
718 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
719 dmas = <&edma 6
720 &edma 5>;
721 dma-names = "tx", "rx";
722 };
723
724 des: des@53701000 {
725 compatible = "ti,omap4-des";
726 ti,hwmods = "des";
727 reg = <0x53701000 0xa0>;
728 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
729 dmas = <&edma 34
730 &edma 33>;
731 dma-names = "tx", "rx";
732 };
733
734 mcasp0: mcasp@48038000 {
735 compatible = "ti,am33xx-mcasp-audio";
736 ti,hwmods = "mcasp0";
737 reg = <0x48038000 0x2000>,
738 <0x46000000 0x400000>;
739 reg-names = "mpu", "dat";
740 interrupts = <80>, <81>;
741 interrupt-names = "tx", "rx";
742 status = "disabled";
743 dmas = <&edma 8>,
744 <&edma 9>;
745 dma-names = "tx", "rx";
746 };
747
748 mcasp1: mcasp@4803C000 {
749 compatible = "ti,am33xx-mcasp-audio";
750 ti,hwmods = "mcasp1";
751 reg = <0x4803C000 0x2000>,
752 <0x46400000 0x400000>;
753 reg-names = "mpu", "dat";
754 interrupts = <82>, <83>;
755 interrupt-names = "tx", "rx";
756 status = "disabled";
757 dmas = <&edma 10>,
758 <&edma 11>;
759 dma-names = "tx", "rx";
760 };
761
762 elm: elm@48080000 {
763 compatible = "ti,am3352-elm";
764 reg = <0x48080000 0x2000>;
765 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
766 ti,hwmods = "elm";
767 clocks = <&l4ls_gclk>;
768 clock-names = "fck";
769 status = "disabled";
770 };
771
772 gpmc: gpmc@50000000 {
773 compatible = "ti,am3352-gpmc";
774 ti,hwmods = "gpmc";
775 clocks = <&l3s_gclk>;
776 clock-names = "fck";
777 reg = <0x50000000 0x2000>;
778 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
779 gpmc,num-cs = <7>;
780 gpmc,num-waitpins = <2>;
781 #address-cells = <2>;
782 #size-cells = <1>;
783 status = "disabled";
784 };
785
786 am43xx_control_usb2phy1: control-phy@44e10620 {
787 compatible = "ti,control-phy-usb2-am437";
788 reg = <0x44e10620 0x4>;
789 reg-names = "power";
790 };
791
792 am43xx_control_usb2phy2: control-phy@0x44e10628 {
793 compatible = "ti,control-phy-usb2-am437";
794 reg = <0x44e10628 0x4>;
795 reg-names = "power";
796 };
797
798 ocp2scp0: ocp2scp@483a8000 {
799 compatible = "ti,omap-ocp2scp";
800 #address-cells = <1>;
801 #size-cells = <1>;
802 ranges;
803 ti,hwmods = "ocp2scp0";
804
805 usb2_phy1: phy@483a8000 {
806 compatible = "ti,am437x-usb2";
807 reg = <0x483a8000 0x8000>;
808 ctrl-module = <&am43xx_control_usb2phy1>;
809 clocks = <&usb_phy0_always_on_clk32k>,
810 <&usb_otg_ss0_refclk960m>;
811 clock-names = "wkupclk", "refclk";
812 #phy-cells = <0>;
813 status = "disabled";
814 };
815 };
816
817 ocp2scp1: ocp2scp@483e8000 {
818 compatible = "ti,omap-ocp2scp";
819 #address-cells = <1>;
820 #size-cells = <1>;
821 ranges;
822 ti,hwmods = "ocp2scp1";
823
824 usb2_phy2: phy@483e8000 {
825 compatible = "ti,am437x-usb2";
826 reg = <0x483e8000 0x8000>;
827 ctrl-module = <&am43xx_control_usb2phy2>;
828 clocks = <&usb_phy1_always_on_clk32k>,
829 <&usb_otg_ss1_refclk960m>;
830 clock-names = "wkupclk", "refclk";
831 #phy-cells = <0>;
832 status = "disabled";
833 };
834 };
835
836 dwc3_1: omap_dwc3@48380000 {
837 compatible = "ti,am437x-dwc3";
838 ti,hwmods = "usb_otg_ss0";
839 reg = <0x48380000 0x10000>;
840 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
841 #address-cells = <1>;
842 #size-cells = <1>;
843 utmi-mode = <1>;
844 ranges;
845
846 usb1: usb@48390000 {
847 compatible = "synopsys,dwc3";
848 reg = <0x48390000 0x10000>;
849 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
850 phys = <&usb2_phy1>;
851 phy-names = "usb2-phy";
852 maximum-speed = "high-speed";
853 dr_mode = "otg";
854 status = "disabled";
855 snps,dis_u3_susphy_quirk;
856 snps,dis_u2_susphy_quirk;
857 };
858 };
859
860 dwc3_2: omap_dwc3@483c0000 {
861 compatible = "ti,am437x-dwc3";
862 ti,hwmods = "usb_otg_ss1";
863 reg = <0x483c0000 0x10000>;
864 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>;
866 #size-cells = <1>;
867 utmi-mode = <1>;
868 ranges;
869
870 usb2: usb@483d0000 {
871 compatible = "synopsys,dwc3";
872 reg = <0x483d0000 0x10000>;
873 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
874 phys = <&usb2_phy2>;
875 phy-names = "usb2-phy";
876 maximum-speed = "high-speed";
877 dr_mode = "otg";
878 status = "disabled";
879 snps,dis_u3_susphy_quirk;
880 snps,dis_u2_susphy_quirk;
881 };
882 };
883
884 qspi: qspi@47900000 {
885 compatible = "ti,am4372-qspi";
886 reg = <0x47900000 0x100>;
887 #address-cells = <1>;
888 #size-cells = <0>;
889 ti,hwmods = "qspi";
890 interrupts = <0 138 0x4>;
891 num-cs = <4>;
892 status = "disabled";
893 };
894
895 hdq: hdq@48347000 {
896 compatible = "ti,am43xx-hdq";
897 reg = <0x48347000 0x1000>;
898 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&func_12m_clk>;
900 clock-names = "fck";
901 ti,hwmods = "hdq1w";
902 status = "disabled";
903 };
904
905 dss: dss@4832a000 {
906 compatible = "ti,omap3-dss";
907 reg = <0x4832a000 0x200>;
908 status = "disabled";
909 ti,hwmods = "dss_core";
910 clocks = <&disp_clk>;
911 clock-names = "fck";
912 #address-cells = <1>;
913 #size-cells = <1>;
914 ranges;
915
916 dispc: dispc@4832a400 {
917 compatible = "ti,omap3-dispc";
918 reg = <0x4832a400 0x400>;
919 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
920 ti,hwmods = "dss_dispc";
921 clocks = <&disp_clk>;
922 clock-names = "fck";
923 };
924
925 rfbi: rfbi@4832a800 {
926 compatible = "ti,omap3-rfbi";
927 reg = <0x4832a800 0x100>;
928 ti,hwmods = "dss_rfbi";
929 clocks = <&disp_clk>;
930 clock-names = "fck";
931 };
932 };
933
934 ocmcram: ocmcram@40300000 {
935 compatible = "mmio-sram";
936 reg = <0x40300000 0x40000>; /* 256k */
937 };
938
939 dcan0: can@481cc000 {
940 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
941 ti,hwmods = "d_can0";
942 clocks = <&dcan0_fck>;
943 clock-names = "fck";
944 reg = <0x481cc000 0x2000>;
945 syscon-raminit = <&am43xx_control_module 0x644 0>;
946 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
947 status = "disabled";
948 };
949
950 dcan1: can@481d0000 {
951 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
952 ti,hwmods = "d_can1";
953 clocks = <&dcan1_fck>;
954 clock-names = "fck";
955 reg = <0x481d0000 0x2000>;
956 syscon-raminit = <&am43xx_control_module 0x644 1>;
957 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
958 status = "disabled";
959 };
960
961 vpfe0: vpfe@48326000 {
962 compatible = "ti,am437x-vpfe";
963 reg = <0x48326000 0x2000>;
964 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
965 ti,hwmods = "vpfe0";
966 status = "disabled";
967 };
968
969 vpfe1: vpfe@48328000 {
970 compatible = "ti,am437x-vpfe";
971 reg = <0x48328000 0x2000>;
972 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
973 ti,hwmods = "vpfe1";
974 status = "disabled";
975 };
976 };
977 };
978
979 /include/ "am43xx-clocks.dtsi"
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