arch/arm/boot/dts/am437x-gp-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM437x GP EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/pwm/pwm.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17
  18 / {
  19         model = "TI AM437x GP EVM";
  20         compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  21
  22         aliases {
  23                 display0 = &lcd0;
  24         };
  25
  26         chosen {
  27                 stdout-path = &uart0;
  28         };
  29
  30         evm_v3_3d: fixedregulator-v3_3d {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "evm_v3_3d";
  33                 regulator-min-microvolt = <3300000>;
  34                 regulator-max-microvolt = <3300000>;
  35                 enable-active-high;
  36         };
  37
  38         vtt_fixed: fixedregulator-vtt {
  39                 compatible = "regulator-fixed";
  40                 regulator-name = "vtt_fixed";
  41                 regulator-min-microvolt = <1500000>;
  42                 regulator-max-microvolt = <1500000>;
  43                 regulator-always-on;
  44                 regulator-boot-on;
  45                 enable-active-high;
  46                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  47         };
  48
  49         vmmcwl_fixed: fixedregulator-mmcwl {
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "vmmcwl_fixed";
  52                 regulator-min-microvolt = <1800000>;
  53                 regulator-max-microvolt = <1800000>;
  54                 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  55                 enable-active-high;
  56         };
  57
  58         backlight {
  59                 compatible = "pwm-backlight";
  60                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  61                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
  62                 default-brightness-level = <8>;
  63         };
  64
  65         matrix_keypad: matrix_keypad0 {
  66                 compatible = "gpio-matrix-keypad";
  67                 debounce-delay-ms = <5>;
  68                 col-scan-delay-us = <2>;
  69
  70                 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
  71                                 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  72                                 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  73
  74                 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  75                                 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  76
  77                 linux,keymap = <0x00000201      /* P1 */
  78                                 0x00010202      /* P2 */
  79                                 0x01000067      /* UP */
  80                                 0x0101006a      /* RIGHT */
  81                                 0x02000069      /* LEFT */
  82                                 0x0201006c>;      /* DOWN */
  83                 };
  84
  85         lcd0: display {
  86                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  87                 label = "lcd";
  88
  89                 panel-timing {
  90                         clock-frequency = <33000000>;
  91                         hactive = <800>;
  92                         vactive = <480>;
  93                         hfront-porch = <210>;
  94                         hback-porch = <16>;
  95                         hsync-len = <30>;
  96                         vback-porch = <10>;
  97                         vfront-porch = <22>;
  98                         vsync-len = <13>;
  99                         hsync-active = <0>;
 100                         vsync-active = <0>;
 101                         de-active = <1>;
 102                         pixelclk-active = <1>;
 103                 };
 104
 105                 port {
 106                         lcd_in: endpoint {
 107                                 remote-endpoint = <&dpi_out>;
 108                         };
 109                 };
 110         };
 111
 112         /* fixed 12MHz oscillator */
 113         refclk: oscillator {
 114                 #clock-cells = <0>;
 115                 compatible = "fixed-clock";
 116                 clock-frequency = <12000000>;
 117         };
 118
 119         /* fixed 32k external oscillator clock */
 120         clk_32k_rtc: clk_32k_rtc {
 121                 #clock-cells = <0>;
 122                 compatible = "fixed-clock";
 123                 clock-frequency = <32768>;
 124         };
 125
 126         sound0: sound0 {
 127                 compatible = "simple-audio-card";
 128                 simple-audio-card,name = "AM437x-GP-EVM";
 129                 simple-audio-card,widgets =
 130                         "Headphone", "Headphone Jack",
 131                         "Line", "Line In";
 132                 simple-audio-card,routing =
 133                         "Headphone Jack",       "HPLOUT",
 134                         "Headphone Jack",       "HPROUT",
 135                         "LINE1L",               "Line In",
 136                         "LINE1R",               "Line In";
 137                 simple-audio-card,format = "dsp_b";
 138                 simple-audio-card,bitclock-master = <&sound0_master>;
 139                 simple-audio-card,frame-master = <&sound0_master>;
 140                 simple-audio-card,bitclock-inversion;
 141
 142                 simple-audio-card,cpu {
 143                         sound-dai = <&mcasp1>;
 144                         system-clock-frequency = <12000000>;
 145                 };
 146
 147                 sound0_master: simple-audio-card,codec {
 148                         sound-dai = <&tlv320aic3106>;
 149                         system-clock-frequency = <12000000>;
 150                 };
 151         };
 152 };
 153
 154 &am43xx_pinmux {
 155         pinctrl-names = "default", "sleep";
 156         pinctrl-0 = <&wlan_pins_default>;
 157         pinctrl-1 = <&wlan_pins_sleep>;
 158
 159         i2c0_pins: i2c0_pins {
 160                 pinctrl-single,pins = <
 161                         AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
 162                         AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 163                 >;
 164         };
 165
 166         i2c1_pins: i2c1_pins {
 167                 pinctrl-single,pins = <
 168                         AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
 169                         AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 170                 >;
 171         };
 172
 173         mmc1_pins: pinmux_mmc1_pins {
 174                 pinctrl-single,pins = <
 175                         AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 176                 >;
 177         };
 178
 179         ecap0_pins: backlight_pins {
 180                 pinctrl-single,pins = <
 181                         AM4372_IOPAD(0x964, MUX_MODE0)       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 182                 >;
 183         };
 184
 185         pixcir_ts_pins: pixcir_ts_pins {
 186                 pinctrl-single,pins = <
 187                         AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
 188                 >;
 189         };
 190
 191         cpsw_default: cpsw_default {
 192                 pinctrl-single,pins = <
 193                         /* Slave 1 */
 194                         AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_txen */
 195                         AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rxctl */
 196                         AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd3 */
 197                         AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd2 */
 198                         AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd1 */
 199                         AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd0 */
 200                         AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rmii1_tclk */
 201                         AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rmii1_rclk */
 202                         AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rxd3 */
 203                         AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rxd2 */
 204                         AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rxd1 */
 205                         AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rxd0 */
 206                 >;
 207         };
 208
 209         cpsw_sleep: cpsw_sleep {
 210                 pinctrl-single,pins = <
 211                         /* Slave 1 reset value */
 212                         AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
 213                         AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
 214                         AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 215                         AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
 216                         AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
 217                         AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
 218                         AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 219                         AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
 220                         AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
 221                         AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
 222                         AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 223                         AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
 224                 >;
 225         };
 226
 227         davinci_mdio_default: davinci_mdio_default {
 228                 pinctrl-single,pins = <
 229                         /* MDIO */
 230                         AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
 231                         AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
 232                 >;
 233         };
 234
 235         davinci_mdio_sleep: davinci_mdio_sleep {
 236                 pinctrl-single,pins = <
 237                         /* MDIO reset value */
 238                         AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
 239                         AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 240                 >;
 241         };
 242
 243         nand_flash_x8: nand_flash_x8 {
 244                 pinctrl-single,pins = <
 245                         AM4372_IOPAD(0x800, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad0.gpmc_ad0 */
 246                         AM4372_IOPAD(0x804, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad1.gpmc_ad1 */
 247                         AM4372_IOPAD(0x808, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad2.gpmc_ad2 */
 248                         AM4372_IOPAD(0x80c, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad3.gpmc_ad3 */
 249                         AM4372_IOPAD(0x810, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
 250                         AM4372_IOPAD(0x814, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
 251                         AM4372_IOPAD(0x818, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
 252                         AM4372_IOPAD(0x81c, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
 253                         AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
 254                         AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_wpn.gpmc_wpn */
 255                         AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
 256                         AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
 257                         AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
 258                         AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
 259                         AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
 260                 >;
 261         };
 262
 263         dss_pins: dss_pins {
 264                 pinctrl-single,pins = <
 265                         AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 266                         AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
 267                         AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
 268                         AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
 269                         AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
 270                         AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
 271                         AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
 272                         AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 273                         AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 274                         AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 275                         AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 276                         AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
 277                         AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 278                         AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 279                         AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 280                         AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
 281                         AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 282                         AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 283                         AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 284                         AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
 285                         AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 286                         AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 287                         AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 288                         AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 289                         AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 290                         AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 291                         AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 292                         AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 293
 294                 >;
 295         };
 296
 297         display_mux_pins: display_mux_pins {
 298                 pinctrl-single,pins = <
 299                         /* GPIO 5_8 to select LCD / HDMI */
 300                         AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
 301                 >;
 302         };
 303
 304         dcan0_default: dcan0_default_pins {
 305                 pinctrl-single,pins = <
 306                         AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)             /* uart1_ctsn.d_can0_tx */
 307                         AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_rtsn.d_can0_rx */
 308                 >;
 309         };
 310
 311         dcan0_sleep: dcan0_sleep_pins {
 312                 pinctrl-single,pins = <
 313                         AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_ctsn.gpio0_12 */
 314                         AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_rtsn.gpio0_13 */
 315                 >;
 316         };
 317
 318         dcan1_default: dcan1_default_pins {
 319                 pinctrl-single,pins = <
 320                         AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)             /* uart1_rxd.d_can1_tx */
 321                         AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_txd.d_can1_rx */
 322                 >;
 323         };
 324
 325         dcan1_sleep: dcan1_sleep_pins {
 326                 pinctrl-single,pins = <
 327                         AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_rxd.gpio0_14 */
 328                         AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_txd.gpio0_15 */
 329                 >;
 330         };
 331
 332         vpfe0_pins_default: vpfe0_pins_default {
 333                 pinctrl-single,pins = <
 334                         AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
 335                         AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
 336                         AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
 337                         AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
 338                         AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
 339                         AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
 340                         AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
 341                         AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
 342                         AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
 343                         AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
 344                         AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
 345                         AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
 346                         AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
 347                 >;
 348         };
 349
 350         vpfe0_pins_sleep: vpfe0_pins_sleep {
 351                 pinctrl-single,pins = <
 352                         AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
 353                         AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
 354                         AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
 355                         AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
 356                         AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
 357                         AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
 358                         AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
 359                         AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
 360                         AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
 361                         AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
 362                         AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
 363                         AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
 364                         AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
 365                 >;
 366         };
 367
 368         vpfe1_pins_default: vpfe1_pins_default {
 369                 pinctrl-single,pins = <
 370                         AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
 371                         AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
 372                         AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
 373                         AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
 374                         AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
 375                         AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
 376                         AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
 377                         AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
 378                         AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
 379                         AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
 380                         AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
 381                         AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
 382                         AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
 383                 >;
 384         };
 385
 386         vpfe1_pins_sleep: vpfe1_pins_sleep {
 387                 pinctrl-single,pins = <
 388                         AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
 389                         AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
 390                         AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
 391                         AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
 392                         AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
 393                         AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
 394                         AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
 395                         AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
 396                         AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
 397                         AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
 398                         AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
 399                         AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
 400                         AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
 401                 >;
 402         };
 403
 404         mmc3_pins_default: pinmux_mmc3_pins_default {
 405                 pinctrl-single,pins = <
 406                         AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
 407                         AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
 408                         AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
 409                         AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
 410                         AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
 411                         AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
 412                 >;
 413         };
 414
 415         mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
 416                 pinctrl-single,pins = <
 417                         AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_clk.mmc2_clk */
 418                         AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_csn3.mmc2_cmd */
 419                         AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a1.mmc2_dat0 */
 420                         AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a2.mmc2_dat1 */
 421                         AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a3.mmc2_dat2 */
 422                         AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_be1n.mmc2_dat3 */
 423                 >;
 424         };
 425
 426         wlan_pins_default: pinmux_wlan_pins_default {
 427                 pinctrl-single,pins = <
 428                         AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a4.gpio1_20 WL_EN */
 429                         AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)      /* gpmc_a7.gpio1_23 WL_IRQ*/
 430                         AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
 431                 >;
 432         };
 433
 434         wlan_pins_sleep: pinmux_wlan_pins_sleep {
 435                 pinctrl-single,pins = <
 436                         AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a4.gpio1_20 WL_EN */
 437                         AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)      /* gpmc_a7.gpio1_23 WL_IRQ*/
 438                         AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7)              /* gpmc_a0.gpio1_16 BT_EN*/
 439                 >;
 440         };
 441
 442         uart3_pins: uart3_pins {
 443                 pinctrl-single,pins = <
 444                         AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0)              /* uart3_rxd.uart3_rxd */
 445                         AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
 446                         AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart3_ctsn.uart3_ctsn */
 447                         AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
 448                 >;
 449         };
 450
 451         mcasp1_pins: mcasp1_pins {
 452                 pinctrl-single,pins = <
 453                         AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4)    /* mii1_col.mcasp1_axr2 */
 454                         AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* mii1_crs.mcasp1_aclkx */
 455                         AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* mii1_rxerr.mcasp1_fsx */
 456                         AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* rmii1_ref_clk.mcasp1_axr3 */
 457                 >;
 458         };
 459
 460         mcasp1_sleep_pins: mcasp1_sleep_pins {
 461                 pinctrl-single,pins = <
 462                         AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
 463                         AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 464                         AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
 465                         AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
 466                 >;
 467         };
 468
 469         gpio0_pins: gpio0_pins {
 470                 pinctrl-single,pins = <
 471                         AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
 472                 >;
 473         };
 474
 475         emmc_pins_default: emmc_pins_default {
 476                 pinctrl-single,pins = <
 477                         AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
 478                         AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
 479                         AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
 480                         AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
 481                         AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
 482                         AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
 483                         AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
 484                         AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
 485                         AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
 486                         AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
 487                 >;
 488         };
 489
 490         emmc_pins_sleep: emmc_pins_sleep {
 491                 pinctrl-single,pins = <
 492                         AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
 493                         AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
 494                         AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
 495                         AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
 496                         AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
 497                         AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
 498                         AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
 499                         AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
 500                         AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
 501                         AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
 502                 >;
 503         };
 504 };
 505
 506 &i2c0 {
 507         status = "okay";
 508         pinctrl-names = "default";
 509         pinctrl-0 = <&i2c0_pins>;
 510         clock-frequency = <100000>;
 511
 512         tps65218: tps65218@24 {
 513                 reg = <0x24>;
 514                 compatible = "ti,tps65218";
 515                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
 516                 interrupt-controller;
 517                 #interrupt-cells = <2>;
 518
 519                 dcdc1: regulator-dcdc1 {
 520                         regulator-name = "vdd_core";
 521                         regulator-min-microvolt = <912000>;
 522                         regulator-max-microvolt = <1144000>;
 523                         regulator-boot-on;
 524                         regulator-always-on;
 525                 };
 526
 527                 dcdc2: regulator-dcdc2 {
 528                         regulator-name = "vdd_mpu";
 529                         regulator-min-microvolt = <912000>;
 530                         regulator-max-microvolt = <1378000>;
 531                         regulator-boot-on;
 532                         regulator-always-on;
 533                 };
 534
 535                 dcdc3: regulator-dcdc3 {
 536                         regulator-name = "vdcdc3";
 537                         regulator-min-microvolt = <1500000>;
 538                         regulator-max-microvolt = <1500000>;
 539                         regulator-boot-on;
 540                         regulator-always-on;
 541                         regulator-state-mem {
 542                                 regulator-on-in-suspend;
 543                         };
 544                         regulator-state-disk {
 545                                 regulator-off-in-suspend;
 546                         };
 547                 };
 548
 549                 dcdc5: regulator-dcdc5 {
 550                         regulator-name = "v1_0bat";
 551                         regulator-min-microvolt = <1000000>;
 552                         regulator-max-microvolt = <1000000>;
 553                         regulator-boot-on;
 554                         regulator-always-on;
 555                         regulator-state-mem {
 556                                 regulator-on-in-suspend;
 557                         };
 558                 };
 559
 560                 dcdc6: regulator-dcdc6 {
 561                         regulator-name = "v1_8bat";
 562                         regulator-min-microvolt = <1800000>;
 563                         regulator-max-microvolt = <1800000>;
 564                         regulator-boot-on;
 565                         regulator-always-on;
 566                         regulator-state-mem {
 567                                 regulator-on-in-suspend;
 568                         };
 569                 };
 570
 571                 ldo1: regulator-ldo1 {
 572                         regulator-min-microvolt = <1800000>;
 573                         regulator-max-microvolt = <1800000>;
 574                         regulator-boot-on;
 575                         regulator-always-on;
 576                 };
 577         };
 578
 579         ov2659@30 {
 580                 compatible = "ovti,ov2659";
 581                 reg = <0x30>;
 582
 583                 clocks = <&refclk 0>;
 584                 clock-names = "xvclk";
 585
 586                 port {
 587                         ov2659_0: endpoint {
 588                                 remote-endpoint = <&vpfe1_ep>;
 589                                 link-frequencies = /bits/ 64 <70000000>;
 590                         };
 591                 };
 592         };
 593 };
 594
 595 &i2c1 {
 596         status = "okay";
 597         pinctrl-names = "default";
 598         pinctrl-0 = <&i2c1_pins>;
 599         pixcir_ts@5c {
 600                 compatible = "pixcir,pixcir_tangoc";
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&pixcir_ts_pins>;
 603                 reg = <0x5c>;
 604
 605                 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 606
 607                 /*
 608                  * 0x264 represents the offset of padconf register of
 609                  * gpio3_22 from am43xx_pinmux base.
 610                  */
 611                 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
 612                                       <&am43xx_pinmux 0x264>;
 613                 interrupt-names = "tsc", "wakeup";
 614
 615                 touchscreen-size-x = <1024>;
 616                 touchscreen-size-y = <600>;
 617                 wakeup-source;
 618         };
 619
 620         ov2659@30 {
 621                 compatible = "ovti,ov2659";
 622                 reg = <0x30>;
 623
 624                 clocks = <&refclk 0>;
 625                 clock-names = "xvclk";
 626
 627                 port {
 628                         ov2659_1: endpoint {
 629                                 remote-endpoint = <&vpfe0_ep>;
 630                                 link-frequencies = /bits/ 64 <70000000>;
 631                         };
 632                 };
 633         };
 634
 635         tlv320aic3106: tlv320aic3106@1b {
 636                 #sound-dai-cells = <0>;
 637                 compatible = "ti,tlv320aic3106";
 638                 reg = <0x1b>;
 639                 status = "okay";
 640
 641                 /* Regulators */
 642                 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
 643                 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
 644                 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
 645                 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
 646         };
 647 };
 648
 649 &epwmss0 {
 650         status = "okay";
 651 };
 652
 653 &tscadc {
 654         status = "okay";
 655
 656         adc {
 657                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 658         };
 659 };
 660
 661 &ecap0 {
 662         status = "okay";
 663         pinctrl-names = "default";
 664         pinctrl-0 = <&ecap0_pins>;
 665 };
 666
 667 &gpio0 {
 668         pinctrl-names = "default";
 669         pinctrl-0 = <&gpio0_pins>;
 670         status = "okay";
 671
 672         p23 {
 673                 gpio-hog;
 674                 gpios = <23 GPIO_ACTIVE_HIGH>;
 675                 /* SelEMMCorNAND selects between eMMC and NAND:
 676                  * Low: NAND
 677                  * High: eMMC
 678                  * When changing this line make sure the newly
 679                  * selected device node is enabled and the previously
 680                  * selected device node is disabled.
 681                  */
 682                 output-low;
 683                 line-name = "SelEMMCorNAND";
 684         };
 685 };
 686
 687 &gpio1 {
 688         status = "okay";
 689 };
 690
 691 &gpio3 {
 692         status = "okay";
 693 };
 694
 695 &gpio4 {
 696         status = "okay";
 697 };
 698
 699 &gpio5 {
 700         pinctrl-names = "default";
 701         pinctrl-0 = <&display_mux_pins>;
 702         status = "okay";
 703         ti,no-reset-on-init;
 704
 705         p8 {
 706                 /*
 707                  * SelLCDorHDMI selects between display and audio paths:
 708                  * Low: HDMI display with audio via HDMI
 709                  * High: LCD display with analog audio via aic3111 codec
 710                  */
 711                 gpio-hog;
 712                 gpios = <8 GPIO_ACTIVE_HIGH>;
 713                 output-high;
 714                 line-name = "SelLCDorHDMI";
 715         };
 716 };
 717
 718 &mmc1 {
 719         status = "okay";
 720         vmmc-supply = <&evm_v3_3d>;
 721         bus-width = <4>;
 722         pinctrl-names = "default";
 723         pinctrl-0 = <&mmc1_pins>;
 724         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 725 };
 726
 727 /* eMMC sits on mmc2 */
 728 &mmc2 {
 729         /*
 730          * When enabling eMMC, disable GPMC/NAND and set
 731          * SelEMMCorNAND to output-high
 732          */
 733         status = "disabled";
 734         vmmc-supply = <&evm_v3_3d>;
 735         bus-width = <8>;
 736         pinctrl-names = "default", "sleep";
 737         pinctrl-0 = <&emmc_pins_default>;
 738         pinctrl-1 = <&emmc_pins_sleep>;
 739         ti,non-removable;
 740 };
 741
 742 &mmc3 {
 743         status = "okay";
 744         /* these are on the crossbar and are outlined in the
 745            xbar-event-map element */
 746         dmas = <&edma_xbar 30 0 1>,
 747                 <&edma_xbar 31 0 2>;
 748         dma-names = "tx", "rx";
 749         vmmc-supply = <&vmmcwl_fixed>;
 750         bus-width = <4>;
 751         pinctrl-names = "default", "sleep";
 752         pinctrl-0 = <&mmc3_pins_default>;
 753         pinctrl-1 = <&mmc3_pins_sleep>;
 754         cap-power-off-card;
 755         keep-power-in-suspend;
 756         ti,non-removable;
 757
 758         #address-cells = <1>;
 759         #size-cells = <0>;
 760         wlcore: wlcore@0 {
 761                 compatible = "ti,wl1835";
 762                 reg = <2>;
 763                 interrupt-parent = <&gpio1>;
 764                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
 765         };
 766 };
 767
 768 &uart3 {
 769         status = "okay";
 770         pinctrl-names = "default";
 771         pinctrl-0 = <&uart3_pins>;
 772 };
 773
 774 &usb2_phy1 {
 775         status = "okay";
 776 };
 777
 778 &usb1 {
 779         dr_mode = "peripheral";
 780         status = "okay";
 781 };
 782
 783 &usb2_phy2 {
 784         status = "okay";
 785 };
 786
 787 &usb2 {
 788         dr_mode = "host";
 789         status = "okay";
 790 };
 791
 792 &mac {
 793         slaves = <1>;
 794         pinctrl-names = "default", "sleep";
 795         pinctrl-0 = <&cpsw_default>;
 796         pinctrl-1 = <&cpsw_sleep>;
 797         status = "okay";
 798 };
 799
 800 &davinci_mdio {
 801         pinctrl-names = "default", "sleep";
 802         pinctrl-0 = <&davinci_mdio_default>;
 803         pinctrl-1 = <&davinci_mdio_sleep>;
 804         status = "okay";
 805 };
 806
 807 &cpsw_emac0 {
 808         phy_id = <&davinci_mdio>, <0>;
 809         phy-mode = "rgmii";
 810 };
 811
 812 &elm {
 813         status = "okay";
 814 };
 815
 816 &gpmc {
 817         /*
 818          * When enabling GPMC, disable eMMC and set
 819          * SelEMMCorNAND to output-low
 820          */
 821         status = "okay";
 822         pinctrl-names = "default";
 823         pinctrl-0 = <&nand_flash_x8>;
 824         ranges = <0 0 0x08000000 0x01000000>;   /* CS0 space. Min partition = 16MB */
 825         nand@0,0 {
 826                 compatible = "ti,omap2-nand";
 827                 reg = <0 0 4>;          /* device IO registers */
 828                 interrupt-parent = <&gpmc>;
 829                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 830                              <1 IRQ_TYPE_NONE>; /* termcount */
 831                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
 832                 ti,nand-ecc-opt = "bch16";
 833                 ti,elm-id = <&elm>;
 834                 nand-bus-width = <8>;
 835                 gpmc,device-width = <1>;
 836                 gpmc,sync-clk-ps = <0>;
 837                 gpmc,cs-on-ns = <0>;
 838                 gpmc,cs-rd-off-ns = <40>;
 839                 gpmc,cs-wr-off-ns = <40>;
 840                 gpmc,adv-on-ns = <0>;
 841                 gpmc,adv-rd-off-ns = <25>;
 842                 gpmc,adv-wr-off-ns = <25>;
 843                 gpmc,we-on-ns = <0>;
 844                 gpmc,we-off-ns = <20>;
 845                 gpmc,oe-on-ns = <3>;
 846                 gpmc,oe-off-ns = <30>;
 847                 gpmc,access-ns = <30>;
 848                 gpmc,rd-cycle-ns = <40>;
 849                 gpmc,wr-cycle-ns = <40>;
 850                 gpmc,bus-turnaround-ns = <0>;
 851                 gpmc,cycle2cycle-delay-ns = <0>;
 852                 gpmc,clk-activation-ns = <0>;
 853                 gpmc,wr-access-ns = <40>;
 854                 gpmc,wr-data-mux-bus-ns = <0>;
 855                 /* MTD partition table */
 856                 /* All SPL-* partitions are sized to minimal length
 857                  * which can be independently programmable. For
 858                  * NAND flash this is equal to size of erase-block */
 859                 #address-cells = <1>;
 860                 #size-cells = <1>;
 861                 partition@0 {
 862                         label = "NAND.SPL";
 863                         reg = <0x00000000 0x00040000>;
 864                 };
 865                 partition@1 {
 866                         label = "NAND.SPL.backup1";
 867                         reg = <0x00040000 0x00040000>;
 868                 };
 869                 partition@2 {
 870                         label = "NAND.SPL.backup2";
 871                         reg = <0x00080000 0x00040000>;
 872                 };
 873                 partition@3 {
 874                         label = "NAND.SPL.backup3";
 875                         reg = <0x000c0000 0x00040000>;
 876                 };
 877                 partition@4 {
 878                         label = "NAND.u-boot-spl-os";
 879                         reg = <0x00100000 0x00080000>;
 880                 };
 881                 partition@5 {
 882                         label = "NAND.u-boot";
 883                         reg = <0x00180000 0x00100000>;
 884                 };
 885                 partition@6 {
 886                         label = "NAND.u-boot-env";
 887                         reg = <0x00280000 0x00040000>;
 888                 };
 889                 partition@7 {
 890                         label = "NAND.u-boot-env.backup1";
 891                         reg = <0x002c0000 0x00040000>;
 892                 };
 893                 partition@8 {
 894                         label = "NAND.kernel";
 895                         reg = <0x00300000 0x00700000>;
 896                 };
 897                 partition@9 {
 898                         label = "NAND.file-system";
 899                         reg = <0x00a00000 0x1f600000>;
 900                 };
 901         };
 902 };
 903
 904 &dss {
 905         status = "ok";
 906
 907         pinctrl-names = "default";
 908         pinctrl-0 = <&dss_pins>;
 909
 910         port {
 911                 dpi_out: endpoint {
 912                         remote-endpoint = <&lcd_in>;
 913                         data-lines = <24>;
 914                 };
 915         };
 916 };
 917
 918 &dcan0 {
 919         pinctrl-names = "default", "sleep";
 920         pinctrl-0 = <&dcan0_default>;
 921         pinctrl-1 = <&dcan0_sleep>;
 922         status = "okay";
 923 };
 924
 925 &dcan1 {
 926         pinctrl-names = "default", "sleep";
 927         pinctrl-0 = <&dcan1_default>;
 928         pinctrl-1 = <&dcan1_sleep>;
 929         status = "okay";
 930 };
 931
 932 &vpfe0 {
 933         status = "okay";
 934         pinctrl-names = "default", "sleep";
 935         pinctrl-0 = <&vpfe0_pins_default>;
 936         pinctrl-1 = <&vpfe0_pins_sleep>;
 937
 938         port {
 939                 vpfe0_ep: endpoint {
 940                         remote-endpoint = <&ov2659_1>;
 941                         ti,am437x-vpfe-interface = <0>;
 942                         bus-width = <8>;
 943                         hsync-active = <0>;
 944                         vsync-active = <0>;
 945                 };
 946         };
 947 };
 948
 949 &vpfe1 {
 950         status = "okay";
 951         pinctrl-names = "default", "sleep";
 952         pinctrl-0 = <&vpfe1_pins_default>;
 953         pinctrl-1 = <&vpfe1_pins_sleep>;
 954
 955         port {
 956                 vpfe1_ep: endpoint {
 957                         remote-endpoint = <&ov2659_0>;
 958                         ti,am437x-vpfe-interface = <0>;
 959                         bus-width = <8>;
 960                         hsync-active = <0>;
 961                         vsync-active = <0>;
 962                 };
 963         };
 964 };
 965
 966 &mcasp1 {
 967         #sound-dai-cells = <0>;
 968         pinctrl-names = "default", "sleep";
 969         pinctrl-0 = <&mcasp1_pins>;
 970         pinctrl-1 = <&mcasp1_sleep_pins>;
 971
 972         status = "okay";
 973
 974         op-mode = <0>; /* MCASP_IIS_MODE */
 975         tdm-slots = <2>;
 976         /* 4 serializers */
 977         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 978                 0 0 1 2
 979         >;
 980         tx-num-evt = <32>;
 981         rx-num-evt = <32>;
 982 };
 983
 984 &rtc {
 985         clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
 986         clock-names = "ext-clk", "int-clk";
 987         status = "okay";
 988 };
 989
 990 &cpu {
 991         cpu0-supply = <&dcdc2>;
 992 };