arch/arm/boot/dts/am437x-gp-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM437x GP EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/pwm/pwm.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17
  18 / {
  19         model = "TI AM437x GP EVM";
  20         compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  21
  22         aliases {
  23                 display0 = &lcd0;
  24                 serial3 = &uart3;
  25         };
  26
  27         vmmcsd_fixed: fixedregulator-sd {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "vmmcsd_fixed";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32                 enable-active-high;
  33         };
  34
  35         vtt_fixed: fixedregulator-vtt {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "vtt_fixed";
  38                 regulator-min-microvolt = <1500000>;
  39                 regulator-max-microvolt = <1500000>;
  40                 regulator-always-on;
  41                 regulator-boot-on;
  42                 enable-active-high;
  43                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  44         };
  45
  46         vmmcwl_fixed: fixedregulator-mmcwl {
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "vmmcwl_fixed";
  49                 regulator-min-microvolt = <1800000>;
  50                 regulator-max-microvolt = <1800000>;
  51                 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  52                 enable-active-high;
  53         };
  54
  55         backlight {
  56                 compatible = "pwm-backlight";
  57                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  58                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
  59                 default-brightness-level = <8>;
  60         };
  61
  62         matrix_keypad: matrix_keypad@0 {
  63                 compatible = "gpio-matrix-keypad";
  64                 debounce-delay-ms = <5>;
  65                 col-scan-delay-us = <2>;
  66
  67                 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
  68                                 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  69                                 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  70
  71                 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  72                                 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  73
  74                 linux,keymap = <0x00000201      /* P1 */
  75                                 0x00010202      /* P2 */
  76                                 0x01000067      /* UP */
  77                                 0x0101006a      /* RIGHT */
  78                                 0x02000069      /* LEFT */
  79                                 0x0201006c>;      /* DOWN */
  80                 };
  81
  82         lcd0: display {
  83                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  84                 label = "lcd";
  85
  86                 pinctrl-names = "default";
  87                 pinctrl-0 = <&lcd_pins>;
  88
  89                 /*
  90                  * SelLCDorHDMI, LOW to select HDMI. This is not really the
  91                  * panel's enable GPIO, but we don't have HDMI driver support nor
  92                  * support to switch between two displays, so using this gpio as
  93                  * panel's enable should be safe.
  94                  */
  95                 enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
  96
  97                 panel-timing {
  98                         clock-frequency = <33000000>;
  99                         hactive = <800>;
 100                         vactive = <480>;
 101                         hfront-porch = <210>;
 102                         hback-porch = <16>;
 103                         hsync-len = <30>;
 104                         vback-porch = <10>;
 105                         vfront-porch = <22>;
 106                         vsync-len = <13>;
 107                         hsync-active = <0>;
 108                         vsync-active = <0>;
 109                         de-active = <1>;
 110                         pixelclk-active = <1>;
 111                 };
 112
 113                 port {
 114                         lcd_in: endpoint {
 115                                 remote-endpoint = <&dpi_out>;
 116                         };
 117                 };
 118         };
 119
 120         /* fixed 12MHz oscillator */
 121         refclk: oscillator {
 122                 #clock-cells = <0>;
 123                 compatible = "fixed-clock";
 124                 clock-frequency = <12000000>;
 125         };
 126
 127 };
 128
 129 &am43xx_pinmux {
 130         pinctrl-names = "default", "sleep";
 131         pinctrl-0 = <&wlan_pins_default>;
 132         pinctrl-1 = <&wlan_pins_sleep>;
 133
 134         i2c0_pins: i2c0_pins {
 135                 pinctrl-single,pins = <
 136                         0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
 137                         0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 138                 >;
 139         };
 140
 141         i2c1_pins: i2c1_pins {
 142                 pinctrl-single,pins = <
 143                         0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
 144                         0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 145                 >;
 146         };
 147
 148         mmc1_pins: pinmux_mmc1_pins {
 149                 pinctrl-single,pins = <
 150                         0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 151                 >;
 152         };
 153
 154         ecap0_pins: backlight_pins {
 155                 pinctrl-single,pins = <
 156                         0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 157                 >;
 158         };
 159
 160         pixcir_ts_pins: pixcir_ts_pins {
 161                 pinctrl-single,pins = <
 162                         0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
 163                 >;
 164         };
 165
 166         cpsw_default: cpsw_default {
 167                 pinctrl-single,pins = <
 168                         /* Slave 1 */
 169                         0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
 170                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rxctl */
 171                         0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
 172                         0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
 173                         0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
 174                         0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
 175                         0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
 176                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
 177                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd3 */
 178                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd2 */
 179                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
 180                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
 181                 >;
 182         };
 183
 184         cpsw_sleep: cpsw_sleep {
 185                 pinctrl-single,pins = <
 186                         /* Slave 1 reset value */
 187                         0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 188                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 189                         0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 190                         0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 191                         0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 192                         0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 193                         0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 194                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 195                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 196                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 197                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 198                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 199                 >;
 200         };
 201
 202         davinci_mdio_default: davinci_mdio_default {
 203                 pinctrl-single,pins = <
 204                         /* MDIO */
 205                         0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 206                         0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 207                 >;
 208         };
 209
 210         davinci_mdio_sleep: davinci_mdio_sleep {
 211                 pinctrl-single,pins = <
 212                         /* MDIO reset value */
 213                         0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 214                         0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 215                 >;
 216         };
 217
 218         nand_flash_x8: nand_flash_x8 {
 219                 pinctrl-single,pins = <
 220                         0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* spi2_cs0.gpio/eMMCorNANDsel */
 221                         0x0  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
 222                         0x4  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
 223                         0x8  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
 224                         0xc  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
 225                         0x10 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
 226                         0x14 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
 227                         0x18 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
 228                         0x1c (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
 229                         0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 230                         0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
 231                         0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 232                         0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 233                         0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 234                         0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 235                         0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 236                 >;
 237         };
 238
 239         dss_pins: dss_pins {
 240                 pinctrl-single,pins = <
 241                         0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 242                         0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 243                         0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 244                         0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
 245                         0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 246                         0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 247                         0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 248                         0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 249                         0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 250                         0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 251                         0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 252                         0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
 253                         0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 254                         0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 255                         0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 256                         0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
 257                         0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 258                         0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 259                         0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 260                         0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
 261                         0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 262                         0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 263                         0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 264                         0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 265                         0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 266                         0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 267                         0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 268                         0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 269
 270                 >;
 271         };
 272
 273         lcd_pins: lcd_pins {
 274                 pinctrl-single,pins = <
 275                         /* GPIO 5_8 to select LCD / HDMI */
 276                         0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
 277                 >;
 278         };
 279
 280         dcan0_default: dcan0_default_pins {
 281                 pinctrl-single,pins = <
 282                         0x178 (PIN_OUTPUT | MUX_MODE2)          /* uart1_ctsn.d_can0_tx */
 283                         0x17c (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
 284                 >;
 285         };
 286
 287         dcan1_default: dcan1_default_pins {
 288                 pinctrl-single,pins = <
 289                         0x180 (PIN_OUTPUT | MUX_MODE2)          /* uart1_rxd.d_can1_tx */
 290                         0x184 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_txd.d_can1_rx */
 291                 >;
 292         };
 293
 294         vpfe0_pins_default: vpfe0_pins_default {
 295                 pinctrl-single,pins = <
 296                         0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
 297                         0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
 298                         0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
 299                         0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
 300                         0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
 301                         0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
 302                         0x20C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
 303                         0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
 304                         0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
 305                         0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
 306                         0x21C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
 307                         0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
 308                         0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
 309                 >;
 310         };
 311
 312         vpfe0_pins_sleep: vpfe0_pins_sleep {
 313                 pinctrl-single,pins = <
 314                         0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
 315                         0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
 316                         0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
 317                         0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
 318                         0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
 319                         0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
 320                         0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
 321                         0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
 322                         0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
 323                         0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
 324                         0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
 325                         0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
 326                         0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
 327                 >;
 328         };
 329
 330         vpfe1_pins_default: vpfe1_pins_default {
 331                 pinctrl-single,pins = <
 332                         0x1CC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
 333                         0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
 334                         0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
 335                         0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
 336                         0x1DC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
 337                         0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
 338                         0x1EC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
 339                         0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
 340                         0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
 341                         0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
 342                         0x1FC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
 343                         0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
 344                         0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
 345                 >;
 346         };
 347
 348         vpfe1_pins_sleep: vpfe1_pins_sleep {
 349                 pinctrl-single,pins = <
 350                         0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
 351                         0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
 352                         0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
 353                         0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
 354                         0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
 355                         0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
 356                         0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
 357                         0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
 358                         0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
 359                         0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
 360                         0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
 361                         0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
 362                         0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
 363                 >;
 364         };
 365
 366         mmc3_pins_default: pinmux_mmc3_pins_default {
 367                 pinctrl-single,pins = <
 368                         0x8c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
 369                         0x88 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
 370                         0x44 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
 371                         0x48 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
 372                         0x4c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
 373                         0x78 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
 374                 >;
 375         };
 376
 377         mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
 378                 pinctrl-single,pins = <
 379                         0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_clk.mmc2_clk */
 380                         0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_csn3.mmc2_cmd */
 381                         0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a1.mmc2_dat0 */
 382                         0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a2.mmc2_dat1 */
 383                         0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a3.mmc2_dat2 */
 384                         0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_be1n.mmc2_dat3 */
 385                 >;
 386         };
 387
 388         wlan_pins_default: pinmux_wlan_pins_default {
 389                 pinctrl-single,pins = <
 390                         0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
 391                         0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
 392                         0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a0.gpio1_16 BT_EN*/
 393                 >;
 394         };
 395
 396         wlan_pins_sleep: pinmux_wlan_pins_sleep {
 397                 pinctrl-single,pins = <
 398                         0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
 399                         0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
 400                         0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
 401                 >;
 402         };
 403
 404         uart3_pins: uart3_pins {
 405                 pinctrl-single,pins = <
 406                         0x228 (PIN_INPUT | MUX_MODE0)           /* uart3_rxd.uart3_rxd */
 407                         0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
 408                         0x230 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart3_ctsn.uart3_ctsn */
 409                         0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
 410                 >;
 411         };
 412 };
 413
 414 &i2c0 {
 415         status = "okay";
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&i2c0_pins>;
 418         clock-frequency = <100000>;
 419
 420         tps65218: tps65218@24 {
 421                 reg = <0x24>;
 422                 compatible = "ti,tps65218";
 423                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
 424                 interrupt-controller;
 425                 #interrupt-cells = <2>;
 426
 427                 dcdc1: regulator-dcdc1 {
 428                         compatible = "ti,tps65218-dcdc1";
 429                         regulator-name = "vdd_core";
 430                         regulator-min-microvolt = <912000>;
 431                         regulator-max-microvolt = <1144000>;
 432                         regulator-boot-on;
 433                         regulator-always-on;
 434                 };
 435
 436                 dcdc2: regulator-dcdc2 {
 437                         compatible = "ti,tps65218-dcdc2";
 438                         regulator-name = "vdd_mpu";
 439                         regulator-min-microvolt = <912000>;
 440                         regulator-max-microvolt = <1378000>;
 441                         regulator-boot-on;
 442                         regulator-always-on;
 443                 };
 444
 445                 dcdc3: regulator-dcdc3 {
 446                         compatible = "ti,tps65218-dcdc3";
 447                         regulator-name = "vdcdc3";
 448                         regulator-min-microvolt = <1500000>;
 449                         regulator-max-microvolt = <1500000>;
 450                         regulator-boot-on;
 451                         regulator-always-on;
 452                 };
 453                 dcdc5: regulator-dcdc5 {
 454                         compatible = "ti,tps65218-dcdc5";
 455                         regulator-name = "v1_0bat";
 456                         regulator-min-microvolt = <1000000>;
 457                         regulator-max-microvolt = <1000000>;
 458                 };
 459
 460                 dcdc6: regulator-dcdc6 {
 461                         compatible = "ti,tps65218-dcdc6";
 462                         regulator-name = "v1_8bat";
 463                         regulator-min-microvolt = <1800000>;
 464                         regulator-max-microvolt = <1800000>;
 465                 };
 466
 467                 ldo1: regulator-ldo1 {
 468                         compatible = "ti,tps65218-ldo1";
 469                         regulator-min-microvolt = <1800000>;
 470                         regulator-max-microvolt = <1800000>;
 471                         regulator-boot-on;
 472                         regulator-always-on;
 473                 };
 474         };
 475
 476         ov2659@30 {
 477                 compatible = "ovti,ov2659";
 478                 reg = <0x30>;
 479
 480                 clocks = <&refclk 0>;
 481                 clock-names = "xvclk";
 482
 483                 port {
 484                         ov2659_0: endpoint {
 485                                 remote-endpoint = <&vpfe1_ep>;
 486                                 link-frequencies = /bits/ 64 <70000000>;
 487                         };
 488                 };
 489         };
 490 };
 491
 492 &i2c1 {
 493         status = "okay";
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&i2c1_pins>;
 496         pixcir_ts@5c {
 497                 compatible = "pixcir,pixcir_tangoc";
 498                 pinctrl-names = "default";
 499                 pinctrl-0 = <&pixcir_ts_pins>;
 500                 reg = <0x5c>;
 501                 interrupt-parent = <&gpio3>;
 502                 interrupts = <22 0>;
 503
 504                 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 505
 506                 touchscreen-size-x = <1024>;
 507                 touchscreen-size-y = <600>;
 508         };
 509
 510         ov2659@30 {
 511                 compatible = "ovti,ov2659";
 512                 reg = <0x30>;
 513
 514                 clocks = <&refclk 0>;
 515                 clock-names = "xvclk";
 516
 517                 port {
 518                         ov2659_1: endpoint {
 519                                 remote-endpoint = <&vpfe0_ep>;
 520                                 link-frequencies = /bits/ 64 <70000000>;
 521                         };
 522                 };
 523         };
 524 };
 525
 526 &epwmss0 {
 527         status = "okay";
 528 };
 529
 530 &tscadc {
 531         status = "okay";
 532
 533         adc {
 534                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 535         };
 536 };
 537
 538 &ecap0 {
 539         status = "okay";
 540         pinctrl-names = "default";
 541         pinctrl-0 = <&ecap0_pins>;
 542 };
 543
 544 &gpio0 {
 545         status = "okay";
 546 };
 547
 548 &gpio1 {
 549         status = "okay";
 550 };
 551
 552 &gpio3 {
 553         status = "okay";
 554 };
 555
 556 &gpio4 {
 557         status = "okay";
 558 };
 559
 560 &gpio5 {
 561         status = "okay";
 562         ti,no-reset-on-init;
 563 };
 564
 565 &mmc1 {
 566         status = "okay";
 567         vmmc-supply = <&vmmcsd_fixed>;
 568         bus-width = <4>;
 569         pinctrl-names = "default";
 570         pinctrl-0 = <&mmc1_pins>;
 571         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 572 };
 573
 574 &mmc3 {
 575         status = "okay";
 576         /* these are on the crossbar and are outlined in the
 577            xbar-event-map element */
 578         dmas = <&edma 30
 579                 &edma 31>;
 580         dma-names = "tx", "rx";
 581         vmmc-supply = <&vmmcwl_fixed>;
 582         bus-width = <4>;
 583         pinctrl-names = "default", "sleep";
 584         pinctrl-0 = <&mmc3_pins_default>;
 585         pinctrl-1 = <&mmc3_pins_sleep>;
 586         cap-power-off-card;
 587         keep-power-in-suspend;
 588         ti,non-removable;
 589
 590         #address-cells = <1>;
 591         #size-cells = <0>;
 592         wlcore: wlcore@0 {
 593                 compatible = "ti,wl1835";
 594                 reg = <2>;
 595                 interrupt-parent = <&gpio1>;
 596                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
 597         };
 598 };
 599
 600 &edma {
 601         ti,edma-xbar-event-map = /bits/ 16 <1 30
 602                                             2 31>;
 603 };
 604
 605 &uart3 {
 606         status = "okay";
 607         pinctrl-names = "default";
 608         pinctrl-0 = <&uart3_pins>;
 609 };
 610
 611 &usb2_phy1 {
 612         status = "okay";
 613 };
 614
 615 &usb1 {
 616         dr_mode = "peripheral";
 617         status = "okay";
 618 };
 619
 620 &usb2_phy2 {
 621         status = "okay";
 622 };
 623
 624 &usb2 {
 625         dr_mode = "host";
 626         status = "okay";
 627 };
 628
 629 &mac {
 630         slaves = <1>;
 631         pinctrl-names = "default", "sleep";
 632         pinctrl-0 = <&cpsw_default>;
 633         pinctrl-1 = <&cpsw_sleep>;
 634         status = "okay";
 635 };
 636
 637 &davinci_mdio {
 638         pinctrl-names = "default", "sleep";
 639         pinctrl-0 = <&davinci_mdio_default>;
 640         pinctrl-1 = <&davinci_mdio_sleep>;
 641         status = "okay";
 642 };
 643
 644 &cpsw_emac0 {
 645         phy_id = <&davinci_mdio>, <0>;
 646         phy-mode = "rgmii";
 647 };
 648
 649 &elm {
 650         status = "okay";
 651 };
 652
 653 &gpmc {
 654         status = "okay";
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&nand_flash_x8>;
 657         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 658         nand@0,0 {
 659                 reg = <0 0 4>;          /* device IO registers */
 660                 ti,nand-ecc-opt = "bch16";
 661                 ti,elm-id = <&elm>;
 662                 nand-bus-width = <8>;
 663                 gpmc,device-width = <1>;
 664                 gpmc,sync-clk-ps = <0>;
 665                 gpmc,cs-on-ns = <0>;
 666                 gpmc,cs-rd-off-ns = <40>;
 667                 gpmc,cs-wr-off-ns = <40>;
 668                 gpmc,adv-on-ns = <0>;
 669                 gpmc,adv-rd-off-ns = <25>;
 670                 gpmc,adv-wr-off-ns = <25>;
 671                 gpmc,we-on-ns = <0>;
 672                 gpmc,we-off-ns = <20>;
 673                 gpmc,oe-on-ns = <3>;
 674                 gpmc,oe-off-ns = <30>;
 675                 gpmc,access-ns = <30>;
 676                 gpmc,rd-cycle-ns = <40>;
 677                 gpmc,wr-cycle-ns = <40>;
 678                 gpmc,wait-pin = <0>;
 679                 gpmc,bus-turnaround-ns = <0>;
 680                 gpmc,cycle2cycle-delay-ns = <0>;
 681                 gpmc,clk-activation-ns = <0>;
 682                 gpmc,wait-monitoring-ns = <0>;
 683                 gpmc,wr-access-ns = <40>;
 684                 gpmc,wr-data-mux-bus-ns = <0>;
 685                 /* MTD partition table */
 686                 /* All SPL-* partitions are sized to minimal length
 687                  * which can be independently programmable. For
 688                  * NAND flash this is equal to size of erase-block */
 689                 #address-cells = <1>;
 690                 #size-cells = <1>;
 691                 partition@0 {
 692                         label = "NAND.SPL";
 693                         reg = <0x00000000 0x00040000>;
 694                 };
 695                 partition@1 {
 696                         label = "NAND.SPL.backup1";
 697                         reg = <0x00040000 0x00040000>;
 698                 };
 699                 partition@2 {
 700                         label = "NAND.SPL.backup2";
 701                         reg = <0x00080000 0x00040000>;
 702                 };
 703                 partition@3 {
 704                         label = "NAND.SPL.backup3";
 705                         reg = <0x000c0000 0x00040000>;
 706                 };
 707                 partition@4 {
 708                         label = "NAND.u-boot-spl-os";
 709                         reg = <0x00100000 0x00080000>;
 710                 };
 711                 partition@5 {
 712                         label = "NAND.u-boot";
 713                         reg = <0x00180000 0x00100000>;
 714                 };
 715                 partition@6 {
 716                         label = "NAND.u-boot-env";
 717                         reg = <0x00280000 0x00040000>;
 718                 };
 719                 partition@7 {
 720                         label = "NAND.u-boot-env.backup1";
 721                         reg = <0x002c0000 0x00040000>;
 722                 };
 723                 partition@8 {
 724                         label = "NAND.kernel";
 725                         reg = <0x00300000 0x00700000>;
 726                 };
 727                 partition@9 {
 728                         label = "NAND.file-system";
 729                         reg = <0x00a00000 0x1f600000>;
 730                 };
 731         };
 732 };
 733
 734 &dss {
 735         status = "ok";
 736
 737         pinctrl-names = "default";
 738         pinctrl-0 = <&dss_pins>;
 739
 740         port {
 741                 dpi_out: endpoint@0 {
 742                         remote-endpoint = <&lcd_in>;
 743                         data-lines = <24>;
 744                 };
 745         };
 746 };
 747
 748 &dcan0 {
 749         pinctrl-names = "default";
 750         pinctrl-0 = <&dcan0_default>;
 751         status = "okay";
 752 };
 753
 754 &dcan1 {
 755         pinctrl-names = "default";
 756         pinctrl-0 = <&dcan1_default>;
 757         status = "okay";
 758 };
 759
 760 &vpfe0 {
 761         status = "okay";
 762         pinctrl-names = "default", "sleep";
 763         pinctrl-0 = <&vpfe0_pins_default>;
 764         pinctrl-1 = <&vpfe0_pins_sleep>;
 765
 766         port {
 767                 vpfe0_ep: endpoint {
 768                         remote-endpoint = <&ov2659_1>;
 769                         ti,am437x-vpfe-interface = <0>;
 770                         bus-width = <8>;
 771                         hsync-active = <0>;
 772                         vsync-active = <0>;
 773                 };
 774         };
 775 };
 776
 777 &vpfe1 {
 778         status = "okay";
 779         pinctrl-names = "default", "sleep";
 780         pinctrl-0 = <&vpfe1_pins_default>;
 781         pinctrl-1 = <&vpfe1_pins_sleep>;
 782
 783         port {
 784                 vpfe1_ep: endpoint {
 785                         remote-endpoint = <&ov2659_0>;
 786                         ti,am437x-vpfe-interface = <0>;
 787                         bus-width = <8>;
 788                         hsync-active = <0>;
 789                         vsync-active = <0>;
 790                 };
 791         };
 792 };