2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
13 #include "am4372.dtsi"
14 #include <dt-bindings/pinctrl/am43xx.h>
15 #include <dt-bindings/pwm/pwm.h>
16 #include <dt-bindings/gpio/gpio.h>
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
26 vmmcsd_fixed: fixedregulator-sd {
27 compatible = "regulator-fixed";
28 regulator-name = "vmmcsd_fixed";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
34 vtt_fixed: fixedregulator-vtt {
35 compatible = "regulator-fixed";
36 regulator-name = "vtt_fixed";
37 regulator-min-microvolt = <1500000>;
38 regulator-max-microvolt = <1500000>;
42 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
46 compatible = "pwm-backlight";
47 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
48 brightness-levels = <0 51 53 56 62 75 101 152 255>;
49 default-brightness-level = <8>;
52 matrix_keypad: matrix_keypad@0 {
53 compatible = "gpio-matrix-keypad";
54 debounce-delay-ms = <5>;
55 col-scan-delay-us = <2>;
57 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
58 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
59 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
61 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
62 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
64 linux,keymap = <0x00000201 /* P1 */
67 0x0101006a /* RIGHT */
69 0x0201006c>; /* DOWN */
73 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
76 pinctrl-names = "default";
77 pinctrl-0 = <&lcd_pins>;
80 * SelLCDorHDMI, LOW to select HDMI. This is not really the
81 * panel's enable GPIO, but we don't have HDMI driver support nor
82 * support to switch between two displays, so using this gpio as
83 * panel's enable should be safe.
85 enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
88 clock-frequency = <33000000>;
100 pixelclk-active = <1>;
105 remote-endpoint = <&dpi_out>;
112 i2c0_pins: i2c0_pins {
113 pinctrl-single,pins = <
114 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
115 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
119 i2c1_pins: i2c1_pins {
120 pinctrl-single,pins = <
121 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
122 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
126 mmc1_pins: pinmux_mmc1_pins {
127 pinctrl-single,pins = <
128 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
132 ecap0_pins: backlight_pins {
133 pinctrl-single,pins = <
134 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
138 pixcir_ts_pins: pixcir_ts_pins {
139 pinctrl-single,pins = <
140 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
144 cpsw_default: cpsw_default {
145 pinctrl-single,pins = <
147 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
148 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
149 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
150 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
151 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
152 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
153 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
154 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
155 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
156 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
157 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
158 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
162 cpsw_sleep: cpsw_sleep {
163 pinctrl-single,pins = <
164 /* Slave 1 reset value */
165 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
166 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
167 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
168 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
169 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
170 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
171 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
172 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
173 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
174 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
175 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
176 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
180 davinci_mdio_default: davinci_mdio_default {
181 pinctrl-single,pins = <
183 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
184 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
188 davinci_mdio_sleep: davinci_mdio_sleep {
189 pinctrl-single,pins = <
190 /* MDIO reset value */
191 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
192 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
196 nand_flash_x8: nand_flash_x8 {
197 pinctrl-single,pins = <
198 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
199 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
200 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
201 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
202 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
203 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
204 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
205 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
206 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
207 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
208 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
209 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
210 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
211 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
212 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
213 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
218 pinctrl-single,pins = <
219 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
220 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
221 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
222 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
223 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
224 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
225 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
226 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
227 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
228 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
229 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
230 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
231 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
232 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
233 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
234 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
235 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
236 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
237 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
238 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
239 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
240 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
241 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
242 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
243 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
244 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
245 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
246 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
252 pinctrl-single,pins = <
253 /* GPIO 5_8 to select LCD / HDMI */
254 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
258 dcan0_default: dcan0_default_pins {
259 pinctrl-single,pins = <
260 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
261 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
265 dcan1_default: dcan1_default_pins {
266 pinctrl-single,pins = <
267 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
268 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
272 vpfe0_pins_default: vpfe0_pins_default {
273 pinctrl-single,pins = <
274 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
275 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
276 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
277 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
278 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
279 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
280 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
281 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
282 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
283 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
284 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
285 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
286 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
290 vpfe0_pins_sleep: vpfe0_pins_sleep {
291 pinctrl-single,pins = <
292 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
293 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
294 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
295 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
296 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
297 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
298 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
299 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
300 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
301 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
302 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
303 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
304 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
308 vpfe1_pins_default: vpfe1_pins_default {
309 pinctrl-single,pins = <
310 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
311 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
312 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
313 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
314 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
315 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
316 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
317 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
318 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
319 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
320 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
321 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
322 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
326 vpfe1_pins_sleep: vpfe1_pins_sleep {
327 pinctrl-single,pins = <
328 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
329 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
330 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
331 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
332 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
333 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
334 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
335 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
336 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
337 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
338 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
339 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
340 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c0_pins>;
349 clock-frequency = <100000>;
351 tps65218: tps65218@24 {
353 compatible = "ti,tps65218";
354 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
355 interrupt-controller;
356 #interrupt-cells = <2>;
358 dcdc1: regulator-dcdc1 {
359 compatible = "ti,tps65218-dcdc1";
360 regulator-name = "vdd_core";
361 regulator-min-microvolt = <912000>;
362 regulator-max-microvolt = <1144000>;
367 dcdc2: regulator-dcdc2 {
368 compatible = "ti,tps65218-dcdc2";
369 regulator-name = "vdd_mpu";
370 regulator-min-microvolt = <912000>;
371 regulator-max-microvolt = <1378000>;
376 dcdc3: regulator-dcdc3 {
377 compatible = "ti,tps65218-dcdc3";
378 regulator-name = "vdcdc3";
379 regulator-min-microvolt = <1500000>;
380 regulator-max-microvolt = <1500000>;
384 dcdc5: regulator-dcdc5 {
385 compatible = "ti,tps65218-dcdc5";
386 regulator-name = "v1_0bat";
387 regulator-min-microvolt = <1000000>;
388 regulator-max-microvolt = <1000000>;
391 dcdc6: regulator-dcdc6 {
392 compatible = "ti,tps65218-dcdc6";
393 regulator-name = "v1_8bat";
394 regulator-min-microvolt = <1800000>;
395 regulator-max-microvolt = <1800000>;
398 ldo1: regulator-ldo1 {
399 compatible = "ti,tps65218-ldo1";
400 regulator-min-microvolt = <1800000>;
401 regulator-max-microvolt = <1800000>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2c1_pins>;
413 compatible = "pixcir,pixcir_tangoc";
414 pinctrl-names = "default";
415 pinctrl-0 = <&pixcir_ts_pins>;
417 interrupt-parent = <&gpio3>;
420 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
422 touchscreen-size-x = <1024>;
423 touchscreen-size-y = <600>;
435 ti,adc-channels = <0 1 2 3 4 5 6 7>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&ecap0_pins>;
464 vmmc-supply = <&vmmcsd_fixed>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&mmc1_pins>;
468 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
476 dr_mode = "peripheral";
491 pinctrl-names = "default", "sleep";
492 pinctrl-0 = <&cpsw_default>;
493 pinctrl-1 = <&cpsw_sleep>;
498 pinctrl-names = "default", "sleep";
499 pinctrl-0 = <&davinci_mdio_default>;
500 pinctrl-1 = <&davinci_mdio_sleep>;
505 phy_id = <&davinci_mdio>, <0>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&nand_flash_x8>;
517 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
519 reg = <0 0 4>; /* device IO registers */
520 ti,nand-ecc-opt = "bch16";
522 nand-bus-width = <8>;
523 gpmc,device-width = <1>;
524 gpmc,sync-clk-ps = <0>;
526 gpmc,cs-rd-off-ns = <40>;
527 gpmc,cs-wr-off-ns = <40>;
528 gpmc,adv-on-ns = <0>;
529 gpmc,adv-rd-off-ns = <25>;
530 gpmc,adv-wr-off-ns = <25>;
532 gpmc,we-off-ns = <20>;
534 gpmc,oe-off-ns = <30>;
535 gpmc,access-ns = <30>;
536 gpmc,rd-cycle-ns = <40>;
537 gpmc,wr-cycle-ns = <40>;
539 gpmc,bus-turnaround-ns = <0>;
540 gpmc,cycle2cycle-delay-ns = <0>;
541 gpmc,clk-activation-ns = <0>;
542 gpmc,wait-monitoring-ns = <0>;
543 gpmc,wr-access-ns = <40>;
544 gpmc,wr-data-mux-bus-ns = <0>;
545 /* MTD partition table */
546 /* All SPL-* partitions are sized to minimal length
547 * which can be independently programmable. For
548 * NAND flash this is equal to size of erase-block */
549 #address-cells = <1>;
553 reg = <0x00000000 0x00040000>;
556 label = "NAND.SPL.backup1";
557 reg = <0x00040000 0x00040000>;
560 label = "NAND.SPL.backup2";
561 reg = <0x00080000 0x00040000>;
564 label = "NAND.SPL.backup3";
565 reg = <0x000c0000 0x00040000>;
568 label = "NAND.u-boot-spl-os";
569 reg = <0x00100000 0x00080000>;
572 label = "NAND.u-boot";
573 reg = <0x00180000 0x00100000>;
576 label = "NAND.u-boot-env";
577 reg = <0x00280000 0x00040000>;
580 label = "NAND.u-boot-env.backup1";
581 reg = <0x002c0000 0x00040000>;
584 label = "NAND.kernel";
585 reg = <0x00300000 0x00700000>;
588 label = "NAND.file-system";
589 reg = <0x00a00000 0x1f600000>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&dss_pins>;
601 dpi_out: endpoint@0 {
602 remote-endpoint = <&lcd_in>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&dcan0_default>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&dcan1_default>;
622 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&vpfe0_pins_default>;
624 pinctrl-1 = <&vpfe0_pins_sleep>;
628 /* remote-endpoint = <&sensor>; add once we have it */
629 ti,am437x-vpfe-interface = <0>;
639 pinctrl-names = "default", "sleep";
640 pinctrl-0 = <&vpfe1_pins_default>;
641 pinctrl-1 = <&vpfe1_pins_sleep>;
645 /* remote-endpoint = <&sensor>; add once we have it */
646 ti,am437x-vpfe-interface = <0>;