arch/arm/boot/dts/arm-realview-eb.dts

   1 /*
   2  * Copyright 2016 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 /dts-v1/;
  24 #include <dt-bindings/interrupt-controller/irq.h>
  25 #include <dt-bindings/gpio/gpio.h>
  26 #include "arm-realview-eb.dtsi"
  27
  28 / {
  29         model = "ARM RealView Emulation Baseboard";
  30         compatible = "arm,realview-eb";
  31         arm,hbi = <0x140>;
  32
  33         /*
  34          * This is the core tile with the CPU and GIC etc for the
  35          * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
  36          * or PMU.
  37          *
  38          * To run this machine with QEMU, specify the following:
  39          * qemu-system-arm -M realview-eb
  40          * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
  41          * Switches -cpu arm1136 or -cpu arm1176 emulates the other
  42          * core tiles.
  43          */
  44         soc {
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 compatible = "arm,realview-eb-soc", "simple-bus";
  48                 regmap = <&syscon>;
  49                 ranges;
  50
  51                 intc: interrupt-controller@10040000 {
  52                         compatible = "arm,pl390";
  53                         #interrupt-cells = <3>;
  54                         #address-cells = <1>;
  55                         interrupt-controller;
  56                         reg = <0x10041000 0x1000>,
  57                               <0x10040000 0x100>;
  58                 };
  59         };
  60 };
  61
  62 /*
  63  * This adapts all the peripherals to the interrupt routing
  64  * to the GIC on the core tile.
  65  */
  66
  67 &ethernet {
  68         interrupt-parent = <&intc>;
  69         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
  70 };
  71
  72 &usb {
  73         interrupt-parent = <&intc>;
  74         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
  75 };
  76
  77 &aaci {
  78         interrupt-parent = <&intc>;
  79         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
  80 };
  81
  82 &mmc {
  83         interrupt-parent = <&intc>;
  84         interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
  85                         <0 18 IRQ_TYPE_LEVEL_HIGH>;
  86 };
  87
  88 &kmi0 {
  89         interrupt-parent = <&intc>;
  90         interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
  91 };
  92
  93 &kmi1 {
  94         interrupt-parent = <&intc>;
  95         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
  96 };
  97
  98 &charlcd {
  99         interrupt-parent = <&intc>;
 100         interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 101 };
 102
 103 &serial0 {
 104         interrupt-parent = <&intc>;
 105         interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
 106 };
 107
 108 &serial1 {
 109         interrupt-parent = <&intc>;
 110         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 111 };
 112
 113 &serial2 {
 114         interrupt-parent = <&intc>;
 115         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 116 };
 117
 118 &serial3 {
 119         interrupt-parent = <&intc>;
 120         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 121 };
 122
 123 &ssp {
 124         interrupt-parent = <&intc>;
 125         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 126 };
 127
 128 &wdog {
 129         interrupt-parent = <&intc>;
 130         interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
 131 };
 132
 133 &timer01 {
 134         interrupt-parent = <&intc>;
 135         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 136 };
 137
 138 &timer23 {
 139         interrupt-parent = <&intc>;
 140         interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 141 };
 142
 143 &gpio0 {
 144         interrupt-parent = <&intc>;
 145         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 146 };
 147
 148 &gpio1 {
 149         interrupt-parent = <&intc>;
 150         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 151 };
 152
 153 &gpio2 {
 154         interrupt-parent = <&intc>;
 155         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 156 };
 157
 158 &rtc {
 159         interrupt-parent = <&intc>;
 160         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 161 };
 162
 163 &clcd {
 164         interrupt-parent = <&intc>;
 165         interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 166 };