arch/arm/boot/dts/arm-realview-eb.dtsi

   1 /*
   2  * Copyright 2016 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include <dt-bindings/interrupt-controller/irq.h>
  24 #include <dt-bindings/gpio/gpio.h>
  25 #include "skeleton.dtsi"
  26
  27 / {
  28         compatible = "arm,realview-eb";
  29
  30         chosen { };
  31
  32         aliases {
  33                 serial0 = &serial0;
  34                 serial1 = &serial1;
  35                 serial2 = &serial2;
  36                 serial3 = &serial3;
  37                 i2c0 = &i2c;
  38         };
  39
  40         memory {
  41                 /* 128 MiB memory @ 0x0 */
  42                 reg = <0x00000000 0x08000000>;
  43         };
  44
  45         /* The voltage to the MMC card is hardwired at 3.3V */
  46         vmmc: fixedregulator@0 {
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "vmmc";
  49                 regulator-min-microvolt = <3300000>;
  50                 regulator-max-microvolt = <3300000>;
  51                 regulator-boot-on;
  52         };
  53
  54         xtal24mhz: xtal24mhz@24M {
  55                 #clock-cells = <0>;
  56                 compatible = "fixed-clock";
  57                 clock-frequency = <24000000>;
  58         };
  59
  60         timclk: timclk@1M {
  61                 #clock-cells = <0>;
  62                 compatible = "fixed-factor-clock";
  63                 clock-div = <24>;
  64                 clock-mult = <1>;
  65                 clocks = <&xtal24mhz>;
  66         };
  67
  68         mclk: mclk@24M {
  69                 #clock-cells = <0>;
  70                 compatible = "fixed-factor-clock";
  71                 clock-div = <1>;
  72                 clock-mult = <1>;
  73                 clocks = <&xtal24mhz>;
  74         };
  75
  76         kmiclk: kmiclk@24M {
  77                 #clock-cells = <0>;
  78                 compatible = "fixed-factor-clock";
  79                 clock-div = <1>;
  80                 clock-mult = <1>;
  81                 clocks = <&xtal24mhz>;
  82         };
  83
  84         sspclk: sspclk@24M {
  85                 #clock-cells = <0>;
  86                 compatible = "fixed-factor-clock";
  87                 clock-div = <1>;
  88                 clock-mult = <1>;
  89                 clocks = <&xtal24mhz>;
  90         };
  91
  92         uartclk: uartclk@24M {
  93                 #clock-cells = <0>;
  94                 compatible = "fixed-factor-clock";
  95                 clock-div = <1>;
  96                 clock-mult = <1>;
  97                 clocks = <&xtal24mhz>;
  98         };
  99
 100         wdogclk: wdogclk@24M {
 101                 #clock-cells = <0>;
 102                 compatible = "fixed-factor-clock";
 103                 clock-div = <1>;
 104                 clock-mult = <1>;
 105                 clocks = <&xtal24mhz>;
 106         };
 107
 108         /* FIXME: this actually hangs off the PLL clocks */
 109         pclk: pclk@0 {
 110                 #clock-cells = <0>;
 111                 compatible = "fixed-clock";
 112                 clock-frequency = <0>;
 113         };
 114
 115         flash0@40000000 {
 116                 /* 2 * 32MiB NOR Flash memory */
 117                 compatible = "arm,versatile-flash", "cfi-flash";
 118                 reg = <0x40000000 0x04000000>;
 119                 bank-width = <4>;
 120         };
 121
 122         flash1@44000000 {
 123                 /* 2 * 32MiB NOR Flash memory */
 124                 compatible = "arm,versatile-flash", "cfi-flash";
 125                 reg = <0x44000000 0x04000000>;
 126                 bank-width = <4>;
 127         };
 128
 129         /* SMSC LAN91C111 ethernet with PHY and EEPROM */
 130         ethernet: ethernet@4e000000 {
 131                 compatible = "smsc,lan91c111";
 132                 reg = <0x4e000000 0x10000>;
 133                 /*
 134                  * This means the adapter can be accessed with 8, 16 or
 135                  * 32 bit reads/writes.
 136                  */
 137                 reg-io-width = <7>;
 138         };
 139
 140         usb: usb@4f000000 {
 141                 compatible = "nxp,usb-isp1761";
 142                 reg = <0x4f000000 0x20000>;
 143                 port1-otg;
 144         };
 145
 146         /* These peripherals are inside the FPGA */
 147         fpga {
 148                 #address-cells = <1>;
 149                 #size-cells = <1>;
 150                 compatible = "simple-bus";
 151                 ranges;
 152
 153                 syscon: syscon@10000000 {
 154                         compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
 155                         reg = <0x10000000 0x1000>;
 156
 157                         led@08.0 {
 158                                 compatible = "register-bit-led";
 159                                 offset = <0x08>;
 160                                 mask = <0x01>;
 161                                 label = "versatile:0";
 162                                 linux,default-trigger = "heartbeat";
 163                                 default-state = "on";
 164                         };
 165                         led@08.1 {
 166                                 compatible = "register-bit-led";
 167                                 offset = <0x08>;
 168                                 mask = <0x02>;
 169                                 label = "versatile:1";
 170                                 linux,default-trigger = "mmc0";
 171                                 default-state = "off";
 172                         };
 173                         led@08.2 {
 174                                 compatible = "register-bit-led";
 175                                 offset = <0x08>;
 176                                 mask = <0x04>;
 177                                 label = "versatile:2";
 178                                 linux,default-trigger = "cpu0";
 179                                 default-state = "off";
 180                         };
 181                         led@08.3 {
 182                                 compatible = "register-bit-led";
 183                                 offset = <0x08>;
 184                                 mask = <0x08>;
 185                                 label = "versatile:3";
 186                                 default-state = "off";
 187                         };
 188                         led@08.4 {
 189                                 compatible = "register-bit-led";
 190                                 offset = <0x08>;
 191                                 mask = <0x10>;
 192                                 label = "versatile:4";
 193                                 default-state = "off";
 194                         };
 195                         led@08.5 {
 196                                 compatible = "register-bit-led";
 197                                 offset = <0x08>;
 198                                 mask = <0x20>;
 199                                 label = "versatile:5";
 200                                 default-state = "off";
 201                         };
 202                         led@08.6 {
 203                                 compatible = "register-bit-led";
 204                                 offset = <0x08>;
 205                                 mask = <0x40>;
 206                                 label = "versatile:6";
 207                                 default-state = "off";
 208                         };
 209                         led@08.7 {
 210                                 compatible = "register-bit-led";
 211                                 offset = <0x08>;
 212                                 mask = <0x80>;
 213                                 label = "versatile:7";
 214                                 default-state = "off";
 215                         };
 216                         oscclk0: osc0@0c {
 217                                 compatible = "arm,syscon-icst307";
 218                                 #clock-cells = <0>;
 219                                 lock-offset = <0x20>;
 220                                 vco-offset = <0x0C>;
 221                                 clocks = <&xtal24mhz>;
 222                         };
 223                         oscclk1: osc1@10 {
 224                                 compatible = "arm,syscon-icst307";
 225                                 #clock-cells = <0>;
 226                                 lock-offset = <0x20>;
 227                                 vco-offset = <0x10>;
 228                                 clocks = <&xtal24mhz>;
 229                         };
 230                         oscclk2: osc2@14 {
 231                                 compatible = "arm,syscon-icst307";
 232                                 #clock-cells = <0>;
 233                                 lock-offset = <0x20>;
 234                                 vco-offset = <0x14>;
 235                                 clocks = <&xtal24mhz>;
 236                         };
 237                         oscclk3: osc3@18 {
 238                                 compatible = "arm,syscon-icst307";
 239                                 #clock-cells = <0>;
 240                                 lock-offset = <0x20>;
 241                                 vco-offset = <0x18>;
 242                                 clocks = <&xtal24mhz>;
 243                         };
 244                         oscclk4: osc4@1c {
 245                                 compatible = "arm,syscon-icst307";
 246                                 #clock-cells = <0>;
 247                                 lock-offset = <0x20>;
 248                                 vco-offset = <0x1c>;
 249                                 clocks = <&xtal24mhz>;
 250                         };
 251                 };
 252
 253                 i2c: i2c@10002000 {
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         compatible = "arm,versatile-i2c";
 257                         reg = <0x10002000 0x1000>;
 258
 259                         rtc@68 {
 260                                 compatible = "dallas,ds1338";
 261                                 reg = <0x68>;
 262                         };
 263                 };
 264
 265                 aaci: aaci@10004000 {
 266                         compatible = "arm,pl041", "arm,primecell";
 267                         reg = <0x10004000 0x1000>;
 268                         clocks = <&pclk>;
 269                         clock-names = "apb_pclk";
 270                 };
 271
 272                 mmc: mmcsd@10005000 {
 273                         compatible = "arm,pl18x", "arm,primecell";
 274                         reg = <0x10005000 0x1000>;
 275
 276                         /* Due to frequent FIFO overruns, use just 500 kHz */
 277                         max-frequency = <500000>;
 278                         bus-width = <4>;
 279                         cap-sd-highspeed;
 280                         cap-mmc-highspeed;
 281                         clocks = <&mclk>, <&pclk>;
 282                         clock-names = "mclk", "apb_pclk";
 283                         vmmc-supply = <&vmmc>;
 284                         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 285                         wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 286                 };
 287
 288                 kmi0: kmi@10006000 {
 289                         compatible = "arm,pl050", "arm,primecell";
 290                         reg = <0x10006000 0x1000>;
 291                         clocks = <&kmiclk>, <&pclk>;
 292                         clock-names = "KMIREFCLK", "apb_pclk";
 293                 };
 294
 295                 kmi1: kmi@10007000 {
 296                         compatible = "arm,pl050", "arm,primecell";
 297                         reg = <0x10007000 0x1000>;
 298                         clocks = <&kmiclk>, <&pclk>;
 299                         clock-names = "KMIREFCLK", "apb_pclk";
 300                 };
 301
 302                 charlcd: fpga_charlcd: charlcd@10008000 {
 303                         compatible = "arm,versatile-lcd";
 304                         reg = <0x10008000 0x1000>;
 305                         clocks = <&pclk>;
 306                         clock-names = "apb_pclk";
 307                 };
 308
 309                 serial0: serial@10009000 {
 310                         compatible = "arm,pl011", "arm,primecell";
 311                         reg = <0x10009000 0x1000>;
 312                         clocks = <&uartclk>, <&pclk>;
 313                         clock-names = "uartclk", "apb_pclk";
 314                 };
 315
 316                 serial1: serial@1000a000 {
 317                         compatible = "arm,pl011", "arm,primecell";
 318                         reg = <0x1000a000 0x1000>;
 319                         clocks = <&uartclk>, <&pclk>;
 320                         clock-names = "uartclk", "apb_pclk";
 321                 };
 322
 323                 serial2: serial@1000b000 {
 324                         compatible = "arm,pl011", "arm,primecell";
 325                         reg = <0x1000b000 0x1000>;
 326                         clocks = <&uartclk>, <&pclk>;
 327                         clock-names = "uartclk", "apb_pclk";
 328                 };
 329
 330                 serial3: serial@1000c000 {
 331                         compatible = "arm,pl011", "arm,primecell";
 332                         reg = <0x1000c000 0x1000>;
 333                         clocks = <&uartclk>, <&pclk>;
 334                         clock-names = "uartclk", "apb_pclk";
 335                 };
 336
 337                 ssp: ssp@1000d000 {
 338                         compatible = "arm,pl022", "arm,primecell";
 339                         reg = <0x1000d000 0x1000>;
 340                         clocks = <&sspclk>, <&pclk>;
 341                         clock-names = "SSPCLK", "apb_pclk";
 342                 };
 343
 344                 wdog: watchdog@10010000 {
 345                         compatible = "arm,sp805", "arm,primecell";
 346                         reg = <0x10010000 0x1000>;
 347                         clocks = <&wdogclk>, <&pclk>;
 348                         clock-names = "wdogclk", "apb_pclk";
 349                         status = "disabled";
 350                 };
 351
 352                 timer01: timer@10011000 {
 353                         compatible = "arm,sp804", "arm,primecell";
 354                         reg = <0x10011000 0x1000>;
 355                         clocks = <&timclk>, <&timclk>, <&pclk>;
 356                         clock-names = "timer1", "timer2", "apb_pclk";
 357                 };
 358
 359                 timer23: timer@10012000 {
 360                         compatible = "arm,sp804", "arm,primecell";
 361                         reg = <0x10012000 0x1000>;
 362                         clocks = <&timclk>, <&timclk>, <&pclk>;
 363                         clock-names = "timer1", "timer2", "apb_pclk";
 364                 };
 365
 366                 gpio0: gpio@10013000 {
 367                         compatible = "arm,pl061", "arm,primecell";
 368                         reg = <0x10013000 0x1000>;
 369                         gpio-controller;
 370                         #gpio-cells = <2>;
 371                         interrupt-controller;
 372                         #interrupt-cells = <2>;
 373                         clocks = <&pclk>;
 374                         clock-names = "apb_pclk";
 375                 };
 376
 377                 gpio1: gpio@10014000 {
 378                         compatible = "arm,pl061", "arm,primecell";
 379                         reg = <0x10014000 0x1000>;
 380                         gpio-controller;
 381                         #gpio-cells = <2>;
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                         clocks = <&pclk>;
 385                         clock-names = "apb_pclk";
 386                 };
 387
 388                 gpio2: gpio@10015000 {
 389                         compatible = "arm,pl061", "arm,primecell";
 390                         reg = <0x10015000 0x1000>;
 391                         gpio-controller;
 392                         #gpio-cells = <2>;
 393                         interrupt-controller;
 394                         #interrupt-cells = <2>;
 395                         clocks = <&pclk>;
 396                         clock-names = "apb_pclk";
 397                 };
 398
 399                 rtc: rtc@10017000 {
 400                         compatible = "arm,pl031", "arm,primecell";
 401                         reg = <0x10017000 0x1000>;
 402                         clocks = <&pclk>;
 403                         clock-names = "apb_pclk";
 404                 };
 405
 406                 clcd: clcd@10020000 {
 407                         compatible = "arm,pl111", "arm,primecell";
 408                         reg = <0x10020000 0x1000>;
 409                         interrupt-names = "combined";
 410                         clocks = <&oscclk0>, <&pclk>;
 411                         clock-names = "clcdclk", "apb_pclk";
 412
 413                         port {
 414                                 clcd_pads: endpoint {
 415                                         remote-endpoint = <&clcd_panel>;
 416                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 417                                 };
 418                         };
 419
 420                         panel {
 421                                 compatible = "panel-dpi";
 422
 423                                 port {
 424                                         clcd_panel: endpoint {
 425                                                 remote-endpoint = <&clcd_pads>;
 426                                         };
 427                                 };
 428
 429                                 /* Standard 640x480 VGA timings */
 430                                 panel-timing {
 431                                         clock-frequency = <25175000>;
 432                                         hactive = <640>;
 433                                         hback-porch = <48>;
 434                                         hfront-porch = <16>;
 435                                         hsync-len = <96>;
 436                                         vactive = <480>;
 437                                         vback-porch = <33>;
 438                                         vfront-porch = <10>;
 439                                         vsync-len = <2>;
 440                                 };
 441                         };
 442                 };
 443         };
 444 };