arch/arm/boot/dts/armada-375-db.dts

   1 /*
   2  * Device Tree file for Marvell Armada 375 evaluation board
   3  * (DB-88F6720)
   4  *
   5  *  Copyright (C) 2014 Marvell
   6  *
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is dual-licensed: you can use it either under the terms
  11  * of the GPL or the X11 license, at your option. Note that this dual
  12  * licensing only applies to this file, and not this project as a
  13  * whole.
  14  *
  15  *  a) This file is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of the
  18  *     License, or (at your option) any later version.
  19  *
  20  *     This file is distributed in the hope that it will be useful
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 /dts-v1/;
  50 #include <dt-bindings/gpio/gpio.h>
  51 #include "armada-375.dtsi"
  52
  53 / {
  54         model = "Marvell Armada 375 Development Board";
  55         compatible = "marvell,a375-db", "marvell,armada375";
  56
  57         chosen {
  58                 stdout-path = "serial0:115200n8";
  59         };
  60
  61         memory@0 {
  62                 device_type = "memory";
  63                 reg = <0x00000000 0x40000000>; /* 1 GB */
  64         };
  65
  66         soc {
  67                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  68                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  69                           MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
  70                           MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
  71
  72         };
  73 };
  74 &pciec {
  75         status = "okay";
  76 };
  77
  78 /*
  79  * The two PCIe units are accessible through
  80  * standard PCIe slots on the board.
  81  */
  82 &pcie0 {
  83         /* Port 0, Lane 0 */
  84         status = "okay";
  85 };
  86
  87 &pcie1 {
  88         /* Port 1, Lane 0 */
  89         status = "okay";
  90 };
  91
  92
  93 &spi0 {
  94         pinctrl-0 = <&spi0_pins>;
  95         pinctrl-names = "default";
  96
  97         /*
  98          * SPI conflicts with NAND, so we disable it here, and
  99          * select NAND as the enabled device by default.
 100          */
 101
 102         status = "disabled";
 103
 104         spi-flash@0 {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 compatible = "n25q128a13", "jedec,spi-nor";
 108                 reg = <0>; /* Chip select 0 */
 109                 spi-max-frequency = <108000000>;
 110         };
 111 };
 112
 113 &i2c0 {
 114         status = "okay";
 115         clock-frequency = <100000>;
 116         pinctrl-0 = <&i2c0_pins>;
 117         pinctrl-names = "default";
 118 };
 119
 120 &i2c1 {
 121         status = "okay";
 122         clock-frequency = <100000>;
 123         pinctrl-0 = <&i2c1_pins>;
 124         pinctrl-names = "default";
 125 };
 126
 127 &uart0 {
 128         status = "okay";
 129 };
 130
 131 &pinctrl {
 132         sdio_st_pins: sdio-st-pins {
 133                 marvell,pins = "mpp44", "mpp45";
 134                 marvell,function = "gpio";
 135         };
 136 };
 137
 138 &sata {
 139         status = "okay";
 140         nr-ports = <2>;
 141 };
 142
 143 &nand {
 144         pinctrl-0 = <&nand_pins>;
 145         pinctrl-names = "default";
 146         status = "okay";
 147         num-cs = <1>;
 148         marvell,nand-keep-config;
 149         marvell,nand-enable-arbiter;
 150         nand-on-flash-bbt;
 151         nand-ecc-strength = <4>;
 152         nand-ecc-step-size = <512>;
 153
 154         partition@0 {
 155                 label = "U-Boot";
 156                 reg = <0 0x800000>;
 157         };
 158         partition@800000 {
 159                 label = "Linux";
 160                 reg = <0x800000 0x800000>;
 161         };
 162         partition@1000000 {
 163                 label = "Filesystem";
 164                 reg = <0x1000000 0x3f000000>;
 165         };
 166 };
 167
 168 &usb1 {
 169         status = "okay";
 170 };
 171
 172 &usb2 {
 173         status = "okay";
 174 };
 175
 176 &sdio {
 177         pinctrl-0 = <&sdio_pins &sdio_st_pins>;
 178         pinctrl-names = "default";
 179         status = "okay";
 180         cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 181         wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
 182 };
 183
 184 &mdio {
 185         phy0: ethernet-phy@0 {
 186                 reg = <0>;
 187         };
 188
 189         phy3: ethernet-phy@3 {
 190                 reg = <3>;
 191         };
 192 };
 193
 194 &ethernet {
 195         status = "okay";
 196 };
 197
 198
 199 &eth0 {
 200         status = "okay";
 201         phy = <&phy0>;
 202         phy-mode = "rgmii-id";
 203 };
 204
 205 &eth1 {
 206         status = "okay";
 207         phy = <&phy3>;
 208         phy-mode = "gmii";
 209 };