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Merge tag 'v3.17-rc3' into next
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / armada-375.dtsi
1 /*
2 * Device Tree Include file for Marvell Armada 375 family SoC
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include "skeleton.dtsi"
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17
18 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
19
20 / {
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
23
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 gpio2 = &gpio2;
28 ethernet0 = &eth0;
29 ethernet1 = &eth1;
30 };
31
32 clocks {
33 /* 2 GHz fixed main PLL */
34 mainpll: mainpll {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <2000000000>;
38 };
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "marvell,armada-375-smp";
45
46 cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a9";
49 reg = <0>;
50 };
51 cpu@1 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a9";
54 reg = <1>;
55 };
56 };
57
58 soc {
59 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
60 #address-cells = <2>;
61 #size-cells = <1>;
62 controller = <&mbusc>;
63 interrupt-parent = <&gic>;
64 pcie-mem-aperture = <0xe0000000 0x8000000>;
65 pcie-io-aperture = <0xe8000000 0x100000>;
66
67 bootrom {
68 compatible = "marvell,bootrom";
69 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
70 };
71
72 devbus-bootcs {
73 compatible = "marvell,mvebu-devbus";
74 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
75 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
76 #address-cells = <1>;
77 #size-cells = <1>;
78 clocks = <&coreclk 0>;
79 status = "disabled";
80 };
81
82 devbus-cs0 {
83 compatible = "marvell,mvebu-devbus";
84 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
85 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88 clocks = <&coreclk 0>;
89 status = "disabled";
90 };
91
92 devbus-cs1 {
93 compatible = "marvell,mvebu-devbus";
94 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
95 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
96 #address-cells = <1>;
97 #size-cells = <1>;
98 clocks = <&coreclk 0>;
99 status = "disabled";
100 };
101
102 devbus-cs2 {
103 compatible = "marvell,mvebu-devbus";
104 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
105 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
106 #address-cells = <1>;
107 #size-cells = <1>;
108 clocks = <&coreclk 0>;
109 status = "disabled";
110 };
111
112 devbus-cs3 {
113 compatible = "marvell,mvebu-devbus";
114 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
115 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
116 #address-cells = <1>;
117 #size-cells = <1>;
118 clocks = <&coreclk 0>;
119 status = "disabled";
120 };
121
122 internal-regs {
123 compatible = "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
127
128 L2: cache-controller@8000 {
129 compatible = "arm,pl310-cache";
130 reg = <0x8000 0x1000>;
131 cache-unified;
132 cache-level = <2>;
133 };
134
135 scu@c000 {
136 compatible = "arm,cortex-a9-scu";
137 reg = <0xc000 0x58>;
138 };
139
140 timer@c600 {
141 compatible = "arm,cortex-a9-twd-timer";
142 reg = <0xc600 0x20>;
143 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
144 clocks = <&coreclk 2>;
145 };
146
147 gic: interrupt-controller@d000 {
148 compatible = "arm,cortex-a9-gic";
149 #interrupt-cells = <3>;
150 #size-cells = <0>;
151 interrupt-controller;
152 reg = <0xd000 0x1000>,
153 <0xc100 0x100>;
154 };
155
156 mdio {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "marvell,orion-mdio";
160 reg = <0xc0054 0x4>;
161 clocks = <&gateclk 19>;
162 };
163
164 /* Network controller */
165 ethernet@f0000 {
166 compatible = "marvell,armada-375-pp2";
167 reg = <0xf0000 0xa000>, /* Packet Processor regs */
168 <0xc0000 0x3060>, /* LMS regs */
169 <0xc4000 0x100>, /* eth0 regs */
170 <0xc5000 0x100>; /* eth1 regs */
171 clocks = <&gateclk 3>, <&gateclk 19>;
172 clock-names = "pp_clk", "gop_clk";
173 status = "disabled";
174
175 eth0: eth0@c4000 {
176 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
177 port-id = <0>;
178 status = "disabled";
179 };
180
181 eth1: eth1@c5000 {
182 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
183 port-id = <1>;
184 status = "disabled";
185 };
186 };
187
188 spi0: spi@10600 {
189 compatible = "marvell,orion-spi";
190 reg = <0x10600 0x50>;
191 #address-cells = <1>;
192 #size-cells = <0>;
193 cell-index = <0>;
194 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&coreclk 0>;
196 status = "disabled";
197 };
198
199 spi1: spi@10680 {
200 compatible = "marvell,orion-spi";
201 reg = <0x10680 0x50>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 cell-index = <1>;
205 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&coreclk 0>;
207 status = "disabled";
208 };
209
210 i2c0: i2c@11000 {
211 compatible = "marvell,mv64xxx-i2c";
212 reg = <0x11000 0x20>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
216 timeout-ms = <1000>;
217 clocks = <&coreclk 0>;
218 status = "disabled";
219 };
220
221 i2c1: i2c@11100 {
222 compatible = "marvell,mv64xxx-i2c";
223 reg = <0x11100 0x20>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
227 timeout-ms = <1000>;
228 clocks = <&coreclk 0>;
229 status = "disabled";
230 };
231
232 serial@12000 {
233 compatible = "snps,dw-apb-uart";
234 reg = <0x12000 0x100>;
235 reg-shift = <2>;
236 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
237 reg-io-width = <1>;
238 clocks = <&coreclk 0>;
239 status = "disabled";
240 };
241
242 serial@12100 {
243 compatible = "snps,dw-apb-uart";
244 reg = <0x12100 0x100>;
245 reg-shift = <2>;
246 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
247 reg-io-width = <1>;
248 clocks = <&coreclk 0>;
249 status = "disabled";
250 };
251
252 pinctrl {
253 compatible = "marvell,mv88f6720-pinctrl";
254 reg = <0x18000 0x24>;
255
256 i2c0_pins: i2c0-pins {
257 marvell,pins = "mpp14", "mpp15";
258 marvell,function = "i2c0";
259 };
260
261 i2c1_pins: i2c1-pins {
262 marvell,pins = "mpp61", "mpp62";
263 marvell,function = "i2c1";
264 };
265
266 nand_pins: nand-pins {
267 marvell,pins = "mpp0", "mpp1", "mpp2",
268 "mpp3", "mpp4", "mpp5",
269 "mpp6", "mpp7", "mpp8",
270 "mpp9", "mpp10", "mpp11",
271 "mpp12", "mpp13";
272 marvell,function = "nand";
273 };
274
275 sdio_pins: sdio-pins {
276 marvell,pins = "mpp24", "mpp25", "mpp26",
277 "mpp27", "mpp28", "mpp29";
278 marvell,function = "sd";
279 };
280
281 spi0_pins: spi0-pins {
282 marvell,pins = "mpp0", "mpp1", "mpp4",
283 "mpp5", "mpp8", "mpp9";
284 marvell,function = "spi0";
285 };
286 };
287
288 gpio0: gpio@18100 {
289 compatible = "marvell,orion-gpio";
290 reg = <0x18100 0x40>;
291 ngpios = <32>;
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
300 };
301
302 gpio1: gpio@18140 {
303 compatible = "marvell,orion-gpio";
304 reg = <0x18140 0x40>;
305 ngpios = <32>;
306 gpio-controller;
307 #gpio-cells = <2>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
314 };
315
316 gpio2: gpio@18180 {
317 compatible = "marvell,orion-gpio";
318 reg = <0x18180 0x40>;
319 ngpios = <3>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
325 };
326
327 system-controller@18200 {
328 compatible = "marvell,armada-375-system-controller";
329 reg = <0x18200 0x100>;
330 };
331
332 gateclk: clock-gating-control@18220 {
333 compatible = "marvell,armada-375-gating-clock";
334 reg = <0x18220 0x4>;
335 clocks = <&coreclk 0>;
336 #clock-cells = <1>;
337 };
338
339 mbusc: mbus-controller@20000 {
340 compatible = "marvell,mbus-controller";
341 reg = <0x20000 0x100>, <0x20180 0x20>;
342 };
343
344 mpic: interrupt-controller@20000 {
345 compatible = "marvell,mpic";
346 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
347 #interrupt-cells = <1>;
348 #size-cells = <1>;
349 interrupt-controller;
350 msi-controller;
351 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
352 };
353
354 timer@20300 {
355 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
356 reg = <0x20300 0x30>, <0x21040 0x30>;
357 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
358 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
359 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
360 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
361 <&mpic 5>,
362 <&mpic 6>;
363 clocks = <&coreclk 0>;
364 };
365
366 watchdog@20300 {
367 compatible = "marvell,armada-375-wdt";
368 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
369 clocks = <&coreclk 0>;
370 };
371
372 cpurst@20800 {
373 compatible = "marvell,armada-370-cpu-reset";
374 reg = <0x20800 0x10>;
375 };
376
377 coherency-fabric@21010 {
378 compatible = "marvell,armada-375-coherency-fabric";
379 reg = <0x21010 0x1c>;
380 };
381
382 usb@50000 {
383 compatible = "marvell,orion-ehci";
384 reg = <0x50000 0x500>;
385 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&gateclk 18>;
387 status = "disabled";
388 };
389
390 usb@54000 {
391 compatible = "marvell,orion-ehci";
392 reg = <0x54000 0x500>;
393 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&gateclk 26>;
395 status = "disabled";
396 };
397
398 usb3@58000 {
399 compatible = "marvell,armada-375-xhci";
400 reg = <0x58000 0x20000>,<0x5b880 0x80>;
401 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&gateclk 16>;
403 status = "disabled";
404 };
405
406 xor@60800 {
407 compatible = "marvell,orion-xor";
408 reg = <0x60800 0x100
409 0x60A00 0x100>;
410 clocks = <&gateclk 22>;
411 status = "okay";
412
413 xor00 {
414 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
415 dmacap,memcpy;
416 dmacap,xor;
417 };
418 xor01 {
419 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
420 dmacap,memcpy;
421 dmacap,xor;
422 dmacap,memset;
423 };
424 };
425
426 xor@60900 {
427 compatible = "marvell,orion-xor";
428 reg = <0x60900 0x100
429 0x60b00 0x100>;
430 clocks = <&gateclk 23>;
431 status = "okay";
432
433 xor10 {
434 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
435 dmacap,memcpy;
436 dmacap,xor;
437 };
438 xor11 {
439 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
440 dmacap,memcpy;
441 dmacap,xor;
442 dmacap,memset;
443 };
444 };
445
446 sata@a0000 {
447 compatible = "marvell,orion-sata";
448 reg = <0xa0000 0x5000>;
449 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&gateclk 14>, <&gateclk 20>;
451 clock-names = "0", "1";
452 status = "disabled";
453 };
454
455 nand@d0000 {
456 compatible = "marvell,armada370-nand";
457 reg = <0xd0000 0x54>;
458 #address-cells = <1>;
459 #size-cells = <1>;
460 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&gateclk 11>;
462 status = "disabled";
463 };
464
465 mvsdio@d4000 {
466 compatible = "marvell,orion-sdio";
467 reg = <0xd4000 0x200>;
468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&gateclk 17>;
470 bus-width = <4>;
471 cap-sdio-irq;
472 cap-sd-highspeed;
473 cap-mmc-highspeed;
474 status = "disabled";
475 };
476
477 thermal@e8078 {
478 compatible = "marvell,armada375-thermal";
479 reg = <0xe8078 0x4>, <0xe807c 0x8>;
480 status = "okay";
481 };
482
483 coreclk: mvebu-sar@e8204 {
484 compatible = "marvell,armada-375-core-clock";
485 reg = <0xe8204 0x04>;
486 #clock-cells = <1>;
487 };
488
489 coredivclk: corediv-clock@e8250 {
490 compatible = "marvell,armada-375-corediv-clock";
491 reg = <0xe8250 0xc>;
492 #clock-cells = <1>;
493 clocks = <&mainpll>;
494 clock-output-names = "nand";
495 };
496 };
497
498 pcie-controller {
499 compatible = "marvell,armada-370-pcie";
500 status = "disabled";
501 device_type = "pci";
502
503 #address-cells = <3>;
504 #size-cells = <2>;
505
506 msi-parent = <&mpic>;
507 bus-range = <0x00 0xff>;
508
509 ranges =
510 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
511 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
512 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
513 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
514 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
515 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
516
517 pcie@1,0 {
518 device_type = "pci";
519 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
520 reg = <0x0800 0 0 0 0>;
521 #address-cells = <3>;
522 #size-cells = <2>;
523 #interrupt-cells = <1>;
524 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
525 0x81000000 0 0 0x81000000 0x1 0 1 0>;
526 interrupt-map-mask = <0 0 0 0>;
527 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
528 marvell,pcie-port = <0>;
529 marvell,pcie-lane = <0>;
530 clocks = <&gateclk 5>;
531 status = "disabled";
532 };
533
534 pcie@2,0 {
535 device_type = "pci";
536 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
537 reg = <0x1000 0 0 0 0>;
538 #address-cells = <3>;
539 #size-cells = <2>;
540 #interrupt-cells = <1>;
541 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
542 0x81000000 0 0 0x81000000 0x2 0 1 0>;
543 interrupt-map-mask = <0 0 0 0>;
544 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
545 marvell,pcie-port = <0>;
546 marvell,pcie-lane = <1>;
547 clocks = <&gateclk 6>;
548 status = "disabled";
549 };
550
551 };
552 };
553 };
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