arch/arm/boot/dts/armada-385.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 385 SoC.
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include "armada-38x.dtsi"
  16
  17 / {
  18         model = "Marvell Armada 385 family SoC";
  19         compatible = "marvell,armada385", "marvell,armada380";
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 enable-method = "marvell,armada-380-smp";
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <0>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                 };
  36         };
  37
  38         soc {
  39                 internal-regs {
  40                         pinctrl {
  41                                 compatible = "marvell,mv88f6820-pinctrl";
  42                                 reg = <0x18000 0x20>;
  43                         };
  44                 };
  45
  46                 pcie-controller {
  47                         compatible = "marvell,armada-370-pcie";
  48                         status = "disabled";
  49                         device_type = "pci";
  50
  51                         #address-cells = <3>;
  52                         #size-cells = <2>;
  53
  54                         msi-parent = <&mpic>;
  55                         bus-range = <0x00 0xff>;
  56
  57                         ranges =
  58                                <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  59                                 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  60                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
  61                                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
  62                                 0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
  63                                 0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
  64                                 0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
  65                                 0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
  66                                 0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
  67                                 0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
  68                                 0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
  69                                 0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
  70
  71                         /*
  72                          * This port can be either x4 or x1. When
  73                          * configured in x4 by the bootloader, then
  74                          * pcie@4,0 is not available.
  75                          */
  76                         pcie@1,0 {
  77                                 device_type = "pci";
  78                                 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
  79                                 reg = <0x0800 0 0 0 0>;
  80                                 #address-cells = <3>;
  81                                 #size-cells = <2>;
  82                                 #interrupt-cells = <1>;
  83                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  84                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
  85                                 interrupt-map-mask = <0 0 0 0>;
  86                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  87                                 marvell,pcie-port = <0>;
  88                                 marvell,pcie-lane = <0>;
  89                                 clocks = <&gateclk 8>;
  90                                 status = "disabled";
  91                         };
  92
  93                         /* x1 port */
  94                         pcie@2,0 {
  95                                 device_type = "pci";
  96                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  97                                 reg = <0x1000 0 0 0 0>;
  98                                 #address-cells = <3>;
  99                                 #size-cells = <2>;
 100                                 #interrupt-cells = <1>;
 101                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 102                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 103                                 interrupt-map-mask = <0 0 0 0>;
 104                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 105                                 marvell,pcie-port = <1>;
 106                                 marvell,pcie-lane = <0>;
 107                                 clocks = <&gateclk 5>;
 108                                 status = "disabled";
 109                         };
 110
 111                         /* x1 port */
 112                         pcie@3,0 {
 113                                 device_type = "pci";
 114                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 115                                 reg = <0x1800 0 0 0 0>;
 116                                 #address-cells = <3>;
 117                                 #size-cells = <2>;
 118                                 #interrupt-cells = <1>;
 119                                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 120                                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
 121                                 interrupt-map-mask = <0 0 0 0>;
 122                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 123                                 marvell,pcie-port = <2>;
 124                                 marvell,pcie-lane = <0>;
 125                                 clocks = <&gateclk 6>;
 126                                 status = "disabled";
 127                         };
 128
 129                         /*
 130                          * x1 port only available when pcie@1,0 is
 131                          * configured as a x1 port
 132                          */
 133                         pcie@4,0 {
 134                                 device_type = "pci";
 135                                 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 136                                 reg = <0x2000 0 0 0 0>;
 137                                 #address-cells = <3>;
 138                                 #size-cells = <2>;
 139                                 #interrupt-cells = <1>;
 140                                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 141                                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
 142                                 interrupt-map-mask = <0 0 0 0>;
 143                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 144                                 marvell,pcie-port = <3>;
 145                                 marvell,pcie-lane = <0>;
 146                                 clocks = <&gateclk 7>;
 147                                 status = "disabled";
 148                         };
 149                 };
 150         };
 151 };