2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
4 * Copyright (C) 2014 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
49 #include "skeleton.dtsi"
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
56 model = "Marvell Armada 38x family SoC";
57 compatible = "marvell,armada380";
68 compatible = "marvell,armada380-mbus", "simple-bus";
71 controller = <&mbusc>;
72 interrupt-parent = <&gic>;
73 pcie-mem-aperture = <0xe0000000 0x8000000>;
74 pcie-io-aperture = <0xe8000000 0x100000>;
77 compatible = "marvell,bootrom";
78 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
82 compatible = "marvell,mvebu-devbus";
83 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
84 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
87 clocks = <&coreclk 0>;
92 compatible = "marvell,mvebu-devbus";
93 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
94 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
97 clocks = <&coreclk 0>;
102 compatible = "marvell,mvebu-devbus";
103 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
104 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
105 #address-cells = <1>;
107 clocks = <&coreclk 0>;
112 compatible = "marvell,mvebu-devbus";
113 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
114 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
115 #address-cells = <1>;
117 clocks = <&coreclk 0>;
122 compatible = "marvell,mvebu-devbus";
123 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
124 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
125 #address-cells = <1>;
127 clocks = <&coreclk 0>;
132 compatible = "simple-bus";
133 #address-cells = <1>;
135 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
137 L2: cache-controller@8000 {
138 compatible = "arm,pl310-cache";
139 reg = <0x8000 0x1000>;
145 compatible = "arm,cortex-a9-scu";
150 compatible = "arm,cortex-a9-twd-timer";
152 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
153 clocks = <&coreclk 2>;
156 gic: interrupt-controller@d000 {
157 compatible = "arm,cortex-a9-gic";
158 #interrupt-cells = <3>;
160 interrupt-controller;
161 reg = <0xd000 0x1000>,
166 compatible = "marvell,orion-spi";
167 reg = <0x10600 0x50>;
168 #address-cells = <1>;
171 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&coreclk 0>;
177 compatible = "marvell,orion-spi";
178 reg = <0x10680 0x50>;
179 #address-cells = <1>;
182 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&coreclk 0>;
188 compatible = "marvell,mv64xxx-i2c";
189 reg = <0x11000 0x20>;
190 #address-cells = <1>;
192 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&coreclk 0>;
199 compatible = "marvell,mv64xxx-i2c";
200 reg = <0x11100 0x20>;
201 #address-cells = <1>;
203 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&coreclk 0>;
209 uart0: serial@12000 {
210 compatible = "snps,dw-apb-uart";
211 reg = <0x12000 0x100>;
213 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&coreclk 0>;
220 compatible = "snps,dw-apb-uart";
221 reg = <0x12100 0x100>;
223 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&coreclk 0>;
229 pinctrl: pinctrl@18000 {
230 reg = <0x18000 0x20>;
232 ge0_rgmii_pins: ge-rgmii-pins-0 {
233 marvell,pins = "mpp6", "mpp7", "mpp8",
234 "mpp9", "mpp10", "mpp11",
235 "mpp12", "mpp13", "mpp14",
236 "mpp15", "mpp16", "mpp17";
237 marvell,function = "ge0";
240 ge1_rgmii_pins: ge-rgmii-pins-1 {
241 marvell,pins = "mpp21", "mpp27", "mpp28",
242 "mpp29", "mpp30", "mpp31",
243 "mpp32", "mpp37", "mpp38",
244 "mpp39", "mpp40", "mpp41";
245 marvell,function = "ge1";
248 i2c0_pins: i2c-pins-0 {
249 marvell,pins = "mpp2", "mpp3";
250 marvell,function = "i2c0";
253 mdio_pins: mdio-pins {
254 marvell,pins = "mpp4", "mpp5";
255 marvell,function = "ge";
258 ref_clk0_pins: ref-clk-pins-0 {
259 marvell,pins = "mpp45";
260 marvell,function = "ref";
263 ref_clk1_pins: ref-clk-pins-1 {
264 marvell,pins = "mpp46";
265 marvell,function = "ref";
268 spi0_pins: spi-pins-0 {
269 marvell,pins = "mpp22", "mpp23", "mpp24",
271 marvell,function = "spi0";
274 spi1_pins: spi-pins-1 {
275 marvell,pins = "mpp56", "mpp57", "mpp58",
277 marvell,function = "spi1";
280 uart0_pins: uart-pins-0 {
281 marvell,pins = "mpp0", "mpp1";
282 marvell,function = "ua0";
285 uart1_pins: uart-pins-1 {
286 marvell,pins = "mpp19", "mpp20";
287 marvell,function = "ua1";
290 sdhci_pins: sdhci-pins {
291 marvell,pins = "mpp48", "mpp49", "mpp50",
292 "mpp52", "mpp53", "mpp54",
293 "mpp55", "mpp57", "mpp58",
295 marvell,function = "sd0";
298 sata0_pins: sata-pins-0 {
299 marvell,pins = "mpp20";
300 marvell,function = "sata0";
303 sata1_pins: sata-pins-1 {
304 marvell,pins = "mpp19";
305 marvell,function = "sata1";
308 sata2_pins: sata-pins-2 {
309 marvell,pins = "mpp47";
310 marvell,function = "sata2";
313 sata3_pins: sata-pins-3 {
314 marvell,pins = "mpp44";
315 marvell,function = "sata3";
320 compatible = "marvell,orion-gpio";
321 reg = <0x18100 0x40>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
334 compatible = "marvell,orion-gpio";
335 reg = <0x18140 0x40>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
347 system-controller@18200 {
348 compatible = "marvell,armada-380-system-controller",
349 "marvell,armada-370-xp-system-controller";
350 reg = <0x18200 0x100>;
353 gateclk: clock-gating-control@18220 {
354 compatible = "marvell,armada-380-gating-clock";
356 clocks = <&coreclk 0>;
360 coreclk: mvebu-sar@18600 {
361 compatible = "marvell,armada-380-core-clock";
362 reg = <0x18600 0x04>;
366 mbusc: mbus-controller@20000 {
367 compatible = "marvell,mbus-controller";
368 reg = <0x20000 0x100>, <0x20180 0x20>;
371 mpic: interrupt-controller@20000 {
372 compatible = "marvell,mpic";
373 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
374 #interrupt-cells = <1>;
376 interrupt-controller;
378 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
382 compatible = "marvell,armada-380-timer",
383 "marvell,armada-xp-timer";
384 reg = <0x20300 0x30>, <0x21040 0x30>;
385 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
386 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
387 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
388 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
391 clocks = <&coreclk 2>, <&refclk>;
392 clock-names = "nbclk", "fixed";
396 compatible = "marvell,armada-380-wdt";
397 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
398 clocks = <&coreclk 2>, <&refclk>;
399 clock-names = "nbclk", "fixed";
403 compatible = "marvell,armada-370-cpu-reset";
404 reg = <0x20800 0x10>;
407 mpcore-soc-ctrl@20d20 {
408 compatible = "marvell,armada-380-mpcore-soc-ctrl";
409 reg = <0x20d20 0x6c>;
412 coherency-fabric@21010 {
413 compatible = "marvell,armada-380-coherency-fabric";
414 reg = <0x21010 0x1c>;
418 compatible = "marvell,armada-380-pmsu";
419 reg = <0x22000 0x1000>;
422 eth1: ethernet@30000 {
423 compatible = "marvell,armada-370-neta";
424 reg = <0x30000 0x4000>;
425 interrupts-extended = <&mpic 10>;
426 clocks = <&gateclk 3>;
430 eth2: ethernet@34000 {
431 compatible = "marvell,armada-370-neta";
432 reg = <0x34000 0x4000>;
433 interrupts-extended = <&mpic 12>;
434 clocks = <&gateclk 2>;
439 compatible = "marvell,orion-ehci";
440 reg = <0x58000 0x500>;
441 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&gateclk 18>;
447 compatible = "marvell,orion-xor";
450 clocks = <&gateclk 22>;
454 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
459 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
467 compatible = "marvell,orion-xor";
470 clocks = <&gateclk 28>;
474 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
479 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
486 eth0: ethernet@70000 {
487 compatible = "marvell,armada-370-neta";
488 reg = <0x70000 0x4000>;
489 interrupts-extended = <&mpic 8>;
490 clocks = <&gateclk 4>;
495 #address-cells = <1>;
497 compatible = "marvell,orion-mdio";
499 clocks = <&gateclk 4>;
503 compatible = "marvell,armada-380-rtc";
504 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
505 reg-names = "rtc", "rtc-soc";
506 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
510 compatible = "marvell,armada-380-ahci";
511 reg = <0xa8000 0x2000>;
512 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&gateclk 15>;
518 compatible = "marvell,armada-380-ahci";
519 reg = <0xe0000 0x2000>;
520 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&gateclk 30>;
525 coredivclk: clock@e4250 {
526 compatible = "marvell,armada-380-corediv-clock";
530 clock-output-names = "nand";
534 compatible = "marvell,armada380-thermal";
535 reg = <0xe4078 0x4>, <0xe4074 0x4>;
540 compatible = "marvell,armada370-nand";
541 reg = <0xd0000 0x54>;
542 #address-cells = <1>;
544 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&coredivclk 0>;
550 compatible = "marvell,armada-380-sdhci";
551 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
552 interrupts = <0 25 0x4>;
553 clocks = <&gateclk 17>;
554 mrvl,clk-delay-cycles = <0x1F>;
559 compatible = "marvell,armada-380-xhci";
560 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
561 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&gateclk 9>;
567 compatible = "marvell,armada-380-xhci";
568 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
569 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&gateclk 10>;
577 /* 2 GHz fixed main PLL */
579 compatible = "fixed-clock";
581 clock-frequency = <2000000000>;
584 /* 25 MHz reference crystal */
586 compatible = "fixed-clock";
588 clock-frequency = <25000000>;