2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
4 * Copyright (C) 2014 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
49 #include "skeleton.dtsi"
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
56 model = "Marvell Armada 38x family SoC";
57 compatible = "marvell,armada380";
67 compatible = "arm,cortex-a9-pmu";
68 interrupts-extended = <&mpic 3>;
72 compatible = "marvell,armada380-mbus", "simple-bus";
75 controller = <&mbusc>;
76 interrupt-parent = <&gic>;
77 pcie-mem-aperture = <0xe0000000 0x8000000>;
78 pcie-io-aperture = <0xe8000000 0x100000>;
81 compatible = "marvell,bootrom";
82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
86 compatible = "marvell,mvebu-devbus";
87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
91 clocks = <&coreclk 0>;
96 compatible = "marvell,mvebu-devbus";
97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
101 clocks = <&coreclk 0>;
106 compatible = "marvell,mvebu-devbus";
107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
109 #address-cells = <1>;
111 clocks = <&coreclk 0>;
116 compatible = "marvell,mvebu-devbus";
117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
119 #address-cells = <1>;
121 clocks = <&coreclk 0>;
126 compatible = "marvell,mvebu-devbus";
127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
129 #address-cells = <1>;
131 clocks = <&coreclk 0>;
136 compatible = "simple-bus";
137 #address-cells = <1>;
139 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
141 L2: cache-controller@8000 {
142 compatible = "arm,pl310-cache";
143 reg = <0x8000 0x1000>;
149 compatible = "arm,cortex-a9-scu";
154 compatible = "arm,cortex-a9-twd-timer";
156 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
157 clocks = <&coreclk 2>;
160 gic: interrupt-controller@d000 {
161 compatible = "arm,cortex-a9-gic";
162 #interrupt-cells = <3>;
164 interrupt-controller;
165 reg = <0xd000 0x1000>,
170 compatible = "marvell,orion-spi";
171 reg = <0x10600 0x50>;
172 #address-cells = <1>;
175 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&coreclk 0>;
181 compatible = "marvell,orion-spi";
182 reg = <0x10680 0x50>;
183 #address-cells = <1>;
186 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&coreclk 0>;
192 compatible = "marvell,mv64xxx-i2c";
193 reg = <0x11000 0x20>;
194 #address-cells = <1>;
196 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&coreclk 0>;
203 compatible = "marvell,mv64xxx-i2c";
204 reg = <0x11100 0x20>;
205 #address-cells = <1>;
207 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&coreclk 0>;
213 uart0: serial@12000 {
214 compatible = "snps,dw-apb-uart";
215 reg = <0x12000 0x100>;
217 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&coreclk 0>;
223 uart1: serial@12100 {
224 compatible = "snps,dw-apb-uart";
225 reg = <0x12100 0x100>;
227 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&coreclk 0>;
233 pinctrl: pinctrl@18000 {
234 reg = <0x18000 0x20>;
236 ge0_rgmii_pins: ge-rgmii-pins-0 {
237 marvell,pins = "mpp6", "mpp7", "mpp8",
238 "mpp9", "mpp10", "mpp11",
239 "mpp12", "mpp13", "mpp14",
240 "mpp15", "mpp16", "mpp17";
241 marvell,function = "ge0";
244 ge1_rgmii_pins: ge-rgmii-pins-1 {
245 marvell,pins = "mpp21", "mpp27", "mpp28",
246 "mpp29", "mpp30", "mpp31",
247 "mpp32", "mpp37", "mpp38",
248 "mpp39", "mpp40", "mpp41";
249 marvell,function = "ge1";
252 i2c0_pins: i2c-pins-0 {
253 marvell,pins = "mpp2", "mpp3";
254 marvell,function = "i2c0";
257 mdio_pins: mdio-pins {
258 marvell,pins = "mpp4", "mpp5";
259 marvell,function = "ge";
262 ref_clk0_pins: ref-clk-pins-0 {
263 marvell,pins = "mpp45";
264 marvell,function = "ref";
267 ref_clk1_pins: ref-clk-pins-1 {
268 marvell,pins = "mpp46";
269 marvell,function = "ref";
272 spi0_pins: spi-pins-0 {
273 marvell,pins = "mpp22", "mpp23", "mpp24",
275 marvell,function = "spi0";
278 spi1_pins: spi-pins-1 {
279 marvell,pins = "mpp56", "mpp57", "mpp58",
281 marvell,function = "spi1";
284 uart0_pins: uart-pins-0 {
285 marvell,pins = "mpp0", "mpp1";
286 marvell,function = "ua0";
289 uart1_pins: uart-pins-1 {
290 marvell,pins = "mpp19", "mpp20";
291 marvell,function = "ua1";
294 sdhci_pins: sdhci-pins {
295 marvell,pins = "mpp48", "mpp49", "mpp50",
296 "mpp52", "mpp53", "mpp54",
297 "mpp55", "mpp57", "mpp58",
299 marvell,function = "sd0";
302 sata0_pins: sata-pins-0 {
303 marvell,pins = "mpp20";
304 marvell,function = "sata0";
307 sata1_pins: sata-pins-1 {
308 marvell,pins = "mpp19";
309 marvell,function = "sata1";
312 sata2_pins: sata-pins-2 {
313 marvell,pins = "mpp47";
314 marvell,function = "sata2";
317 sata3_pins: sata-pins-3 {
318 marvell,pins = "mpp44";
319 marvell,function = "sata3";
324 compatible = "marvell,orion-gpio";
325 reg = <0x18100 0x40>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
338 compatible = "marvell,orion-gpio";
339 reg = <0x18140 0x40>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
351 system-controller@18200 {
352 compatible = "marvell,armada-380-system-controller",
353 "marvell,armada-370-xp-system-controller";
354 reg = <0x18200 0x100>;
357 gateclk: clock-gating-control@18220 {
358 compatible = "marvell,armada-380-gating-clock";
360 clocks = <&coreclk 0>;
364 coreclk: mvebu-sar@18600 {
365 compatible = "marvell,armada-380-core-clock";
366 reg = <0x18600 0x04>;
370 mbusc: mbus-controller@20000 {
371 compatible = "marvell,mbus-controller";
372 reg = <0x20000 0x100>, <0x20180 0x20>;
375 mpic: interrupt-controller@20a00 {
376 compatible = "marvell,mpic";
377 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
378 #interrupt-cells = <1>;
380 interrupt-controller;
382 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
386 compatible = "marvell,armada-380-timer",
387 "marvell,armada-xp-timer";
388 reg = <0x20300 0x30>, <0x21040 0x30>;
389 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
390 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
391 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
392 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
395 clocks = <&coreclk 2>, <&refclk>;
396 clock-names = "nbclk", "fixed";
400 compatible = "marvell,armada-380-wdt";
401 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
402 clocks = <&coreclk 2>, <&refclk>;
403 clock-names = "nbclk", "fixed";
407 compatible = "marvell,armada-370-cpu-reset";
408 reg = <0x20800 0x10>;
411 mpcore-soc-ctrl@20d20 {
412 compatible = "marvell,armada-380-mpcore-soc-ctrl";
413 reg = <0x20d20 0x6c>;
416 coherency-fabric@21010 {
417 compatible = "marvell,armada-380-coherency-fabric";
418 reg = <0x21010 0x1c>;
422 compatible = "marvell,armada-380-pmsu";
423 reg = <0x22000 0x1000>;
426 eth1: ethernet@30000 {
427 compatible = "marvell,armada-370-neta";
428 reg = <0x30000 0x4000>;
429 interrupts-extended = <&mpic 10>;
430 clocks = <&gateclk 3>;
434 eth2: ethernet@34000 {
435 compatible = "marvell,armada-370-neta";
436 reg = <0x34000 0x4000>;
437 interrupts-extended = <&mpic 12>;
438 clocks = <&gateclk 2>;
443 compatible = "marvell,orion-ehci";
444 reg = <0x58000 0x500>;
445 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&gateclk 18>;
451 compatible = "marvell,orion-xor";
454 clocks = <&gateclk 22>;
458 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
463 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
471 compatible = "marvell,orion-xor";
474 clocks = <&gateclk 28>;
478 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
483 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
490 eth0: ethernet@70000 {
491 compatible = "marvell,armada-370-neta";
492 reg = <0x70000 0x4000>;
493 interrupts-extended = <&mpic 8>;
494 clocks = <&gateclk 4>;
499 #address-cells = <1>;
501 compatible = "marvell,orion-mdio";
503 clocks = <&gateclk 4>;
507 compatible = "marvell,armada-380-rtc";
508 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
509 reg-names = "rtc", "rtc-soc";
510 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
514 compatible = "marvell,armada-380-ahci";
515 reg = <0xa8000 0x2000>;
516 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gateclk 15>;
522 compatible = "marvell,armada-380-ahci";
523 reg = <0xe0000 0x2000>;
524 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&gateclk 30>;
529 coredivclk: clock@e4250 {
530 compatible = "marvell,armada-380-corediv-clock";
534 clock-output-names = "nand";
538 compatible = "marvell,armada380-thermal";
539 reg = <0xe4078 0x4>, <0xe4074 0x4>;
544 compatible = "marvell,armada370-nand";
545 reg = <0xd0000 0x54>;
546 #address-cells = <1>;
548 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&coredivclk 0>;
554 compatible = "marvell,armada-380-sdhci";
555 reg-names = "sdhci", "mbus", "conf-sdio3";
556 reg = <0xd8000 0x1000>,
559 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&gateclk 17>;
561 mrvl,clk-delay-cycles = <0x1F>;
566 compatible = "marvell,armada-380-xhci";
567 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
568 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&gateclk 9>;
574 compatible = "marvell,armada-380-xhci";
575 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
576 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&gateclk 10>;
584 /* 2 GHz fixed main PLL */
586 compatible = "fixed-clock";
588 clock-frequency = <2000000000>;
591 /* 25 MHz reference crystal */
593 compatible = "fixed-clock";
595 clock-frequency = <25000000>;