arch/arm/boot/dts/armada-xp-axpwifiap.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for Marvell RD-AXPWiFiAP.
   4  *
   5  * Note: this board is shipped with a new generation boot loader that
   6  * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
   7  * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
   8  * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
   9  *
  10  * Copyright (C) 2013 Marvell
  11  *
  12  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  13  */
  14
  15 /dts-v1/;
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18 #include "armada-xp-mv78230.dtsi"
  19
  20 / {
  21         model = "Marvell RD-AXPWiFiAP";
  22         compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         memory@0 {
  29                 device_type = "memory";
  30                 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
  31         };
  32
  33         soc {
  34                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  35                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  36                           MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
  37                           MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
  38
  39                 internal-regs {
  40                         /* UART0 */
  41                         serial@12000 {
  42                                 status = "okay";
  43                         };
  44
  45                         /* UART1 */
  46                         serial@12100 {
  47                                 status = "okay";
  48                         };
  49
  50                         sata@a0000 {
  51                                 nr-ports = <1>;
  52                                 status = "okay";
  53                         };
  54
  55                         ethernet@70000 {
  56                                 pinctrl-0 = <&ge0_rgmii_pins>;
  57                                 pinctrl-names = "default";
  58                                 status = "okay";
  59                                 phy = <&phy0>;
  60                                 phy-mode = "rgmii-id";
  61                         };
  62                         ethernet@74000 {
  63                                 pinctrl-0 = <&ge1_rgmii_pins>;
  64                                 pinctrl-names = "default";
  65                                 status = "okay";
  66                                 phy = <&phy1>;
  67                                 phy-mode = "rgmii-id";
  68                         };
  69                 };
  70         };
  71
  72         gpio_keys {
  73                 compatible = "gpio-keys";
  74                 #address-cells = <1>;
  75                 #size-cells = <0>;
  76                 pinctrl-0 = <&keys_pin>;
  77                 pinctrl-names = "default";
  78
  79                 reset {
  80                         label = "Factory Reset Button";
  81                         linux,code = <KEY_SETUP>;
  82                         gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  83                 };
  84         };
  85 };
  86
  87 &mdio {
  88         phy0: ethernet-phy@0 {
  89                 reg = <0>;
  90         };
  91
  92         phy1: ethernet-phy@1 {
  93                 reg = <1>;
  94         };
  95 };
  96
  97 &pciec {
  98         status = "okay";
  99
 100         /* First mini-PCIe port */
 101         pcie@1,0 {
 102                 /* Port 0, Lane 0 */
 103                 status = "okay";
 104         };
 105
 106         /* Second mini-PCIe port */
 107         pcie@2,0 {
 108                 /* Port 0, Lane 1 */
 109                 status = "okay";
 110         };
 111
 112         /* Renesas uPD720202 USB 3.0 controller */
 113         pcie@3,0 {
 114                 /* Port 0, Lane 3 */
 115                 status = "okay";
 116         };
 117 };
 118
 119 &pinctrl {
 120         pinctrl-0 = <&phy_int_pin>;
 121         pinctrl-names = "default";
 122
 123         keys_pin: keys-pin {
 124                 marvell,pins = "mpp33";
 125                 marvell,function = "gpio";
 126         };
 127
 128         phy_int_pin: phy-int-pin {
 129                 marvell,pins = "mpp32";
 130                 marvell,function = "gpio";
 131         };
 132 };
 133
 134 &spi0 {
 135         status = "okay";
 136
 137         spi-flash@0 {
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 compatible = "n25q128a13", "jedec,spi-nor";
 141                 reg = <0>; /* Chip select 0 */
 142                 spi-max-frequency = <108000000>;
 143         };
 144 };