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ARM: mvebu: Add the reference 25 MHz fixed-clock to Armada XP
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1 /*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
17 */
18
19 #include "armada-370-xp.dtsi"
20
21 / {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 aliases {
26 eth2 = &eth2;
27 };
28
29 soc {
30 compatible = "marvell,armadaxp-mbus", "simple-bus";
31
32 bootrom {
33 compatible = "marvell,bootrom";
34 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
35 };
36
37 internal-regs {
38 L2: l2-cache {
39 compatible = "marvell,aurora-system-cache";
40 reg = <0x08000 0x1000>;
41 cache-id-part = <0x100>;
42 wt-override;
43 };
44
45 interrupt-controller@20000 {
46 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
47 };
48
49 armada-370-xp-pmsu@22000 {
50 compatible = "marvell,armada-370-xp-pmsu";
51 reg = <0x22100 0x430>, <0x20800 0x20>;
52 };
53
54 serial@12200 {
55 compatible = "snps,dw-apb-uart";
56 reg = <0x12200 0x100>;
57 reg-shift = <2>;
58 interrupts = <43>;
59 reg-io-width = <1>;
60 status = "disabled";
61 };
62 serial@12300 {
63 compatible = "snps,dw-apb-uart";
64 reg = <0x12300 0x100>;
65 reg-shift = <2>;
66 interrupts = <44>;
67 reg-io-width = <1>;
68 status = "disabled";
69 };
70
71 timer@20300 {
72 compatible = "marvell,armada-xp-timer";
73 };
74
75 coreclk: mvebu-sar@18230 {
76 compatible = "marvell,armada-xp-core-clock";
77 reg = <0x18230 0x08>;
78 #clock-cells = <1>;
79 };
80
81 cpuclk: clock-complex@18700 {
82 #clock-cells = <1>;
83 compatible = "marvell,armada-xp-cpu-clock";
84 reg = <0x18700 0xA0>;
85 clocks = <&coreclk 1>;
86 };
87
88 gateclk: clock-gating-control@18220 {
89 compatible = "marvell,armada-xp-gating-clock";
90 reg = <0x18220 0x4>;
91 clocks = <&coreclk 0>;
92 #clock-cells = <1>;
93 };
94
95 system-controller@18200 {
96 compatible = "marvell,armada-370-xp-system-controller";
97 reg = <0x18200 0x500>;
98 };
99
100 eth2: ethernet@30000 {
101 compatible = "marvell,armada-370-neta";
102 reg = <0x30000 0x4000>;
103 interrupts = <12>;
104 clocks = <&gateclk 2>;
105 status = "disabled";
106 };
107
108 xor@60900 {
109 compatible = "marvell,orion-xor";
110 reg = <0x60900 0x100
111 0x60b00 0x100>;
112 clocks = <&gateclk 22>;
113 status = "okay";
114
115 xor10 {
116 interrupts = <51>;
117 dmacap,memcpy;
118 dmacap,xor;
119 };
120 xor11 {
121 interrupts = <52>;
122 dmacap,memcpy;
123 dmacap,xor;
124 dmacap,memset;
125 };
126 };
127
128 xor@f0900 {
129 compatible = "marvell,orion-xor";
130 reg = <0xF0900 0x100
131 0xF0B00 0x100>;
132 clocks = <&gateclk 28>;
133 status = "okay";
134
135 xor00 {
136 interrupts = <94>;
137 dmacap,memcpy;
138 dmacap,xor;
139 };
140 xor01 {
141 interrupts = <95>;
142 dmacap,memcpy;
143 dmacap,xor;
144 dmacap,memset;
145 };
146 };
147
148 usb@50000 {
149 clocks = <&gateclk 18>;
150 };
151
152 usb@51000 {
153 clocks = <&gateclk 19>;
154 };
155
156 usb@52000 {
157 compatible = "marvell,orion-ehci";
158 reg = <0x52000 0x500>;
159 interrupts = <47>;
160 clocks = <&gateclk 20>;
161 status = "disabled";
162 };
163
164 thermal@182b0 {
165 compatible = "marvell,armadaxp-thermal";
166 reg = <0x182b0 0x4
167 0x184d0 0x4>;
168 status = "okay";
169 };
170 };
171 };
172
173 clocks {
174 /* 25 MHz reference crystal */
175 refclk: oscillator {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <25000000>;
179 };
180 };
181 };