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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / at91sam9g45.dtsi
1 /*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12 #include "skeleton.dtsi"
13 #include <dt-bindings/dma/at91.h>
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
18
19 / {
20 model = "Atmel AT91SAM9G45 family SoC";
21 compatible = "atmel,at91sam9g45";
22 interrupt-parent = <&aic>;
23
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 serial4 = &usart3;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
36 tcb1 = &tcb1;
37 i2c0 = &i2c0;
38 i2c1 = &i2c1;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
41 pwm0 = &pwm0;
42 };
43 cpus {
44 #address-cells = <0>;
45 #size-cells = <0>;
46
47 cpu {
48 compatible = "arm,arm926ej-s";
49 device_type = "cpu";
50 };
51 };
52
53 memory {
54 reg = <0x70000000 0x10000000>;
55 };
56
57 clocks {
58 slow_xtal: slow_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 main_xtal: main_xtal {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <0>;
68 };
69
70 adc_op_clk: adc_op_clk{
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <300000>;
74 };
75 };
76
77 sram: sram@00300000 {
78 compatible = "mmio-sram";
79 reg = <0x00300000 0x10000>;
80 };
81
82 ahb {
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges;
87
88 apb {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 aic: interrupt-controller@fffff000 {
95 #interrupt-cells = <3>;
96 compatible = "atmel,at91rm9200-aic";
97 interrupt-controller;
98 reg = <0xfffff000 0x200>;
99 atmel,external-irqs = <31>;
100 };
101
102 ramc0: ramc@ffffe400 {
103 compatible = "atmel,at91sam9g45-ddramc";
104 reg = <0xffffe400 0x200>;
105 clocks = <&ddrck>;
106 clock-names = "ddrck";
107 };
108
109 ramc1: ramc@ffffe600 {
110 compatible = "atmel,at91sam9g45-ddramc";
111 reg = <0xffffe600 0x200>;
112 clocks = <&ddrck>;
113 clock-names = "ddrck";
114 };
115
116 pmc: pmc@fffffc00 {
117 compatible = "atmel,at91sam9g45-pmc";
118 reg = <0xfffffc00 0x100>;
119 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
120 interrupt-controller;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 #interrupt-cells = <1>;
124
125 main_osc: main_osc {
126 compatible = "atmel,at91rm9200-clk-main-osc";
127 #clock-cells = <0>;
128 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
129 clocks = <&main_xtal>;
130 };
131
132 main: mainck {
133 compatible = "atmel,at91rm9200-clk-main";
134 #clock-cells = <0>;
135 clocks = <&main_osc>;
136 };
137
138 plla: pllack {
139 compatible = "atmel,at91rm9200-clk-pll";
140 #clock-cells = <0>;
141 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
142 clocks = <&main>;
143 reg = <0>;
144 atmel,clk-input-range = <2000000 32000000>;
145 #atmel,pll-clk-output-range-cells = <4>;
146 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
147 695000000 750000000 1 0
148 645000000 700000000 2 0
149 595000000 650000000 3 0
150 545000000 600000000 0 1
151 495000000 555000000 1 1
152 445000000 500000000 2 1
153 400000000 450000000 3 1>;
154 };
155
156 plladiv: plladivck {
157 compatible = "atmel,at91sam9x5-clk-plldiv";
158 #clock-cells = <0>;
159 clocks = <&plla>;
160 };
161
162 utmi: utmick {
163 compatible = "atmel,at91sam9x5-clk-utmi";
164 #clock-cells = <0>;
165 interrupts-extended = <&pmc AT91_PMC_LOCKU>;
166 clocks = <&main>;
167 };
168
169 mck: masterck {
170 compatible = "atmel,at91rm9200-clk-master";
171 #clock-cells = <0>;
172 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
173 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
174 atmel,clk-output-range = <0 133333333>;
175 atmel,clk-divisors = <1 2 4 3>;
176 };
177
178 usb: usbck {
179 compatible = "atmel,at91sam9x5-clk-usb";
180 #clock-cells = <0>;
181 clocks = <&plladiv>, <&utmi>;
182 };
183
184 prog: progck {
185 compatible = "atmel,at91sam9g45-clk-programmable";
186 #address-cells = <1>;
187 #size-cells = <0>;
188 interrupt-parent = <&pmc>;
189 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
190
191 prog0: prog0 {
192 #clock-cells = <0>;
193 reg = <0>;
194 interrupts = <AT91_PMC_PCKRDY(0)>;
195 };
196
197 prog1: prog1 {
198 #clock-cells = <0>;
199 reg = <1>;
200 interrupts = <AT91_PMC_PCKRDY(1)>;
201 };
202 };
203
204 systemck {
205 compatible = "atmel,at91rm9200-clk-system";
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 ddrck: ddrck {
210 #clock-cells = <0>;
211 reg = <2>;
212 clocks = <&mck>;
213 };
214
215 uhpck: uhpck {
216 #clock-cells = <0>;
217 reg = <6>;
218 clocks = <&usb>;
219 };
220
221 pck0: pck0 {
222 #clock-cells = <0>;
223 reg = <8>;
224 clocks = <&prog0>;
225 };
226
227 pck1: pck1 {
228 #clock-cells = <0>;
229 reg = <9>;
230 clocks = <&prog1>;
231 };
232 };
233
234 periphck {
235 compatible = "atmel,at91rm9200-clk-peripheral";
236 #address-cells = <1>;
237 #size-cells = <0>;
238 clocks = <&mck>;
239
240 pioA_clk: pioA_clk {
241 #clock-cells = <0>;
242 reg = <2>;
243 };
244
245 pioB_clk: pioB_clk {
246 #clock-cells = <0>;
247 reg = <3>;
248 };
249
250 pioC_clk: pioC_clk {
251 #clock-cells = <0>;
252 reg = <4>;
253 };
254
255 pioDE_clk: pioDE_clk {
256 #clock-cells = <0>;
257 reg = <5>;
258 };
259
260 trng_clk: trng_clk {
261 #clock-cells = <0>;
262 reg = <6>;
263 };
264
265 usart0_clk: usart0_clk {
266 #clock-cells = <0>;
267 reg = <7>;
268 };
269
270 usart1_clk: usart1_clk {
271 #clock-cells = <0>;
272 reg = <8>;
273 };
274
275 usart2_clk: usart2_clk {
276 #clock-cells = <0>;
277 reg = <9>;
278 };
279
280 usart3_clk: usart3_clk {
281 #clock-cells = <0>;
282 reg = <10>;
283 };
284
285 mci0_clk: mci0_clk {
286 #clock-cells = <0>;
287 reg = <11>;
288 };
289
290 twi0_clk: twi0_clk {
291 #clock-cells = <0>;
292 reg = <12>;
293 };
294
295 twi1_clk: twi1_clk {
296 #clock-cells = <0>;
297 reg = <13>;
298 };
299
300 spi0_clk: spi0_clk {
301 #clock-cells = <0>;
302 reg = <14>;
303 };
304
305 spi1_clk: spi1_clk {
306 #clock-cells = <0>;
307 reg = <15>;
308 };
309
310 ssc0_clk: ssc0_clk {
311 #clock-cells = <0>;
312 reg = <16>;
313 };
314
315 ssc1_clk: ssc1_clk {
316 #clock-cells = <0>;
317 reg = <17>;
318 };
319
320 tcb0_clk: tcb0_clk {
321 #clock-cells = <0>;
322 reg = <18>;
323 };
324
325 pwm_clk: pwm_clk {
326 #clock-cells = <0>;
327 reg = <19>;
328 };
329
330 adc_clk: adc_clk {
331 #clock-cells = <0>;
332 reg = <20>;
333 };
334
335 dma0_clk: dma0_clk {
336 #clock-cells = <0>;
337 reg = <21>;
338 };
339
340 uhphs_clk: uhphs_clk {
341 #clock-cells = <0>;
342 reg = <22>;
343 };
344
345 lcd_clk: lcd_clk {
346 #clock-cells = <0>;
347 reg = <23>;
348 };
349
350 ac97_clk: ac97_clk {
351 #clock-cells = <0>;
352 reg = <24>;
353 };
354
355 macb0_clk: macb0_clk {
356 #clock-cells = <0>;
357 reg = <25>;
358 };
359
360 isi_clk: isi_clk {
361 #clock-cells = <0>;
362 reg = <26>;
363 };
364
365 udphs_clk: udphs_clk {
366 #clock-cells = <0>;
367 reg = <27>;
368 };
369
370 aestdessha_clk: aestdessha_clk {
371 #clock-cells = <0>;
372 reg = <28>;
373 };
374
375 mci1_clk: mci1_clk {
376 #clock-cells = <0>;
377 reg = <29>;
378 };
379
380 vdec_clk: vdec_clk {
381 #clock-cells = <0>;
382 reg = <30>;
383 };
384 };
385 };
386
387 rstc@fffffd00 {
388 compatible = "atmel,at91sam9g45-rstc";
389 reg = <0xfffffd00 0x10>;
390 };
391
392 pit: timer@fffffd30 {
393 compatible = "atmel,at91sam9260-pit";
394 reg = <0xfffffd30 0xf>;
395 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
396 clocks = <&mck>;
397 };
398
399
400 shdwc@fffffd10 {
401 compatible = "atmel,at91sam9rl-shdwc";
402 reg = <0xfffffd10 0x10>;
403 };
404
405 tcb0: timer@fff7c000 {
406 compatible = "atmel,at91rm9200-tcb";
407 reg = <0xfff7c000 0x100>;
408 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
409 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
410 clock-names = "t0_clk", "t1_clk", "t2_clk";
411 };
412
413 tcb1: timer@fffd4000 {
414 compatible = "atmel,at91rm9200-tcb";
415 reg = <0xfffd4000 0x100>;
416 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
417 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
418 clock-names = "t0_clk", "t1_clk", "t2_clk";
419 };
420
421 dma: dma-controller@ffffec00 {
422 compatible = "atmel,at91sam9g45-dma";
423 reg = <0xffffec00 0x200>;
424 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
425 #dma-cells = <2>;
426 clocks = <&dma0_clk>;
427 clock-names = "dma_clk";
428 };
429
430 pinctrl@fffff200 {
431 #address-cells = <1>;
432 #size-cells = <1>;
433 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
434 ranges = <0xfffff200 0xfffff200 0xa00>;
435
436 atmel,mux-mask = <
437 /* A B */
438 0xffffffff 0xffc003ff /* pioA */
439 0xffffffff 0x800f8f00 /* pioB */
440 0xffffffff 0x00000e00 /* pioC */
441 0xffffffff 0xff0c1381 /* pioD */
442 0xffffffff 0x81ffff81 /* pioE */
443 >;
444
445 /* shared pinctrl settings */
446 adc0 {
447 pinctrl_adc0_adtrg: adc0_adtrg {
448 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
449 };
450 pinctrl_adc0_ad0: adc0_ad0 {
451 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
452 };
453 pinctrl_adc0_ad1: adc0_ad1 {
454 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
455 };
456 pinctrl_adc0_ad2: adc0_ad2 {
457 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
458 };
459 pinctrl_adc0_ad3: adc0_ad3 {
460 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
461 };
462 pinctrl_adc0_ad4: adc0_ad4 {
463 atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
464 };
465 pinctrl_adc0_ad5: adc0_ad5 {
466 atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
467 };
468 pinctrl_adc0_ad6: adc0_ad6 {
469 atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
470 };
471 pinctrl_adc0_ad7: adc0_ad7 {
472 atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
473 };
474 };
475
476 dbgu {
477 pinctrl_dbgu: dbgu-0 {
478 atmel,pins =
479 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
480 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
481 };
482 };
483
484 i2c0 {
485 pinctrl_i2c0: i2c0-0 {
486 atmel,pins =
487 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
488 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
489 };
490 };
491
492 i2c1 {
493 pinctrl_i2c1: i2c1-0 {
494 atmel,pins =
495 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
496 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
497 };
498 };
499
500 isi {
501 pinctrl_isi: isi-0 {
502 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
503 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */
504 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
505 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */
506 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
507 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
508 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
509 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
510 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
511 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
512 AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
513 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
514 AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
515 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
516 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */
517 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>;
518 };
519 };
520
521 usart0 {
522 pinctrl_usart0: usart0-0 {
523 atmel,pins =
524 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
525 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
526 };
527
528 pinctrl_usart0_rts: usart0_rts-0 {
529 atmel,pins =
530 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
531 };
532
533 pinctrl_usart0_cts: usart0_cts-0 {
534 atmel,pins =
535 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
536 };
537 };
538
539 uart1 {
540 pinctrl_usart1: usart1-0 {
541 atmel,pins =
542 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
543 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
544 };
545
546 pinctrl_usart1_rts: usart1_rts-0 {
547 atmel,pins =
548 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
549 };
550
551 pinctrl_usart1_cts: usart1_cts-0 {
552 atmel,pins =
553 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
554 };
555 };
556
557 usart2 {
558 pinctrl_usart2: usart2-0 {
559 atmel,pins =
560 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
561 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
562 };
563
564 pinctrl_usart2_rts: usart2_rts-0 {
565 atmel,pins =
566 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
567 };
568
569 pinctrl_usart2_cts: usart2_cts-0 {
570 atmel,pins =
571 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
572 };
573 };
574
575 usart3 {
576 pinctrl_usart3: usart3-0 {
577 atmel,pins =
578 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
579 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
580 };
581
582 pinctrl_usart3_rts: usart3_rts-0 {
583 atmel,pins =
584 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
585 };
586
587 pinctrl_usart3_cts: usart3_cts-0 {
588 atmel,pins =
589 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
590 };
591 };
592
593 nand {
594 pinctrl_nand: nand-0 {
595 atmel,pins =
596 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
597 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
598 };
599 };
600
601 macb {
602 pinctrl_macb_rmii: macb_rmii-0 {
603 atmel,pins =
604 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
605 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
606 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
607 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
608 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
609 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
610 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
611 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
612 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
613 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
614 };
615
616 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
617 atmel,pins =
618 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
619 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
620 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
621 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
622 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
623 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
624 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
625 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
626 };
627 };
628
629 mmc0 {
630 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
631 atmel,pins =
632 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
633 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
634 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
635 };
636
637 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
638 atmel,pins =
639 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
640 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
641 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
642 };
643
644 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
645 atmel,pins =
646 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
647 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
648 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
649 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
650 };
651 };
652
653 mmc1 {
654 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
655 atmel,pins =
656 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
657 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
658 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
659 };
660
661 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
662 atmel,pins =
663 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
664 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
665 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
666 };
667
668 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
669 atmel,pins =
670 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
671 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
672 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
673 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
674 };
675 };
676
677 ssc0 {
678 pinctrl_ssc0_tx: ssc0_tx-0 {
679 atmel,pins =
680 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
681 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
682 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
683 };
684
685 pinctrl_ssc0_rx: ssc0_rx-0 {
686 atmel,pins =
687 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
688 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
689 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
690 };
691 };
692
693 ssc1 {
694 pinctrl_ssc1_tx: ssc1_tx-0 {
695 atmel,pins =
696 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
697 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
698 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
699 };
700
701 pinctrl_ssc1_rx: ssc1_rx-0 {
702 atmel,pins =
703 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
704 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
705 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
706 };
707 };
708
709 spi0 {
710 pinctrl_spi0: spi0-0 {
711 atmel,pins =
712 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
713 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
714 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
715 };
716 };
717
718 spi1 {
719 pinctrl_spi1: spi1-0 {
720 atmel,pins =
721 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
722 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
723 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
724 };
725 };
726
727 tcb0 {
728 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
729 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
730 };
731
732 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
733 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
734 };
735
736 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
737 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
738 };
739
740 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
741 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
742 };
743
744 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
745 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
746 };
747
748 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
749 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
750 };
751
752 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
753 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
754 };
755
756 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
757 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
758 };
759
760 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
761 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
762 };
763 };
764
765 tcb1 {
766 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
767 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
768 };
769
770 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
771 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
772 };
773
774 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
775 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
776 };
777
778 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
779 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
780 };
781
782 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
783 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
784 };
785
786 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
787 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
788 };
789
790 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
791 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
792 };
793
794 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
795 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
796 };
797
798 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
799 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
800 };
801 };
802
803 fb {
804 pinctrl_fb: fb-0 {
805 atmel,pins =
806 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
807 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
808 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
809 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
810 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
811 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
812 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
813 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
814 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
815 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
816 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
817 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
818 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
819 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
820 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
821 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
822 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
823 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
824 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
825 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
826 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
827 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
828 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
829 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
830 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
831 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
832 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
833 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
834 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
835 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
836 };
837 };
838
839 pioA: gpio@fffff200 {
840 compatible = "atmel,at91rm9200-gpio";
841 reg = <0xfffff200 0x200>;
842 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
843 #gpio-cells = <2>;
844 gpio-controller;
845 interrupt-controller;
846 #interrupt-cells = <2>;
847 clocks = <&pioA_clk>;
848 };
849
850 pioB: gpio@fffff400 {
851 compatible = "atmel,at91rm9200-gpio";
852 reg = <0xfffff400 0x200>;
853 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
854 #gpio-cells = <2>;
855 gpio-controller;
856 interrupt-controller;
857 #interrupt-cells = <2>;
858 clocks = <&pioB_clk>;
859 };
860
861 pioC: gpio@fffff600 {
862 compatible = "atmel,at91rm9200-gpio";
863 reg = <0xfffff600 0x200>;
864 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
865 #gpio-cells = <2>;
866 gpio-controller;
867 interrupt-controller;
868 #interrupt-cells = <2>;
869 clocks = <&pioC_clk>;
870 };
871
872 pioD: gpio@fffff800 {
873 compatible = "atmel,at91rm9200-gpio";
874 reg = <0xfffff800 0x200>;
875 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
876 #gpio-cells = <2>;
877 gpio-controller;
878 interrupt-controller;
879 #interrupt-cells = <2>;
880 clocks = <&pioDE_clk>;
881 };
882
883 pioE: gpio@fffffa00 {
884 compatible = "atmel,at91rm9200-gpio";
885 reg = <0xfffffa00 0x200>;
886 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
887 #gpio-cells = <2>;
888 gpio-controller;
889 interrupt-controller;
890 #interrupt-cells = <2>;
891 clocks = <&pioDE_clk>;
892 };
893 };
894
895 dbgu: serial@ffffee00 {
896 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
897 reg = <0xffffee00 0x200>;
898 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
899 pinctrl-names = "default";
900 pinctrl-0 = <&pinctrl_dbgu>;
901 clocks = <&mck>;
902 clock-names = "usart";
903 status = "disabled";
904 };
905
906 usart0: serial@fff8c000 {
907 compatible = "atmel,at91sam9260-usart";
908 reg = <0xfff8c000 0x200>;
909 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
910 atmel,use-dma-rx;
911 atmel,use-dma-tx;
912 pinctrl-names = "default";
913 pinctrl-0 = <&pinctrl_usart0>;
914 clocks = <&usart0_clk>;
915 clock-names = "usart";
916 status = "disabled";
917 };
918
919 usart1: serial@fff90000 {
920 compatible = "atmel,at91sam9260-usart";
921 reg = <0xfff90000 0x200>;
922 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
923 atmel,use-dma-rx;
924 atmel,use-dma-tx;
925 pinctrl-names = "default";
926 pinctrl-0 = <&pinctrl_usart1>;
927 clocks = <&usart1_clk>;
928 clock-names = "usart";
929 status = "disabled";
930 };
931
932 usart2: serial@fff94000 {
933 compatible = "atmel,at91sam9260-usart";
934 reg = <0xfff94000 0x200>;
935 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
936 atmel,use-dma-rx;
937 atmel,use-dma-tx;
938 pinctrl-names = "default";
939 pinctrl-0 = <&pinctrl_usart2>;
940 clocks = <&usart2_clk>;
941 clock-names = "usart";
942 status = "disabled";
943 };
944
945 usart3: serial@fff98000 {
946 compatible = "atmel,at91sam9260-usart";
947 reg = <0xfff98000 0x200>;
948 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
949 atmel,use-dma-rx;
950 atmel,use-dma-tx;
951 pinctrl-names = "default";
952 pinctrl-0 = <&pinctrl_usart3>;
953 clocks = <&usart3_clk>;
954 clock-names = "usart";
955 status = "disabled";
956 };
957
958 macb0: ethernet@fffbc000 {
959 compatible = "cdns,at91sam9260-macb", "cdns,macb";
960 reg = <0xfffbc000 0x100>;
961 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
962 pinctrl-names = "default";
963 pinctrl-0 = <&pinctrl_macb_rmii>;
964 clocks = <&macb0_clk>, <&macb0_clk>;
965 clock-names = "hclk", "pclk";
966 status = "disabled";
967 };
968
969 trng@fffcc000 {
970 compatible = "atmel,at91sam9g45-trng";
971 reg = <0xfffcc000 0x4000>;
972 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
973 clocks = <&trng_clk>;
974 };
975
976 i2c0: i2c@fff84000 {
977 compatible = "atmel,at91sam9g10-i2c";
978 reg = <0xfff84000 0x100>;
979 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
980 pinctrl-names = "default";
981 pinctrl-0 = <&pinctrl_i2c0>;
982 #address-cells = <1>;
983 #size-cells = <0>;
984 clocks = <&twi0_clk>;
985 status = "disabled";
986 };
987
988 i2c1: i2c@fff88000 {
989 compatible = "atmel,at91sam9g10-i2c";
990 reg = <0xfff88000 0x100>;
991 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
992 pinctrl-names = "default";
993 pinctrl-0 = <&pinctrl_i2c1>;
994 #address-cells = <1>;
995 #size-cells = <0>;
996 clocks = <&twi1_clk>;
997 status = "disabled";
998 };
999
1000 ssc0: ssc@fff9c000 {
1001 compatible = "atmel,at91sam9g45-ssc";
1002 reg = <0xfff9c000 0x4000>;
1003 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
1004 pinctrl-names = "default";
1005 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
1006 clocks = <&ssc0_clk>;
1007 clock-names = "pclk";
1008 status = "disabled";
1009 };
1010
1011 ssc1: ssc@fffa0000 {
1012 compatible = "atmel,at91sam9g45-ssc";
1013 reg = <0xfffa0000 0x4000>;
1014 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
1015 pinctrl-names = "default";
1016 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1017 clocks = <&ssc1_clk>;
1018 clock-names = "pclk";
1019 status = "disabled";
1020 };
1021
1022 adc0: adc@fffb0000 {
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025 compatible = "atmel,at91sam9g45-adc";
1026 reg = <0xfffb0000 0x100>;
1027 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
1028 clocks = <&adc_clk>, <&adc_op_clk>;
1029 clock-names = "adc_clk", "adc_op_clk";
1030 atmel,adc-channels-used = <0xff>;
1031 atmel,adc-vref = <3300>;
1032 atmel,adc-startup-time = <40>;
1033 atmel,adc-res = <8 10>;
1034 atmel,adc-res-names = "lowres", "highres";
1035 atmel,adc-use-res = "highres";
1036
1037 trigger@0 {
1038 reg = <0>;
1039 trigger-name = "external-rising";
1040 trigger-value = <0x1>;
1041 trigger-external;
1042 };
1043 trigger@1 {
1044 reg = <1>;
1045 trigger-name = "external-falling";
1046 trigger-value = <0x2>;
1047 trigger-external;
1048 };
1049
1050 trigger@2 {
1051 reg = <2>;
1052 trigger-name = "external-any";
1053 trigger-value = <0x3>;
1054 trigger-external;
1055 };
1056
1057 trigger@3 {
1058 reg = <3>;
1059 trigger-name = "continuous";
1060 trigger-value = <0x6>;
1061 };
1062 };
1063
1064 isi@fffb4000 {
1065 compatible = "atmel,at91sam9g45-isi";
1066 reg = <0xfffb4000 0x4000>;
1067 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
1068 clocks = <&isi_clk>;
1069 clock-names = "isi_clk";
1070 pinctrl-names = "default";
1071 pinctrl-0 = <&pinctrl_isi>;
1072 status = "disabled";
1073 };
1074
1075 pwm0: pwm@fffb8000 {
1076 compatible = "atmel,at91sam9rl-pwm";
1077 reg = <0xfffb8000 0x300>;
1078 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
1079 #pwm-cells = <3>;
1080 clocks = <&pwm_clk>;
1081 status = "disabled";
1082 };
1083
1084 mmc0: mmc@fff80000 {
1085 compatible = "atmel,hsmci";
1086 reg = <0xfff80000 0x600>;
1087 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1088 pinctrl-names = "default";
1089 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
1090 dma-names = "rxtx";
1091 #address-cells = <1>;
1092 #size-cells = <0>;
1093 clocks = <&mci0_clk>;
1094 clock-names = "mci_clk";
1095 status = "disabled";
1096 };
1097
1098 mmc1: mmc@fffd0000 {
1099 compatible = "atmel,hsmci";
1100 reg = <0xfffd0000 0x600>;
1101 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
1102 pinctrl-names = "default";
1103 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
1104 dma-names = "rxtx";
1105 #address-cells = <1>;
1106 #size-cells = <0>;
1107 clocks = <&mci1_clk>;
1108 clock-names = "mci_clk";
1109 status = "disabled";
1110 };
1111
1112 watchdog@fffffd40 {
1113 compatible = "atmel,at91sam9260-wdt";
1114 reg = <0xfffffd40 0x10>;
1115 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1116 atmel,watchdog-type = "hardware";
1117 atmel,reset-type = "all";
1118 atmel,dbg-halt;
1119 status = "disabled";
1120 };
1121
1122 spi0: spi@fffa4000 {
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 compatible = "atmel,at91rm9200-spi";
1126 reg = <0xfffa4000 0x200>;
1127 interrupts = <14 4 3>;
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&pinctrl_spi0>;
1130 clocks = <&spi0_clk>;
1131 clock-names = "spi_clk";
1132 status = "disabled";
1133 };
1134
1135 spi1: spi@fffa8000 {
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 compatible = "atmel,at91rm9200-spi";
1139 reg = <0xfffa8000 0x200>;
1140 interrupts = <15 4 3>;
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&pinctrl_spi1>;
1143 clocks = <&spi1_clk>;
1144 clock-names = "spi_clk";
1145 status = "disabled";
1146 };
1147
1148 usb2: gadget@fff78000 {
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 compatible = "atmel,at91sam9g45-udc";
1152 reg = <0x00600000 0x80000
1153 0xfff78000 0x400>;
1154 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1155 clocks = <&udphs_clk>, <&utmi>;
1156 clock-names = "pclk", "hclk";
1157 status = "disabled";
1158
1159 ep0 {
1160 reg = <0>;
1161 atmel,fifo-size = <64>;
1162 atmel,nb-banks = <1>;
1163 };
1164
1165 ep1 {
1166 reg = <1>;
1167 atmel,fifo-size = <1024>;
1168 atmel,nb-banks = <2>;
1169 atmel,can-dma;
1170 atmel,can-isoc;
1171 };
1172
1173 ep2 {
1174 reg = <2>;
1175 atmel,fifo-size = <1024>;
1176 atmel,nb-banks = <2>;
1177 atmel,can-dma;
1178 atmel,can-isoc;
1179 };
1180
1181 ep3 {
1182 reg = <3>;
1183 atmel,fifo-size = <1024>;
1184 atmel,nb-banks = <3>;
1185 atmel,can-dma;
1186 };
1187
1188 ep4 {
1189 reg = <4>;
1190 atmel,fifo-size = <1024>;
1191 atmel,nb-banks = <3>;
1192 atmel,can-dma;
1193 };
1194
1195 ep5 {
1196 reg = <5>;
1197 atmel,fifo-size = <1024>;
1198 atmel,nb-banks = <3>;
1199 atmel,can-dma;
1200 atmel,can-isoc;
1201 };
1202
1203 ep6 {
1204 reg = <6>;
1205 atmel,fifo-size = <1024>;
1206 atmel,nb-banks = <3>;
1207 atmel,can-dma;
1208 atmel,can-isoc;
1209 };
1210 };
1211
1212 sckc@fffffd50 {
1213 compatible = "atmel,at91sam9x5-sckc";
1214 reg = <0xfffffd50 0x4>;
1215
1216 slow_osc: slow_osc {
1217 compatible = "atmel,at91sam9x5-clk-slow-osc";
1218 #clock-cells = <0>;
1219 atmel,startup-time-usec = <1200000>;
1220 clocks = <&slow_xtal>;
1221 };
1222
1223 slow_rc_osc: slow_rc_osc {
1224 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1225 #clock-cells = <0>;
1226 atmel,startup-time-usec = <75>;
1227 clock-frequency = <32768>;
1228 clock-accuracy = <50000000>;
1229 };
1230
1231 clk32k: slck {
1232 compatible = "atmel,at91sam9x5-clk-slow";
1233 #clock-cells = <0>;
1234 clocks = <&slow_rc_osc &slow_osc>;
1235 };
1236 };
1237
1238 rtc@fffffd20 {
1239 compatible = "atmel,at91sam9260-rtt";
1240 reg = <0xfffffd20 0x10>;
1241 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1242 clocks = <&clk32k>;
1243 status = "disabled";
1244 };
1245
1246 rtc@fffffdb0 {
1247 compatible = "atmel,at91rm9200-rtc";
1248 reg = <0xfffffdb0 0x30>;
1249 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1250 status = "disabled";
1251 };
1252
1253 gpbr: syscon@fffffd60 {
1254 compatible = "atmel,at91sam9260-gpbr", "syscon";
1255 reg = <0xfffffd60 0x10>;
1256 status = "disabled";
1257 };
1258 };
1259
1260 fb0: fb@0x00500000 {
1261 compatible = "atmel,at91sam9g45-lcdc";
1262 reg = <0x00500000 0x1000>;
1263 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
1264 pinctrl-names = "default";
1265 pinctrl-0 = <&pinctrl_fb>;
1266 clocks = <&lcd_clk>, <&lcd_clk>;
1267 clock-names = "hclk", "lcdc_clk";
1268 status = "disabled";
1269 };
1270
1271 nand0: nand@40000000 {
1272 compatible = "atmel,at91rm9200-nand";
1273 #address-cells = <1>;
1274 #size-cells = <1>;
1275 reg = <0x40000000 0x10000000
1276 0xffffe200 0x200
1277 >;
1278 atmel,nand-addr-offset = <21>;
1279 atmel,nand-cmd-offset = <22>;
1280 atmel,nand-has-dma;
1281 pinctrl-names = "default";
1282 pinctrl-0 = <&pinctrl_nand>;
1283 gpios = <&pioC 8 GPIO_ACTIVE_HIGH
1284 &pioC 14 GPIO_ACTIVE_HIGH
1285 0
1286 >;
1287 status = "disabled";
1288 };
1289
1290 usb0: ohci@00700000 {
1291 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1292 reg = <0x00700000 0x100000>;
1293 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1294 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1295 clock-names = "ohci_clk", "hclk", "uhpck";
1296 status = "disabled";
1297 };
1298
1299 usb1: ehci@00800000 {
1300 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1301 reg = <0x00800000 0x100000>;
1302 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1303 clocks = <&utmi>, <&uhphs_clk>;
1304 clock-names = "usb_clk", "ehci_clk";
1305 status = "disabled";
1306 };
1307 };
1308
1309 i2c@0 {
1310 compatible = "i2c-gpio";
1311 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
1312 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
1313 >;
1314 i2c-gpio,sda-open-drain;
1315 i2c-gpio,scl-open-drain;
1316 i2c-gpio,delay-us = <5>; /* ~100 kHz */
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1319 status = "disabled";
1320 };
1321 };
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