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ARM: dts: at91: Declare EBI/NAND controllers
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1 /*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12 #include "skeleton.dtsi"
13 #include <dt-bindings/dma/at91.h>
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
18
19 / {
20 model = "Atmel AT91SAM9G45 family SoC";
21 compatible = "atmel,at91sam9g45";
22 interrupt-parent = <&aic>;
23
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 serial4 = &usart3;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
36 tcb1 = &tcb1;
37 i2c0 = &i2c0;
38 i2c1 = &i2c1;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
41 pwm0 = &pwm0;
42 };
43 cpus {
44 #address-cells = <0>;
45 #size-cells = <0>;
46
47 cpu {
48 compatible = "arm,arm926ej-s";
49 device_type = "cpu";
50 };
51 };
52
53 memory {
54 reg = <0x70000000 0x10000000>;
55 };
56
57 clocks {
58 slow_xtal: slow_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 main_xtal: main_xtal {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <0>;
68 };
69
70 adc_op_clk: adc_op_clk{
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <300000>;
74 };
75 };
76
77 sram: sram@00300000 {
78 compatible = "mmio-sram";
79 reg = <0x00300000 0x10000>;
80 };
81
82 ahb {
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges;
87
88 apb {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 aic: interrupt-controller@fffff000 {
95 #interrupt-cells = <3>;
96 compatible = "atmel,at91rm9200-aic";
97 interrupt-controller;
98 reg = <0xfffff000 0x200>;
99 atmel,external-irqs = <31>;
100 };
101
102 ramc0: ramc@ffffe400 {
103 compatible = "atmel,at91sam9g45-ddramc";
104 reg = <0xffffe400 0x200>;
105 clocks = <&ddrck>;
106 clock-names = "ddrck";
107 };
108
109 ramc1: ramc@ffffe600 {
110 compatible = "atmel,at91sam9g45-ddramc";
111 reg = <0xffffe600 0x200>;
112 clocks = <&ddrck>;
113 clock-names = "ddrck";
114 };
115
116 smc: smc@ffffe800 {
117 compatible = "atmel,at91sam9260-smc", "syscon";
118 reg = <0xffffe800 0x200>;
119 };
120
121 matrix: matrix@ffffea00 {
122 compatible = "atmel,at91sam9g45-matrix", "syscon";
123 reg = <0xffffea00 0x200>;
124 };
125
126 pmc: pmc@fffffc00 {
127 compatible = "atmel,at91sam9g45-pmc", "syscon";
128 reg = <0xfffffc00 0x100>;
129 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
130 interrupt-controller;
131 #address-cells = <1>;
132 #size-cells = <0>;
133 #interrupt-cells = <1>;
134
135 main_osc: main_osc {
136 compatible = "atmel,at91rm9200-clk-main-osc";
137 #clock-cells = <0>;
138 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
139 clocks = <&main_xtal>;
140 };
141
142 main: mainck {
143 compatible = "atmel,at91rm9200-clk-main";
144 #clock-cells = <0>;
145 clocks = <&main_osc>;
146 };
147
148 plla: pllack {
149 compatible = "atmel,at91rm9200-clk-pll";
150 #clock-cells = <0>;
151 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
152 clocks = <&main>;
153 reg = <0>;
154 atmel,clk-input-range = <2000000 32000000>;
155 #atmel,pll-clk-output-range-cells = <4>;
156 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
157 695000000 750000000 1 0
158 645000000 700000000 2 0
159 595000000 650000000 3 0
160 545000000 600000000 0 1
161 495000000 555000000 1 1
162 445000000 500000000 2 1
163 400000000 450000000 3 1>;
164 };
165
166 plladiv: plladivck {
167 compatible = "atmel,at91sam9x5-clk-plldiv";
168 #clock-cells = <0>;
169 clocks = <&plla>;
170 };
171
172 utmi: utmick {
173 compatible = "atmel,at91sam9x5-clk-utmi";
174 #clock-cells = <0>;
175 interrupts-extended = <&pmc AT91_PMC_LOCKU>;
176 clocks = <&main>;
177 };
178
179 mck: masterck {
180 compatible = "atmel,at91rm9200-clk-master";
181 #clock-cells = <0>;
182 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
183 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
184 atmel,clk-output-range = <0 133333333>;
185 atmel,clk-divisors = <1 2 4 3>;
186 };
187
188 usb: usbck {
189 compatible = "atmel,at91sam9x5-clk-usb";
190 #clock-cells = <0>;
191 clocks = <&plladiv>, <&utmi>;
192 };
193
194 prog: progck {
195 compatible = "atmel,at91sam9g45-clk-programmable";
196 #address-cells = <1>;
197 #size-cells = <0>;
198 interrupt-parent = <&pmc>;
199 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
200
201 prog0: prog0 {
202 #clock-cells = <0>;
203 reg = <0>;
204 interrupts = <AT91_PMC_PCKRDY(0)>;
205 };
206
207 prog1: prog1 {
208 #clock-cells = <0>;
209 reg = <1>;
210 interrupts = <AT91_PMC_PCKRDY(1)>;
211 };
212 };
213
214 systemck {
215 compatible = "atmel,at91rm9200-clk-system";
216 #address-cells = <1>;
217 #size-cells = <0>;
218
219 ddrck: ddrck {
220 #clock-cells = <0>;
221 reg = <2>;
222 clocks = <&mck>;
223 };
224
225 uhpck: uhpck {
226 #clock-cells = <0>;
227 reg = <6>;
228 clocks = <&usb>;
229 };
230
231 pck0: pck0 {
232 #clock-cells = <0>;
233 reg = <8>;
234 clocks = <&prog0>;
235 };
236
237 pck1: pck1 {
238 #clock-cells = <0>;
239 reg = <9>;
240 clocks = <&prog1>;
241 };
242 };
243
244 periphck {
245 compatible = "atmel,at91rm9200-clk-peripheral";
246 #address-cells = <1>;
247 #size-cells = <0>;
248 clocks = <&mck>;
249
250 pioA_clk: pioA_clk {
251 #clock-cells = <0>;
252 reg = <2>;
253 };
254
255 pioB_clk: pioB_clk {
256 #clock-cells = <0>;
257 reg = <3>;
258 };
259
260 pioC_clk: pioC_clk {
261 #clock-cells = <0>;
262 reg = <4>;
263 };
264
265 pioDE_clk: pioDE_clk {
266 #clock-cells = <0>;
267 reg = <5>;
268 };
269
270 trng_clk: trng_clk {
271 #clock-cells = <0>;
272 reg = <6>;
273 };
274
275 usart0_clk: usart0_clk {
276 #clock-cells = <0>;
277 reg = <7>;
278 };
279
280 usart1_clk: usart1_clk {
281 #clock-cells = <0>;
282 reg = <8>;
283 };
284
285 usart2_clk: usart2_clk {
286 #clock-cells = <0>;
287 reg = <9>;
288 };
289
290 usart3_clk: usart3_clk {
291 #clock-cells = <0>;
292 reg = <10>;
293 };
294
295 mci0_clk: mci0_clk {
296 #clock-cells = <0>;
297 reg = <11>;
298 };
299
300 twi0_clk: twi0_clk {
301 #clock-cells = <0>;
302 reg = <12>;
303 };
304
305 twi1_clk: twi1_clk {
306 #clock-cells = <0>;
307 reg = <13>;
308 };
309
310 spi0_clk: spi0_clk {
311 #clock-cells = <0>;
312 reg = <14>;
313 };
314
315 spi1_clk: spi1_clk {
316 #clock-cells = <0>;
317 reg = <15>;
318 };
319
320 ssc0_clk: ssc0_clk {
321 #clock-cells = <0>;
322 reg = <16>;
323 };
324
325 ssc1_clk: ssc1_clk {
326 #clock-cells = <0>;
327 reg = <17>;
328 };
329
330 tcb0_clk: tcb0_clk {
331 #clock-cells = <0>;
332 reg = <18>;
333 };
334
335 pwm_clk: pwm_clk {
336 #clock-cells = <0>;
337 reg = <19>;
338 };
339
340 adc_clk: adc_clk {
341 #clock-cells = <0>;
342 reg = <20>;
343 };
344
345 dma0_clk: dma0_clk {
346 #clock-cells = <0>;
347 reg = <21>;
348 };
349
350 uhphs_clk: uhphs_clk {
351 #clock-cells = <0>;
352 reg = <22>;
353 };
354
355 lcd_clk: lcd_clk {
356 #clock-cells = <0>;
357 reg = <23>;
358 };
359
360 ac97_clk: ac97_clk {
361 #clock-cells = <0>;
362 reg = <24>;
363 };
364
365 macb0_clk: macb0_clk {
366 #clock-cells = <0>;
367 reg = <25>;
368 };
369
370 isi_clk: isi_clk {
371 #clock-cells = <0>;
372 reg = <26>;
373 };
374
375 udphs_clk: udphs_clk {
376 #clock-cells = <0>;
377 reg = <27>;
378 };
379
380 aestdessha_clk: aestdessha_clk {
381 #clock-cells = <0>;
382 reg = <28>;
383 };
384
385 mci1_clk: mci1_clk {
386 #clock-cells = <0>;
387 reg = <29>;
388 };
389
390 vdec_clk: vdec_clk {
391 #clock-cells = <0>;
392 reg = <30>;
393 };
394 };
395 };
396
397 rstc@fffffd00 {
398 compatible = "atmel,at91sam9g45-rstc";
399 reg = <0xfffffd00 0x10>;
400 clocks = <&clk32k>;
401 };
402
403 pit: timer@fffffd30 {
404 compatible = "atmel,at91sam9260-pit";
405 reg = <0xfffffd30 0xf>;
406 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
407 clocks = <&mck>;
408 };
409
410
411 shdwc@fffffd10 {
412 compatible = "atmel,at91sam9rl-shdwc";
413 reg = <0xfffffd10 0x10>;
414 clocks = <&clk32k>;
415 };
416
417 tcb0: timer@fff7c000 {
418 compatible = "atmel,at91rm9200-tcb";
419 reg = <0xfff7c000 0x100>;
420 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
421 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
422 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
423 };
424
425 tcb1: timer@fffd4000 {
426 compatible = "atmel,at91rm9200-tcb";
427 reg = <0xfffd4000 0x100>;
428 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
429 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
430 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
431 };
432
433 dma: dma-controller@ffffec00 {
434 compatible = "atmel,at91sam9g45-dma";
435 reg = <0xffffec00 0x200>;
436 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
437 #dma-cells = <2>;
438 clocks = <&dma0_clk>;
439 clock-names = "dma_clk";
440 };
441
442 pinctrl@fffff200 {
443 #address-cells = <1>;
444 #size-cells = <1>;
445 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
446 ranges = <0xfffff200 0xfffff200 0xa00>;
447
448 atmel,mux-mask = <
449 /* A B */
450 0xffffffff 0xffc003ff /* pioA */
451 0xffffffff 0x800f8f00 /* pioB */
452 0xffffffff 0x00000e00 /* pioC */
453 0xffffffff 0xff0c1381 /* pioD */
454 0xffffffff 0x81ffff81 /* pioE */
455 >;
456
457 /* shared pinctrl settings */
458 adc0 {
459 pinctrl_adc0_adtrg: adc0_adtrg {
460 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
461 };
462 pinctrl_adc0_ad0: adc0_ad0 {
463 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
464 };
465 pinctrl_adc0_ad1: adc0_ad1 {
466 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
467 };
468 pinctrl_adc0_ad2: adc0_ad2 {
469 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
470 };
471 pinctrl_adc0_ad3: adc0_ad3 {
472 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
473 };
474 pinctrl_adc0_ad4: adc0_ad4 {
475 atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
476 };
477 pinctrl_adc0_ad5: adc0_ad5 {
478 atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
479 };
480 pinctrl_adc0_ad6: adc0_ad6 {
481 atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
482 };
483 pinctrl_adc0_ad7: adc0_ad7 {
484 atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
485 };
486 };
487
488 dbgu {
489 pinctrl_dbgu: dbgu-0 {
490 atmel,pins =
491 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
492 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
493 };
494 };
495
496 i2c0 {
497 pinctrl_i2c0: i2c0-0 {
498 atmel,pins =
499 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
500 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
501 };
502 };
503
504 i2c1 {
505 pinctrl_i2c1: i2c1-0 {
506 atmel,pins =
507 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
508 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
509 };
510 };
511
512 isi {
513 pinctrl_isi_data_0_7: isi-0-data-0-7 {
514 atmel,pins =
515 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
516 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
517 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
518 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
519 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
520 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
521 AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
522 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
523 AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
524 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
525 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
526 };
527
528 pinctrl_isi_data_8_9: isi-0-data-8-9 {
529 atmel,pins =
530 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
531 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
532 };
533
534 pinctrl_isi_data_10_11: isi-0-data-10-11 {
535 atmel,pins =
536 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
537 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
538 };
539 };
540
541 usart0 {
542 pinctrl_usart0: usart0-0 {
543 atmel,pins =
544 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
545 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
546 };
547
548 pinctrl_usart0_rts: usart0_rts-0 {
549 atmel,pins =
550 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
551 };
552
553 pinctrl_usart0_cts: usart0_cts-0 {
554 atmel,pins =
555 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
556 };
557 };
558
559 uart1 {
560 pinctrl_usart1: usart1-0 {
561 atmel,pins =
562 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
563 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
564 };
565
566 pinctrl_usart1_rts: usart1_rts-0 {
567 atmel,pins =
568 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
569 };
570
571 pinctrl_usart1_cts: usart1_cts-0 {
572 atmel,pins =
573 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
574 };
575 };
576
577 usart2 {
578 pinctrl_usart2: usart2-0 {
579 atmel,pins =
580 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
581 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
582 };
583
584 pinctrl_usart2_rts: usart2_rts-0 {
585 atmel,pins =
586 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
587 };
588
589 pinctrl_usart2_cts: usart2_cts-0 {
590 atmel,pins =
591 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
592 };
593 };
594
595 usart3 {
596 pinctrl_usart3: usart3-0 {
597 atmel,pins =
598 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
599 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
600 };
601
602 pinctrl_usart3_rts: usart3_rts-0 {
603 atmel,pins =
604 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
605 };
606
607 pinctrl_usart3_cts: usart3_cts-0 {
608 atmel,pins =
609 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
610 };
611 };
612
613 nand {
614 pinctrl_nand: nand-0 {
615 atmel,pins =
616 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
617 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
618 };
619 };
620
621 macb {
622 pinctrl_macb_rmii: macb_rmii-0 {
623 atmel,pins =
624 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
625 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
626 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
627 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
628 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
629 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
630 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
631 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
632 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
633 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
634 };
635
636 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
637 atmel,pins =
638 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
639 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
640 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
641 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
642 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
643 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
644 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
645 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
646 };
647 };
648
649 mmc0 {
650 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
651 atmel,pins =
652 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
653 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
654 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
655 };
656
657 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
658 atmel,pins =
659 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
660 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
661 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
662 };
663
664 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
665 atmel,pins =
666 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
667 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
668 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
669 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
670 };
671 };
672
673 mmc1 {
674 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
675 atmel,pins =
676 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
677 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
678 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
679 };
680
681 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
682 atmel,pins =
683 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
684 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
685 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
686 };
687
688 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
689 atmel,pins =
690 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
691 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
692 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
693 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
694 };
695 };
696
697 ssc0 {
698 pinctrl_ssc0_tx: ssc0_tx-0 {
699 atmel,pins =
700 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
701 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
702 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
703 };
704
705 pinctrl_ssc0_rx: ssc0_rx-0 {
706 atmel,pins =
707 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
708 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
709 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
710 };
711 };
712
713 ssc1 {
714 pinctrl_ssc1_tx: ssc1_tx-0 {
715 atmel,pins =
716 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
717 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
718 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
719 };
720
721 pinctrl_ssc1_rx: ssc1_rx-0 {
722 atmel,pins =
723 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
724 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
725 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
726 };
727 };
728
729 spi0 {
730 pinctrl_spi0: spi0-0 {
731 atmel,pins =
732 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
733 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
734 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
735 };
736 };
737
738 spi1 {
739 pinctrl_spi1: spi1-0 {
740 atmel,pins =
741 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
742 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
743 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
744 };
745 };
746
747 tcb0 {
748 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
749 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
750 };
751
752 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
753 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
754 };
755
756 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
757 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
758 };
759
760 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
761 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
762 };
763
764 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
765 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
766 };
767
768 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
769 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
770 };
771
772 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
773 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
774 };
775
776 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
777 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
778 };
779
780 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
781 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
782 };
783 };
784
785 tcb1 {
786 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
787 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
788 };
789
790 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
791 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
792 };
793
794 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
795 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
796 };
797
798 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
799 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
800 };
801
802 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
803 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
804 };
805
806 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
807 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
808 };
809
810 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
811 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
812 };
813
814 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
815 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
816 };
817
818 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
819 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
820 };
821 };
822
823 fb {
824 pinctrl_fb: fb-0 {
825 atmel,pins =
826 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
827 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
828 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
829 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
830 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
831 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
832 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
833 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
834 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
835 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
836 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
837 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
838 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
839 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
840 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
841 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
842 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
843 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
844 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
845 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
846 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
847 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
848 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
849 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
850 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
851 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
852 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
853 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
854 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
855 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
856 };
857 };
858
859 pioA: gpio@fffff200 {
860 compatible = "atmel,at91rm9200-gpio";
861 reg = <0xfffff200 0x200>;
862 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
863 #gpio-cells = <2>;
864 gpio-controller;
865 interrupt-controller;
866 #interrupt-cells = <2>;
867 clocks = <&pioA_clk>;
868 };
869
870 pioB: gpio@fffff400 {
871 compatible = "atmel,at91rm9200-gpio";
872 reg = <0xfffff400 0x200>;
873 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
874 #gpio-cells = <2>;
875 gpio-controller;
876 interrupt-controller;
877 #interrupt-cells = <2>;
878 clocks = <&pioB_clk>;
879 };
880
881 pioC: gpio@fffff600 {
882 compatible = "atmel,at91rm9200-gpio";
883 reg = <0xfffff600 0x200>;
884 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
885 #gpio-cells = <2>;
886 gpio-controller;
887 interrupt-controller;
888 #interrupt-cells = <2>;
889 clocks = <&pioC_clk>;
890 };
891
892 pioD: gpio@fffff800 {
893 compatible = "atmel,at91rm9200-gpio";
894 reg = <0xfffff800 0x200>;
895 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
896 #gpio-cells = <2>;
897 gpio-controller;
898 interrupt-controller;
899 #interrupt-cells = <2>;
900 clocks = <&pioDE_clk>;
901 };
902
903 pioE: gpio@fffffa00 {
904 compatible = "atmel,at91rm9200-gpio";
905 reg = <0xfffffa00 0x200>;
906 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
907 #gpio-cells = <2>;
908 gpio-controller;
909 interrupt-controller;
910 #interrupt-cells = <2>;
911 clocks = <&pioDE_clk>;
912 };
913 };
914
915 dbgu: serial@ffffee00 {
916 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
917 reg = <0xffffee00 0x200>;
918 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
919 pinctrl-names = "default";
920 pinctrl-0 = <&pinctrl_dbgu>;
921 clocks = <&mck>;
922 clock-names = "usart";
923 status = "disabled";
924 };
925
926 usart0: serial@fff8c000 {
927 compatible = "atmel,at91sam9260-usart";
928 reg = <0xfff8c000 0x200>;
929 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
930 atmel,use-dma-rx;
931 atmel,use-dma-tx;
932 pinctrl-names = "default";
933 pinctrl-0 = <&pinctrl_usart0>;
934 clocks = <&usart0_clk>;
935 clock-names = "usart";
936 status = "disabled";
937 };
938
939 usart1: serial@fff90000 {
940 compatible = "atmel,at91sam9260-usart";
941 reg = <0xfff90000 0x200>;
942 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
943 atmel,use-dma-rx;
944 atmel,use-dma-tx;
945 pinctrl-names = "default";
946 pinctrl-0 = <&pinctrl_usart1>;
947 clocks = <&usart1_clk>;
948 clock-names = "usart";
949 status = "disabled";
950 };
951
952 usart2: serial@fff94000 {
953 compatible = "atmel,at91sam9260-usart";
954 reg = <0xfff94000 0x200>;
955 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
956 atmel,use-dma-rx;
957 atmel,use-dma-tx;
958 pinctrl-names = "default";
959 pinctrl-0 = <&pinctrl_usart2>;
960 clocks = <&usart2_clk>;
961 clock-names = "usart";
962 status = "disabled";
963 };
964
965 usart3: serial@fff98000 {
966 compatible = "atmel,at91sam9260-usart";
967 reg = <0xfff98000 0x200>;
968 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
969 atmel,use-dma-rx;
970 atmel,use-dma-tx;
971 pinctrl-names = "default";
972 pinctrl-0 = <&pinctrl_usart3>;
973 clocks = <&usart3_clk>;
974 clock-names = "usart";
975 status = "disabled";
976 };
977
978 macb0: ethernet@fffbc000 {
979 compatible = "cdns,at91sam9260-macb", "cdns,macb";
980 reg = <0xfffbc000 0x100>;
981 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
982 pinctrl-names = "default";
983 pinctrl-0 = <&pinctrl_macb_rmii>;
984 clocks = <&macb0_clk>, <&macb0_clk>;
985 clock-names = "hclk", "pclk";
986 status = "disabled";
987 };
988
989 trng@fffcc000 {
990 compatible = "atmel,at91sam9g45-trng";
991 reg = <0xfffcc000 0x100>;
992 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
993 clocks = <&trng_clk>;
994 };
995
996 i2c0: i2c@fff84000 {
997 compatible = "atmel,at91sam9g10-i2c";
998 reg = <0xfff84000 0x100>;
999 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&pinctrl_i2c0>;
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 clocks = <&twi0_clk>;
1005 status = "disabled";
1006 };
1007
1008 i2c1: i2c@fff88000 {
1009 compatible = "atmel,at91sam9g10-i2c";
1010 reg = <0xfff88000 0x100>;
1011 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&pinctrl_i2c1>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1016 clocks = <&twi1_clk>;
1017 status = "disabled";
1018 };
1019
1020 ssc0: ssc@fff9c000 {
1021 compatible = "atmel,at91sam9g45-ssc";
1022 reg = <0xfff9c000 0x4000>;
1023 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
1026 clocks = <&ssc0_clk>;
1027 clock-names = "pclk";
1028 status = "disabled";
1029 };
1030
1031 ssc1: ssc@fffa0000 {
1032 compatible = "atmel,at91sam9g45-ssc";
1033 reg = <0xfffa0000 0x4000>;
1034 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
1035 pinctrl-names = "default";
1036 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1037 clocks = <&ssc1_clk>;
1038 clock-names = "pclk";
1039 status = "disabled";
1040 };
1041
1042 adc0: adc@fffb0000 {
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 compatible = "atmel,at91sam9g45-adc";
1046 reg = <0xfffb0000 0x100>;
1047 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
1048 clocks = <&adc_clk>, <&adc_op_clk>;
1049 clock-names = "adc_clk", "adc_op_clk";
1050 atmel,adc-channels-used = <0xff>;
1051 atmel,adc-vref = <3300>;
1052 atmel,adc-startup-time = <40>;
1053 atmel,adc-res = <8 10>;
1054 atmel,adc-res-names = "lowres", "highres";
1055 atmel,adc-use-res = "highres";
1056
1057 trigger0 {
1058 trigger-name = "external-rising";
1059 trigger-value = <0x1>;
1060 trigger-external;
1061 };
1062 trigger1 {
1063 trigger-name = "external-falling";
1064 trigger-value = <0x2>;
1065 trigger-external;
1066 };
1067
1068 trigger2 {
1069 trigger-name = "external-any";
1070 trigger-value = <0x3>;
1071 trigger-external;
1072 };
1073
1074 trigger3 {
1075 trigger-name = "continuous";
1076 trigger-value = <0x6>;
1077 };
1078 };
1079
1080 isi@fffb4000 {
1081 compatible = "atmel,at91sam9g45-isi";
1082 reg = <0xfffb4000 0x4000>;
1083 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
1084 clocks = <&isi_clk>;
1085 clock-names = "isi_clk";
1086 status = "disabled";
1087 port {
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 };
1091 };
1092
1093 pwm0: pwm@fffb8000 {
1094 compatible = "atmel,at91sam9rl-pwm";
1095 reg = <0xfffb8000 0x300>;
1096 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
1097 #pwm-cells = <3>;
1098 clocks = <&pwm_clk>;
1099 status = "disabled";
1100 };
1101
1102 mmc0: mmc@fff80000 {
1103 compatible = "atmel,hsmci";
1104 reg = <0xfff80000 0x600>;
1105 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1106 pinctrl-names = "default";
1107 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
1108 dma-names = "rxtx";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 clocks = <&mci0_clk>;
1112 clock-names = "mci_clk";
1113 status = "disabled";
1114 };
1115
1116 mmc1: mmc@fffd0000 {
1117 compatible = "atmel,hsmci";
1118 reg = <0xfffd0000 0x600>;
1119 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
1120 pinctrl-names = "default";
1121 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
1122 dma-names = "rxtx";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 clocks = <&mci1_clk>;
1126 clock-names = "mci_clk";
1127 status = "disabled";
1128 };
1129
1130 watchdog@fffffd40 {
1131 compatible = "atmel,at91sam9260-wdt";
1132 reg = <0xfffffd40 0x10>;
1133 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1134 clocks = <&clk32k>;
1135 atmel,watchdog-type = "hardware";
1136 atmel,reset-type = "all";
1137 atmel,dbg-halt;
1138 status = "disabled";
1139 };
1140
1141 spi0: spi@fffa4000 {
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144 compatible = "atmel,at91rm9200-spi";
1145 reg = <0xfffa4000 0x200>;
1146 interrupts = <14 4 3>;
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&pinctrl_spi0>;
1149 clocks = <&spi0_clk>;
1150 clock-names = "spi_clk";
1151 status = "disabled";
1152 };
1153
1154 spi1: spi@fffa8000 {
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1157 compatible = "atmel,at91rm9200-spi";
1158 reg = <0xfffa8000 0x200>;
1159 interrupts = <15 4 3>;
1160 pinctrl-names = "default";
1161 pinctrl-0 = <&pinctrl_spi1>;
1162 clocks = <&spi1_clk>;
1163 clock-names = "spi_clk";
1164 status = "disabled";
1165 };
1166
1167 usb2: gadget@fff78000 {
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1170 compatible = "atmel,at91sam9g45-udc";
1171 reg = <0x00600000 0x80000
1172 0xfff78000 0x400>;
1173 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1174 clocks = <&udphs_clk>, <&utmi>;
1175 clock-names = "pclk", "hclk";
1176 status = "disabled";
1177
1178 ep@0 {
1179 reg = <0>;
1180 atmel,fifo-size = <64>;
1181 atmel,nb-banks = <1>;
1182 };
1183
1184 ep@1 {
1185 reg = <1>;
1186 atmel,fifo-size = <1024>;
1187 atmel,nb-banks = <2>;
1188 atmel,can-dma;
1189 atmel,can-isoc;
1190 };
1191
1192 ep@2 {
1193 reg = <2>;
1194 atmel,fifo-size = <1024>;
1195 atmel,nb-banks = <2>;
1196 atmel,can-dma;
1197 atmel,can-isoc;
1198 };
1199
1200 ep@3 {
1201 reg = <3>;
1202 atmel,fifo-size = <1024>;
1203 atmel,nb-banks = <3>;
1204 atmel,can-dma;
1205 };
1206
1207 ep@4 {
1208 reg = <4>;
1209 atmel,fifo-size = <1024>;
1210 atmel,nb-banks = <3>;
1211 atmel,can-dma;
1212 };
1213
1214 ep@5 {
1215 reg = <5>;
1216 atmel,fifo-size = <1024>;
1217 atmel,nb-banks = <3>;
1218 atmel,can-dma;
1219 atmel,can-isoc;
1220 };
1221
1222 ep@6 {
1223 reg = <6>;
1224 atmel,fifo-size = <1024>;
1225 atmel,nb-banks = <3>;
1226 atmel,can-dma;
1227 atmel,can-isoc;
1228 };
1229 };
1230
1231 sckc@fffffd50 {
1232 compatible = "atmel,at91sam9x5-sckc";
1233 reg = <0xfffffd50 0x4>;
1234
1235 slow_osc: slow_osc {
1236 compatible = "atmel,at91sam9x5-clk-slow-osc";
1237 #clock-cells = <0>;
1238 atmel,startup-time-usec = <1200000>;
1239 clocks = <&slow_xtal>;
1240 };
1241
1242 slow_rc_osc: slow_rc_osc {
1243 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1244 #clock-cells = <0>;
1245 atmel,startup-time-usec = <75>;
1246 clock-frequency = <32768>;
1247 clock-accuracy = <50000000>;
1248 };
1249
1250 clk32k: slck {
1251 compatible = "atmel,at91sam9x5-clk-slow";
1252 #clock-cells = <0>;
1253 clocks = <&slow_rc_osc &slow_osc>;
1254 };
1255 };
1256
1257 rtc@fffffd20 {
1258 compatible = "atmel,at91sam9260-rtt";
1259 reg = <0xfffffd20 0x10>;
1260 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1261 clocks = <&clk32k>;
1262 status = "disabled";
1263 };
1264
1265 rtc@fffffdb0 {
1266 compatible = "atmel,at91rm9200-rtc";
1267 reg = <0xfffffdb0 0x30>;
1268 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1269 clocks = <&clk32k>;
1270 status = "disabled";
1271 };
1272
1273 gpbr: syscon@fffffd60 {
1274 compatible = "atmel,at91sam9260-gpbr", "syscon";
1275 reg = <0xfffffd60 0x10>;
1276 status = "disabled";
1277 };
1278 };
1279
1280 fb0: fb@0x00500000 {
1281 compatible = "atmel,at91sam9g45-lcdc";
1282 reg = <0x00500000 0x1000>;
1283 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&pinctrl_fb>;
1286 clocks = <&lcd_clk>, <&lcd_clk>;
1287 clock-names = "hclk", "lcdc_clk";
1288 status = "disabled";
1289 };
1290
1291 nand0: nand@40000000 {
1292 compatible = "atmel,at91rm9200-nand";
1293 #address-cells = <1>;
1294 #size-cells = <1>;
1295 reg = <0x40000000 0x10000000
1296 0xffffe200 0x200
1297 >;
1298 atmel,nand-addr-offset = <21>;
1299 atmel,nand-cmd-offset = <22>;
1300 atmel,nand-has-dma;
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&pinctrl_nand>;
1303 gpios = <&pioC 8 GPIO_ACTIVE_HIGH
1304 &pioC 14 GPIO_ACTIVE_HIGH
1305 0
1306 >;
1307 status = "disabled";
1308 };
1309
1310 usb0: ohci@00700000 {
1311 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1312 reg = <0x00700000 0x100000>;
1313 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1314 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1315 clock-names = "ohci_clk", "hclk", "uhpck";
1316 status = "disabled";
1317 };
1318
1319 usb1: ehci@00800000 {
1320 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1321 reg = <0x00800000 0x100000>;
1322 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1323 clocks = <&utmi>, <&uhphs_clk>;
1324 clock-names = "usb_clk", "ehci_clk";
1325 status = "disabled";
1326 };
1327
1328 ebi: ebi@10000000 {
1329 compatible = "atmel,at91sam9g45-ebi";
1330 #address-cells = <2>;
1331 #size-cells = <1>;
1332 atmel,smc = <&smc>;
1333 atmel,matrix = <&matrix>;
1334 reg = <0x10000000 0x80000000>;
1335 ranges = <0x0 0x0 0x10000000 0x10000000
1336 0x1 0x0 0x20000000 0x10000000
1337 0x2 0x0 0x30000000 0x10000000
1338 0x3 0x0 0x40000000 0x10000000
1339 0x4 0x0 0x50000000 0x10000000
1340 0x5 0x0 0x60000000 0x10000000>;
1341 clocks = <&mck>;
1342 status = "disabled";
1343
1344 nand_controller: nand-controller {
1345 compatible = "atmel,at91sam9g45-nand-controller";
1346 #address-cells = <2>;
1347 #size-cells = <1>;
1348 ranges;
1349 status = "disabled";
1350 };
1351 };
1352 };
1353
1354 i2c-gpio-0 {
1355 compatible = "i2c-gpio";
1356 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
1357 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
1358 >;
1359 i2c-gpio,sda-open-drain;
1360 i2c-gpio,scl-open-drain;
1361 i2c-gpio,delay-us = <5>; /* ~100 kHz */
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 status = "disabled";
1365 };
1366 };