2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
9 * Licensed under GPLv2 or later.
12 /include/ "skeleton.dtsi"
15 model = "Atmel AT91SAM9x5 family SoC";
16 compatible = "atmel,at91sam9x5";
17 interrupt-parent = <&aic>;
37 compatible = "arm,arm926ejs";
42 reg = <0x20000000 0x10000000>;
46 compatible = "simple-bus";
52 compatible = "simple-bus";
57 aic: interrupt-controller@fffff000 {
58 #interrupt-cells = <3>;
59 compatible = "atmel,at91rm9200-aic";
61 reg = <0xfffff000 0x200>;
62 atmel,external-irqs = <31>;
65 ramc0: ramc@ffffe800 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe800 0x200>;
71 compatible = "atmel,at91rm9200-pmc";
72 reg = <0xfffffc00 0x100>;
76 compatible = "atmel,at91sam9g45-rstc";
77 reg = <0xfffffe00 0x10>;
81 compatible = "atmel,at91sam9x5-shdwc";
82 reg = <0xfffffe10 0x10>;
86 compatible = "atmel,at91sam9260-pit";
87 reg = <0xfffffe30 0xf>;
91 tcb0: timer@f8008000 {
92 compatible = "atmel,at91sam9x5-tcb";
93 reg = <0xf8008000 0x100>;
94 interrupts = <17 4 0>;
97 tcb1: timer@f800c000 {
98 compatible = "atmel,at91sam9x5-tcb";
99 reg = <0xf800c000 0x100>;
100 interrupts = <17 4 0>;
103 dma0: dma-controller@ffffec00 {
104 compatible = "atmel,at91sam9g45-dma";
105 reg = <0xffffec00 0x200>;
106 interrupts = <20 4 0>;
109 dma1: dma-controller@ffffee00 {
110 compatible = "atmel,at91sam9g45-dma";
111 reg = <0xffffee00 0x200>;
112 interrupts = <21 4 0>;
116 #address-cells = <1>;
118 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
119 ranges = <0xfffff400 0xfffff400 0x800>;
121 /* shared pinctrl settings */
123 pinctrl_dbgu: dbgu-0 {
125 <0 9 0x1 0x0 /* PA9 periph A */
126 0 10 0x1 0x1>; /* PA10 periph A with pullup */
131 pinctrl_usart0: usart0-0 {
133 <0 0 0x1 0x1 /* PA0 periph A with pullup */
134 0 1 0x1 0x0>; /* PA1 periph A */
137 pinctrl_usart0_rts: usart0_rts-0 {
139 <0 2 0x1 0x0>; /* PA2 periph A */
142 pinctrl_usart0_cts: usart0_cts-0 {
144 <0 3 0x1 0x0>; /* PA3 periph A */
147 pinctrl_usart0_sck: usart0_sck-0 {
149 <0 4 0x1 0x0>; /* PA4 periph A */
154 pinctrl_usart1: usart1-0 {
156 <0 5 0x1 0x1 /* PA5 periph A with pullup */
157 0 6 0x1 0x0>; /* PA6 periph A */
160 pinctrl_usart1_rts: usart1_rts-0 {
162 <2 27 0x3 0x0>; /* PC27 periph C */
165 pinctrl_usart1_cts: usart1_cts-0 {
167 <2 28 0x3 0x0>; /* PC28 periph C */
170 pinctrl_usart1_sck: usart1_sck-0 {
172 <2 28 0x3 0x0>; /* PC29 periph C */
177 pinctrl_usart2: usart2-0 {
179 <0 7 0x1 0x1 /* PA7 periph A with pullup */
180 0 8 0x1 0x0>; /* PA8 periph A */
183 pinctrl_uart2_rts: uart2_rts-0 {
185 <1 0 0x2 0x0>; /* PB0 periph B */
188 pinctrl_uart2_cts: uart2_cts-0 {
190 <1 1 0x2 0x0>; /* PB1 periph B */
193 pinctrl_usart2_sck: usart2_sck-0 {
195 <1 2 0x2 0x0>; /* PB2 periph B */
200 pinctrl_usart3: usart3-0 {
202 <2 22 0x2 0x1 /* PC22 periph B with pullup */
203 2 23 0x2 0x0>; /* PC23 periph B */
206 pinctrl_usart3_rts: usart3_rts-0 {
208 <2 24 0x2 0x0>; /* PC24 periph B */
211 pinctrl_usart3_cts: usart3_cts-0 {
213 <2 25 0x2 0x0>; /* PC25 periph B */
216 pinctrl_usart3_sck: usart3_sck-0 {
218 <2 26 0x2 0x0>; /* PC26 periph B */
223 pinctrl_uart0: uart0-0 {
225 <2 8 0x3 0x0 /* PC8 periph C */
226 2 9 0x3 0x1>; /* PC9 periph C with pullup */
231 pinctrl_uart1: uart1-0 {
233 <2 16 0x3 0x0 /* PC16 periph C */
234 2 17 0x3 0x1>; /* PC17 periph C with pullup */
239 pinctrl_nand: nand-0 {
241 <3 0 0x1 0x0 /* PD0 periph A Read Enable */
242 3 1 0x1 0x0 /* PD1 periph A Write Enable */
243 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */
244 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */
245 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */
246 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */
247 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */
248 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */
249 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */
250 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */
251 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */
252 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */
253 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */
254 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
257 pinctrl_nand_16bits: nand_16bits-0 {
259 <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */
260 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */
261 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */
262 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */
263 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */
264 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */
265 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */
266 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
271 pinctrl_macb0_rmii: macb0_rmii-0 {
273 <1 0 0x1 0x0 /* PB0 periph A */
274 1 1 0x1 0x0 /* PB1 periph A */
275 1 2 0x1 0x0 /* PB2 periph A */
276 1 3 0x1 0x0 /* PB3 periph A */
277 1 4 0x1 0x0 /* PB4 periph A */
278 1 5 0x1 0x0 /* PB5 periph A */
279 1 6 0x1 0x0 /* PB6 periph A */
280 1 7 0x1 0x0 /* PB7 periph A */
281 1 9 0x1 0x0 /* PB9 periph A */
282 1 10 0x1 0x0>; /* PB10 periph A */
285 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
287 <1 8 0x1 0x0 /* PB8 periph A */
288 1 11 0x1 0x0 /* PB11 periph A */
289 1 12 0x1 0x0 /* PB12 periph A */
290 1 13 0x1 0x0 /* PB13 periph A */
291 1 14 0x1 0x0 /* PB14 periph A */
292 1 15 0x1 0x0 /* PB15 periph A */
293 1 16 0x1 0x0 /* PB16 periph A */
294 1 17 0x1 0x0>; /* PB17 periph A */
299 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
301 <0 17 0x1 0x0 /* PA17 periph A */
302 0 16 0x1 0x1 /* PA16 periph A with pullup */
303 0 15 0x1 0x1>; /* PA15 periph A with pullup */
306 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
308 <0 18 0x1 0x1 /* PA18 periph A with pullup */
309 0 19 0x1 0x1 /* PA19 periph A with pullup */
310 0 20 0x1 0x1>; /* PA20 periph A with pullup */
315 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
317 <0 13 0x2 0x0 /* PA13 periph B */
318 0 12 0x2 0x1 /* PA12 periph B with pullup */
319 0 11 0x2 0x1>; /* PA11 periph B with pullup */
322 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
324 <0 2 0x2 0x1 /* PA2 periph B with pullup */
325 0 3 0x2 0x1 /* PA3 periph B with pullup */
326 0 4 0x2 0x1>; /* PA4 periph B with pullup */
331 pinctrl_ssc0_tx: ssc0_tx-0 {
333 <0 24 0x2 0x0 /* PA24 periph B */
334 0 25 0x2 0x0 /* PA25 periph B */
335 0 26 0x2 0x0>; /* PA26 periph B */
338 pinctrl_ssc0_rx: ssc0_rx-0 {
340 <0 27 0x2 0x0 /* PA27 periph B */
341 0 28 0x2 0x0 /* PA28 periph B */
342 0 29 0x2 0x0>; /* PA29 periph B */
347 pinctrl_spi0: spi0-0 {
349 <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
350 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
351 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
356 pinctrl_spi1: spi1-0 {
358 <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
359 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
360 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
364 pioA: gpio@fffff400 {
365 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
366 reg = <0xfffff400 0x200>;
367 interrupts = <2 4 1>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
374 pioB: gpio@fffff600 {
375 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
376 reg = <0xfffff600 0x200>;
377 interrupts = <2 4 1>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
385 pioC: gpio@fffff800 {
386 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
387 reg = <0xfffff800 0x200>;
388 interrupts = <3 4 1>;
391 interrupt-controller;
392 #interrupt-cells = <2>;
395 pioD: gpio@fffffa00 {
396 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
397 reg = <0xfffffa00 0x200>;
398 interrupts = <3 4 1>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
408 compatible = "atmel,at91sam9g45-ssc";
409 reg = <0xf0010000 0x4000>;
410 interrupts = <28 4 5>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
417 compatible = "atmel,hsmci";
418 reg = <0xf0008000 0x600>;
419 interrupts = <12 4 0>;
420 #address-cells = <1>;
426 compatible = "atmel,hsmci";
427 reg = <0xf000c000 0x600>;
428 interrupts = <26 4 0>;
429 #address-cells = <1>;
434 dbgu: serial@fffff200 {
435 compatible = "atmel,at91sam9260-usart";
436 reg = <0xfffff200 0x200>;
437 interrupts = <1 4 7>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_dbgu>;
443 usart0: serial@f801c000 {
444 compatible = "atmel,at91sam9260-usart";
445 reg = <0xf801c000 0x200>;
446 interrupts = <5 4 5>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_usart0>;
452 usart1: serial@f8020000 {
453 compatible = "atmel,at91sam9260-usart";
454 reg = <0xf8020000 0x200>;
455 interrupts = <6 4 5>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&pinctrl_usart1>;
461 usart2: serial@f8024000 {
462 compatible = "atmel,at91sam9260-usart";
463 reg = <0xf8024000 0x200>;
464 interrupts = <7 4 5>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_usart2>;
470 macb0: ethernet@f802c000 {
471 compatible = "cdns,at32ap7000-macb", "cdns,macb";
472 reg = <0xf802c000 0x100>;
473 interrupts = <24 4 3>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_macb0_rmii>;
479 macb1: ethernet@f8030000 {
480 compatible = "cdns,at32ap7000-macb", "cdns,macb";
481 reg = <0xf8030000 0x100>;
482 interrupts = <27 4 3>;
487 compatible = "atmel,at91sam9x5-i2c";
488 reg = <0xf8010000 0x100>;
489 interrupts = <9 4 6>;
490 #address-cells = <1>;
496 compatible = "atmel,at91sam9x5-i2c";
497 reg = <0xf8014000 0x100>;
498 interrupts = <10 4 6>;
499 #address-cells = <1>;
505 compatible = "atmel,at91sam9x5-i2c";
506 reg = <0xf8018000 0x100>;
507 interrupts = <11 4 6>;
508 #address-cells = <1>;
514 compatible = "atmel,at91sam9260-adc";
515 reg = <0xf804c000 0x100>;
516 interrupts = <19 4 0>;
517 atmel,adc-use-external;
518 atmel,adc-channels-used = <0xffff>;
519 atmel,adc-vref = <3300>;
520 atmel,adc-num-channels = <12>;
521 atmel,adc-startup-time = <40>;
522 atmel,adc-channel-base = <0x50>;
523 atmel,adc-drdy-mask = <0x1000000>;
524 atmel,adc-status-register = <0x30>;
525 atmel,adc-trigger-register = <0xc0>;
528 trigger-name = "external-rising";
529 trigger-value = <0x1>;
534 trigger-name = "external-falling";
535 trigger-value = <0x2>;
540 trigger-name = "external-any";
541 trigger-value = <0x3>;
546 trigger-name = "continuous";
547 trigger-value = <0x6>;
552 #address-cells = <1>;
554 compatible = "atmel,at91rm9200-spi";
555 reg = <0xf0000000 0x100>;
556 interrupts = <13 4 3>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_spi0>;
563 #address-cells = <1>;
565 compatible = "atmel,at91rm9200-spi";
566 reg = <0xf0004000 0x100>;
567 interrupts = <14 4 3>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_spi1>;
574 nand0: nand@40000000 {
575 compatible = "atmel,at91rm9200-nand";
576 #address-cells = <1>;
578 reg = <0x40000000 0x10000000
579 0xffffe000 0x600 /* PMECC Registers */
580 0xffffe600 0x200 /* PMECC Error Location Registers */
581 0x00108000 0x18000 /* PMECC looup table in ROM code */
583 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
584 atmel,nand-addr-offset = <21>;
585 atmel,nand-cmd-offset = <22>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_nand>;
595 usb0: ohci@00600000 {
596 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
597 reg = <0x00600000 0x100000>;
598 interrupts = <22 4 2>;
602 usb1: ehci@00700000 {
603 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
604 reg = <0x00700000 0x100000>;
605 interrupts = <22 4 2>;
611 compatible = "i2c-gpio";
612 gpios = <&pioA 30 0 /* sda */
615 i2c-gpio,sda-open-drain;
616 i2c-gpio,scl-open-drain;
617 i2c-gpio,delay-us = <2>; /* ~100 kHz */
618 #address-cells = <1>;
624 compatible = "i2c-gpio";
625 gpios = <&pioC 0 0 /* sda */
628 i2c-gpio,sda-open-drain;
629 i2c-gpio,scl-open-drain;
630 i2c-gpio,delay-us = <2>; /* ~100 kHz */
631 #address-cells = <1>;
637 compatible = "i2c-gpio";
638 gpios = <&pioB 4 0 /* sda */
641 i2c-gpio,sda-open-drain;
642 i2c-gpio,scl-open-drain;
643 i2c-gpio,delay-us = <2>; /* ~100 kHz */
644 #address-cells = <1>;