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1 /*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12 /include/ "skeleton.dtsi"
13
14 / {
15 model = "Atmel AT91SAM9x5 family SoC";
16 compatible = "atmel,at91sam9x5";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 tcb0 = &tcb0;
29 tcb1 = &tcb1;
30 i2c0 = &i2c0;
31 i2c1 = &i2c1;
32 i2c2 = &i2c2;
33 };
34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 memory {
41 reg = <0x20000000 0x10000000>;
42 };
43
44 ahb {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges;
49
50 apb {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55
56 aic: interrupt-controller@fffff000 {
57 #interrupt-cells = <3>;
58 compatible = "atmel,at91rm9200-aic";
59 interrupt-controller;
60 reg = <0xfffff000 0x200>;
61 atmel,external-irqs = <31>;
62 };
63
64 ramc0: ramc@ffffe800 {
65 compatible = "atmel,at91sam9g45-ddramc";
66 reg = <0xffffe800 0x200>;
67 };
68
69 pmc: pmc@fffffc00 {
70 compatible = "atmel,at91rm9200-pmc";
71 reg = <0xfffffc00 0x100>;
72 };
73
74 rstc@fffffe00 {
75 compatible = "atmel,at91sam9g45-rstc";
76 reg = <0xfffffe00 0x10>;
77 };
78
79 shdwc@fffffe10 {
80 compatible = "atmel,at91sam9x5-shdwc";
81 reg = <0xfffffe10 0x10>;
82 };
83
84 pit: timer@fffffe30 {
85 compatible = "atmel,at91sam9260-pit";
86 reg = <0xfffffe30 0xf>;
87 interrupts = <1 4 7>;
88 };
89
90 tcb0: timer@f8008000 {
91 compatible = "atmel,at91sam9x5-tcb";
92 reg = <0xf8008000 0x100>;
93 interrupts = <17 4 0>;
94 };
95
96 tcb1: timer@f800c000 {
97 compatible = "atmel,at91sam9x5-tcb";
98 reg = <0xf800c000 0x100>;
99 interrupts = <17 4 0>;
100 };
101
102 dma0: dma-controller@ffffec00 {
103 compatible = "atmel,at91sam9g45-dma";
104 reg = <0xffffec00 0x200>;
105 interrupts = <20 4 0>;
106 };
107
108 dma1: dma-controller@ffffee00 {
109 compatible = "atmel,at91sam9g45-dma";
110 reg = <0xffffee00 0x200>;
111 interrupts = <21 4 0>;
112 };
113
114 pioA: gpio@fffff400 {
115 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
116 reg = <0xfffff400 0x100>;
117 interrupts = <2 4 1>;
118 #gpio-cells = <2>;
119 gpio-controller;
120 interrupt-controller;
121 #interrupt-cells = <2>;
122 };
123
124 pioB: gpio@fffff600 {
125 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
126 reg = <0xfffff600 0x100>;
127 interrupts = <2 4 1>;
128 #gpio-cells = <2>;
129 gpio-controller;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 };
133
134 pioC: gpio@fffff800 {
135 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
136 reg = <0xfffff800 0x100>;
137 interrupts = <3 4 1>;
138 #gpio-cells = <2>;
139 gpio-controller;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
144 pioD: gpio@fffffa00 {
145 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
146 reg = <0xfffffa00 0x100>;
147 interrupts = <3 4 1>;
148 #gpio-cells = <2>;
149 gpio-controller;
150 interrupt-controller;
151 #interrupt-cells = <2>;
152 };
153
154 dbgu: serial@fffff200 {
155 compatible = "atmel,at91sam9260-usart";
156 reg = <0xfffff200 0x200>;
157 interrupts = <1 4 7>;
158 status = "disabled";
159 };
160
161 usart0: serial@f801c000 {
162 compatible = "atmel,at91sam9260-usart";
163 reg = <0xf801c000 0x200>;
164 interrupts = <5 4 5>;
165 atmel,use-dma-rx;
166 atmel,use-dma-tx;
167 status = "disabled";
168 };
169
170 usart1: serial@f8020000 {
171 compatible = "atmel,at91sam9260-usart";
172 reg = <0xf8020000 0x200>;
173 interrupts = <6 4 5>;
174 atmel,use-dma-rx;
175 atmel,use-dma-tx;
176 status = "disabled";
177 };
178
179 usart2: serial@f8024000 {
180 compatible = "atmel,at91sam9260-usart";
181 reg = <0xf8024000 0x200>;
182 interrupts = <7 4 5>;
183 atmel,use-dma-rx;
184 atmel,use-dma-tx;
185 status = "disabled";
186 };
187
188 macb0: ethernet@f802c000 {
189 compatible = "cdns,at32ap7000-macb", "cdns,macb";
190 reg = <0xf802c000 0x100>;
191 interrupts = <24 4 3>;
192 status = "disabled";
193 };
194
195 macb1: ethernet@f8030000 {
196 compatible = "cdns,at32ap7000-macb", "cdns,macb";
197 reg = <0xf8030000 0x100>;
198 interrupts = <27 4 3>;
199 status = "disabled";
200 };
201
202 i2c0: i2c@f8010000 {
203 compatible = "atmel,at91sam9x5-i2c";
204 reg = <0xf8010000 0x100>;
205 interrupts = <9 4 6>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 status = "disabled";
209 };
210
211 i2c1: i2c@f8014000 {
212 compatible = "atmel,at91sam9x5-i2c";
213 reg = <0xf8014000 0x100>;
214 interrupts = <10 4 6>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 status = "disabled";
218 };
219
220 i2c2: i2c@f8018000 {
221 compatible = "atmel,at91sam9x5-i2c";
222 reg = <0xf8018000 0x100>;
223 interrupts = <11 4 6>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 status = "disabled";
227 };
228
229 adc0: adc@f804c000 {
230 compatible = "atmel,at91sam9260-adc";
231 reg = <0xf804c000 0x100>;
232 interrupts = <19 4 0>;
233 atmel,adc-use-external;
234 atmel,adc-channels-used = <0xffff>;
235 atmel,adc-vref = <3300>;
236 atmel,adc-num-channels = <12>;
237 atmel,adc-startup-time = <40>;
238 atmel,adc-channel-base = <0x50>;
239 atmel,adc-drdy-mask = <0x1000000>;
240 atmel,adc-status-register = <0x30>;
241 atmel,adc-trigger-register = <0xc0>;
242
243 trigger@0 {
244 trigger-name = "external-rising";
245 trigger-value = <0x1>;
246 trigger-external;
247 };
248
249 trigger@1 {
250 trigger-name = "external-falling";
251 trigger-value = <0x2>;
252 trigger-external;
253 };
254
255 trigger@2 {
256 trigger-name = "external-any";
257 trigger-value = <0x3>;
258 trigger-external;
259 };
260
261 trigger@3 {
262 trigger-name = "continuous";
263 trigger-value = <0x6>;
264 };
265 };
266 };
267
268 nand0: nand@40000000 {
269 compatible = "atmel,at91rm9200-nand";
270 #address-cells = <1>;
271 #size-cells = <1>;
272 reg = <0x40000000 0x10000000
273 >;
274 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>;
276 gpios = <&pioD 5 0
277 &pioD 4 0
278 0
279 >;
280 status = "disabled";
281 };
282
283 usb0: ohci@00600000 {
284 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
285 reg = <0x00600000 0x100000>;
286 interrupts = <22 4 2>;
287 status = "disabled";
288 };
289
290 usb1: ehci@00700000 {
291 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
292 reg = <0x00700000 0x100000>;
293 interrupts = <22 4 2>;
294 status = "disabled";
295 };
296 };
297
298 i2c@0 {
299 compatible = "i2c-gpio";
300 gpios = <&pioA 30 0 /* sda */
301 &pioA 31 0 /* scl */
302 >;
303 i2c-gpio,sda-open-drain;
304 i2c-gpio,scl-open-drain;
305 i2c-gpio,delay-us = <2>; /* ~100 kHz */
306 #address-cells = <1>;
307 #size-cells = <0>;
308 status = "disabled";
309 };
310
311 i2c@1 {
312 compatible = "i2c-gpio";
313 gpios = <&pioC 0 0 /* sda */
314 &pioC 1 0 /* scl */
315 >;
316 i2c-gpio,sda-open-drain;
317 i2c-gpio,scl-open-drain;
318 i2c-gpio,delay-us = <2>; /* ~100 kHz */
319 #address-cells = <1>;
320 #size-cells = <0>;
321 status = "disabled";
322 };
323
324 i2c@2 {
325 compatible = "i2c-gpio";
326 gpios = <&pioB 4 0 /* sda */
327 &pioB 5 0 /* scl */
328 >;
329 i2c-gpio,sda-open-drain;
330 i2c-gpio,scl-open-drain;
331 i2c-gpio,delay-us = <2>; /* ~100 kHz */
332 #address-cells = <1>;
333 #size-cells = <0>;
334 status = "disabled";
335 };
336 };