arch/arm/boot/dts/atlas6.dtsi

   1 /*
   2  * DTS file for CSR SiRFatlas6 SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 / {
  10         compatible = "sirf,atlas6";
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         reg = <0x0>;
  21                         d-cache-line-size = <32>;
  22                         i-cache-line-size = <32>;
  23                         d-cache-size = <32768>;
  24                         i-cache-size = <32768>;
  25                         /* from bootloader */
  26                         timebase-frequency = <0>;
  27                         bus-frequency = <0>;
  28                         clock-frequency = <0>;
  29                         clocks = <&clks 12>;
  30                         operating-points = <
  31                                 /* kHz    uV */
  32                                 200000  1025000
  33                                 400000  1025000
  34                                 600000  1050000
  35                                 800000  1100000
  36                         >;
  37                         clock-latency = <150000>;
  38                 };
  39         };
  40
  41         arm-pmu {
  42                 compatible = "arm,cortex-a9-pmu";
  43                 interrupts = <29>;
  44         };
  45
  46         axi {
  47                 compatible = "simple-bus";
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges = <0x40000000 0x40000000 0x80000000>;
  51
  52                 intc: interrupt-controller@80020000 {
  53                         #interrupt-cells = <1>;
  54                         interrupt-controller;
  55                         compatible = "sirf,prima2-intc";
  56                         reg = <0x80020000 0x1000>;
  57                 };
  58
  59                 sys-iobg {
  60                         compatible = "simple-bus";
  61                         #address-cells = <1>;
  62                         #size-cells = <1>;
  63                         ranges = <0x88000000 0x88000000 0x40000>;
  64
  65                         clks: clock-controller@88000000 {
  66                                 compatible = "sirf,atlas6-clkc";
  67                                 reg = <0x88000000 0x1000>;
  68                                 interrupts = <3>;
  69                                 #clock-cells = <1>;
  70                         };
  71
  72                         rstc: reset-controller@88010000 {
  73                                 compatible = "sirf,prima2-rstc";
  74                                 reg = <0x88010000 0x1000>;
  75                                 #reset-cells = <1>;
  76                         };
  77
  78                         rsc-controller@88020000 {
  79                                 compatible = "sirf,prima2-rsc";
  80                                 reg = <0x88020000 0x1000>;
  81                         };
  82
  83                         cphifbg@88030000 {
  84                                 compatible = "sirf,prima2-cphifbg";
  85                                 reg = <0x88030000 0x1000>;
  86                                 clocks = <&clks 42>;
  87                         };
  88                 };
  89
  90                 mem-iobg {
  91                         compatible = "simple-bus";
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         ranges = <0x90000000 0x90000000 0x10000>;
  95
  96                         memory-controller@90000000 {
  97                                 compatible = "sirf,prima2-memc";
  98                                 reg = <0x90000000 0x2000>;
  99                                 interrupts = <27>;
 100                                 clocks = <&clks 5>;
 101                         };
 102
 103                         memc-monitor {
 104                                 compatible = "sirf,prima2-memcmon";
 105                                 reg = <0x90002000 0x200>;
 106                                 interrupts = <4>;
 107                                 clocks = <&clks 32>;
 108                         };
 109                 };
 110
 111                 disp-iobg {
 112                         compatible = "simple-bus";
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115                         ranges = <0x90010000 0x90010000 0x30000>;
 116
 117                         lcd@90010000 {
 118                                 compatible = "sirf,prima2-lcd";
 119                                 reg = <0x90010000 0x20000>;
 120                                 interrupts = <30>;
 121                                 clocks = <&clks 34>;
 122                                 display=<&display>;
 123                                 /* later transfer to pwm */
 124                                 bl-gpio = <&gpio 7 0>;
 125                                 default-panel = <&panel0>;
 126                         };
 127
 128                         vpp@90020000 {
 129                                 compatible = "sirf,prima2-vpp";
 130                                 reg = <0x90020000 0x10000>;
 131                                 interrupts = <31>;
 132                                 clocks = <&clks 35>;
 133                                 resets = <&rstc 6>;
 134                         };
 135                 };
 136
 137                 graphics-iobg {
 138                         compatible = "simple-bus";
 139                         #address-cells = <1>;
 140                         #size-cells = <1>;
 141                         ranges = <0x98000000 0x98000000 0x8000000>;
 142
 143                         graphics@98000000 {
 144                                 compatible = "powervr,sgx510";
 145                                 reg = <0x98000000 0x8000000>;
 146                                 interrupts = <6>;
 147                                 clocks = <&clks 32>;
 148                         };
 149                 };
 150
 151                 graphics2d-iobg {
 152                         compatible = "simple-bus";
 153                         #address-cells = <1>;
 154                         #size-cells = <1>;
 155                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 156
 157                         ble@a0000000 {
 158                                 compatible = "sirf,atlas6-ble";
 159                                 reg = <0xa0000000 0x2000>;
 160                                 interrupts = <5>;
 161                                 clocks = <&clks 33>;
 162                         };
 163                 };
 164
 165                 dsp-iobg {
 166                         compatible = "simple-bus";
 167                         #address-cells = <1>;
 168                         #size-cells = <1>;
 169                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 170
 171                         dspif@a8000000 {
 172                                 compatible = "sirf,prima2-dspif";
 173                                 reg = <0xa8000000 0x10000>;
 174                                 interrupts = <9>;
 175                                 resets = <&rstc 1>;
 176                         };
 177
 178                         gps@a8010000 {
 179                                 compatible = "sirf,prima2-gps";
 180                                 reg = <0xa8010000 0x10000>;
 181                                 interrupts = <7>;
 182                                 clocks = <&clks 9>;
 183                                 resets = <&rstc 2>;
 184                         };
 185
 186                         dsp@a9000000 {
 187                                 compatible = "sirf,prima2-dsp";
 188                                 reg = <0xa9000000 0x1000000>;
 189                                 interrupts = <8>;
 190                                 clocks = <&clks 8>;
 191                                 resets = <&rstc 0>;
 192                         };
 193                 };
 194
 195                 peri-iobg {
 196                         compatible = "simple-bus";
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199                         ranges = <0xb0000000 0xb0000000 0x180000>,
 200                                <0x56000000 0x56000000 0x1b00000>;
 201
 202                         timer@b0020000 {
 203                                 compatible = "sirf,prima2-tick";
 204                                 reg = <0xb0020000 0x1000>;
 205                                 interrupts = <0>;
 206                                 clocks = <&clks 11>;
 207                         };
 208
 209                         nand@b0030000 {
 210                                 compatible = "sirf,prima2-nand";
 211                                 reg = <0xb0030000 0x10000>;
 212                                 interrupts = <41>;
 213                                 clocks = <&clks 26>;
 214                         };
 215
 216                         audio@b0040000 {
 217                                 compatible = "sirf,prima2-audio";
 218                                 reg = <0xb0040000 0x10000>;
 219                                 interrupts = <35>;
 220                                 clocks = <&clks 27>;
 221                         };
 222
 223                         uart0: uart@b0050000 {
 224                                 cell-index = <0>;
 225                                 compatible = "sirf,prima2-uart";
 226                                 reg = <0xb0050000 0x1000>;
 227                                 interrupts = <17>;
 228                                 fifosize = <128>;
 229                                 clocks = <&clks 13>;
 230                                 dmas = <&dmac1 5>, <&dmac0 2>;
 231                                 dma-names = "rx", "tx";
 232                         };
 233
 234                         uart1: uart@b0060000 {
 235                                 cell-index = <1>;
 236                                 compatible = "sirf,prima2-uart";
 237                                 reg = <0xb0060000 0x1000>;
 238                                 interrupts = <18>;
 239                                 fifosize = <32>;
 240                                 clocks = <&clks 14>;
 241                                 dma-names = "no-rx", "no-tx";
 242                         };
 243
 244                         uart2: uart@b0070000 {
 245                                 cell-index = <2>;
 246                                 compatible = "sirf,prima2-uart";
 247                                 reg = <0xb0070000 0x1000>;
 248                                 interrupts = <19>;
 249                                 fifosize = <128>;
 250                                 clocks = <&clks 15>;
 251                                 dmas = <&dmac0 6>, <&dmac0 7>;
 252                                 dma-names = "rx", "tx";
 253                         };
 254
 255                         usp0: usp@b0080000 {
 256                                 cell-index = <0>;
 257                                 compatible = "sirf,prima2-usp";
 258                                 reg = <0xb0080000 0x10000>;
 259                                 interrupts = <20>;
 260                                 fifosize = <128>;
 261                                 clocks = <&clks 28>;
 262                                 dmas = <&dmac1 1>, <&dmac1 2>;
 263                                 dma-names = "rx", "tx";
 264                         };
 265
 266                         usp1: usp@b0090000 {
 267                                 cell-index = <1>;
 268                                 compatible = "sirf,prima2-usp";
 269                                 reg = <0xb0090000 0x10000>;
 270                                 interrupts = <21>;
 271                                 fifosize = <128>;
 272                                 clocks = <&clks 29>;
 273                                 dmas = <&dmac0 14>, <&dmac0 15>;
 274                                 dma-names = "rx", "tx";
 275                         };
 276
 277                         dmac0: dma-controller@b00b0000 {
 278                                 cell-index = <0>;
 279                                 compatible = "sirf,prima2-dmac";
 280                                 reg = <0xb00b0000 0x10000>;
 281                                 interrupts = <12>;
 282                                 clocks = <&clks 24>;
 283                                 #dma-cells = <1>;
 284                         };
 285
 286                         dmac1: dma-controller@b0160000 {
 287                                 cell-index = <1>;
 288                                 compatible = "sirf,prima2-dmac";
 289                                 reg = <0xb0160000 0x10000>;
 290                                 interrupts = <13>;
 291                                 clocks = <&clks 25>;
 292                                 #dma-cells = <1>;
 293                         };
 294
 295                         vip@b00C0000 {
 296                                 compatible = "sirf,prima2-vip";
 297                                 reg = <0xb00C0000 0x10000>;
 298                                 clocks = <&clks 31>;
 299                                 interrupts = <14>;
 300                                 sirf,vip-dma-rx-channel = <16>;
 301                         };
 302
 303                         spi0: spi@b00d0000 {
 304                                 cell-index = <0>;
 305                                 compatible = "sirf,prima2-spi";
 306                                 reg = <0xb00d0000 0x10000>;
 307                                 interrupts = <15>;
 308                                 sirf,spi-num-chipselects = <1>;
 309                                 dmas = <&dmac1 9>,
 310                                      <&dmac1 4>;
 311                                 dma-names = "rx", "tx";
 312                                 #address-cells = <1>;
 313                                 #size-cells = <0>;
 314                                 clocks = <&clks 19>;
 315                                 resets = <&rstc 26>;
 316                                 status = "disabled";
 317                         };
 318
 319                         spi1: spi@b0170000 {
 320                                 cell-index = <1>;
 321                                 compatible = "sirf,prima2-spi";
 322                                 reg = <0xb0170000 0x10000>;
 323                                 interrupts = <16>;
 324                                 sirf,spi-num-chipselects = <1>;
 325                                 dmas = <&dmac0 12>,
 326                                      <&dmac0 13>;
 327                                 dma-names = "rx", "tx";
 328                                 #address-cells = <1>;
 329                                 #size-cells = <0>;
 330                                 clocks = <&clks 20>;
 331                                 resets = <&rstc 27>;
 332                                 status = "disabled";
 333                         };
 334
 335                         i2c0: i2c@b00e0000 {
 336                                 cell-index = <0>;
 337                                 compatible = "sirf,prima2-i2c";
 338                                 reg = <0xb00e0000 0x10000>;
 339                                 interrupts = <24>;
 340                                 #address-cells = <1>;
 341                                 #size-cells = <0>;
 342                                 clocks = <&clks 17>;
 343                         };
 344
 345                         i2c1: i2c@b00f0000 {
 346                                 cell-index = <1>;
 347                                 compatible = "sirf,prima2-i2c";
 348                                 reg = <0xb00f0000 0x10000>;
 349                                 interrupts = <25>;
 350                                 #address-cells = <1>;
 351                                 #size-cells = <0>;
 352                                 clocks = <&clks 18>;
 353                         };
 354
 355                         tsc@b0110000 {
 356                                 compatible = "sirf,prima2-tsc";
 357                                 reg = <0xb0110000 0x10000>;
 358                                 interrupts = <33>;
 359                                 clocks = <&clks 16>;
 360                         };
 361
 362                         gpio: pinctrl@b0120000 {
 363                                 #gpio-cells = <2>;
 364                                 #interrupt-cells = <2>;
 365                                 compatible = "sirf,atlas6-pinctrl";
 366                                 reg = <0xb0120000 0x10000>;
 367                                 interrupts = <43 44 45 46 47>;
 368                                 gpio-controller;
 369                                 interrupt-controller;
 370
 371                                 lcd_16pins_a: lcd0@0 {
 372                                         lcd {
 373                                                 sirf,pins = "lcd_16bitsgrp";
 374                                                 sirf,function = "lcd_16bits";
 375                                         };
 376                                 };
 377                                 lcd_18pins_a: lcd0@1 {
 378                                         lcd {
 379                                                 sirf,pins = "lcd_18bitsgrp";
 380                                                 sirf,function = "lcd_18bits";
 381                                         };
 382                                 };
 383                                 lcd_24pins_a: lcd0@2 {
 384                                         lcd {
 385                                                 sirf,pins = "lcd_24bitsgrp";
 386                                                 sirf,function = "lcd_24bits";
 387                                         };
 388                                 };
 389                                 lcdrom_pins_a: lcdrom0@0 {
 390                                         lcd {
 391                                                 sirf,pins = "lcdromgrp";
 392                                                 sirf,function = "lcdrom";
 393                                         };
 394                                 };
 395                                 uart0_pins_a: uart0@0 {
 396                                         uart {
 397                                                 sirf,pins = "uart0grp";
 398                                                 sirf,function = "uart0";
 399                                         };
 400                                 };
 401                                 uart0_noflow_pins_a: uart0@1 {
 402                                         uart {
 403                                                 sirf,pins = "uart0_nostreamctrlgrp";
 404                                                 sirf,function = "uart0_nostreamctrl";
 405                                         };
 406                                 };
 407                                 uart1_pins_a: uart1@0 {
 408                                         uart {
 409                                                 sirf,pins = "uart1grp";
 410                                                 sirf,function = "uart1";
 411                                         };
 412                                 };
 413                                 uart2_pins_a: uart2@0 {
 414                                         uart {
 415                                                 sirf,pins = "uart2grp";
 416                                                 sirf,function = "uart2";
 417                                         };
 418                                 };
 419                                 uart2_noflow_pins_a: uart2@1 {
 420                                         uart {
 421                                                 sirf,pins = "uart2_nostreamctrlgrp";
 422                                                 sirf,function = "uart2_nostreamctrl";
 423                                         };
 424                                 };
 425                                 spi0_pins_a: spi0@0 {
 426                                         spi {
 427                                                 sirf,pins = "spi0grp";
 428                                                 sirf,function = "spi0";
 429                                         };
 430                                 };
 431                                 spi1_pins_a: spi1@0 {
 432                                         spi {
 433                                                 sirf,pins = "spi1grp";
 434                                                 sirf,function = "spi1";
 435                                         };
 436                                 };
 437                                 i2c0_pins_a: i2c0@0 {
 438                                         i2c {
 439                                                 sirf,pins = "i2c0grp";
 440                                                 sirf,function = "i2c0";
 441                                         };
 442                                 };
 443                                 i2c1_pins_a: i2c1@0 {
 444                                         i2c {
 445                                                 sirf,pins = "i2c1grp";
 446                                                 sirf,function = "i2c1";
 447                                         };
 448                                 };
 449                                 pwm0_pins_a: pwm0@0 {
 450                                         pwm {
 451                                                 sirf,pins = "pwm0grp";
 452                                                 sirf,function = "pwm0";
 453                                         };
 454                                 };
 455                                 pwm1_pins_a: pwm1@0 {
 456                                         pwm {
 457                                                 sirf,pins = "pwm1grp";
 458                                                 sirf,function = "pwm1";
 459                                         };
 460                                 };
 461                                 pwm2_pins_a: pwm2@0 {
 462                                         pwm {
 463                                                 sirf,pins = "pwm2grp";
 464                                                 sirf,function = "pwm2";
 465                                         };
 466                                 };
 467                                 pwm3_pins_a: pwm3@0 {
 468                                         pwm {
 469                                                 sirf,pins = "pwm3grp";
 470                                                 sirf,function = "pwm3";
 471                                         };
 472                                 };
 473                                 pwm4_pins_a: pwm4@0 {
 474                                         pwm {
 475                                                 sirf,pins = "pwm4grp";
 476                                                 sirf,function = "pwm4";
 477                                         };
 478                                 };
 479                                 gps_pins_a: gps@0 {
 480                                         gps {
 481                                                 sirf,pins = "gpsgrp";
 482                                                 sirf,function = "gps";
 483                                         };
 484                                 };
 485                                 vip_pins_a: vip@0 {
 486                                         vip {
 487                                                 sirf,pins = "vipgrp";
 488                                                 sirf,function = "vip";
 489                                         };
 490                                 };
 491                                 sdmmc0_pins_a: sdmmc0@0 {
 492                                         sdmmc0 {
 493                                                 sirf,pins = "sdmmc0grp";
 494                                                 sirf,function = "sdmmc0";
 495                                         };
 496                                 };
 497                                 sdmmc1_pins_a: sdmmc1@0 {
 498                                         sdmmc1 {
 499                                                 sirf,pins = "sdmmc1grp";
 500                                                 sirf,function = "sdmmc1";
 501                                         };
 502                                 };
 503                                 sdmmc2_pins_a: sdmmc2@0 {
 504                                         sdmmc2 {
 505                                                 sirf,pins = "sdmmc2grp";
 506                                                 sirf,function = "sdmmc2";
 507                                         };
 508                                 };
 509                                 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
 510                                         sdmmc2_nowp {
 511                                                 sirf,pins = "sdmmc2_nowpgrp";
 512                                                 sirf,function = "sdmmc2_nowp";
 513                                         };
 514                                 };
 515                                 sdmmc3_pins_a: sdmmc3@0 {
 516                                         sdmmc3 {
 517                                                 sirf,pins = "sdmmc3grp";
 518                                                 sirf,function = "sdmmc3";
 519                                         };
 520                                 };
 521                                 sdmmc5_pins_a: sdmmc5@0 {
 522                                         sdmmc5 {
 523                                                 sirf,pins = "sdmmc5grp";
 524                                                 sirf,function = "sdmmc5";
 525                                         };
 526                                 };
 527                                 i2s_mclk_pins_a: i2s_mclk@0 {
 528                                         i2s_mclk {
 529                                                 sirf,pins = "i2smclkgrp";
 530                                                 sirf,function = "i2s_mclk";
 531                                         };
 532                                 };
 533                                 i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
 534                                         i2s_ext_clk_input {
 535                                                 sirf,pins = "i2s_ext_clk_inputgrp";
 536                                                 sirf,function = "i2s_ext_clk_input";
 537                                         };
 538                                 };
 539                                 i2s_pins_a: i2s@0 {
 540                                         i2s {
 541                                                 sirf,pins = "i2sgrp";
 542                                                 sirf,function = "i2s";
 543                                         };
 544                                 };
 545                                 i2s_no_din_pins_a: i2s_no_din@0 {
 546                                         i2s_no_din {
 547                                                 sirf,pins = "i2s_no_dingrp";
 548                                                 sirf,function = "i2s_no_din";
 549                                         };
 550                                 };
 551                                 i2s_6chn_pins_a: i2s_6chn@0 {
 552                                         i2s_6chn {
 553                                                 sirf,pins = "i2s_6chngrp";
 554                                                 sirf,function = "i2s_6chn";
 555                                         };
 556                                 };
 557                                 ac97_pins_a: ac97@0 {
 558                                         ac97 {
 559                                                 sirf,pins = "ac97grp";
 560                                                 sirf,function = "ac97";
 561                                         };
 562                                 };
 563                                 nand_pins_a: nand@0 {
 564                                         nand {
 565                                                 sirf,pins = "nandgrp";
 566                                                 sirf,function = "nand";
 567                                         };
 568                                 };
 569                                 usp0_pins_a: usp0@0 {
 570                                         usp0 {
 571                                                 sirf,pins = "usp0grp";
 572                                                 sirf,function = "usp0";
 573                                         };
 574                                 };
 575                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 576                                         usp0 {
 577                                                 sirf,pins = "usp0_uart_nostreamctrl_grp";
 578                                                 sirf,function = "usp0_uart_nostreamctrl";
 579                                         };
 580                                 };
 581                                 usp0_only_utfs_pins_a: usp0@2 {
 582                                         usp0 {
 583                                                 sirf,pins = "usp0_only_utfs_grp";
 584                                                 sirf,function = "usp0_only_utfs";
 585                                         };
 586                                 };
 587                                 usp0_only_urfs_pins_a: usp0@3 {
 588                                         usp0 {
 589                                                 sirf,pins = "usp0_only_urfs_grp";
 590                                                 sirf,function = "usp0_only_urfs";
 591                                         };
 592                                 };
 593                                 usp1_pins_a: usp1@0 {
 594                                         usp1 {
 595                                                 sirf,pins = "usp1grp";
 596                                                 sirf,function = "usp1";
 597                                         };
 598                                 };
 599                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
 600                                         usp1 {
 601                                                 sirf,pins = "usp1_uart_nostreamctrl_grp";
 602                                                 sirf,function = "usp1_uart_nostreamctrl";
 603                                         };
 604                                 };
 605                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
 606                                         usb0_upli_drvbus {
 607                                                 sirf,pins = "usb0_upli_drvbusgrp";
 608                                                 sirf,function = "usb0_upli_drvbus";
 609                                         };
 610                                 };
 611                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 612                                         usb1_utmi_drvbus {
 613                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 614                                                 sirf,function = "usb1_utmi_drvbus";
 615                                         };
 616                                 };
 617                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 618                                         usb1_dp_dn {
 619                                                 sirf,pins = "usb1_dp_dngrp";
 620                                                 sirf,function = "usb1_dp_dn";
 621                                         };
 622                                 };
 623                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 624                                         uart1_route_io_usb1 {
 625                                                 sirf,pins = "uart1_route_io_usb1grp";
 626                                                 sirf,function = "uart1_route_io_usb1";
 627                                         };
 628                                 };
 629                                 warm_rst_pins_a: warm_rst@0 {
 630                                         warm_rst {
 631                                                 sirf,pins = "warm_rstgrp";
 632                                                 sirf,function = "warm_rst";
 633                                         };
 634                                 };
 635                                 pulse_count_pins_a: pulse_count@0 {
 636                                         pulse_count {
 637                                                 sirf,pins = "pulse_countgrp";
 638                                                 sirf,function = "pulse_count";
 639                                         };
 640                                 };
 641                                 cko0_pins_a: cko0@0 {
 642                                         cko0 {
 643                                                 sirf,pins = "cko0grp";
 644                                                 sirf,function = "cko0";
 645                                         };
 646                                 };
 647                                 cko1_pins_a: cko1@0 {
 648                                         cko1 {
 649                                                 sirf,pins = "cko1grp";
 650                                                 sirf,function = "cko1";
 651                                         };
 652                                 };
 653                         };
 654
 655                         pwm@b0130000 {
 656                                 compatible = "sirf,prima2-pwm";
 657                                 reg = <0xb0130000 0x10000>;
 658                                 clocks = <&clks 21>;
 659                         };
 660
 661                         efusesys@b0140000 {
 662                                 compatible = "sirf,prima2-efuse";
 663                                 reg = <0xb0140000 0x10000>;
 664                                 clocks = <&clks 22>;
 665                         };
 666
 667                         pulsec@b0150000 {
 668                                 compatible = "sirf,prima2-pulsec";
 669                                 reg = <0xb0150000 0x10000>;
 670                                 interrupts = <48>;
 671                                 clocks = <&clks 23>;
 672                         };
 673
 674                         pci-iobg {
 675                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 676                                 #address-cells = <1>;
 677                                 #size-cells = <1>;
 678                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 679
 680                                 sd0: sdhci@56000000 {
 681                                         cell-index = <0>;
 682                                         compatible = "sirf,prima2-sdhc";
 683                                         reg = <0x56000000 0x100000>;
 684                                         interrupts = <38>;
 685                                         bus-width = <8>;
 686                                         clocks = <&clks 36>;
 687                                 };
 688
 689                                 sd1: sdhci@56100000 {
 690                                         cell-index = <1>;
 691                                         compatible = "sirf,prima2-sdhc";
 692                                         reg = <0x56100000 0x100000>;
 693                                         interrupts = <38>;
 694                                         status = "disabled";
 695                                         bus-width = <4>;
 696                                         clocks = <&clks 36>;
 697                                 };
 698
 699                                 sd2: sdhci@56200000 {
 700                                         cell-index = <2>;
 701                                         compatible = "sirf,prima2-sdhc";
 702                                         reg = <0x56200000 0x100000>;
 703                                         interrupts = <23>;
 704                                         status = "disabled";
 705                                         bus-width = <4>;
 706                                         clocks = <&clks 37>;
 707                                 };
 708
 709                                 sd3: sdhci@56300000 {
 710                                         cell-index = <3>;
 711                                         compatible = "sirf,prima2-sdhc";
 712                                         reg = <0x56300000 0x100000>;
 713                                         interrupts = <23>;
 714                                         status = "disabled";
 715                                         bus-width = <4>;
 716                                         clocks = <&clks 37>;
 717                                 };
 718
 719                                 sd5: sdhci@56500000 {
 720                                         cell-index = <5>;
 721                                         compatible = "sirf,prima2-sdhc";
 722                                         reg = <0x56500000 0x100000>;
 723                                         interrupts = <39>;
 724                                         status = "disabled";
 725                                         bus-width = <4>;
 726                                         clocks = <&clks 38>;
 727                                 };
 728
 729                                 pci-copy@57900000 {
 730                                         compatible = "sirf,prima2-pcicp";
 731                                         reg = <0x57900000 0x100000>;
 732                                         interrupts = <40>;
 733                                 };
 734
 735                                 rom-interface@57a00000 {
 736                                         compatible = "sirf,prima2-romif";
 737                                         reg = <0x57a00000 0x100000>;
 738                                 };
 739                         };
 740                 };
 741
 742                 rtc-iobg {
 743                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 744                         #address-cells = <1>;
 745                         #size-cells = <1>;
 746                         reg = <0x80030000 0x10000>;
 747
 748                         gpsrtc@1000 {
 749                                 compatible = "sirf,prima2-gpsrtc";
 750                                 reg = <0x1000 0x1000>;
 751                                 interrupts = <55 56 57>;
 752                         };
 753
 754                         sysrtc@2000 {
 755                                 compatible = "sirf,prima2-sysrtc";
 756                                 reg = <0x2000 0x1000>;
 757                                 interrupts = <52 53 54>;
 758                         };
 759
 760                         minigpsrtc@2000 {
 761                                 compatible = "sirf,prima2-minigpsrtc";
 762                                 reg = <0x2000 0x1000>;
 763                                 interrupts = <54>;
 764                         };
 765
 766                         pwrc@3000 {
 767                                 compatible = "sirf,prima2-pwrc";
 768                                 reg = <0x3000 0x1000>;
 769                                 interrupts = <32>;
 770                         };
 771                 };
 772
 773                 uus-iobg {
 774                         compatible = "simple-bus";
 775                         #address-cells = <1>;
 776                         #size-cells = <1>;
 777                         ranges = <0xb8000000 0xb8000000 0x40000>;
 778
 779                         usb0: usb@b00e0000 {
 780                                 compatible = "chipidea,ci13611a-prima2";
 781                                 reg = <0xb8000000 0x10000>;
 782                                 interrupts = <10>;
 783                                 clocks = <&clks 40>;
 784                         };
 785
 786                         usb1: usb@b00f0000 {
 787                                 compatible = "chipidea,ci13611a-prima2";
 788                                 reg = <0xb8010000 0x10000>;
 789                                 interrupts = <11>;
 790                                 clocks = <&clks 41>;
 791                         };
 792
 793                         security@b00f0000 {
 794                                 compatible = "sirf,prima2-security";
 795                                 reg = <0xb8030000 0x10000>;
 796                                 interrupts = <42>;
 797                                 clocks = <&clks 7>;
 798                         };
 799                 };
 800         };
 801 };