4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
37 #include "skeleton.dtsi"
40 compatible = "brcm,cygnus";
41 model = "Broadcom Cygnus SoC";
42 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
56 /include/ "bcm-cygnus-clock.dtsi"
59 compatible = "simple-bus";
60 ranges = <0x00000000 0x19000000 0x1000000>;
65 compatible = "arm,cortex-a9-global-timer";
66 reg = <0x20200 0x100>;
67 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&periph_clk>;
71 gic: interrupt-controller@21000 {
72 compatible = "arm,cortex-a9-gic";
73 #interrupt-cells = <3>;
76 reg = <0x21000 0x1000>,
81 compatible = "arm,pl310-cache";
82 reg = <0x22000 0x1000>;
89 compatible = "simple-bus";
95 compatible = "brcm,ocotp";
96 reg = <0x0301c800 0x2c>;
97 brcm,ocotp-size = <2048>;
101 pcie_phy: phy@0301d0a0 {
102 compatible = "brcm,cygnus-pcie-phy";
103 reg = <0x0301d0a0 0x14>;
104 #address-cells = <1>;
118 pinctrl: pinctrl@0301d0c8 {
119 compatible = "brcm,cygnus-pinmux";
120 reg = <0x0301d0c8 0x30>,
124 mailbox: mailbox@03024024 {
125 compatible = "brcm,iproc-mailbox";
126 reg = <0x03024024 0x40>;
127 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
128 #interrupt-cells = <1>;
129 interrupt-controller;
133 gpio_crmu: gpio@03024800 {
134 compatible = "brcm,cygnus-crmu-gpio";
135 reg = <0x03024800 0x50>,
140 interrupt-controller;
141 interrupt-parent = <&mailbox>;
146 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
147 reg = <0x18008000 0x100>;
148 #address-cells = <1>;
150 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
151 clock-frequency = <100000>;
156 compatible = "arm,sp805" , "arm,primecell";
157 reg = <0x18009000 0x1000>;
158 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&axi81_clk>;
160 clock-names = "apb_pclk";
163 gpio_ccm: gpio@1800a000 {
164 compatible = "brcm,cygnus-ccm-gpio";
165 reg = <0x1800a000 0x50>,
170 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-controller;
175 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
176 reg = <0x1800b000 0x100>;
177 #address-cells = <1>;
179 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
180 clock-frequency = <100000>;
184 pcie0: pcie@18012000 {
185 compatible = "brcm,iproc-pcie";
186 reg = <0x18012000 0x1000>;
188 #interrupt-cells = <1>;
189 interrupt-map-mask = <0 0 0 0>;
190 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
192 linux,pci-domain = <0>;
194 bus-range = <0x00 0xff>;
196 #address-cells = <3>;
199 ranges = <0x81000000 0 0 0x28000000 0 0x00010000
200 0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
203 phy-names = "pcie-phy";
207 msi-parent = <&msi0>;
209 compatible = "brcm,iproc-msi";
211 interrupt-parent = <&gic>;
212 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
213 <GIC_SPI 97 IRQ_TYPE_NONE>,
214 <GIC_SPI 98 IRQ_TYPE_NONE>,
215 <GIC_SPI 99 IRQ_TYPE_NONE>;
219 pcie1: pcie@18013000 {
220 compatible = "brcm,iproc-pcie";
221 reg = <0x18013000 0x1000>;
223 #interrupt-cells = <1>;
224 interrupt-map-mask = <0 0 0 0>;
225 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
227 linux,pci-domain = <1>;
229 bus-range = <0x00 0xff>;
231 #address-cells = <3>;
234 ranges = <0x81000000 0 0 0x48000000 0 0x00010000
235 0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
238 phy-names = "pcie-phy";
242 msi-parent = <&msi1>;
244 compatible = "brcm,iproc-msi";
246 interrupt-parent = <&gic>;
247 interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
248 <GIC_SPI 103 IRQ_TYPE_NONE>,
249 <GIC_SPI 104 IRQ_TYPE_NONE>,
250 <GIC_SPI 105 IRQ_TYPE_NONE>;
254 uart0: serial@18020000 {
255 compatible = "snps,dw-apb-uart";
256 reg = <0x18020000 0x100>;
259 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&axi81_clk>;
261 clock-frequency = <100000000>;
265 uart1: serial@18021000 {
266 compatible = "snps,dw-apb-uart";
267 reg = <0x18021000 0x100>;
270 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&axi81_clk>;
272 clock-frequency = <100000000>;
276 uart2: serial@18022000 {
277 compatible = "snps,dw-apb-uart";
278 reg = <0x18020000 0x100>;
281 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&axi81_clk>;
283 clock-frequency = <100000000>;
287 uart3: serial@18023000 {
288 compatible = "snps,dw-apb-uart";
289 reg = <0x18023000 0x100>;
292 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&axi81_clk>;
294 clock-frequency = <100000000>;
298 nand: nand@18046000 {
299 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
300 reg = <0x18046000 0x600>, <0xf8105408 0x600>,
302 reg-names = "nand", "iproc-idm", "iproc-ext";
303 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>;
311 gpio_asiu: gpio@180a5000 {
312 compatible = "brcm,cygnus-asiu-gpio";
313 reg = <0x180a5000 0x668>;
318 interrupt-controller;
319 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
320 gpio-ranges = <&pinctrl 0 42 1>,
332 <&pinctrl 24 130 10>,
347 <&pinctrl 70 156 17>,
348 <&pinctrl 87 104 12>,
351 <&pinctrl 105 116 6>,
352 <&pinctrl 111 100 2>,
353 <&pinctrl 113 122 4>,
373 ts_adc_syscon: ts_adc_syscon@180a6000 {
374 compatible = "brcm,iproc-ts-adc-syscon", "syscon";
375 reg = <0x180a6000 0xc30>;
378 touchscreen: touchscreen@180a6000 {
379 compatible = "brcm,iproc-touchscreen";
380 #address-cells = <1>;
382 ts_syscon = <&ts_adc_syscon>;
383 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
384 clock-names = "tsc_clk";
385 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
390 compatible = "brcm,iproc-static-adc";
391 #io-channel-cells = <1>;
393 adc-syscon = <&ts_adc_syscon>;
394 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
395 clock-names = "tsc_clk";
396 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;