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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
37 #include "skeleton.dtsi"
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
57 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
59 enable-method = "brcm,bcm-nsp-smp";
60 secondary-boot-reg = <0xffff042c>;
66 compatible = "arm,cortex-a9-pmu";
67 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
68 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>;
73 compatible = "simple-bus";
74 ranges = <0x00000000 0x19000000 0x00023000>;
78 a9pll: arm_clk@00000 {
80 compatible = "brcm,nsp-armpll";
82 reg = <0x00000 0x1000>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x20200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&periph_clk>;
93 compatible = "arm,cortex-a9-twd-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_LEVEL_HIGH)>;
97 clocks = <&periph_clk>;
101 compatible = "arm,cortex-a9-twd-wdt";
102 reg = <0x20620 0x20>;
103 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_LEVEL_HIGH)>;
105 clocks = <&periph_clk>;
108 gic: interrupt-controller@21000 {
109 compatible = "arm,cortex-a9-gic";
110 #interrupt-cells = <3>;
111 #address-cells = <0>;
112 interrupt-controller;
113 reg = <0x21000 0x1000>,
118 compatible = "arm,pl310-cache";
119 reg = <0x22000 0x1000>;
126 #address-cells = <1>;
132 compatible = "fixed-clock";
133 clock-frequency = <25000000>;
138 compatible = "fixed-factor-clock";
139 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
144 iprocslow: iprocslow {
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
152 periph_clk: periph_clk {
154 compatible = "fixed-factor-clock";
162 compatible = "simple-bus";
163 ranges = <0x00000000 0x18000000 0x0011ba08>;
164 #address-cells = <1>;
168 compatible = "brcm,nsp-gpio-a";
174 interrupt-controller;
175 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-ranges = <&pinctrl 0 0 32>;
180 compatible = "ns16550a";
181 reg = <0x0300 0x100>;
182 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
188 compatible = "ns16550a";
189 reg = <0x0400 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
197 reg = <0x026000 0x600>,
200 reg-names = "nand", "iproc-idm", "iproc-ext";
201 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
203 #address-cells = <1>;
210 compatible = "brcm,bcm-nsp-rng";
211 reg = <0x33000 0x14>;
214 ccbtimer0: timer@34000 {
215 compatible = "arm,sp804";
216 reg = <0x34000 0x1000>;
217 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&iprocslow>;
220 clock-names = "apb_pclk";
223 ccbtimer1: timer@35000 {
224 compatible = "arm,sp804";
225 reg = <0x35000 0x1000>;
226 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&iprocslow>;
229 clock-names = "apb_pclk";
233 compatible = "brcm,iproc-i2c";
234 reg = <0x38000 0x50>;
235 #address-cells = <1>;
237 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
238 clock-frequency = <100000>;
242 compatible = "arm,sp805", "arm,primecell";
243 reg = <0x39000 0x1000>;
244 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&iprocslow>, <&iprocslow>;
246 clock-names = "wdogclk", "apb_pclk";
249 lcpll0: lcpll0@3f100 {
251 compatible = "brcm,nsp-lcpll0";
252 reg = <0x3f100 0x14>;
254 clock-output-names = "lcpll0", "pcie_phy", "sdio",
258 genpll: genpll@3f140 {
260 compatible = "brcm,nsp-genpll";
261 reg = <0x3f140 0x24>;
263 clock-output-names = "genpll", "phy", "ethernetclk",
264 "usbclk", "iprocfast", "sata1",
268 pinctrl: pinctrl@3f1c0 {
269 compatible = "brcm,nsp-pinmux";
270 reg = <0x3f1c0 0x04>,
275 sata_phy: sata_phy@40100 {
276 compatible = "brcm,iproc-nsp-sata-phy";
277 reg = <0x40100 0x340>;
279 #address-cells = <1>;
282 sata_phy0: sata-phy@0 {
288 sata_phy1: sata-phy@1 {
296 compatible = "brcm,bcm-nsp-ahci";
297 reg-names = "ahci", "top-ctrl";
298 reg = <0x41000 0x1000>, <0x40020 0x1c>;
299 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
307 phy-names = "sata-phy";
313 phy-names = "sata-phy";
318 pcie0: pcie@18012000 {
319 compatible = "brcm,iproc-pcie";
320 reg = <0x18012000 0x1000>;
322 #interrupt-cells = <1>;
323 interrupt-map-mask = <0 0 0 0>;
324 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
326 linux,pci-domain = <0>;
328 bus-range = <0x00 0xff>;
330 #address-cells = <3>;
334 /* Note: The HW does not support I/O resources. So,
335 * only the memory resource range is being specified.
337 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
342 pcie1: pcie@18013000 {
343 compatible = "brcm,iproc-pcie";
344 reg = <0x18013000 0x1000>;
346 #interrupt-cells = <1>;
347 interrupt-map-mask = <0 0 0 0>;
348 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
350 linux,pci-domain = <1>;
352 bus-range = <0x00 0xff>;
354 #address-cells = <3>;
358 /* Note: The HW does not support I/O resources. So,
359 * only the memory resource range is being specified.
361 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
366 pcie2: pcie@18014000 {
367 compatible = "brcm,iproc-pcie";
368 reg = <0x18014000 0x1000>;
370 #interrupt-cells = <1>;
371 interrupt-map-mask = <0 0 0 0>;
372 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
374 linux,pci-domain = <2>;
376 bus-range = <0x00 0xff>;
378 #address-cells = <3>;
382 /* Note: The HW does not support I/O resources. So,
383 * only the memory resource range is being specified.
385 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;