4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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17 * contributors may be used to endorse or promote products derived
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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
37 #include "skeleton.dtsi"
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
57 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
59 enable-method = "brcm,bcm-nsp-smp";
60 secondary-boot-reg = <0xffff0fec>;
66 compatible = "arm,cortex-a9-pmu";
67 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
68 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>;
73 compatible = "simple-bus";
74 ranges = <0x00000000 0x19000000 0x00023000>;
78 a9pll: arm_clk@00000 {
80 compatible = "brcm,nsp-armpll";
82 reg = <0x00000 0x1000>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x20200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&periph_clk>;
93 compatible = "arm,cortex-a9-twd-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_LEVEL_HIGH)>;
97 clocks = <&periph_clk>;
101 compatible = "arm,cortex-a9-twd-wdt";
102 reg = <0x20620 0x20>;
103 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_LEVEL_HIGH)>;
105 clocks = <&periph_clk>;
108 gic: interrupt-controller@21000 {
109 compatible = "arm,cortex-a9-gic";
110 #interrupt-cells = <3>;
111 #address-cells = <0>;
112 interrupt-controller;
113 reg = <0x21000 0x1000>,
118 compatible = "arm,pl310-cache";
119 reg = <0x22000 0x1000>;
126 #address-cells = <1>;
132 compatible = "fixed-clock";
133 clock-frequency = <25000000>;
138 compatible = "fixed-factor-clock";
139 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
144 iprocslow: iprocslow {
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
152 periph_clk: periph_clk {
154 compatible = "fixed-factor-clock";
162 compatible = "simple-bus";
163 ranges = <0x00000000 0x18000000 0x0011c40c>;
164 #address-cells = <1>;
168 compatible = "brcm,nsp-gpio-a";
174 interrupt-controller;
175 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-ranges = <&pinctrl 0 0 32>;
180 compatible = "ns16550a";
181 reg = <0x0300 0x100>;
182 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
188 compatible = "ns16550a";
189 reg = <0x0400 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "arm,pl330", "arm,primecell";
197 reg = <0x20000 0x1000>;
198 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&iprocslow>;
208 clock-names = "apb_pclk";
213 compatible = "brcm,sdhci-iproc-cygnus";
214 reg = <0x21000 0x100>;
215 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
221 amac0: ethernet@22000 {
222 compatible = "brcm,nsp-amac";
223 reg = <0x022000 0x1000>,
225 reg-names = "amac_base", "idm_base";
226 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
230 amac1: ethernet@23000 {
231 compatible = "brcm,nsp-amac";
232 reg = <0x023000 0x1000>,
234 reg-names = "amac_base", "idm_base";
235 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
239 amac2: ethernet@24000 {
240 compatible = "brcm,nsp-amac";
241 reg = <0x024000 0x1000>,
243 reg-names = "amac_base", "idm_base";
244 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
248 mailbox: mailbox@25000 {
249 compatible = "brcm,iproc-fa2-mbox";
250 reg = <0x25000 0x445>;
251 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
253 brcm,rx-status-len = <32>;
258 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
259 reg = <0x026000 0x600>,
262 reg-names = "nand", "iproc-idm", "iproc-ext";
263 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
265 #address-cells = <1>;
272 compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
273 reg = <0x027200 0x184>,
277 reg-names = "mspi", "bspi", "intr_regs",
279 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
286 interrupt-names = "spi_lr_fullness_reached",
287 "spi_lr_session_aborted",
289 "spi_lr_session_done",
293 clocks = <&iprocmed>;
294 clock-names = "iprocmed";
296 #address-cells = <1>;
301 compatible = "brcm,spum-nsp-crypto";
302 reg = <0x2f000 0x900>;
303 mboxes = <&mailbox 0>;
307 compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
308 reg = <0x30000 0x50>;
312 interrupt-controller;
313 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
317 compatible = "brcm,iproc-pwm";
318 reg = <0x31000 0x28>;
325 compatible = "generic-ehci";
326 reg = <0x2a000 0x100>;
327 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
332 compatible = "generic-ohci";
333 reg = <0x2b000 0x100>;
334 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
339 compatible = "brcm,bcm-nsp-rng";
340 reg = <0x33000 0x14>;
343 ccbtimer0: timer@34000 {
344 compatible = "arm,sp804";
345 reg = <0x34000 0x1000>;
346 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&iprocslow>;
349 clock-names = "apb_pclk";
352 ccbtimer1: timer@35000 {
353 compatible = "arm,sp804";
354 reg = <0x35000 0x1000>;
355 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&iprocslow>;
358 clock-names = "apb_pclk";
362 compatible = "brcm,nsp-srab";
363 reg = <0x36000 0x1000>;
364 #address-cells = <1>;
369 /* ports are defined in board DTS */
373 compatible = "brcm,iproc-i2c";
374 reg = <0x38000 0x50>;
375 #address-cells = <1>;
377 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
378 clock-frequency = <100000>;
383 compatible = "arm,sp805", "arm,primecell";
384 reg = <0x39000 0x1000>;
385 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&iprocslow>, <&iprocslow>;
387 clock-names = "wdogclk", "apb_pclk";
390 lcpll0: lcpll0@3f100 {
392 compatible = "brcm,nsp-lcpll0";
393 reg = <0x3f100 0x14>;
395 clock-output-names = "lcpll0", "pcie_phy", "sdio",
399 genpll: genpll@3f140 {
401 compatible = "brcm,nsp-genpll";
402 reg = <0x3f140 0x24>;
404 clock-output-names = "genpll", "phy", "ethernetclk",
405 "usbclk", "iprocfast", "sata1",
409 pinctrl: pinctrl@3f1c0 {
410 compatible = "brcm,nsp-pinmux";
411 reg = <0x3f1c0 0x04>,
416 thermal: thermal@3f2c0 {
417 compatible = "brcm,ns-thermal";
418 reg = <0x3f2c0 0x10>;
419 #thermal-sensor-cells = <0>;
422 sata_phy: sata_phy@40100 {
423 compatible = "brcm,iproc-nsp-sata-phy";
424 reg = <0x40100 0x340>;
426 #address-cells = <1>;
429 sata_phy0: sata-phy@0 {
435 sata_phy1: sata-phy@1 {
443 compatible = "brcm,bcm-nsp-ahci";
444 reg-names = "ahci", "top-ctrl";
445 reg = <0x41000 0x1000>, <0x40020 0x1c>;
446 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
447 #address-cells = <1>;
454 phy-names = "sata-phy";
460 phy-names = "sata-phy";
465 pcie0: pcie@18012000 {
466 compatible = "brcm,iproc-pcie";
467 reg = <0x18012000 0x1000>;
469 #interrupt-cells = <1>;
470 interrupt-map-mask = <0 0 0 0>;
471 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
473 linux,pci-domain = <0>;
475 bus-range = <0x00 0xff>;
477 #address-cells = <3>;
481 /* Note: The HW does not support I/O resources. So,
482 * only the memory resource range is being specified.
484 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
488 msi-parent = <&msi0>;
489 msi0: msi-controller {
490 compatible = "brcm,iproc-msi";
492 interrupt-parent = <&gic>;
493 interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
494 <GIC_SPI 128 IRQ_TYPE_NONE>,
495 <GIC_SPI 129 IRQ_TYPE_NONE>,
496 <GIC_SPI 130 IRQ_TYPE_NONE>;
501 pcie1: pcie@18013000 {
502 compatible = "brcm,iproc-pcie";
503 reg = <0x18013000 0x1000>;
505 #interrupt-cells = <1>;
506 interrupt-map-mask = <0 0 0 0>;
507 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
509 linux,pci-domain = <1>;
511 bus-range = <0x00 0xff>;
513 #address-cells = <3>;
517 /* Note: The HW does not support I/O resources. So,
518 * only the memory resource range is being specified.
520 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
524 msi-parent = <&msi1>;
525 msi1: msi-controller {
526 compatible = "brcm,iproc-msi";
528 interrupt-parent = <&gic>;
529 interrupts = <GIC_SPI 133 IRQ_TYPE_NONE>,
530 <GIC_SPI 134 IRQ_TYPE_NONE>,
531 <GIC_SPI 135 IRQ_TYPE_NONE>,
532 <GIC_SPI 136 IRQ_TYPE_NONE>;
537 pcie2: pcie@18014000 {
538 compatible = "brcm,iproc-pcie";
539 reg = <0x18014000 0x1000>;
541 #interrupt-cells = <1>;
542 interrupt-map-mask = <0 0 0 0>;
543 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
545 linux,pci-domain = <2>;
547 bus-range = <0x00 0xff>;
549 #address-cells = <3>;
553 /* Note: The HW does not support I/O resources. So,
554 * only the memory resource range is being specified.
556 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
560 msi-parent = <&msi2>;
561 msi2: msi-controller {
562 compatible = "brcm,iproc-msi";
564 interrupt-parent = <&gic>;
565 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>,
566 <GIC_SPI 140 IRQ_TYPE_NONE>,
567 <GIC_SPI 141 IRQ_TYPE_NONE>,
568 <GIC_SPI 142 IRQ_TYPE_NONE>;
575 polling-delay-passive = <0>;
576 polling-delay = <1000>;
577 coefficients = <(-556) 418000>;
578 thermal-sensors = <&thermal>;
582 temperature = <125000>;