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efi: Change down_interruptible() in virt_efi_reset_system() to down_trylock()
[mirror_ubuntu-jammy-kernel.git] / arch / arm / boot / dts / bcm2711.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
3
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
6
7 / {
8 compatible = "brcm,bcm2711";
9
10 #address-cells = <2>;
11 #size-cells = <1>;
12
13 interrupt-parent = <&gicv2>;
14
15 vc4: gpu {
16 compatible = "brcm,bcm2711-vc5";
17 status = "disabled";
18 };
19
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
25 };
26
27 clk_108MHz: clk-108M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
32 };
33
34 soc {
35 /*
36 * Defined ranges:
37 * Common BCM283x peripherals
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
40 */
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
46
47 /*
48 * This node is the provider for the enable-method for
49 * bringing up secondary cores.
50 */
51 local_intc: local_intc@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
53 reg = <0x40000000 0x100>;
54 };
55
56 gicv2: interrupt-controller@40041000 {
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
60 reg = <0x40041000 0x1000>,
61 <0x40042000 0x2000>,
62 <0x40044000 0x2000>,
63 <0x40046000 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
65 IRQ_TYPE_LEVEL_HIGH)>;
66 };
67
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
71 reg = <0x7d5d2000 0xf00>;
72
73 thermal: thermal {
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
76 };
77 };
78
79 dma: dma@7e007000 {
80 compatible = "brcm,bcm2835-dma";
81 reg = <0x7e007000 0xb00>;
82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
89 /* DMA lite 7 - 10 */
90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-names = "dma0",
95 "dma1",
96 "dma2",
97 "dma3",
98 "dma4",
99 "dma5",
100 "dma6",
101 "dma7",
102 "dma8",
103 "dma9",
104 "dma10";
105 #dma-cells = <1>;
106 brcm,dma-channel-mask = <0x07f5>;
107 };
108
109 pm: watchdog@7e100000 {
110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
112 #reset-cells = <1>;
113 reg = <0x7e100000 0x114>,
114 <0x7e00a000 0x24>,
115 <0x7ec11000 0x20>;
116 clocks = <&clocks BCM2835_CLOCK_V3D>,
117 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
118 <&clocks BCM2835_CLOCK_H264>,
119 <&clocks BCM2835_CLOCK_ISP>;
120 clock-names = "v3d", "peri_image", "h264", "isp";
121 system-power-controller;
122 };
123
124 rng@7e104000 {
125 compatible = "brcm,bcm2711-rng200";
126 reg = <0x7e104000 0x28>;
127 };
128
129 uart2: serial@7e201400 {
130 compatible = "arm,pl011", "arm,primecell";
131 reg = <0x7e201400 0x200>;
132 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&clocks BCM2835_CLOCK_UART>,
134 <&clocks BCM2835_CLOCK_VPU>;
135 clock-names = "uartclk", "apb_pclk";
136 arm,primecell-periphid = <0x00241011>;
137 status = "disabled";
138 };
139
140 uart3: serial@7e201600 {
141 compatible = "arm,pl011", "arm,primecell";
142 reg = <0x7e201600 0x200>;
143 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&clocks BCM2835_CLOCK_UART>,
145 <&clocks BCM2835_CLOCK_VPU>;
146 clock-names = "uartclk", "apb_pclk";
147 arm,primecell-periphid = <0x00241011>;
148 status = "disabled";
149 };
150
151 uart4: serial@7e201800 {
152 compatible = "arm,pl011", "arm,primecell";
153 reg = <0x7e201800 0x200>;
154 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&clocks BCM2835_CLOCK_UART>,
156 <&clocks BCM2835_CLOCK_VPU>;
157 clock-names = "uartclk", "apb_pclk";
158 arm,primecell-periphid = <0x00241011>;
159 status = "disabled";
160 };
161
162 uart5: serial@7e201a00 {
163 compatible = "arm,pl011", "arm,primecell";
164 reg = <0x7e201a00 0x200>;
165 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&clocks BCM2835_CLOCK_UART>,
167 <&clocks BCM2835_CLOCK_VPU>;
168 clock-names = "uartclk", "apb_pclk";
169 arm,primecell-periphid = <0x00241011>;
170 status = "disabled";
171 };
172
173 spi3: spi@7e204600 {
174 compatible = "brcm,bcm2835-spi";
175 reg = <0x7e204600 0x0200>;
176 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&clocks BCM2835_CLOCK_VPU>;
178 #address-cells = <1>;
179 #size-cells = <0>;
180 status = "disabled";
181 };
182
183 spi4: spi@7e204800 {
184 compatible = "brcm,bcm2835-spi";
185 reg = <0x7e204800 0x0200>;
186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clocks BCM2835_CLOCK_VPU>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190 status = "disabled";
191 };
192
193 spi5: spi@7e204a00 {
194 compatible = "brcm,bcm2835-spi";
195 reg = <0x7e204a00 0x0200>;
196 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clocks BCM2835_CLOCK_VPU>;
198 #address-cells = <1>;
199 #size-cells = <0>;
200 status = "disabled";
201 };
202
203 spi6: spi@7e204c00 {
204 compatible = "brcm,bcm2835-spi";
205 reg = <0x7e204c00 0x0200>;
206 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clocks BCM2835_CLOCK_VPU>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 status = "disabled";
211 };
212
213 i2c3: i2c@7e205600 {
214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
215 reg = <0x7e205600 0x200>;
216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clocks BCM2835_CLOCK_VPU>;
218 #address-cells = <1>;
219 #size-cells = <0>;
220 status = "disabled";
221 };
222
223 i2c4: i2c@7e205800 {
224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
225 reg = <0x7e205800 0x200>;
226 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clocks BCM2835_CLOCK_VPU>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230 status = "disabled";
231 };
232
233 i2c5: i2c@7e205a00 {
234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
235 reg = <0x7e205a00 0x200>;
236 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clocks BCM2835_CLOCK_VPU>;
238 #address-cells = <1>;
239 #size-cells = <0>;
240 status = "disabled";
241 };
242
243 i2c6: i2c@7e205c00 {
244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
245 reg = <0x7e205c00 0x200>;
246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clocks BCM2835_CLOCK_VPU>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 status = "disabled";
251 };
252
253 pixelvalve0: pixelvalve@7e206000 {
254 compatible = "brcm,bcm2711-pixelvalve0";
255 reg = <0x7e206000 0x100>;
256 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
257 status = "disabled";
258 };
259
260 pixelvalve1: pixelvalve@7e207000 {
261 compatible = "brcm,bcm2711-pixelvalve1";
262 reg = <0x7e207000 0x100>;
263 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
264 status = "disabled";
265 };
266
267 pixelvalve2: pixelvalve@7e20a000 {
268 compatible = "brcm,bcm2711-pixelvalve2";
269 reg = <0x7e20a000 0x100>;
270 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
271 status = "disabled";
272 };
273
274 pwm1: pwm@7e20c800 {
275 compatible = "brcm,bcm2835-pwm";
276 reg = <0x7e20c800 0x28>;
277 clocks = <&clocks BCM2835_CLOCK_PWM>;
278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
279 assigned-clock-rates = <10000000>;
280 #pwm-cells = <2>;
281 status = "disabled";
282 };
283
284 pixelvalve4: pixelvalve@7e216000 {
285 compatible = "brcm,bcm2711-pixelvalve4";
286 reg = <0x7e216000 0x100>;
287 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
288 status = "disabled";
289 };
290
291 hvs: hvs@7e400000 {
292 compatible = "brcm,bcm2711-hvs";
293 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
294 };
295
296 pixelvalve3: pixelvalve@7ec12000 {
297 compatible = "brcm,bcm2711-pixelvalve3";
298 reg = <0x7ec12000 0x100>;
299 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
300 status = "disabled";
301 };
302
303 dvp: clock@7ef00000 {
304 compatible = "brcm,brcm2711-dvp";
305 reg = <0x7ef00000 0x10>;
306 clocks = <&clk_108MHz>;
307 #clock-cells = <1>;
308 #reset-cells = <1>;
309 };
310
311 aon_intr: interrupt-controller@7ef00100 {
312 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
313 reg = <0x7ef00100 0x30>;
314 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
315 interrupt-controller;
316 #interrupt-cells = <1>;
317 };
318
319 hdmi0: hdmi@7ef00700 {
320 compatible = "brcm,bcm2711-hdmi0";
321 reg = <0x7ef00700 0x300>,
322 <0x7ef00300 0x200>,
323 <0x7ef00f00 0x80>,
324 <0x7ef00f80 0x80>,
325 <0x7ef01b00 0x200>,
326 <0x7ef01f00 0x400>,
327 <0x7ef00200 0x80>,
328 <0x7ef04300 0x100>,
329 <0x7ef20000 0x100>;
330 reg-names = "hdmi",
331 "dvp",
332 "phy",
333 "rm",
334 "packet",
335 "metadata",
336 "csc",
337 "cec",
338 "hd";
339 clock-names = "hdmi", "bvb", "audio", "cec";
340 resets = <&dvp 0>;
341 interrupt-parent = <&aon_intr>;
342 interrupts = <0>, <1>, <2>,
343 <3>, <4>, <5>;
344 interrupt-names = "cec-tx", "cec-rx", "cec-low",
345 "wakeup", "hpd-connected", "hpd-removed";
346 ddc = <&ddc0>;
347 dmas = <&dma 10>;
348 dma-names = "audio-rx";
349 status = "disabled";
350 };
351
352 ddc0: i2c@7ef04500 {
353 compatible = "brcm,bcm2711-hdmi-i2c";
354 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
355 reg-names = "bsc", "auto-i2c";
356 clock-frequency = <97500>;
357 status = "disabled";
358 };
359
360 hdmi1: hdmi@7ef05700 {
361 compatible = "brcm,bcm2711-hdmi1";
362 reg = <0x7ef05700 0x300>,
363 <0x7ef05300 0x200>,
364 <0x7ef05f00 0x80>,
365 <0x7ef05f80 0x80>,
366 <0x7ef06b00 0x200>,
367 <0x7ef06f00 0x400>,
368 <0x7ef00280 0x80>,
369 <0x7ef09300 0x100>,
370 <0x7ef20000 0x100>;
371 reg-names = "hdmi",
372 "dvp",
373 "phy",
374 "rm",
375 "packet",
376 "metadata",
377 "csc",
378 "cec",
379 "hd";
380 ddc = <&ddc1>;
381 clock-names = "hdmi", "bvb", "audio", "cec";
382 resets = <&dvp 1>;
383 interrupt-parent = <&aon_intr>;
384 interrupts = <8>, <7>, <6>,
385 <9>, <10>, <11>;
386 interrupt-names = "cec-tx", "cec-rx", "cec-low",
387 "wakeup", "hpd-connected", "hpd-removed";
388 dmas = <&dma 17>;
389 dma-names = "audio-rx";
390 status = "disabled";
391 };
392
393 ddc1: i2c@7ef09500 {
394 compatible = "brcm,bcm2711-hdmi-i2c";
395 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
396 reg-names = "bsc", "auto-i2c";
397 clock-frequency = <97500>;
398 status = "disabled";
399 };
400 };
401
402 /*
403 * emmc2 has different DMA constraints based on SoC revisions. It was
404 * moved into its own bus, so as for RPi4's firmware to update them.
405 * The firmware will find whether the emmc2bus alias is defined, and if
406 * so, it'll edit the dma-ranges property below accordingly.
407 */
408 emmc2bus: emmc2bus {
409 compatible = "simple-bus";
410 #address-cells = <2>;
411 #size-cells = <1>;
412
413 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
414 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
415
416 emmc2: mmc@7e340000 {
417 compatible = "brcm,bcm2711-emmc2";
418 reg = <0x0 0x7e340000 0x100>;
419 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
421 status = "disabled";
422 };
423 };
424
425 arm-pmu {
426 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
427 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
432 };
433
434 timer {
435 compatible = "arm,armv8-timer";
436 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
437 IRQ_TYPE_LEVEL_LOW)>,
438 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
439 IRQ_TYPE_LEVEL_LOW)>,
440 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
441 IRQ_TYPE_LEVEL_LOW)>,
442 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
443 IRQ_TYPE_LEVEL_LOW)>;
444 /* This only applies to the ARMv7 stub */
445 arm,cpu-registers-not-fw-configured;
446 };
447
448 cpus: cpus {
449 #address-cells = <1>;
450 #size-cells = <0>;
451 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
452
453 cpu0: cpu@0 {
454 device_type = "cpu";
455 compatible = "arm,cortex-a72";
456 reg = <0>;
457 enable-method = "spin-table";
458 cpu-release-addr = <0x0 0x000000d8>;
459 };
460
461 cpu1: cpu@1 {
462 device_type = "cpu";
463 compatible = "arm,cortex-a72";
464 reg = <1>;
465 enable-method = "spin-table";
466 cpu-release-addr = <0x0 0x000000e0>;
467 };
468
469 cpu2: cpu@2 {
470 device_type = "cpu";
471 compatible = "arm,cortex-a72";
472 reg = <2>;
473 enable-method = "spin-table";
474 cpu-release-addr = <0x0 0x000000e8>;
475 };
476
477 cpu3: cpu@3 {
478 device_type = "cpu";
479 compatible = "arm,cortex-a72";
480 reg = <3>;
481 enable-method = "spin-table";
482 cpu-release-addr = <0x0 0x000000f0>;
483 };
484 };
485
486 scb {
487 compatible = "simple-bus";
488 #address-cells = <2>;
489 #size-cells = <1>;
490
491 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
492 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
493
494 pcie0: pcie@7d500000 {
495 compatible = "brcm,bcm2711-pcie";
496 reg = <0x0 0x7d500000 0x9310>;
497 device_type = "pci";
498 #address-cells = <3>;
499 #interrupt-cells = <1>;
500 #size-cells = <2>;
501 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "pcie", "msi";
504 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
505 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
506 IRQ_TYPE_LEVEL_HIGH>;
507 msi-controller;
508 msi-parent = <&pcie0>;
509
510 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
511 0x0 0x04000000>;
512 /*
513 * The wrapper around the PCIe block has a bug
514 * preventing it from accessing beyond the first 3GB of
515 * memory.
516 */
517 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
518 0x0 0xc0000000>;
519 brcm,enable-ssc;
520 };
521
522 genet: ethernet@7d580000 {
523 compatible = "brcm,bcm2711-genet-v5";
524 reg = <0x0 0x7d580000 0x10000>;
525 #address-cells = <0x1>;
526 #size-cells = <0x1>;
527 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
529 status = "disabled";
530
531 genet_mdio: mdio@e14 {
532 compatible = "brcm,genet-mdio-v5";
533 reg = <0xe14 0x8>;
534 reg-names = "mdio";
535 #address-cells = <0x0>;
536 #size-cells = <0x1>;
537 };
538 };
539 };
540 };
541
542 &clk_osc {
543 clock-frequency = <54000000>;
544 };
545
546 &clocks {
547 compatible = "brcm,bcm2711-cprman";
548 };
549
550 &cpu_thermal {
551 coefficients = <(-487) 410040>;
552 thermal-sensors = <&thermal>;
553 };
554
555 &dsi0 {
556 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
557 };
558
559 &dsi1 {
560 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
561 compatible = "brcm,bcm2711-dsi1";
562 };
563
564 &gpio {
565 compatible = "brcm,bcm2711-gpio";
566 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
570
571 gpclk0_gpio49: gpclk0_gpio49 {
572 pin-gpclk {
573 pins = "gpio49";
574 function = "alt1";
575 bias-disable;
576 };
577 };
578 gpclk1_gpio50: gpclk1_gpio50 {
579 pin-gpclk {
580 pins = "gpio50";
581 function = "alt1";
582 bias-disable;
583 };
584 };
585 gpclk2_gpio51: gpclk2_gpio51 {
586 pin-gpclk {
587 pins = "gpio51";
588 function = "alt1";
589 bias-disable;
590 };
591 };
592
593 i2c0_gpio46: i2c0_gpio46 {
594 pin-sda {
595 function = "alt0";
596 pins = "gpio46";
597 bias-pull-up;
598 };
599 pin-scl {
600 function = "alt0";
601 pins = "gpio47";
602 bias-disable;
603 };
604 };
605 i2c1_gpio46: i2c1_gpio46 {
606 pin-sda {
607 function = "alt1";
608 pins = "gpio46";
609 bias-pull-up;
610 };
611 pin-scl {
612 function = "alt1";
613 pins = "gpio47";
614 bias-disable;
615 };
616 };
617 i2c3_gpio2: i2c3_gpio2 {
618 pin-sda {
619 function = "alt5";
620 pins = "gpio2";
621 bias-pull-up;
622 };
623 pin-scl {
624 function = "alt5";
625 pins = "gpio3";
626 bias-disable;
627 };
628 };
629 i2c3_gpio4: i2c3_gpio4 {
630 pin-sda {
631 function = "alt5";
632 pins = "gpio4";
633 bias-pull-up;
634 };
635 pin-scl {
636 function = "alt5";
637 pins = "gpio5";
638 bias-disable;
639 };
640 };
641 i2c4_gpio6: i2c4_gpio6 {
642 pin-sda {
643 function = "alt5";
644 pins = "gpio6";
645 bias-pull-up;
646 };
647 pin-scl {
648 function = "alt5";
649 pins = "gpio7";
650 bias-disable;
651 };
652 };
653 i2c4_gpio8: i2c4_gpio8 {
654 pin-sda {
655 function = "alt5";
656 pins = "gpio8";
657 bias-pull-up;
658 };
659 pin-scl {
660 function = "alt5";
661 pins = "gpio9";
662 bias-disable;
663 };
664 };
665 i2c5_gpio10: i2c5_gpio10 {
666 pin-sda {
667 function = "alt5";
668 pins = "gpio10";
669 bias-pull-up;
670 };
671 pin-scl {
672 function = "alt5";
673 pins = "gpio11";
674 bias-disable;
675 };
676 };
677 i2c5_gpio12: i2c5_gpio12 {
678 pin-sda {
679 function = "alt5";
680 pins = "gpio12";
681 bias-pull-up;
682 };
683 pin-scl {
684 function = "alt5";
685 pins = "gpio13";
686 bias-disable;
687 };
688 };
689 i2c6_gpio0: i2c6_gpio0 {
690 pin-sda {
691 function = "alt5";
692 pins = "gpio0";
693 bias-pull-up;
694 };
695 pin-scl {
696 function = "alt5";
697 pins = "gpio1";
698 bias-disable;
699 };
700 };
701 i2c6_gpio22: i2c6_gpio22 {
702 pin-sda {
703 function = "alt5";
704 pins = "gpio22";
705 bias-pull-up;
706 };
707 pin-scl {
708 function = "alt5";
709 pins = "gpio23";
710 bias-disable;
711 };
712 };
713 i2c_slave_gpio8: i2c_slave_gpio8 {
714 pins-i2c-slave {
715 pins = "gpio8",
716 "gpio9",
717 "gpio10",
718 "gpio11";
719 function = "alt3";
720 };
721 };
722
723 jtag_gpio48: jtag_gpio48 {
724 pins-jtag {
725 pins = "gpio48",
726 "gpio49",
727 "gpio50",
728 "gpio51",
729 "gpio52",
730 "gpio53";
731 function = "alt4";
732 };
733 };
734
735 mii_gpio28: mii_gpio28 {
736 pins-mii {
737 pins = "gpio28",
738 "gpio29",
739 "gpio30",
740 "gpio31";
741 function = "alt4";
742 };
743 };
744 mii_gpio36: mii_gpio36 {
745 pins-mii {
746 pins = "gpio36",
747 "gpio37",
748 "gpio38",
749 "gpio39";
750 function = "alt5";
751 };
752 };
753
754 pcm_gpio50: pcm_gpio50 {
755 pins-pcm {
756 pins = "gpio50",
757 "gpio51",
758 "gpio52",
759 "gpio53";
760 function = "alt2";
761 };
762 };
763
764 pwm0_0_gpio12: pwm0_0_gpio12 {
765 pin-pwm {
766 pins = "gpio12";
767 function = "alt0";
768 bias-disable;
769 };
770 };
771 pwm0_0_gpio18: pwm0_0_gpio18 {
772 pin-pwm {
773 pins = "gpio18";
774 function = "alt5";
775 bias-disable;
776 };
777 };
778 pwm1_0_gpio40: pwm1_0_gpio40 {
779 pin-pwm {
780 pins = "gpio40";
781 function = "alt0";
782 bias-disable;
783 };
784 };
785 pwm0_1_gpio13: pwm0_1_gpio13 {
786 pin-pwm {
787 pins = "gpio13";
788 function = "alt0";
789 bias-disable;
790 };
791 };
792 pwm0_1_gpio19: pwm0_1_gpio19 {
793 pin-pwm {
794 pins = "gpio19";
795 function = "alt5";
796 bias-disable;
797 };
798 };
799 pwm1_1_gpio41: pwm1_1_gpio41 {
800 pin-pwm {
801 pins = "gpio41";
802 function = "alt0";
803 bias-disable;
804 };
805 };
806 pwm0_1_gpio45: pwm0_1_gpio45 {
807 pin-pwm {
808 pins = "gpio45";
809 function = "alt0";
810 bias-disable;
811 };
812 };
813 pwm0_0_gpio52: pwm0_0_gpio52 {
814 pin-pwm {
815 pins = "gpio52";
816 function = "alt1";
817 bias-disable;
818 };
819 };
820 pwm0_1_gpio53: pwm0_1_gpio53 {
821 pin-pwm {
822 pins = "gpio53";
823 function = "alt1";
824 bias-disable;
825 };
826 };
827
828 rgmii_gpio35: rgmii_gpio35 {
829 pin-start-stop {
830 pins = "gpio35";
831 function = "alt4";
832 };
833 pin-rx-ok {
834 pins = "gpio36";
835 function = "alt4";
836 };
837 };
838 rgmii_irq_gpio34: rgmii_irq_gpio34 {
839 pin-irq {
840 pins = "gpio34";
841 function = "alt5";
842 };
843 };
844 rgmii_irq_gpio39: rgmii_irq_gpio39 {
845 pin-irq {
846 pins = "gpio39";
847 function = "alt4";
848 };
849 };
850 rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
851 pins-mdio {
852 pins = "gpio28",
853 "gpio29";
854 function = "alt5";
855 };
856 };
857 rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
858 pins-mdio {
859 pins = "gpio37",
860 "gpio38";
861 function = "alt4";
862 };
863 };
864
865 spi0_gpio46: spi0_gpio46 {
866 pins-spi {
867 pins = "gpio46",
868 "gpio47",
869 "gpio48",
870 "gpio49";
871 function = "alt2";
872 };
873 };
874 spi2_gpio46: spi2_gpio46 {
875 pins-spi {
876 pins = "gpio46",
877 "gpio47",
878 "gpio48",
879 "gpio49",
880 "gpio50";
881 function = "alt5";
882 };
883 };
884 spi3_gpio0: spi3_gpio0 {
885 pins-spi {
886 pins = "gpio0",
887 "gpio1",
888 "gpio2",
889 "gpio3";
890 function = "alt3";
891 };
892 };
893 spi4_gpio4: spi4_gpio4 {
894 pins-spi {
895 pins = "gpio4",
896 "gpio5",
897 "gpio6",
898 "gpio7";
899 function = "alt3";
900 };
901 };
902 spi5_gpio12: spi5_gpio12 {
903 pins-spi {
904 pins = "gpio12",
905 "gpio13",
906 "gpio14",
907 "gpio15";
908 function = "alt3";
909 };
910 };
911 spi6_gpio18: spi6_gpio18 {
912 pins-spi {
913 pins = "gpio18",
914 "gpio19",
915 "gpio20",
916 "gpio21";
917 function = "alt3";
918 };
919 };
920
921 uart2_gpio0: uart2_gpio0 {
922 pin-tx {
923 pins = "gpio0";
924 function = "alt4";
925 bias-disable;
926 };
927 pin-rx {
928 pins = "gpio1";
929 function = "alt4";
930 bias-pull-up;
931 };
932 };
933 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
934 pin-cts {
935 pins = "gpio2";
936 function = "alt4";
937 bias-pull-up;
938 };
939 pin-rts {
940 pins = "gpio3";
941 function = "alt4";
942 bias-disable;
943 };
944 };
945 uart3_gpio4: uart3_gpio4 {
946 pin-tx {
947 pins = "gpio4";
948 function = "alt4";
949 bias-disable;
950 };
951 pin-rx {
952 pins = "gpio5";
953 function = "alt4";
954 bias-pull-up;
955 };
956 };
957 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
958 pin-cts {
959 pins = "gpio6";
960 function = "alt4";
961 bias-pull-up;
962 };
963 pin-rts {
964 pins = "gpio7";
965 function = "alt4";
966 bias-disable;
967 };
968 };
969 uart4_gpio8: uart4_gpio8 {
970 pin-tx {
971 pins = "gpio8";
972 function = "alt4";
973 bias-disable;
974 };
975 pin-rx {
976 pins = "gpio9";
977 function = "alt4";
978 bias-pull-up;
979 };
980 };
981 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
982 pin-cts {
983 pins = "gpio10";
984 function = "alt4";
985 bias-pull-up;
986 };
987 pin-rts {
988 pins = "gpio11";
989 function = "alt4";
990 bias-disable;
991 };
992 };
993 uart5_gpio12: uart5_gpio12 {
994 pin-tx {
995 pins = "gpio12";
996 function = "alt4";
997 bias-disable;
998 };
999 pin-rx {
1000 pins = "gpio13";
1001 function = "alt4";
1002 bias-pull-up;
1003 };
1004 };
1005 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1006 pin-cts {
1007 pins = "gpio14";
1008 function = "alt4";
1009 bias-pull-up;
1010 };
1011 pin-rts {
1012 pins = "gpio15";
1013 function = "alt4";
1014 bias-disable;
1015 };
1016 };
1017 };
1018
1019 &rmem {
1020 #address-cells = <2>;
1021 };
1022
1023 &cma {
1024 /*
1025 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
1026 * that's not good enough for the BCM2711 as some devices can
1027 * only address the lower 1G of memory (ZONE_DMA).
1028 */
1029 alloc-ranges = <0x0 0x00000000 0x40000000>;
1030 };
1031
1032 &i2c0 {
1033 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1034 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1035 };
1036
1037 &i2c1 {
1038 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1039 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1040 };
1041
1042 &mailbox {
1043 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1044 };
1045
1046 &sdhci {
1047 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1048 };
1049
1050 &sdhost {
1051 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1052 };
1053
1054 &spi {
1055 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1056 };
1057
1058 &spi1 {
1059 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1060 };
1061
1062 &spi2 {
1063 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1064 };
1065
1066 &system_timer {
1067 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1069 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1070 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1071 };
1072
1073 &txp {
1074 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1075 };
1076
1077 &uart0 {
1078 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1079 };
1080
1081 &uart1 {
1082 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1083 };
1084
1085 &usb {
1086 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1087 };
1088
1089 &vec {
1090 compatible = "brcm,bcm2711-vec";
1091 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1092 };
Ubuntu Jammy Linux kernel mirror