1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
6 /* This include file covers the common peripherals and configuration between
7 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
8 * bcm2835.dtsi and bcm2836.dtsi.
12 compatible = "brcm,bcm2835";
14 interrupt-parent = <&intc>;
19 bootargs = "earlyprintk console=ttyAMA0";
23 compatible = "simple-bus";
28 compatible = "brcm,bcm2835-system-timer";
29 reg = <0x7e003000 0x1000>;
30 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
31 /* This could be a reference to BCM2835_CLOCK_TIMER,
32 * but we don't have the driver using the common clock
35 clock-frequency = <1000000>;
39 compatible = "brcm,bcm2835-dma";
40 reg = <0x7e007000 0xf00>;
52 /* dma channel 11-14 share one irq */
57 /* unused shared irq for all channels */
59 interrupt-names = "dma0",
76 brcm,dma-channel-mask = <0x7f35>;
79 intc: interrupt-controller@7e00b200 {
80 compatible = "brcm,bcm2835-armctrl-ic";
81 reg = <0x7e00b200 0x200>;
83 #interrupt-cells = <2>;
87 compatible = "brcm,bcm2835-pm-wdt";
88 reg = <0x7e100000 0x28>;
91 clocks: cprman@7e101000 {
92 compatible = "brcm,bcm2835-cprman";
94 reg = <0x7e101000 0x2000>;
96 /* CPRMAN derives almost everything from the
97 * platform's oscillator. However, the DSI
98 * pixel clocks come from the DSI analog PHY.
101 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
102 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
106 compatible = "brcm,bcm2835-rng";
107 reg = <0x7e104000 0x10>;
110 mailbox: mailbox@7e00b880 {
111 compatible = "brcm,bcm2835-mbox";
112 reg = <0x7e00b880 0x40>;
117 gpio: gpio@7e200000 {
118 compatible = "brcm,bcm2835-gpio";
119 reg = <0x7e200000 0xb4>;
121 * The GPIO IP block is designed for 3 banks of GPIOs.
122 * Each bank has a GPIO interrupt for itself.
123 * There is an overall "any bank" interrupt.
124 * In order, these are GIC interrupts 17, 18, 19, 20.
125 * Since the BCM2835 only has 2 banks, the 2nd bank
126 * interrupt output appears to be mirrored onto the
127 * 3rd bank's interrupt signal.
128 * So, a bank0 interrupt shows up on 17, 20, and
129 * a bank1 interrupt shows up on 18, 19, 20!
131 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
139 /* Defines pin muxing groups according to
140 * BCM2835-ARM-Peripherals.pdf page 102.
142 * While each pin can have its mux selected
143 * for various functions individually, some
144 * groups only make sense to switch to a
145 * particular function together.
147 dpi_gpio0: dpi_gpio0 {
148 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
149 12 13 14 15 16 17 18 19
150 20 21 22 23 24 25 26 27>;
151 brcm,function = <BCM2835_FSEL_ALT2>;
153 emmc_gpio22: emmc_gpio22 {
154 brcm,pins = <22 23 24 25 26 27>;
155 brcm,function = <BCM2835_FSEL_ALT3>;
157 emmc_gpio34: emmc_gpio34 {
158 brcm,pins = <34 35 36 37 38 39>;
159 brcm,function = <BCM2835_FSEL_ALT3>;
160 brcm,pull = <BCM2835_PUD_OFF
167 emmc_gpio48: emmc_gpio48 {
168 brcm,pins = <48 49 50 51 52 53>;
169 brcm,function = <BCM2835_FSEL_ALT3>;
172 gpclk0_gpio4: gpclk0_gpio4 {
174 brcm,function = <BCM2835_FSEL_ALT0>;
176 gpclk1_gpio5: gpclk1_gpio5 {
178 brcm,function = <BCM2835_FSEL_ALT0>;
180 gpclk1_gpio42: gpclk1_gpio42 {
182 brcm,function = <BCM2835_FSEL_ALT0>;
184 gpclk1_gpio44: gpclk1_gpio44 {
186 brcm,function = <BCM2835_FSEL_ALT0>;
188 gpclk2_gpio6: gpclk2_gpio6 {
190 brcm,function = <BCM2835_FSEL_ALT0>;
192 gpclk2_gpio43: gpclk2_gpio43 {
194 brcm,function = <BCM2835_FSEL_ALT0>;
197 i2c0_gpio0: i2c0_gpio0 {
199 brcm,function = <BCM2835_FSEL_ALT0>;
201 i2c0_gpio32: i2c0_gpio32 {
203 brcm,function = <BCM2835_FSEL_ALT0>;
205 i2c0_gpio44: i2c0_gpio44 {
207 brcm,function = <BCM2835_FSEL_ALT1>;
209 i2c1_gpio2: i2c1_gpio2 {
211 brcm,function = <BCM2835_FSEL_ALT0>;
213 i2c1_gpio44: i2c1_gpio44 {
215 brcm,function = <BCM2835_FSEL_ALT2>;
217 i2c_slave_gpio18: i2c_slave_gpio18 {
218 brcm,pins = <18 19 20 21>;
219 brcm,function = <BCM2835_FSEL_ALT3>;
222 jtag_gpio4: jtag_gpio4 {
223 brcm,pins = <4 5 6 12 13>;
224 brcm,function = <BCM2835_FSEL_ALT4>;
226 jtag_gpio22: jtag_gpio22 {
227 brcm,pins = <22 23 24 25 26 27>;
228 brcm,function = <BCM2835_FSEL_ALT4>;
231 pcm_gpio18: pcm_gpio18 {
232 brcm,pins = <18 19 20 21>;
233 brcm,function = <BCM2835_FSEL_ALT0>;
235 pcm_gpio28: pcm_gpio28 {
236 brcm,pins = <28 29 30 31>;
237 brcm,function = <BCM2835_FSEL_ALT2>;
240 pwm0_gpio12: pwm0_gpio12 {
242 brcm,function = <BCM2835_FSEL_ALT0>;
244 pwm0_gpio18: pwm0_gpio18 {
246 brcm,function = <BCM2835_FSEL_ALT5>;
248 pwm0_gpio40: pwm0_gpio40 {
250 brcm,function = <BCM2835_FSEL_ALT0>;
252 pwm1_gpio13: pwm1_gpio13 {
254 brcm,function = <BCM2835_FSEL_ALT0>;
256 pwm1_gpio19: pwm1_gpio19 {
258 brcm,function = <BCM2835_FSEL_ALT5>;
260 pwm1_gpio41: pwm1_gpio41 {
262 brcm,function = <BCM2835_FSEL_ALT0>;
264 pwm1_gpio45: pwm1_gpio45 {
266 brcm,function = <BCM2835_FSEL_ALT0>;
269 sdhost_gpio48: sdhost_gpio48 {
270 brcm,pins = <48 49 50 51 52 53>;
271 brcm,function = <BCM2835_FSEL_ALT0>;
274 spi0_gpio7: spi0_gpio7 {
275 brcm,pins = <7 8 9 10 11>;
276 brcm,function = <BCM2835_FSEL_ALT0>;
278 spi0_gpio35: spi0_gpio35 {
279 brcm,pins = <35 36 37 38 39>;
280 brcm,function = <BCM2835_FSEL_ALT0>;
282 spi1_gpio16: spi1_gpio16 {
283 brcm,pins = <16 17 18 19 20 21>;
284 brcm,function = <BCM2835_FSEL_ALT4>;
286 spi2_gpio40: spi2_gpio40 {
287 brcm,pins = <40 41 42 43 44 45>;
288 brcm,function = <BCM2835_FSEL_ALT4>;
291 uart0_gpio14: uart0_gpio14 {
293 brcm,function = <BCM2835_FSEL_ALT0>;
295 /* Separate from the uart0_gpio14 group
296 * because it conflicts with spi1_gpio16, and
297 * people often run uart0 on the two pins
298 * without flow contrl.
300 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
302 brcm,function = <BCM2835_FSEL_ALT3>;
304 uart0_gpio30: uart0_gpio30 {
306 brcm,function = <BCM2835_FSEL_ALT3>;
308 uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
310 brcm,function = <BCM2835_FSEL_ALT3>;
313 uart1_gpio14: uart1_gpio14 {
315 brcm,function = <BCM2835_FSEL_ALT5>;
317 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
319 brcm,function = <BCM2835_FSEL_ALT5>;
321 uart1_gpio32: uart1_gpio32 {
323 brcm,function = <BCM2835_FSEL_ALT5>;
325 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
327 brcm,function = <BCM2835_FSEL_ALT5>;
329 uart1_gpio36: uart1_gpio36 {
330 brcm,pins = <36 37 38 39>;
331 brcm,function = <BCM2835_FSEL_ALT2>;
333 uart1_gpio40: uart1_gpio40 {
335 brcm,function = <BCM2835_FSEL_ALT5>;
337 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
339 brcm,function = <BCM2835_FSEL_ALT5>;
343 uart0: serial@7e201000 {
344 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
345 reg = <0x7e201000 0x1000>;
347 clocks = <&clocks BCM2835_CLOCK_UART>,
348 <&clocks BCM2835_CLOCK_VPU>;
349 clock-names = "uartclk", "apb_pclk";
350 arm,primecell-periphid = <0x00241011>;
354 compatible = "brcm,bcm2835-i2s";
355 reg = <0x7e203000 0x20>,
360 dma-names = "tx", "rx";
365 compatible = "brcm,bcm2835-spi";
366 reg = <0x7e204000 0x1000>;
368 clocks = <&clocks BCM2835_CLOCK_VPU>;
369 #address-cells = <1>;
372 cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
376 compatible = "brcm,bcm2835-i2c";
377 reg = <0x7e205000 0x1000>;
379 clocks = <&clocks BCM2835_CLOCK_VPU>;
380 #address-cells = <1>;
385 pixelvalve@7e206000 {
386 compatible = "brcm,bcm2835-pixelvalve0";
387 reg = <0x7e206000 0x100>;
388 interrupts = <2 13>; /* pwa0 */
391 pixelvalve@7e207000 {
392 compatible = "brcm,bcm2835-pixelvalve1";
393 reg = <0x7e207000 0x100>;
394 interrupts = <2 14>; /* pwa1 */
398 compatible = "brcm,bcm2835-dsi0";
399 reg = <0x7e209000 0x78>;
401 #address-cells = <1>;
405 clocks = <&clocks BCM2835_PLLA_DSI0>,
406 <&clocks BCM2835_CLOCK_DSI0E>,
407 <&clocks BCM2835_CLOCK_DSI0P>;
408 clock-names = "phy", "escape", "pixel";
410 clock-output-names = "dsi0_byte",
417 thermal: thermal@7e212000 {
418 compatible = "brcm,bcm2835-thermal";
419 reg = <0x7e212000 0x8>;
420 clocks = <&clocks BCM2835_CLOCK_TSENS>;
424 aux: aux@0x7e215000 {
425 compatible = "brcm,bcm2835-aux";
427 reg = <0x7e215000 0x8>;
428 clocks = <&clocks BCM2835_CLOCK_VPU>;
431 uart1: serial@7e215040 {
432 compatible = "brcm,bcm2835-aux-uart";
433 reg = <0x7e215040 0x40>;
435 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
440 compatible = "brcm,bcm2835-aux-spi";
441 reg = <0x7e215080 0x40>;
443 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
444 #address-cells = <1>;
450 compatible = "brcm,bcm2835-aux-spi";
451 reg = <0x7e2150c0 0x40>;
453 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
454 #address-cells = <1>;
460 compatible = "brcm,bcm2835-pwm";
461 reg = <0x7e20c000 0x28>;
462 clocks = <&clocks BCM2835_CLOCK_PWM>;
463 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
464 assigned-clock-rates = <10000000>;
469 sdhci: sdhci@7e300000 {
470 compatible = "brcm,bcm2835-sdhci";
471 reg = <0x7e300000 0x100>;
473 clocks = <&clocks BCM2835_CLOCK_EMMC>;
478 compatible = "brcm,bcm2835-hvs";
479 reg = <0x7e400000 0x6000>;
484 compatible = "brcm,bcm2835-dsi1";
485 reg = <0x7e700000 0x8c>;
487 #address-cells = <1>;
491 clocks = <&clocks BCM2835_PLLD_DSI1>,
492 <&clocks BCM2835_CLOCK_DSI1E>,
493 <&clocks BCM2835_CLOCK_DSI1P>;
494 clock-names = "phy", "escape", "pixel";
496 clock-output-names = "dsi1_byte",
504 compatible = "brcm,bcm2835-i2c";
505 reg = <0x7e804000 0x1000>;
507 clocks = <&clocks BCM2835_CLOCK_VPU>;
508 #address-cells = <1>;
514 compatible = "brcm,bcm2835-i2c";
515 reg = <0x7e805000 0x1000>;
517 clocks = <&clocks BCM2835_CLOCK_VPU>;
518 #address-cells = <1>;
523 pixelvalve@7e807000 {
524 compatible = "brcm,bcm2835-pixelvalve2";
525 reg = <0x7e807000 0x100>;
526 interrupts = <2 10>; /* pixelvalve */
529 hdmi: hdmi@7e902000 {
530 compatible = "brcm,bcm2835-hdmi";
531 reg = <0x7e902000 0x600>,
533 interrupts = <2 8>, <2 9>;
535 clocks = <&clocks BCM2835_PLLH_PIX>,
536 <&clocks BCM2835_CLOCK_HSM>;
537 clock-names = "pixel", "hdmi";
542 compatible = "brcm,bcm2835-usb";
543 reg = <0x7e980000 0x10000>;
545 #address-cells = <1>;
552 compatible = "brcm,bcm2835-v3d";
553 reg = <0x7ec00000 0x1000>;
558 compatible = "brcm,bcm2835-vc4";
563 compatible = "simple-bus";
564 #address-cells = <1>;
567 /* The oscillator is the root of the clock tree. */
569 compatible = "fixed-clock";
572 clock-output-names = "osc";
573 clock-frequency = <19200000>;
577 compatible = "fixed-clock";
580 clock-output-names = "otg";
581 clock-frequency = <480000000>;