arch/arm/boot/dts/bcm283x.dtsi

   1 #include <dt-bindings/pinctrl/bcm2835.h>
   2 #include <dt-bindings/clock/bcm2835.h>
   3 #include <dt-bindings/clock/bcm2835-aux.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5
   6 /* firmware-provided startup stubs live here, where the secondary CPUs are
   7  * spinning.
   8  */
   9 /memreserve/ 0x00000000 0x00001000;
  10
  11 /* This include file covers the common peripherals and configuration between
  12  * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
  13  * bcm2835.dtsi and bcm2836.dtsi.
  14  */
  15
  16 / {
  17         compatible = "brcm,bcm2835";
  18         model = "BCM2835";
  19         interrupt-parent = <&intc>;
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         chosen {
  24                 bootargs = "earlyprintk console=ttyAMA0";
  25         };
  26
  27         soc {
  28                 compatible = "simple-bus";
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31
  32                 timer@7e003000 {
  33                         compatible = "brcm,bcm2835-system-timer";
  34                         reg = <0x7e003000 0x1000>;
  35                         interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
  36                         /* This could be a reference to BCM2835_CLOCK_TIMER,
  37                          * but we don't have the driver using the common clock
  38                          * support yet.
  39                          */
  40                         clock-frequency = <1000000>;
  41                 };
  42
  43                 dma: dma@7e007000 {
  44                         compatible = "brcm,bcm2835-dma";
  45                         reg = <0x7e007000 0xf00>;
  46                         interrupts = <1 16>,
  47                                      <1 17>,
  48                                      <1 18>,
  49                                      <1 19>,
  50                                      <1 20>,
  51                                      <1 21>,
  52                                      <1 22>,
  53                                      <1 23>,
  54                                      <1 24>,
  55                                      <1 25>,
  56                                      <1 26>,
  57                                      /* dma channel 11-14 share one irq */
  58                                      <1 27>,
  59                                      <1 27>,
  60                                      <1 27>,
  61                                      <1 27>,
  62                                      /* unused shared irq for all channels */
  63                                      <1 28>;
  64                         interrupt-names = "dma0",
  65                                           "dma1",
  66                                           "dma2",
  67                                           "dma3",
  68                                           "dma4",
  69                                           "dma5",
  70                                           "dma6",
  71                                           "dma7",
  72                                           "dma8",
  73                                           "dma9",
  74                                           "dma10",
  75                                           "dma11",
  76                                           "dma12",
  77                                           "dma13",
  78                                           "dma14",
  79                                           "dma-shared-all";
  80                         #dma-cells = <1>;
  81                         brcm,dma-channel-mask = <0x7f35>;
  82                 };
  83
  84                 intc: interrupt-controller@7e00b200 {
  85                         compatible = "brcm,bcm2835-armctrl-ic";
  86                         reg = <0x7e00b200 0x200>;
  87                         interrupt-controller;
  88                         #interrupt-cells = <2>;
  89                 };
  90
  91                 watchdog@7e100000 {
  92                         compatible = "brcm,bcm2835-pm-wdt";
  93                         reg = <0x7e100000 0x28>;
  94                 };
  95
  96                 clocks: cprman@7e101000 {
  97                         compatible = "brcm,bcm2835-cprman";
  98                         #clock-cells = <1>;
  99                         reg = <0x7e101000 0x2000>;
 100
 101                         /* CPRMAN derives almost everything from the
 102                          * platform's oscillator.  However, the DSI
 103                          * pixel clocks come from the DSI analog PHY.
 104                          */
 105                         clocks = <&clk_osc>,
 106                                 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
 107                                 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
 108                 };
 109
 110                 rng@7e104000 {
 111                         compatible = "brcm,bcm2835-rng";
 112                         reg = <0x7e104000 0x10>;
 113                 };
 114
 115                 mailbox: mailbox@7e00b880 {
 116                         compatible = "brcm,bcm2835-mbox";
 117                         reg = <0x7e00b880 0x40>;
 118                         interrupts = <0 1>;
 119                         #mbox-cells = <0>;
 120                 };
 121
 122                 gpio: gpio@7e200000 {
 123                         compatible = "brcm,bcm2835-gpio";
 124                         reg = <0x7e200000 0xb4>;
 125                         /*
 126                          * The GPIO IP block is designed for 3 banks of GPIOs.
 127                          * Each bank has a GPIO interrupt for itself.
 128                          * There is an overall "any bank" interrupt.
 129                          * In order, these are GIC interrupts 17, 18, 19, 20.
 130                          * Since the BCM2835 only has 2 banks, the 2nd bank
 131                          * interrupt output appears to be mirrored onto the
 132                          * 3rd bank's interrupt signal.
 133                          * So, a bank0 interrupt shows up on 17, 20, and
 134                          * a bank1 interrupt shows up on 18, 19, 20!
 135                          */
 136                         interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
 137
 138                         gpio-controller;
 139                         #gpio-cells = <2>;
 140
 141                         interrupt-controller;
 142                         #interrupt-cells = <2>;
 143
 144                         /* Defines pin muxing groups according to
 145                          * BCM2835-ARM-Peripherals.pdf page 102.
 146                          *
 147                          * While each pin can have its mux selected
 148                          * for various functions individually, some
 149                          * groups only make sense to switch to a
 150                          * particular function together.
 151                          */
 152                         dpi_gpio0: dpi_gpio0 {
 153                                 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
 154                                              12 13 14 15 16 17 18 19
 155                                              20 21 22 23 24 25 26 27>;
 156                                 brcm,function = <BCM2835_FSEL_ALT2>;
 157                         };
 158                         emmc_gpio22: emmc_gpio22 {
 159                                 brcm,pins = <22 23 24 25 26 27>;
 160                                 brcm,function = <BCM2835_FSEL_ALT3>;
 161                         };
 162                         emmc_gpio34: emmc_gpio34 {
 163                                 brcm,pins = <34 35 36 37 38 39>;
 164                                 brcm,function = <BCM2835_FSEL_ALT3>;
 165                                 brcm,pull = <BCM2835_PUD_OFF
 166                                              BCM2835_PUD_UP
 167                                              BCM2835_PUD_UP
 168                                              BCM2835_PUD_UP
 169                                              BCM2835_PUD_UP
 170                                              BCM2835_PUD_UP>;
 171                         };
 172                         emmc_gpio48: emmc_gpio48 {
 173                                 brcm,pins = <48 49 50 51 52 53>;
 174                                 brcm,function = <BCM2835_FSEL_ALT3>;
 175                         };
 176
 177                         gpclk0_gpio4: gpclk0_gpio4 {
 178                                 brcm,pins = <4>;
 179                                 brcm,function = <BCM2835_FSEL_ALT0>;
 180                         };
 181                         gpclk1_gpio5: gpclk1_gpio5 {
 182                                 brcm,pins = <5>;
 183                                 brcm,function = <BCM2835_FSEL_ALT0>;
 184                         };
 185                         gpclk1_gpio42: gpclk1_gpio42 {
 186                                 brcm,pins = <42>;
 187                                 brcm,function = <BCM2835_FSEL_ALT0>;
 188                         };
 189                         gpclk1_gpio44: gpclk1_gpio44 {
 190                                 brcm,pins = <44>;
 191                                 brcm,function = <BCM2835_FSEL_ALT0>;
 192                         };
 193                         gpclk2_gpio6: gpclk2_gpio6 {
 194                                 brcm,pins = <6>;
 195                                 brcm,function = <BCM2835_FSEL_ALT0>;
 196                         };
 197                         gpclk2_gpio43: gpclk2_gpio43 {
 198                                 brcm,pins = <43>;
 199                                 brcm,function = <BCM2835_FSEL_ALT0>;
 200                         };
 201
 202                         i2c0_gpio0: i2c0_gpio0 {
 203                                 brcm,pins = <0 1>;
 204                                 brcm,function = <BCM2835_FSEL_ALT0>;
 205                         };
 206                         i2c0_gpio28: i2c0_gpio28 {
 207                                 brcm,pins = <28 29>;
 208                                 brcm,function = <BCM2835_FSEL_ALT0>;
 209                         };
 210                         i2c0_gpio44: i2c0_gpio44 {
 211                                 brcm,pins = <44 45>;
 212                                 brcm,function = <BCM2835_FSEL_ALT1>;
 213                         };
 214                         i2c1_gpio2: i2c1_gpio2 {
 215                                 brcm,pins = <2 3>;
 216                                 brcm,function = <BCM2835_FSEL_ALT0>;
 217                         };
 218                         i2c1_gpio44: i2c1_gpio44 {
 219                                 brcm,pins = <44 45>;
 220                                 brcm,function = <BCM2835_FSEL_ALT2>;
 221                         };
 222                         i2c_slave_gpio18: i2c_slave_gpio18 {
 223                                 brcm,pins = <18 19 20 21>;
 224                                 brcm,function = <BCM2835_FSEL_ALT3>;
 225                         };
 226
 227                         jtag_gpio4: jtag_gpio4 {
 228                                 brcm,pins = <4 5 6 12 13>;
 229                                 brcm,function = <BCM2835_FSEL_ALT4>;
 230                         };
 231                         jtag_gpio22: jtag_gpio22 {
 232                                 brcm,pins = <22 23 24 25 26 27>;
 233                                 brcm,function = <BCM2835_FSEL_ALT4>;
 234                         };
 235
 236                         pcm_gpio18: pcm_gpio18 {
 237                                 brcm,pins = <18 19 20 21>;
 238                                 brcm,function = <BCM2835_FSEL_ALT0>;
 239                         };
 240                         pcm_gpio28: pcm_gpio28 {
 241                                 brcm,pins = <28 29 30 31>;
 242                                 brcm,function = <BCM2835_FSEL_ALT2>;
 243                         };
 244
 245                         pwm0_gpio12: pwm0_gpio12 {
 246                                 brcm,pins = <12>;
 247                                 brcm,function = <BCM2835_FSEL_ALT0>;
 248                         };
 249                         pwm0_gpio18: pwm0_gpio18 {
 250                                 brcm,pins = <18>;
 251                                 brcm,function = <BCM2835_FSEL_ALT5>;
 252                         };
 253                         pwm0_gpio40: pwm0_gpio40 {
 254                                 brcm,pins = <40>;
 255                                 brcm,function = <BCM2835_FSEL_ALT0>;
 256                         };
 257                         pwm1_gpio13: pwm1_gpio13 {
 258                                 brcm,pins = <13>;
 259                                 brcm,function = <BCM2835_FSEL_ALT0>;
 260                         };
 261                         pwm1_gpio19: pwm1_gpio19 {
 262                                 brcm,pins = <19>;
 263                                 brcm,function = <BCM2835_FSEL_ALT5>;
 264                         };
 265                         pwm1_gpio41: pwm1_gpio41 {
 266                                 brcm,pins = <41>;
 267                                 brcm,function = <BCM2835_FSEL_ALT0>;
 268                         };
 269                         pwm1_gpio45: pwm1_gpio45 {
 270                                 brcm,pins = <45>;
 271                                 brcm,function = <BCM2835_FSEL_ALT0>;
 272                         };
 273
 274                         sdhost_gpio48: sdhost_gpio48 {
 275                                 brcm,pins = <48 49 50 51 52 53>;
 276                                 brcm,function = <BCM2835_FSEL_ALT0>;
 277                         };
 278
 279                         spi0_gpio7: spi0_gpio7 {
 280                                 brcm,pins = <7 8 9 10 11>;
 281                                 brcm,function = <BCM2835_FSEL_ALT0>;
 282                         };
 283                         spi0_gpio35: spi0_gpio35 {
 284                                 brcm,pins = <35 36 37 38 39>;
 285                                 brcm,function = <BCM2835_FSEL_ALT0>;
 286                         };
 287                         spi1_gpio16: spi1_gpio16 {
 288                                 brcm,pins = <16 17 18 19 20 21>;
 289                                 brcm,function = <BCM2835_FSEL_ALT4>;
 290                         };
 291                         spi2_gpio40: spi2_gpio40 {
 292                                 brcm,pins = <40 41 42 43 44 45>;
 293                                 brcm,function = <BCM2835_FSEL_ALT4>;
 294                         };
 295
 296                         uart0_gpio14: uart0_gpio14 {
 297                                 brcm,pins = <14 15>;
 298                                 brcm,function = <BCM2835_FSEL_ALT0>;
 299                         };
 300                         /* Separate from the uart0_gpio14 group
 301                          * because it conflicts with spi1_gpio16, and
 302                          * people often run uart0 on the two pins
 303                          * without flow control.
 304                          */
 305                         uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
 306                                 brcm,pins = <16 17>;
 307                                 brcm,function = <BCM2835_FSEL_ALT3>;
 308                         };
 309                         uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
 310                                 brcm,pins = <30 31>;
 311                                 brcm,function = <BCM2835_FSEL_ALT3>;
 312                         };
 313                         uart0_gpio32: uart0_gpio32 {
 314                                 brcm,pins = <32 33>;
 315                                 brcm,function = <BCM2835_FSEL_ALT3>;
 316                         };
 317                         uart0_gpio36: uart0_gpio36 {
 318                                 brcm,pins = <36 37>;
 319                                 brcm,function = <BCM2835_FSEL_ALT2>;
 320                         };
 321                         uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
 322                                 brcm,pins = <38 39>;
 323                                 brcm,function = <BCM2835_FSEL_ALT2>;
 324                         };
 325
 326                         uart1_gpio14: uart1_gpio14 {
 327                                 brcm,pins = <14 15>;
 328                                 brcm,function = <BCM2835_FSEL_ALT5>;
 329                         };
 330                         uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
 331                                 brcm,pins = <16 17>;
 332                                 brcm,function = <BCM2835_FSEL_ALT5>;
 333                         };
 334                         uart1_gpio32: uart1_gpio32 {
 335                                 brcm,pins = <32 33>;
 336                                 brcm,function = <BCM2835_FSEL_ALT5>;
 337                         };
 338                         uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
 339                                 brcm,pins = <30 31>;
 340                                 brcm,function = <BCM2835_FSEL_ALT5>;
 341                         };
 342                         uart1_gpio40: uart1_gpio40 {
 343                                 brcm,pins = <40 41>;
 344                                 brcm,function = <BCM2835_FSEL_ALT5>;
 345                         };
 346                         uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
 347                                 brcm,pins = <42 43>;
 348                                 brcm,function = <BCM2835_FSEL_ALT5>;
 349                         };
 350                 };
 351
 352                 uart0: serial@7e201000 {
 353                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 354                         reg = <0x7e201000 0x1000>;
 355                         interrupts = <2 25>;
 356                         clocks = <&clocks BCM2835_CLOCK_UART>,
 357                                  <&clocks BCM2835_CLOCK_VPU>;
 358                         clock-names = "uartclk", "apb_pclk";
 359                         arm,primecell-periphid = <0x00241011>;
 360                 };
 361
 362                 sdhost: mmc@7e202000 {
 363                         compatible = "brcm,bcm2835-sdhost";
 364                         reg = <0x7e202000 0x100>;
 365                         interrupts = <2 24>;
 366                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 367                         dmas = <&dma 13>;
 368                         dma-names = "rx-tx";
 369                         status = "disabled";
 370                 };
 371
 372                 i2s: i2s@7e203000 {
 373                         compatible = "brcm,bcm2835-i2s";
 374                         reg = <0x7e203000 0x20>,
 375                               <0x7e101098 0x02>;
 376
 377                         dmas = <&dma 2>,
 378                                <&dma 3>;
 379                         dma-names = "tx", "rx";
 380                         status = "disabled";
 381                 };
 382
 383                 spi: spi@7e204000 {
 384                         compatible = "brcm,bcm2835-spi";
 385                         reg = <0x7e204000 0x1000>;
 386                         interrupts = <2 22>;
 387                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         status = "disabled";
 391                 };
 392
 393                 i2c0: i2c@7e205000 {
 394                         compatible = "brcm,bcm2835-i2c";
 395                         reg = <0x7e205000 0x1000>;
 396                         interrupts = <2 21>;
 397                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         status = "disabled";
 401                 };
 402
 403                 pixelvalve@7e206000 {
 404                         compatible = "brcm,bcm2835-pixelvalve0";
 405                         reg = <0x7e206000 0x100>;
 406                         interrupts = <2 13>; /* pwa0 */
 407                 };
 408
 409                 pixelvalve@7e207000 {
 410                         compatible = "brcm,bcm2835-pixelvalve1";
 411                         reg = <0x7e207000 0x100>;
 412                         interrupts = <2 14>; /* pwa1 */
 413                 };
 414
 415                 dsi0: dsi@7e209000 {
 416                         compatible = "brcm,bcm2835-dsi0";
 417                         reg = <0x7e209000 0x78>;
 418                         interrupts = <2 4>;
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         #clock-cells = <1>;
 422
 423                         clocks = <&clocks BCM2835_PLLA_DSI0>,
 424                                  <&clocks BCM2835_CLOCK_DSI0E>,
 425                                  <&clocks BCM2835_CLOCK_DSI0P>;
 426                         clock-names = "phy", "escape", "pixel";
 427
 428                         clock-output-names = "dsi0_byte",
 429                                              "dsi0_ddr2",
 430                                              "dsi0_ddr";
 431
 432                 };
 433
 434                 thermal: thermal@7e212000 {
 435                         compatible = "brcm,bcm2835-thermal";
 436                         reg = <0x7e212000 0x8>;
 437                         clocks = <&clocks BCM2835_CLOCK_TSENS>;
 438                         status = "disabled";
 439                 };
 440
 441                 aux: aux@0x7e215000 {
 442                         compatible = "brcm,bcm2835-aux";
 443                         #clock-cells = <1>;
 444                         reg = <0x7e215000 0x8>;
 445                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 446                 };
 447
 448                 uart1: serial@7e215040 {
 449                         compatible = "brcm,bcm2835-aux-uart";
 450                         reg = <0x7e215040 0x40>;
 451                         interrupts = <1 29>;
 452                         clocks = <&aux BCM2835_AUX_CLOCK_UART>;
 453                         status = "disabled";
 454                 };
 455
 456                 spi1: spi@7e215080 {
 457                         compatible = "brcm,bcm2835-aux-spi";
 458                         reg = <0x7e215080 0x40>;
 459                         interrupts = <1 29>;
 460                         clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         status = "disabled";
 464                 };
 465
 466                 spi2: spi@7e2150c0 {
 467                         compatible = "brcm,bcm2835-aux-spi";
 468                         reg = <0x7e2150c0 0x40>;
 469                         interrupts = <1 29>;
 470                         clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         status = "disabled";
 474                 };
 475
 476                 pwm: pwm@7e20c000 {
 477                         compatible = "brcm,bcm2835-pwm";
 478                         reg = <0x7e20c000 0x28>;
 479                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 480                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 481                         assigned-clock-rates = <10000000>;
 482                         #pwm-cells = <2>;
 483                         status = "disabled";
 484                 };
 485
 486                 sdhci: sdhci@7e300000 {
 487                         compatible = "brcm,bcm2835-sdhci";
 488                         reg = <0x7e300000 0x100>;
 489                         interrupts = <2 30>;
 490                         clocks = <&clocks BCM2835_CLOCK_EMMC>;
 491                         status = "disabled";
 492                 };
 493
 494                 hvs@7e400000 {
 495                         compatible = "brcm,bcm2835-hvs";
 496                         reg = <0x7e400000 0x6000>;
 497                         interrupts = <2 1>;
 498                 };
 499
 500                 dsi1: dsi@7e700000 {
 501                         compatible = "brcm,bcm2835-dsi1";
 502                         reg = <0x7e700000 0x8c>;
 503                         interrupts = <2 12>;
 504                         #address-cells = <1>;
 505                         #size-cells = <0>;
 506                         #clock-cells = <1>;
 507
 508                         clocks = <&clocks BCM2835_PLLD_DSI1>,
 509                                  <&clocks BCM2835_CLOCK_DSI1E>,
 510                                  <&clocks BCM2835_CLOCK_DSI1P>;
 511                         clock-names = "phy", "escape", "pixel";
 512
 513                         clock-output-names = "dsi1_byte",
 514                                              "dsi1_ddr2",
 515                                              "dsi1_ddr";
 516
 517                         status = "disabled";
 518                 };
 519
 520                 i2c1: i2c@7e804000 {
 521                         compatible = "brcm,bcm2835-i2c";
 522                         reg = <0x7e804000 0x1000>;
 523                         interrupts = <2 21>;
 524                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         status = "disabled";
 528                 };
 529
 530                 i2c2: i2c@7e805000 {
 531                         compatible = "brcm,bcm2835-i2c";
 532                         reg = <0x7e805000 0x1000>;
 533                         interrupts = <2 21>;
 534                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         status = "disabled";
 538                 };
 539
 540                 vec: vec@7e806000 {
 541                         compatible = "brcm,bcm2835-vec";
 542                         reg = <0x7e806000 0x1000>;
 543                         clocks = <&clocks BCM2835_CLOCK_VEC>;
 544                         interrupts = <2 27>;
 545                         status = "disabled";
 546                 };
 547
 548                 pixelvalve@7e807000 {
 549                         compatible = "brcm,bcm2835-pixelvalve2";
 550                         reg = <0x7e807000 0x100>;
 551                         interrupts = <2 10>; /* pixelvalve */
 552                 };
 553
 554                 hdmi: hdmi@7e902000 {
 555                         compatible = "brcm,bcm2835-hdmi";
 556                         reg = <0x7e902000 0x600>,
 557                               <0x7e808000 0x100>;
 558                         interrupts = <2 8>, <2 9>;
 559                         ddc = <&i2c2>;
 560                         clocks = <&clocks BCM2835_PLLH_PIX>,
 561                                  <&clocks BCM2835_CLOCK_HSM>;
 562                         clock-names = "pixel", "hdmi";
 563                         dmas = <&dma 17>;
 564                         dma-names = "audio-rx";
 565                         status = "disabled";
 566                 };
 567
 568                 usb: usb@7e980000 {
 569                         compatible = "brcm,bcm2835-usb";
 570                         reg = <0x7e980000 0x10000>;
 571                         interrupts = <1 9>;
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         clocks = <&clk_usb>;
 575                         clock-names = "otg";
 576                 };
 577
 578                 v3d: v3d@7ec00000 {
 579                         compatible = "brcm,bcm2835-v3d";
 580                         reg = <0x7ec00000 0x1000>;
 581                         interrupts = <1 10>;
 582                 };
 583
 584                 vc4: gpu {
 585                         compatible = "brcm,bcm2835-vc4";
 586                 };
 587         };
 588
 589         clocks {
 590                 compatible = "simple-bus";
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593
 594                 /* The oscillator is the root of the clock tree. */
 595                 clk_osc: clock@3 {
 596                         compatible = "fixed-clock";
 597                         reg = <3>;
 598                         #clock-cells = <0>;
 599                         clock-output-names = "osc";
 600                         clock-frequency = <19200000>;
 601                 };
 602
 603                 clk_usb: clock@4 {
 604                         compatible = "fixed-clock";
 605                         reg = <4>;
 606                         #clock-cells = <0>;
 607                         clock-output-names = "otg";
 608                         clock-frequency = <480000000>;
 609                 };
 610         };
 611 };